module IntXbar( // @[:freechips.rocketchip.system.LowRiscConfig.fir@3.2]
input auto_int_in_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
input auto_int_in_1, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
input auto_int_in_2, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
input auto_int_in_3, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
output auto_int_out_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
output auto_int_out_1, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
output auto_int_out_2, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
output auto_int_out_3 // @[:freechips.rocketchip.system.LowRiscConfig.fir@6.4]
);
assign auto_int_out_0 = auto_int_in_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15.4]
assign auto_int_out_1 = auto_int_in_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15.4]
assign auto_int_out_2 = auto_int_in_2; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15.4]
assign auto_int_out_3 = auto_int_in_3; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15.4]
endmodule
module TLMonitor( // @[:freechips.rocketchip.system.LowRiscConfig.fir@29.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [1:0] io_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [31:0] io_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [2:0] io_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [2:0] io_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [3:0] io_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [3:0] io_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [31:0] io_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input io_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
input [1:0] io_in_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@32.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@2900.4]
wire [1:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@49.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@55.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@56.6]
wire _T_39; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62.6]
wire _T_40; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63.6]
wire [26:0] _T_42; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65.6]
wire [11:0] _T_43; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@66.6]
wire [11:0] _T_44; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67.6]
wire [31:0] _GEN_33; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68.6]
wire [31:0] _T_45; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68.6]
wire _T_46; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@69.6]
wire [1:0] _T_48; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@71.6]
wire [3:0] _T_49; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@72.6]
wire [2:0] _T_50; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@73.6]
wire [2:0] _T_51; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@74.6]
wire _T_52; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@75.6]
wire _T_53; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@76.6]
wire _T_54; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77.6]
wire _T_55; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@78.6]
wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@80.6]
wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@81.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@83.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@84.6]
wire _T_62; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@85.6]
wire _T_63; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@86.6]
wire _T_64; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@87.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@88.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@89.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@90.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@91.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@92.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@93.6]
wire _T_71; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@94.6]
wire _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@95.6]
wire _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@96.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@97.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@98.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@99.6]
wire _T_77; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@100.6]
wire _T_78; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@101.6]
wire _T_79; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@102.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@103.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@104.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@105.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@106.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@107.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@108.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@109.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@110.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@111.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@112.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@113.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@114.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@115.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@116.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@117.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@118.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@119.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@120.6]
wire _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@121.6]
wire _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@122.6]
wire _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@123.6]
wire _T_101; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@124.6]
wire _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@125.6]
wire _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@126.6]
wire [7:0] _T_110; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@133.6]
wire [32:0] _T_121; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@144.6]
wire _T_147; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@174.6]
wire [31:0] _T_149; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@177.8]
wire [32:0] _T_150; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@178.8]
wire [32:0] _T_151; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@179.8]
wire [32:0] _T_152; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@180.8]
wire _T_153; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@181.8]
wire [31:0] _T_154; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@182.8]
wire [32:0] _T_155; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@183.8]
wire [32:0] _T_156; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@184.8]
wire [32:0] _T_157; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@185.8]
wire _T_158; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@186.8]
wire [31:0] _T_159; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@187.8]
wire [32:0] _T_160; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@188.8]
wire [32:0] _T_161; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@189.8]
wire [32:0] _T_162; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@190.8]
wire _T_163; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@191.8]
wire [31:0] _T_164; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@192.8]
wire [32:0] _T_165; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@193.8]
wire [32:0] _T_166; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@194.8]
wire [32:0] _T_167; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@195.8]
wire _T_168; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@196.8]
wire [32:0] _T_171; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@199.8]
wire [32:0] _T_172; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@200.8]
wire _T_173; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@201.8]
wire [31:0] _T_174; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@202.8]
wire [32:0] _T_175; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@203.8]
wire [32:0] _T_176; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@204.8]
wire [32:0] _T_177; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@205.8]
wire _T_178; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@206.8]
wire _T_186; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@214.8]
wire [31:0] _T_189; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@217.8]
wire [32:0] _T_190; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@218.8]
wire [32:0] _T_191; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@219.8]
wire [32:0] _T_192; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@220.8]
wire _T_193; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@221.8]
wire _T_194; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@222.8]
wire _T_198; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@226.8]
wire _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@227.8]
wire _T_219; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@247.8]
wire _T_221; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@248.8]
wire _T_229; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@256.8]
wire _T_230; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@257.8]
wire _T_232; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@263.8]
wire _T_233; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@264.8]
wire _T_236; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@271.8]
wire _T_237; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@272.8]
wire _T_239; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@278.8]
wire _T_240; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@279.8]
wire _T_241; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@284.8]
wire _T_243; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@286.8]
wire _T_244; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@287.8]
wire [7:0] _T_245; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@292.8]
wire _T_246; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@293.8]
wire _T_248; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@295.8]
wire _T_249; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@296.8]
wire _T_250; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@301.8]
wire _T_252; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@303.8]
wire _T_253; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@304.8]
wire _T_254; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@310.6]
wire _T_352; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@428.8]
wire _T_354; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@430.8]
wire _T_355; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@431.8]
wire _T_365; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@454.6]
wire _T_400; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@490.8]
wire _T_401; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@491.8]
wire _T_402; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@492.8]
wire _T_403; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@493.8]
wire _T_404; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@494.8]
wire _T_405; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@495.8]
wire _T_407; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@497.8]
wire _T_415; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@505.8]
wire _T_417; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@507.8]
wire _T_419; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@509.8]
wire _T_420; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@510.8]
wire _T_427; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@529.8]
wire _T_429; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@531.8]
wire _T_430; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@532.8]
wire _T_431; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@537.8]
wire _T_433; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@539.8]
wire _T_434; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@540.8]
wire _T_439; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@554.6]
wire _T_471; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@587.8]
wire _T_472; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@588.8]
wire _T_473; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@589.8]
wire _T_474; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@590.8]
wire _T_476; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@592.8]
wire _T_484; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@600.8]
wire _T_497; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@613.8]
wire _T_498; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@614.8]
wire _T_500; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@616.8]
wire _T_501; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@617.8]
wire _T_516; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@653.6]
wire [7:0] _T_589; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@743.8]
wire [7:0] _T_590; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@744.8]
wire _T_591; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@745.8]
wire _T_593; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@747.8]
wire _T_594; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@748.8]
wire _T_595; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@754.6]
wire _T_616; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@776.8]
wire _T_639; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@799.8]
wire _T_640; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@800.8]
wire _T_641; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@801.8]
wire _T_642; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@802.8]
wire _T_646; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@806.8]
wire _T_647; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@807.8]
wire _T_654; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@826.8]
wire _T_656; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@828.8]
wire _T_657; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@829.8]
wire _T_662; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@843.6]
wire _T_721; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@915.8]
wire _T_723; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@917.8]
wire _T_724; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@918.8]
wire _T_729; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@932.6]
wire _T_780; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@984.8]
wire _T_781; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@985.8]
wire _T_796; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@1023.6]
wire _T_798; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@1025.6]
wire _T_799; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@1026.6]
wire [1:0] _T_802; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@1033.6]
wire _T_803; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@1034.6]
wire _T_808; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1039.6]
wire _T_809; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1040.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1046.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1047.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@1049.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1052.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1053.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@1058.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@1060.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@1061.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@1066.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@1068.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@1069.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@1074.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@1076.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@1077.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@1082.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@1084.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@1085.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@1091.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@1115.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@1117.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@1118.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@1123.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@1125.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@1126.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@1149.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@1190.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@1192.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@1193.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@1208.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@1243.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@1279.6]
wire [32:0] _T_965; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1334.6]
wire [31:0] _T_991; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1364.6]
wire [32:0] _T_992; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1365.6]
wire [32:0] _T_993; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1366.6]
wire [32:0] _T_994; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1367.6]
wire _T_995; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1368.6]
wire [31:0] _T_996; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1369.6]
wire [32:0] _T_997; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1370.6]
wire [32:0] _T_998; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1371.6]
wire [32:0] _T_999; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1372.6]
wire _T_1000; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1373.6]
wire [31:0] _T_1001; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1374.6]
wire [32:0] _T_1002; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1375.6]
wire [32:0] _T_1003; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1376.6]
wire [32:0] _T_1004; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1377.6]
wire _T_1005; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1378.6]
wire [31:0] _T_1006; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1379.6]
wire [32:0] _T_1007; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1380.6]
wire [32:0] _T_1008; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1381.6]
wire [32:0] _T_1009; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1382.6]
wire _T_1010; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1383.6]
wire [32:0] _T_1013; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1386.6]
wire [32:0] _T_1014; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1387.6]
wire _T_1015; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1388.6]
wire [31:0] _T_1016; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1389.6]
wire [32:0] _T_1017; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1390.6]
wire [32:0] _T_1018; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1391.6]
wire [32:0] _T_1019; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1392.6]
wire _T_1020; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1393.6]
wire [31:0] _T_1021; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1394.6]
wire [32:0] _T_1022; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1395.6]
wire [32:0] _T_1023; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1396.6]
wire [32:0] _T_1024; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1397.6]
wire _T_1025; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1398.6]
wire _T_1039; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1408.6]
wire _T_1040; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1409.6]
wire _T_1041; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1410.6]
wire _T_1042; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1411.6]
wire _T_1043; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1412.6]
wire _T_1044; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1413.6]
wire [26:0] _T_1046; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@1415.6]
wire [11:0] _T_1047; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@1416.6]
wire [11:0] _T_1048; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@1417.6]
wire [31:0] _GEN_34; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1418.6]
wire [31:0] _T_1049; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1418.6]
wire _T_1050; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@1419.6]
wire _T_1176; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@1540.8]
wire _T_1177; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@1541.8]
wire _T_1182; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@1554.8]
wire _T_1183; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@1555.8]
wire _T_1184; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@1560.8]
wire _T_1186; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@1562.8]
wire _T_1187; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@1563.8]
wire [1:0] _T_1334; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@1889.6]
wire _T_1335; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@1890.6]
wire _T_1340; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1895.6]
wire _T_1341; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1896.6]
wire _T_1351; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1902.6]
wire _T_1352; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1903.6]
wire [26:0] _T_1354; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@1905.6]
wire [11:0] _T_1355; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@1906.6]
wire [11:0] _T_1356; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@1907.6]
wire [31:0] _GEN_35; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1908.6]
wire [31:0] _T_1357; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1908.6]
wire _T_1358; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@1909.6]
wire [31:0] _T_1359; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1910.6]
wire [32:0] _T_1360; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1911.6]
wire [32:0] _T_1361; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1912.6]
wire [32:0] _T_1362; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1913.6]
wire _T_1363; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1914.6]
wire [31:0] _T_1364; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1915.6]
wire [32:0] _T_1365; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1916.6]
wire [32:0] _T_1366; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1917.6]
wire [32:0] _T_1367; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1918.6]
wire _T_1368; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1919.6]
wire [31:0] _T_1369; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1920.6]
wire [32:0] _T_1370; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1921.6]
wire [32:0] _T_1371; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1922.6]
wire [32:0] _T_1372; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1923.6]
wire _T_1373; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1924.6]
wire [31:0] _T_1374; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1925.6]
wire [32:0] _T_1375; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1926.6]
wire [32:0] _T_1376; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1927.6]
wire [32:0] _T_1377; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1928.6]
wire _T_1378; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1929.6]
wire [32:0] _T_1380; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1931.6]
wire [32:0] _T_1381; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1932.6]
wire [32:0] _T_1382; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1933.6]
wire _T_1383; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1934.6]
wire [31:0] _T_1384; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1935.6]
wire [32:0] _T_1385; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1936.6]
wire [32:0] _T_1386; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1937.6]
wire [32:0] _T_1387; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1938.6]
wire _T_1388; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1939.6]
wire [31:0] _T_1389; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1940.6]
wire [32:0] _T_1390; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1941.6]
wire [32:0] _T_1391; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1942.6]
wire [32:0] _T_1392; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1943.6]
wire _T_1393; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1944.6]
wire _T_1407; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1954.6]
wire _T_1408; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1955.6]
wire _T_1409; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1956.6]
wire _T_1410; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1957.6]
wire _T_1411; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1958.6]
wire _T_1412; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1959.6]
wire _T_1449; // @[Monitor.scala 207:25:freechips.rocketchip.system.LowRiscConfig.fir@2000.6]
wire _T_1451; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2003.8]
wire _T_1452; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2004.8]
wire _T_1454; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@2010.8]
wire _T_1455; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@2011.8]
wire _T_1456; // @[Monitor.scala 210:27:freechips.rocketchip.system.LowRiscConfig.fir@2016.8]
wire _T_1458; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@2018.8]
wire _T_1459; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@2019.8]
wire _T_1461; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@2025.8]
wire _T_1462; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@2026.8]
wire _T_1463; // @[Bundles.scala 121:29:freechips.rocketchip.system.LowRiscConfig.fir@2031.8]
wire _T_1465; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@2033.8]
wire _T_1466; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@2034.8]
wire _T_1467; // @[Monitor.scala 213:15:freechips.rocketchip.system.LowRiscConfig.fir@2039.8]
wire _T_1469; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@2041.8]
wire _T_1470; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@2042.8]
wire _T_1471; // @[Monitor.scala 216:25:freechips.rocketchip.system.LowRiscConfig.fir@2048.6]
wire _T_1489; // @[Monitor.scala 224:25:freechips.rocketchip.system.LowRiscConfig.fir@2088.6]
wire _T_1528; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@2128.8]
wire _T_1536; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@2136.8]
wire _T_1540; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2140.8]
wire _T_1541; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2141.8]
wire _T_1561; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@2161.8]
wire _T_1563; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@2162.8]
wire _T_1571; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@2170.8]
wire _T_1572; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@2171.8]
wire _T_1583; // @[Bundles.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@2198.8]
wire _T_1585; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@2200.8]
wire _T_1586; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@2201.8]
wire _T_1591; // @[Monitor.scala 234:25:freechips.rocketchip.system.LowRiscConfig.fir@2215.6]
wire _T_1689; // @[Monitor.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@2334.6]
wire _T_1699; // @[Monitor.scala 247:28:freechips.rocketchip.system.LowRiscConfig.fir@2357.8]
wire _T_1701; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@2359.8]
wire _T_1702; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@2360.8]
wire _T_1707; // @[Monitor.scala 251:25:freechips.rocketchip.system.LowRiscConfig.fir@2374.6]
wire _T_1721; // @[Monitor.scala 258:25:freechips.rocketchip.system.LowRiscConfig.fir@2406.6]
wire _T_1743; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2457.4]
wire [8:0] _T_1748; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@2462.4]
wire _T_1749; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@2463.4]
wire _T_1750; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@2464.4]
reg [8:0] _T_1753; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2466.4]
reg [31:0] _RAND_0;
wire [9:0] _T_1754; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2467.4]
wire [9:0] _T_1755; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2468.4]
wire [8:0] _T_1756; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2469.4]
wire _T_1757; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2470.4]
reg [2:0] _T_1766; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@2481.4]
reg [31:0] _RAND_1;
reg [2:0] _T_1768; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@2482.4]
reg [31:0] _RAND_2;
reg [3:0] _T_1770; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@2483.4]
reg [31:0] _RAND_3;
reg [3:0] _T_1772; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@2484.4]
reg [31:0] _RAND_4;
reg [31:0] _T_1774; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@2485.4]
reg [31:0] _RAND_5;
wire _T_1775; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@2486.4]
wire _T_1776; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@2487.4]
wire _T_1777; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@2489.6]
wire _T_1779; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@2491.6]
wire _T_1780; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@2492.6]
wire _T_1781; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@2497.6]
wire _T_1783; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@2499.6]
wire _T_1784; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@2500.6]
wire _T_1785; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@2505.6]
wire _T_1787; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@2507.6]
wire _T_1788; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@2508.6]
wire _T_1789; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@2513.6]
wire _T_1791; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@2515.6]
wire _T_1792; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@2516.6]
wire _T_1793; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@2521.6]
wire _T_1795; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@2523.6]
wire _T_1796; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@2524.6]
wire _T_1798; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@2531.4]
wire _T_1799; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2539.4]
wire [26:0] _T_1801; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@2541.4]
wire [11:0] _T_1802; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@2542.4]
wire [11:0] _T_1803; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@2543.4]
wire [8:0] _T_1804; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@2544.4]
wire _T_1805; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@2545.4]
reg [8:0] _T_1808; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2547.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1809; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2548.4]
wire [9:0] _T_1810; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2549.4]
wire [8:0] _T_1811; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2550.4]
wire _T_1812; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2551.4]
reg [2:0] _T_1821; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@2562.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1823; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@2563.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1825; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@2564.4]
reg [31:0] _RAND_9;
reg [3:0] _T_1827; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@2565.4]
reg [31:0] _RAND_10;
reg [1:0] _T_1829; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@2566.4]
reg [31:0] _RAND_11;
reg _T_1831; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@2567.4]
reg [31:0] _RAND_12;
wire _T_1832; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@2568.4]
wire _T_1833; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@2569.4]
wire _T_1834; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@2571.6]
wire _T_1836; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@2573.6]
wire _T_1837; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@2574.6]
wire _T_1838; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@2579.6]
wire _T_1840; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@2581.6]
wire _T_1841; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@2582.6]
wire _T_1842; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@2587.6]
wire _T_1844; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@2589.6]
wire _T_1845; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@2590.6]
wire _T_1846; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@2595.6]
wire _T_1848; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@2597.6]
wire _T_1849; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@2598.6]
wire _T_1850; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@2603.6]
wire _T_1852; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@2605.6]
wire _T_1853; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@2606.6]
wire _T_1854; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@2611.6]
wire _T_1856; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@2613.6]
wire _T_1857; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@2614.6]
wire _T_1859; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@2621.4]
wire _T_1860; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2630.4]
reg [8:0] _T_1870; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2639.4]
reg [31:0] _RAND_13;
wire [9:0] _T_1871; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2640.4]
wire [9:0] _T_1872; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2641.4]
wire [8:0] _T_1873; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2642.4]
wire _T_1874; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2643.4]
reg [1:0] _T_1885; // @[Monitor.scala 373:22:freechips.rocketchip.system.LowRiscConfig.fir@2655.4]
reg [31:0] _RAND_14;
reg [31:0] _T_1891; // @[Monitor.scala 376:22:freechips.rocketchip.system.LowRiscConfig.fir@2658.4]
reg [31:0] _RAND_15;
wire _T_1892; // @[Monitor.scala 377:22:freechips.rocketchip.system.LowRiscConfig.fir@2659.4]
wire _T_1893; // @[Monitor.scala 377:19:freechips.rocketchip.system.LowRiscConfig.fir@2660.4]
wire _T_1898; // @[Monitor.scala 379:29:freechips.rocketchip.system.LowRiscConfig.fir@2670.6]
wire _T_1900; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@2672.6]
wire _T_1901; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@2673.6]
wire _T_1910; // @[Monitor.scala 382:29:freechips.rocketchip.system.LowRiscConfig.fir@2694.6]
wire _T_1912; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@2696.6]
wire _T_1913; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@2697.6]
wire _T_1915; // @[Monitor.scala 384:20:freechips.rocketchip.system.LowRiscConfig.fir@2704.4]
wire _T_1916; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2712.4]
wire [8:0] _T_1921; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@2717.4]
wire _T_1922; // @[Edges.scala 102:36:freechips.rocketchip.system.LowRiscConfig.fir@2718.4]
reg [8:0] _T_1925; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2720.4]
reg [31:0] _RAND_16;
wire [9:0] _T_1926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2721.4]
wire [9:0] _T_1927; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2722.4]
wire [8:0] _T_1928; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2723.4]
wire _T_1929; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2724.4]
reg [2:0] _T_1938; // @[Monitor.scala 395:22:freechips.rocketchip.system.LowRiscConfig.fir@2735.4]
reg [31:0] _RAND_17;
reg [2:0] _T_1940; // @[Monitor.scala 396:22:freechips.rocketchip.system.LowRiscConfig.fir@2736.4]
reg [31:0] _RAND_18;
reg [3:0] _T_1942; // @[Monitor.scala 397:22:freechips.rocketchip.system.LowRiscConfig.fir@2737.4]
reg [31:0] _RAND_19;
reg [3:0] _T_1944; // @[Monitor.scala 398:22:freechips.rocketchip.system.LowRiscConfig.fir@2738.4]
reg [31:0] _RAND_20;
reg [31:0] _T_1946; // @[Monitor.scala 399:22:freechips.rocketchip.system.LowRiscConfig.fir@2739.4]
reg [31:0] _RAND_21;
wire _T_1947; // @[Monitor.scala 400:22:freechips.rocketchip.system.LowRiscConfig.fir@2740.4]
wire _T_1948; // @[Monitor.scala 400:19:freechips.rocketchip.system.LowRiscConfig.fir@2741.4]
wire _T_1949; // @[Monitor.scala 401:29:freechips.rocketchip.system.LowRiscConfig.fir@2743.6]
wire _T_1951; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@2745.6]
wire _T_1952; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@2746.6]
wire _T_1953; // @[Monitor.scala 402:29:freechips.rocketchip.system.LowRiscConfig.fir@2751.6]
wire _T_1955; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@2753.6]
wire _T_1956; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@2754.6]
wire _T_1957; // @[Monitor.scala 403:29:freechips.rocketchip.system.LowRiscConfig.fir@2759.6]
wire _T_1959; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@2761.6]
wire _T_1960; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@2762.6]
wire _T_1961; // @[Monitor.scala 404:29:freechips.rocketchip.system.LowRiscConfig.fir@2767.6]
wire _T_1963; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@2769.6]
wire _T_1964; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@2770.6]
wire _T_1965; // @[Monitor.scala 405:29:freechips.rocketchip.system.LowRiscConfig.fir@2775.6]
wire _T_1967; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@2777.6]
wire _T_1968; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@2778.6]
wire _T_1970; // @[Monitor.scala 407:20:freechips.rocketchip.system.LowRiscConfig.fir@2785.4]
reg [8:0] _T_1972; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@2793.4]
reg [31:0] _RAND_22;
reg [8:0] _T_1983; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2803.4]
reg [31:0] _RAND_23;
wire [9:0] _T_1984; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2804.4]
wire [9:0] _T_1985; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2805.4]
wire [8:0] _T_1986; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2806.4]
wire _T_1987; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2807.4]
reg [8:0] _T_2004; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2826.4]
reg [31:0] _RAND_24;
wire [9:0] _T_2005; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2827.4]
wire [9:0] _T_2006; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2828.4]
wire [8:0] _T_2007; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2829.4]
wire _T_2008; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2830.4]
wire _T_2019; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@2845.4]
wire [15:0] _T_2021; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2848.6]
wire [8:0] _T_2022; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@2850.6]
wire _T_2023; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@2851.6]
wire _T_2024; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@2852.6]
wire _T_2026; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@2854.6]
wire _T_2027; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@2855.6]
wire [15:0] _GEN_27; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@2847.4]
wire _T_2032; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@2866.4]
wire _T_2034; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@2868.4]
wire _T_2035; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@2869.4]
wire [15:0] _T_2036; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2871.6]
wire [8:0] _T_2017; // @[:freechips.rocketchip.system.LowRiscConfig.fir@2841.4 :freechips.rocketchip.system.LowRiscConfig.fir@2843.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@2849.6]
wire [8:0] _T_2037; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@2873.6]
wire [8:0] _T_2038; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@2874.6]
wire _T_2039; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@2875.6]
wire _T_2041; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@2877.6]
wire _T_2042; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@2878.6]
wire [15:0] _GEN_28; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@2870.4]
wire [8:0] _T_2029; // @[:freechips.rocketchip.system.LowRiscConfig.fir@2861.4 :freechips.rocketchip.system.LowRiscConfig.fir@2863.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@2872.6]
wire _T_2043; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@2884.4]
wire _T_2044; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@2885.4]
wire _T_2045; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@2886.4]
wire _T_2046; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@2887.4]
wire _T_2048; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@2889.4]
wire _T_2049; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@2890.4]
wire [8:0] _T_2050; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@2895.4]
wire [8:0] _T_2051; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@2896.4]
wire [8:0] _T_2052; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@2897.4]
reg [31:0] _T_2054; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@2899.4]
reg [31:0] _RAND_25;
wire _T_2055; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@2902.4]
wire _T_2056; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@2903.4]
wire _T_2057; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@2904.4]
wire _T_2058; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@2905.4]
wire _T_2059; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@2906.4]
wire _T_2060; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@2907.4]
wire _T_2062; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@2909.4]
wire _T_2063; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@2910.4]
wire [31:0] _T_2065; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@2916.4]
wire _T_2068; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@2920.4]
reg [3:0] _T_2070; // @[Monitor.scala 486:27:freechips.rocketchip.system.LowRiscConfig.fir@2924.4]
reg [31:0] _RAND_26;
reg [8:0] _T_2080; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@2933.4]
reg [31:0] _RAND_27;
wire [9:0] _T_2081; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2934.4]
wire [9:0] _T_2082; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2935.4]
wire [8:0] _T_2083; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2936.4]
wire _T_2084; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2937.4]
wire _T_2095; // @[Monitor.scala 492:27:freechips.rocketchip.system.LowRiscConfig.fir@2952.4]
wire _T_2096; // @[Edges.scala 71:36:freechips.rocketchip.system.LowRiscConfig.fir@2953.4]
wire _T_2097; // @[Edges.scala 71:52:freechips.rocketchip.system.LowRiscConfig.fir@2954.4]
wire _T_2098; // @[Edges.scala 71:43:freechips.rocketchip.system.LowRiscConfig.fir@2955.4]
wire _T_2099; // @[Edges.scala 71:40:freechips.rocketchip.system.LowRiscConfig.fir@2956.4]
wire _T_2100; // @[Monitor.scala 492:38:freechips.rocketchip.system.LowRiscConfig.fir@2957.4]
wire [3:0] _T_2101; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2959.6]
wire [3:0] _T_2102; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@2961.6]
wire _T_2103; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@2962.6]
wire _T_2104; // @[Monitor.scala 494:14:freechips.rocketchip.system.LowRiscConfig.fir@2963.6]
wire _T_2106; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@2965.6]
wire _T_2107; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@2966.6]
wire [3:0] _GEN_31; // @[Monitor.scala 492:72:freechips.rocketchip.system.LowRiscConfig.fir@2958.4]
wire [3:0] _T_2113; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2979.6]
wire [3:0] _T_2114; // @[Monitor.scala 500:21:freechips.rocketchip.system.LowRiscConfig.fir@2981.6]
wire [3:0] _T_2115; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@2982.6]
wire _T_2116; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@2983.6]
wire _T_2118; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@2985.6]
wire _T_2119; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@2986.6]
wire [3:0] _GEN_32; // @[Monitor.scala 498:73:freechips.rocketchip.system.LowRiscConfig.fir@2978.4]
wire [3:0] _T_2120; // @[Monitor.scala 505:27:freechips.rocketchip.system.LowRiscConfig.fir@2992.4]
wire [3:0] _T_2121; // @[Monitor.scala 505:38:freechips.rocketchip.system.LowRiscConfig.fir@2993.4]
wire [3:0] _T_2122; // @[Monitor.scala 505:36:freechips.rocketchip.system.LowRiscConfig.fir@2994.4]
wire _GEN_36; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@229.10]
wire _GEN_52; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@365.10]
wire _GEN_70; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@512.10]
wire _GEN_82; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@619.10]
wire _GEN_92; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@718.10]
wire _GEN_102; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@809.10]
wire _GEN_112; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@898.10]
wire _GEN_122; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@987.10]
wire _GEN_132; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1055.10]
wire _GEN_142; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@1097.10]
wire _GEN_152; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@1155.10]
wire _GEN_162; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@1214.10]
wire _GEN_168; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@1249.10]
wire _GEN_174; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@1285.10]
wire _GEN_180; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2006.10]
wire _GEN_192; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@2054.10]
wire _GEN_202; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2143.10]
wire _GEN_216; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@2270.10]
wire _GEN_228; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@2340.10]
wire _GEN_238; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@2380.10]
wire _GEN_246; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@2412.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@2900.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@49.6]
assign _T_23 = _T_22 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50.6]
assign _T_28 = io_in_a_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@55.6]
assign _T_29 = io_in_a_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@56.6]
assign _T_39 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62.6]
assign _T_40 = _T_39 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63.6]
assign _T_42 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65.6]
assign _T_43 = _T_42[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@66.6]
assign _T_44 = ~ _T_43; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67.6]
assign _GEN_33 = {{20'd0}, _T_44}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68.6]
assign _T_45 = io_in_a_bits_address & _GEN_33; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68.6]
assign _T_46 = _T_45 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@69.6]
assign _T_48 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@71.6]
assign _T_49 = 4'h1 << _T_48; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@72.6]
assign _T_50 = _T_49[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@73.6]
assign _T_51 = _T_50 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@74.6]
assign _T_52 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@75.6]
assign _T_53 = _T_51[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@76.6]
assign _T_54 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77.6]
assign _T_55 = _T_54 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@78.6]
assign _T_57 = _T_53 & _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@80.6]
assign _T_58 = _T_52 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@81.6]
assign _T_60 = _T_53 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@83.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@84.6]
assign _T_62 = _T_51[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@85.6]
assign _T_63 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@86.6]
assign _T_64 = _T_63 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@87.6]
assign _T_65 = _T_55 & _T_64; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@88.6]
assign _T_66 = _T_62 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@89.6]
assign _T_67 = _T_58 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@90.6]
assign _T_68 = _T_55 & _T_63; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@91.6]
assign _T_69 = _T_62 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@92.6]
assign _T_70 = _T_58 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@93.6]
assign _T_71 = _T_54 & _T_64; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@94.6]
assign _T_72 = _T_62 & _T_71; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@95.6]
assign _T_73 = _T_61 | _T_72; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@96.6]
assign _T_74 = _T_54 & _T_63; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@97.6]
assign _T_75 = _T_62 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@98.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@99.6]
assign _T_77 = _T_51[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@100.6]
assign _T_78 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@101.6]
assign _T_79 = _T_78 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@102.6]
assign _T_80 = _T_65 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@103.6]
assign _T_81 = _T_77 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@104.6]
assign _T_82 = _T_67 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@105.6]
assign _T_83 = _T_65 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@106.6]
assign _T_84 = _T_77 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@107.6]
assign _T_85 = _T_67 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@108.6]
assign _T_86 = _T_68 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@109.6]
assign _T_87 = _T_77 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@110.6]
assign _T_88 = _T_70 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@111.6]
assign _T_89 = _T_68 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@112.6]
assign _T_90 = _T_77 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@113.6]
assign _T_91 = _T_70 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@114.6]
assign _T_92 = _T_71 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@115.6]
assign _T_93 = _T_77 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@116.6]
assign _T_94 = _T_73 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@117.6]
assign _T_95 = _T_71 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@118.6]
assign _T_96 = _T_77 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@119.6]
assign _T_97 = _T_73 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@120.6]
assign _T_98 = _T_74 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@121.6]
assign _T_99 = _T_77 & _T_98; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@122.6]
assign _T_100 = _T_76 | _T_99; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@123.6]
assign _T_101 = _T_74 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@124.6]
assign _T_102 = _T_77 & _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@125.6]
assign _T_103 = _T_76 | _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@126.6]
assign _T_110 = {_T_103,_T_100,_T_97,_T_94,_T_91,_T_88,_T_85,_T_82}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@133.6]
assign _T_121 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@144.6]
assign _T_147 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@174.6]
assign _T_149 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@177.8]
assign _T_150 = {1'b0,$signed(_T_149)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@178.8]
assign _T_151 = $signed(_T_150) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@179.8]
assign _T_152 = $signed(_T_151); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@180.8]
assign _T_153 = $signed(_T_152) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@181.8]
assign _T_154 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@182.8]
assign _T_155 = {1'b0,$signed(_T_154)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@183.8]
assign _T_156 = $signed(_T_155) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@184.8]
assign _T_157 = $signed(_T_156); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@185.8]
assign _T_158 = $signed(_T_157) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@186.8]
assign _T_159 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@187.8]
assign _T_160 = {1'b0,$signed(_T_159)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@188.8]
assign _T_161 = $signed(_T_160) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@189.8]
assign _T_162 = $signed(_T_161); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@190.8]
assign _T_163 = $signed(_T_162) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@191.8]
assign _T_164 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@192.8]
assign _T_165 = {1'b0,$signed(_T_164)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@193.8]
assign _T_166 = $signed(_T_165) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@194.8]
assign _T_167 = $signed(_T_166); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@195.8]
assign _T_168 = $signed(_T_167) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@196.8]
assign _T_171 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@199.8]
assign _T_172 = $signed(_T_171); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@200.8]
assign _T_173 = $signed(_T_172) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@201.8]
assign _T_174 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@202.8]
assign _T_175 = {1'b0,$signed(_T_174)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@203.8]
assign _T_176 = $signed(_T_175) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@204.8]
assign _T_177 = $signed(_T_176); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@205.8]
assign _T_178 = $signed(_T_177) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@206.8]
assign _T_186 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@214.8]
assign _T_189 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@217.8]
assign _T_190 = {1'b0,$signed(_T_189)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@218.8]
assign _T_191 = $signed(_T_190) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@219.8]
assign _T_192 = $signed(_T_191); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@220.8]
assign _T_193 = $signed(_T_192) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@221.8]
assign _T_194 = _T_186 & _T_193; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@222.8]
assign _T_198 = _T_194 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@226.8]
assign _T_199 = _T_198 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@227.8]
assign _T_219 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@247.8]
assign _T_221 = _T_23 ? _T_219 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@248.8]
assign _T_229 = _T_221 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@256.8]
assign _T_230 = _T_229 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@257.8]
assign _T_232 = _T_40 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@263.8]
assign _T_233 = _T_232 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@264.8]
assign _T_236 = _T_52 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@271.8]
assign _T_237 = _T_236 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@272.8]
assign _T_239 = _T_46 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@278.8]
assign _T_240 = _T_239 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@279.8]
assign _T_241 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@284.8]
assign _T_243 = _T_241 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@286.8]
assign _T_244 = _T_243 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@287.8]
assign _T_245 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@292.8]
assign _T_246 = _T_245 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@293.8]
assign _T_248 = _T_246 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@295.8]
assign _T_249 = _T_248 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@296.8]
assign _T_250 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@301.8]
assign _T_252 = _T_250 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@303.8]
assign _T_253 = _T_252 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@304.8]
assign _T_254 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@310.6]
assign _T_352 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@428.8]
assign _T_354 = _T_352 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@430.8]
assign _T_355 = _T_354 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@431.8]
assign _T_365 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@454.6]
assign _T_400 = _T_153 | _T_163; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@490.8]
assign _T_401 = _T_400 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@491.8]
assign _T_402 = _T_401 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@492.8]
assign _T_403 = _T_402 | _T_178; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@493.8]
assign _T_404 = _T_403 | _T_193; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@494.8]
assign _T_405 = _T_186 & _T_404; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@495.8]
assign _T_407 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@497.8]
assign _T_415 = _T_407 & _T_158; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@505.8]
assign _T_417 = _T_405 | _T_415; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@507.8]
assign _T_419 = _T_417 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@509.8]
assign _T_420 = _T_419 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@510.8]
assign _T_427 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@529.8]
assign _T_429 = _T_427 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@531.8]
assign _T_430 = _T_429 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@532.8]
assign _T_431 = io_in_a_bits_mask == _T_110; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@537.8]
assign _T_433 = _T_431 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@539.8]
assign _T_434 = _T_433 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@540.8]
assign _T_439 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@554.6]
assign _T_471 = _T_163 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@587.8]
assign _T_472 = _T_471 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@588.8]
assign _T_473 = _T_472 | _T_193; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@589.8]
assign _T_474 = _T_186 & _T_473; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@590.8]
assign _T_476 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@592.8]
assign _T_484 = _T_476 & _T_153; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@600.8]
assign _T_497 = _T_474 | _T_484; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@613.8]
assign _T_498 = _T_497 | _T_415; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@614.8]
assign _T_500 = _T_498 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@616.8]
assign _T_501 = _T_500 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@617.8]
assign _T_516 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@653.6]
assign _T_589 = ~ _T_110; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@743.8]
assign _T_590 = io_in_a_bits_mask & _T_589; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@744.8]
assign _T_591 = _T_590 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@745.8]
assign _T_593 = _T_591 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@747.8]
assign _T_594 = _T_593 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@748.8]
assign _T_595 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@754.6]
assign _T_616 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@776.8]
assign _T_639 = _T_158 | _T_163; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@799.8]
assign _T_640 = _T_639 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@800.8]
assign _T_641 = _T_640 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@801.8]
assign _T_642 = _T_616 & _T_641; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@802.8]
assign _T_646 = _T_642 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@806.8]
assign _T_647 = _T_646 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@807.8]
assign _T_654 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@826.8]
assign _T_656 = _T_654 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@828.8]
assign _T_657 = _T_656 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@829.8]
assign _T_662 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@843.6]
assign _T_721 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@915.8]
assign _T_723 = _T_721 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@917.8]
assign _T_724 = _T_723 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@918.8]
assign _T_729 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@932.6]
assign _T_780 = _T_415 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@984.8]
assign _T_781 = _T_780 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@985.8]
assign _T_796 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@1023.6]
assign _T_798 = _T_796 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@1025.6]
assign _T_799 = _T_798 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@1026.6]
assign _T_802 = io_in_d_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@1033.6]
assign _T_803 = _T_802 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@1034.6]
assign _T_808 = io_in_d_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1039.6]
assign _T_809 = io_in_d_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1040.6]
assign _T_819 = _T_803 | _T_808; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1046.6]
assign _T_820 = _T_819 | _T_809; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1047.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@1049.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1052.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1053.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@1058.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@1060.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@1061.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@1066.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@1068.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@1069.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@1074.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@1076.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@1077.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@1082.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@1084.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@1085.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@1091.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@1115.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@1117.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@1118.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@1123.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@1125.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@1126.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@1149.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@1190.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@1192.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@1193.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@1208.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@1243.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@1279.6]
assign _T_965 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1334.6]
assign _T_991 = io_in_b_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1364.6]
assign _T_992 = {1'b0,$signed(_T_991)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1365.6]
assign _T_993 = $signed(_T_992) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1366.6]
assign _T_994 = $signed(_T_993); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1367.6]
assign _T_995 = $signed(_T_994) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1368.6]
assign _T_996 = io_in_b_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1369.6]
assign _T_997 = {1'b0,$signed(_T_996)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1370.6]
assign _T_998 = $signed(_T_997) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1371.6]
assign _T_999 = $signed(_T_998); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1372.6]
assign _T_1000 = $signed(_T_999) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1373.6]
assign _T_1001 = io_in_b_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1374.6]
assign _T_1002 = {1'b0,$signed(_T_1001)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1375.6]
assign _T_1003 = $signed(_T_1002) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1376.6]
assign _T_1004 = $signed(_T_1003); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1377.6]
assign _T_1005 = $signed(_T_1004) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1378.6]
assign _T_1006 = io_in_b_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1379.6]
assign _T_1007 = {1'b0,$signed(_T_1006)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1380.6]
assign _T_1008 = $signed(_T_1007) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1381.6]
assign _T_1009 = $signed(_T_1008); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1382.6]
assign _T_1010 = $signed(_T_1009) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1383.6]
assign _T_1013 = $signed(_T_965) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1386.6]
assign _T_1014 = $signed(_T_1013); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1387.6]
assign _T_1015 = $signed(_T_1014) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1388.6]
assign _T_1016 = io_in_b_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1389.6]
assign _T_1017 = {1'b0,$signed(_T_1016)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1390.6]
assign _T_1018 = $signed(_T_1017) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1391.6]
assign _T_1019 = $signed(_T_1018); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1392.6]
assign _T_1020 = $signed(_T_1019) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1393.6]
assign _T_1021 = io_in_b_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1394.6]
assign _T_1022 = {1'b0,$signed(_T_1021)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1395.6]
assign _T_1023 = $signed(_T_1022) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1396.6]
assign _T_1024 = $signed(_T_1023); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1397.6]
assign _T_1025 = $signed(_T_1024) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1398.6]
assign _T_1039 = _T_995 | _T_1000; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1408.6]
assign _T_1040 = _T_1039 | _T_1005; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1409.6]
assign _T_1041 = _T_1040 | _T_1010; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1410.6]
assign _T_1042 = _T_1041 | _T_1015; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1411.6]
assign _T_1043 = _T_1042 | _T_1020; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1412.6]
assign _T_1044 = _T_1043 | _T_1025; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1413.6]
assign _T_1046 = 27'hfff << 4'h6; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@1415.6]
assign _T_1047 = _T_1046[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@1416.6]
assign _T_1048 = ~ _T_1047; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@1417.6]
assign _GEN_34 = {{20'd0}, _T_1048}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1418.6]
assign _T_1049 = io_in_b_bits_address & _GEN_34; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1418.6]
assign _T_1050 = _T_1049 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@1419.6]
assign _T_1176 = _T_1044 | reset; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@1540.8]
assign _T_1177 = _T_1176 == 1'h0; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@1541.8]
assign _T_1182 = _T_1050 | reset; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@1554.8]
assign _T_1183 = _T_1182 == 1'h0; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@1555.8]
assign _T_1184 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@1560.8]
assign _T_1186 = _T_1184 | reset; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@1562.8]
assign _T_1187 = _T_1186 == 1'h0; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@1563.8]
assign _T_1334 = io_in_c_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@1889.6]
assign _T_1335 = _T_1334 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@1890.6]
assign _T_1340 = io_in_c_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1895.6]
assign _T_1341 = io_in_c_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@1896.6]
assign _T_1351 = _T_1335 | _T_1340; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1902.6]
assign _T_1352 = _T_1351 | _T_1341; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@1903.6]
assign _T_1354 = 27'hfff << io_in_c_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@1905.6]
assign _T_1355 = _T_1354[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@1906.6]
assign _T_1356 = ~ _T_1355; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@1907.6]
assign _GEN_35 = {{20'd0}, _T_1356}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1908.6]
assign _T_1357 = io_in_c_bits_address & _GEN_35; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@1908.6]
assign _T_1358 = _T_1357 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@1909.6]
assign _T_1359 = io_in_c_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1910.6]
assign _T_1360 = {1'b0,$signed(_T_1359)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1911.6]
assign _T_1361 = $signed(_T_1360) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1912.6]
assign _T_1362 = $signed(_T_1361); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1913.6]
assign _T_1363 = $signed(_T_1362) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1914.6]
assign _T_1364 = io_in_c_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1915.6]
assign _T_1365 = {1'b0,$signed(_T_1364)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1916.6]
assign _T_1366 = $signed(_T_1365) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1917.6]
assign _T_1367 = $signed(_T_1366); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1918.6]
assign _T_1368 = $signed(_T_1367) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1919.6]
assign _T_1369 = io_in_c_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1920.6]
assign _T_1370 = {1'b0,$signed(_T_1369)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1921.6]
assign _T_1371 = $signed(_T_1370) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1922.6]
assign _T_1372 = $signed(_T_1371); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1923.6]
assign _T_1373 = $signed(_T_1372) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1924.6]
assign _T_1374 = io_in_c_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1925.6]
assign _T_1375 = {1'b0,$signed(_T_1374)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1926.6]
assign _T_1376 = $signed(_T_1375) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1927.6]
assign _T_1377 = $signed(_T_1376); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1928.6]
assign _T_1378 = $signed(_T_1377) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1929.6]
assign _T_1380 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1931.6]
assign _T_1381 = $signed(_T_1380) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1932.6]
assign _T_1382 = $signed(_T_1381); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1933.6]
assign _T_1383 = $signed(_T_1382) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1934.6]
assign _T_1384 = io_in_c_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1935.6]
assign _T_1385 = {1'b0,$signed(_T_1384)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1936.6]
assign _T_1386 = $signed(_T_1385) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1937.6]
assign _T_1387 = $signed(_T_1386); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1938.6]
assign _T_1388 = $signed(_T_1387) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1939.6]
assign _T_1389 = io_in_c_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@1940.6]
assign _T_1390 = {1'b0,$signed(_T_1389)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@1941.6]
assign _T_1391 = $signed(_T_1390) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1942.6]
assign _T_1392 = $signed(_T_1391); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@1943.6]
assign _T_1393 = $signed(_T_1392) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@1944.6]
assign _T_1407 = _T_1363 | _T_1368; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1954.6]
assign _T_1408 = _T_1407 | _T_1373; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1955.6]
assign _T_1409 = _T_1408 | _T_1378; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1956.6]
assign _T_1410 = _T_1409 | _T_1383; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1957.6]
assign _T_1411 = _T_1410 | _T_1388; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1958.6]
assign _T_1412 = _T_1411 | _T_1393; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@1959.6]
assign _T_1449 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 207:25:freechips.rocketchip.system.LowRiscConfig.fir@2000.6]
assign _T_1451 = _T_1412 | reset; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2003.8]
assign _T_1452 = _T_1451 == 1'h0; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2004.8]
assign _T_1454 = _T_1352 | reset; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@2010.8]
assign _T_1455 = _T_1454 == 1'h0; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@2011.8]
assign _T_1456 = io_in_c_bits_size >= 4'h3; // @[Monitor.scala 210:27:freechips.rocketchip.system.LowRiscConfig.fir@2016.8]
assign _T_1458 = _T_1456 | reset; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@2018.8]
assign _T_1459 = _T_1458 == 1'h0; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@2019.8]
assign _T_1461 = _T_1358 | reset; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@2025.8]
assign _T_1462 = _T_1461 == 1'h0; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@2026.8]
assign _T_1463 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 121:29:freechips.rocketchip.system.LowRiscConfig.fir@2031.8]
assign _T_1465 = _T_1463 | reset; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@2033.8]
assign _T_1466 = _T_1465 == 1'h0; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@2034.8]
assign _T_1467 = io_in_c_bits_corrupt == 1'h0; // @[Monitor.scala 213:15:freechips.rocketchip.system.LowRiscConfig.fir@2039.8]
assign _T_1469 = _T_1467 | reset; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@2041.8]
assign _T_1470 = _T_1469 == 1'h0; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@2042.8]
assign _T_1471 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 216:25:freechips.rocketchip.system.LowRiscConfig.fir@2048.6]
assign _T_1489 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 224:25:freechips.rocketchip.system.LowRiscConfig.fir@2088.6]
assign _T_1528 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@2128.8]
assign _T_1536 = _T_1528 & _T_1393; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@2136.8]
assign _T_1540 = _T_1536 | reset; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2140.8]
assign _T_1541 = _T_1540 == 1'h0; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2141.8]
assign _T_1561 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@2161.8]
assign _T_1563 = _T_1335 ? _T_1561 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@2162.8]
assign _T_1571 = _T_1563 | reset; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@2170.8]
assign _T_1572 = _T_1571 == 1'h0; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@2171.8]
assign _T_1583 = io_in_c_bits_param <= 3'h2; // @[Bundles.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@2198.8]
assign _T_1585 = _T_1583 | reset; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@2200.8]
assign _T_1586 = _T_1585 == 1'h0; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@2201.8]
assign _T_1591 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 234:25:freechips.rocketchip.system.LowRiscConfig.fir@2215.6]
assign _T_1689 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@2334.6]
assign _T_1699 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 247:28:freechips.rocketchip.system.LowRiscConfig.fir@2357.8]
assign _T_1701 = _T_1699 | reset; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@2359.8]
assign _T_1702 = _T_1701 == 1'h0; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@2360.8]
assign _T_1707 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 251:25:freechips.rocketchip.system.LowRiscConfig.fir@2374.6]
assign _T_1721 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 258:25:freechips.rocketchip.system.LowRiscConfig.fir@2406.6]
assign _T_1743 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2457.4]
assign _T_1748 = _T_44[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@2462.4]
assign _T_1749 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@2463.4]
assign _T_1750 = _T_1749 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@2464.4]
assign _T_1754 = _T_1753 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2467.4]
assign _T_1755 = $unsigned(_T_1754); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2468.4]
assign _T_1756 = _T_1755[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2469.4]
assign _T_1757 = _T_1753 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2470.4]
assign _T_1775 = _T_1757 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@2486.4]
assign _T_1776 = io_in_a_valid & _T_1775; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@2487.4]
assign _T_1777 = io_in_a_bits_opcode == _T_1766; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@2489.6]
assign _T_1779 = _T_1777 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@2491.6]
assign _T_1780 = _T_1779 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@2492.6]
assign _T_1781 = io_in_a_bits_param == _T_1768; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@2497.6]
assign _T_1783 = _T_1781 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@2499.6]
assign _T_1784 = _T_1783 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@2500.6]
assign _T_1785 = io_in_a_bits_size == _T_1770; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@2505.6]
assign _T_1787 = _T_1785 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@2507.6]
assign _T_1788 = _T_1787 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@2508.6]
assign _T_1789 = io_in_a_bits_source == _T_1772; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@2513.6]
assign _T_1791 = _T_1789 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@2515.6]
assign _T_1792 = _T_1791 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@2516.6]
assign _T_1793 = io_in_a_bits_address == _T_1774; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@2521.6]
assign _T_1795 = _T_1793 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@2523.6]
assign _T_1796 = _T_1795 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@2524.6]
assign _T_1798 = _T_1743 & _T_1757; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@2531.4]
assign _T_1799 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2539.4]
assign _T_1801 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@2541.4]
assign _T_1802 = _T_1801[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@2542.4]
assign _T_1803 = ~ _T_1802; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@2543.4]
assign _T_1804 = _T_1803[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@2544.4]
assign _T_1805 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@2545.4]
assign _T_1809 = _T_1808 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2548.4]
assign _T_1810 = $unsigned(_T_1809); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2549.4]
assign _T_1811 = _T_1810[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2550.4]
assign _T_1812 = _T_1808 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2551.4]
assign _T_1832 = _T_1812 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@2568.4]
assign _T_1833 = io_in_d_valid & _T_1832; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@2569.4]
assign _T_1834 = io_in_d_bits_opcode == _T_1821; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@2571.6]
assign _T_1836 = _T_1834 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@2573.6]
assign _T_1837 = _T_1836 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@2574.6]
assign _T_1838 = io_in_d_bits_param == _T_1823; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@2579.6]
assign _T_1840 = _T_1838 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@2581.6]
assign _T_1841 = _T_1840 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@2582.6]
assign _T_1842 = io_in_d_bits_size == _T_1825; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@2587.6]
assign _T_1844 = _T_1842 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@2589.6]
assign _T_1845 = _T_1844 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@2590.6]
assign _T_1846 = io_in_d_bits_source == _T_1827; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@2595.6]
assign _T_1848 = _T_1846 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@2597.6]
assign _T_1849 = _T_1848 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@2598.6]
assign _T_1850 = io_in_d_bits_sink == _T_1829; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@2603.6]
assign _T_1852 = _T_1850 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@2605.6]
assign _T_1853 = _T_1852 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@2606.6]
assign _T_1854 = io_in_d_bits_denied == _T_1831; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@2611.6]
assign _T_1856 = _T_1854 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@2613.6]
assign _T_1857 = _T_1856 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@2614.6]
assign _T_1859 = _T_1799 & _T_1812; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@2621.4]
assign _T_1860 = io_in_b_ready & io_in_b_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2630.4]
assign _T_1871 = _T_1870 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2640.4]
assign _T_1872 = $unsigned(_T_1871); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2641.4]
assign _T_1873 = _T_1872[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2642.4]
assign _T_1874 = _T_1870 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2643.4]
assign _T_1892 = _T_1874 == 1'h0; // @[Monitor.scala 377:22:freechips.rocketchip.system.LowRiscConfig.fir@2659.4]
assign _T_1893 = io_in_b_valid & _T_1892; // @[Monitor.scala 377:19:freechips.rocketchip.system.LowRiscConfig.fir@2660.4]
assign _T_1898 = io_in_b_bits_param == _T_1885; // @[Monitor.scala 379:29:freechips.rocketchip.system.LowRiscConfig.fir@2670.6]
assign _T_1900 = _T_1898 | reset; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@2672.6]
assign _T_1901 = _T_1900 == 1'h0; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@2673.6]
assign _T_1910 = io_in_b_bits_address == _T_1891; // @[Monitor.scala 382:29:freechips.rocketchip.system.LowRiscConfig.fir@2694.6]
assign _T_1912 = _T_1910 | reset; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@2696.6]
assign _T_1913 = _T_1912 == 1'h0; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@2697.6]
assign _T_1915 = _T_1860 & _T_1874; // @[Monitor.scala 384:20:freechips.rocketchip.system.LowRiscConfig.fir@2704.4]
assign _T_1916 = io_in_c_ready & io_in_c_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@2712.4]
assign _T_1921 = _T_1356[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@2717.4]
assign _T_1922 = io_in_c_bits_opcode[0]; // @[Edges.scala 102:36:freechips.rocketchip.system.LowRiscConfig.fir@2718.4]
assign _T_1926 = _T_1925 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2721.4]
assign _T_1927 = $unsigned(_T_1926); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2722.4]
assign _T_1928 = _T_1927[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2723.4]
assign _T_1929 = _T_1925 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2724.4]
assign _T_1947 = _T_1929 == 1'h0; // @[Monitor.scala 400:22:freechips.rocketchip.system.LowRiscConfig.fir@2740.4]
assign _T_1948 = io_in_c_valid & _T_1947; // @[Monitor.scala 400:19:freechips.rocketchip.system.LowRiscConfig.fir@2741.4]
assign _T_1949 = io_in_c_bits_opcode == _T_1938; // @[Monitor.scala 401:29:freechips.rocketchip.system.LowRiscConfig.fir@2743.6]
assign _T_1951 = _T_1949 | reset; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@2745.6]
assign _T_1952 = _T_1951 == 1'h0; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@2746.6]
assign _T_1953 = io_in_c_bits_param == _T_1940; // @[Monitor.scala 402:29:freechips.rocketchip.system.LowRiscConfig.fir@2751.6]
assign _T_1955 = _T_1953 | reset; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@2753.6]
assign _T_1956 = _T_1955 == 1'h0; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@2754.6]
assign _T_1957 = io_in_c_bits_size == _T_1942; // @[Monitor.scala 403:29:freechips.rocketchip.system.LowRiscConfig.fir@2759.6]
assign _T_1959 = _T_1957 | reset; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@2761.6]
assign _T_1960 = _T_1959 == 1'h0; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@2762.6]
assign _T_1961 = io_in_c_bits_source == _T_1944; // @[Monitor.scala 404:29:freechips.rocketchip.system.LowRiscConfig.fir@2767.6]
assign _T_1963 = _T_1961 | reset; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@2769.6]
assign _T_1964 = _T_1963 == 1'h0; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@2770.6]
assign _T_1965 = io_in_c_bits_address == _T_1946; // @[Monitor.scala 405:29:freechips.rocketchip.system.LowRiscConfig.fir@2775.6]
assign _T_1967 = _T_1965 | reset; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@2777.6]
assign _T_1968 = _T_1967 == 1'h0; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@2778.6]
assign _T_1970 = _T_1916 & _T_1929; // @[Monitor.scala 407:20:freechips.rocketchip.system.LowRiscConfig.fir@2785.4]
assign _T_1984 = _T_1983 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2804.4]
assign _T_1985 = $unsigned(_T_1984); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2805.4]
assign _T_1986 = _T_1985[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2806.4]
assign _T_1987 = _T_1983 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2807.4]
assign _T_2005 = _T_2004 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2827.4]
assign _T_2006 = $unsigned(_T_2005); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2828.4]
assign _T_2007 = _T_2006[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2829.4]
assign _T_2008 = _T_2004 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2830.4]
assign _T_2019 = _T_1743 & _T_1987; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@2845.4]
assign _T_2021 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2848.6]
assign _T_2022 = _T_1972 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@2850.6]
assign _T_2023 = _T_2022[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@2851.6]
assign _T_2024 = _T_2023 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@2852.6]
assign _T_2026 = _T_2024 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@2854.6]
assign _T_2027 = _T_2026 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@2855.6]
assign _GEN_27 = _T_2019 ? _T_2021 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@2847.4]
assign _T_2032 = _T_1799 & _T_2008; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@2866.4]
assign _T_2034 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@2868.4]
assign _T_2035 = _T_2032 & _T_2034; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@2869.4]
assign _T_2036 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2871.6]
assign _T_2017 = _GEN_27[8:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@2841.4 :freechips.rocketchip.system.LowRiscConfig.fir@2843.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@2849.6]
assign _T_2037 = _T_2017 | _T_1972; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@2873.6]
assign _T_2038 = _T_2037 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@2874.6]
assign _T_2039 = _T_2038[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@2875.6]
assign _T_2041 = _T_2039 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@2877.6]
assign _T_2042 = _T_2041 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@2878.6]
assign _GEN_28 = _T_2035 ? _T_2036 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@2870.4]
assign _T_2029 = _GEN_28[8:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@2861.4 :freechips.rocketchip.system.LowRiscConfig.fir@2863.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@2872.6]
assign _T_2043 = _T_2017 != _T_2029; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@2884.4]
assign _T_2044 = _T_2017 != 9'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@2885.4]
assign _T_2045 = _T_2044 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@2886.4]
assign _T_2046 = _T_2043 | _T_2045; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@2887.4]
assign _T_2048 = _T_2046 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@2889.4]
assign _T_2049 = _T_2048 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@2890.4]
assign _T_2050 = _T_1972 | _T_2017; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@2895.4]
assign _T_2051 = ~ _T_2029; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@2896.4]
assign _T_2052 = _T_2050 & _T_2051; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@2897.4]
assign _T_2055 = _T_1972 != 9'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@2902.4]
assign _T_2056 = _T_2055 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@2903.4]
assign _T_2057 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@2904.4]
assign _T_2058 = _T_2056 | _T_2057; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@2905.4]
assign _T_2059 = _T_2054 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@2906.4]
assign _T_2060 = _T_2058 | _T_2059; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@2907.4]
assign _T_2062 = _T_2060 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@2909.4]
assign _T_2063 = _T_2062 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@2910.4]
assign _T_2065 = _T_2054 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@2916.4]
assign _T_2068 = _T_1743 | _T_1799; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@2920.4]
assign _T_2081 = _T_2080 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2934.4]
assign _T_2082 = $unsigned(_T_2081); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2935.4]
assign _T_2083 = _T_2082[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@2936.4]
assign _T_2084 = _T_2080 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@2937.4]
assign _T_2095 = _T_1799 & _T_2084; // @[Monitor.scala 492:27:freechips.rocketchip.system.LowRiscConfig.fir@2952.4]
assign _T_2096 = io_in_d_bits_opcode[2]; // @[Edges.scala 71:36:freechips.rocketchip.system.LowRiscConfig.fir@2953.4]
assign _T_2097 = io_in_d_bits_opcode[1]; // @[Edges.scala 71:52:freechips.rocketchip.system.LowRiscConfig.fir@2954.4]
assign _T_2098 = _T_2097 == 1'h0; // @[Edges.scala 71:43:freechips.rocketchip.system.LowRiscConfig.fir@2955.4]
assign _T_2099 = _T_2096 & _T_2098; // @[Edges.scala 71:40:freechips.rocketchip.system.LowRiscConfig.fir@2956.4]
assign _T_2100 = _T_2095 & _T_2099; // @[Monitor.scala 492:38:freechips.rocketchip.system.LowRiscConfig.fir@2957.4]
assign _T_2101 = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2959.6]
assign _T_2102 = _T_2070 >> io_in_d_bits_sink; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@2961.6]
assign _T_2103 = _T_2102[0]; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@2962.6]
assign _T_2104 = _T_2103 == 1'h0; // @[Monitor.scala 494:14:freechips.rocketchip.system.LowRiscConfig.fir@2963.6]
assign _T_2106 = _T_2104 | reset; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@2965.6]
assign _T_2107 = _T_2106 == 1'h0; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@2966.6]
assign _GEN_31 = _T_2100 ? _T_2101 : 4'h0; // @[Monitor.scala 492:72:freechips.rocketchip.system.LowRiscConfig.fir@2958.4]
assign _T_2113 = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@2979.6]
assign _T_2114 = _GEN_31 | _T_2070; // @[Monitor.scala 500:21:freechips.rocketchip.system.LowRiscConfig.fir@2981.6]
assign _T_2115 = _T_2114 >> io_in_e_bits_sink; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@2982.6]
assign _T_2116 = _T_2115[0]; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@2983.6]
assign _T_2118 = _T_2116 | reset; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@2985.6]
assign _T_2119 = _T_2118 == 1'h0; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@2986.6]
assign _GEN_32 = io_in_e_valid ? _T_2113 : 4'h0; // @[Monitor.scala 498:73:freechips.rocketchip.system.LowRiscConfig.fir@2978.4]
assign _T_2120 = _T_2070 | _GEN_31; // @[Monitor.scala 505:27:freechips.rocketchip.system.LowRiscConfig.fir@2992.4]
assign _T_2121 = ~ _GEN_32; // @[Monitor.scala 505:38:freechips.rocketchip.system.LowRiscConfig.fir@2993.4]
assign _T_2122 = _T_2120 & _T_2121; // @[Monitor.scala 505:36:freechips.rocketchip.system.LowRiscConfig.fir@2994.4]
assign _GEN_36 = io_in_a_valid & _T_147; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@229.10]
assign _GEN_52 = io_in_a_valid & _T_254; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@365.10]
assign _GEN_70 = io_in_a_valid & _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@512.10]
assign _GEN_82 = io_in_a_valid & _T_439; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@619.10]
assign _GEN_92 = io_in_a_valid & _T_516; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@718.10]
assign _GEN_102 = io_in_a_valid & _T_595; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@809.10]
assign _GEN_112 = io_in_a_valid & _T_662; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@898.10]
assign _GEN_122 = io_in_a_valid & _T_729; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@987.10]
assign _GEN_132 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1055.10]
assign _GEN_142 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@1097.10]
assign _GEN_152 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@1155.10]
assign _GEN_162 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@1214.10]
assign _GEN_168 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@1249.10]
assign _GEN_174 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@1285.10]
assign _GEN_180 = io_in_c_valid & _T_1449; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2006.10]
assign _GEN_192 = io_in_c_valid & _T_1471; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@2054.10]
assign _GEN_202 = io_in_c_valid & _T_1489; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2143.10]
assign _GEN_216 = io_in_c_valid & _T_1591; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@2270.10]
assign _GEN_228 = io_in_c_valid & _T_1689; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@2340.10]
assign _GEN_238 = io_in_c_valid & _T_1707; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@2380.10]
assign _GEN_246 = io_in_c_valid & _T_1721; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@2412.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1753 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1766 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1768 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1770 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_1772 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_1774 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1808 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1821 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1823 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1825 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1827 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1829 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1831 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1870 = _RAND_13[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1885 = _RAND_14[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1891 = _RAND_15[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1925 = _RAND_16[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_1938 = _RAND_17[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_1940 = _RAND_18[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_1942 = _RAND_19[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_1944 = _RAND_20[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_1946 = _RAND_21[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_22 = {1{`RANDOM}};
_T_1972 = _RAND_22[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_23 = {1{`RANDOM}};
_T_1983 = _RAND_23[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_24 = {1{`RANDOM}};
_T_2004 = _RAND_24[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_25 = {1{`RANDOM}};
_T_2054 = _RAND_25[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_26 = {1{`RANDOM}};
_T_2070 = _RAND_26[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_27 = {1{`RANDOM}};
_T_2080 = _RAND_27[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_1753 <= 9'h0;
end else begin
if (_T_1743) begin
if (_T_1757) begin
if (_T_1750) begin
_T_1753 <= _T_1748;
end else begin
_T_1753 <= 9'h0;
end
end else begin
_T_1753 <= _T_1756;
end
end
end
if (_T_1798) begin
_T_1766 <= io_in_a_bits_opcode;
end
if (_T_1798) begin
_T_1768 <= io_in_a_bits_param;
end
if (_T_1798) begin
_T_1770 <= io_in_a_bits_size;
end
if (_T_1798) begin
_T_1772 <= io_in_a_bits_source;
end
if (_T_1798) begin
_T_1774 <= io_in_a_bits_address;
end
if (reset) begin
_T_1808 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_1812) begin
if (_T_1805) begin
_T_1808 <= _T_1804;
end else begin
_T_1808 <= 9'h0;
end
end else begin
_T_1808 <= _T_1811;
end
end
end
if (_T_1859) begin
_T_1821 <= io_in_d_bits_opcode;
end
if (_T_1859) begin
_T_1823 <= io_in_d_bits_param;
end
if (_T_1859) begin
_T_1825 <= io_in_d_bits_size;
end
if (_T_1859) begin
_T_1827 <= io_in_d_bits_source;
end
if (_T_1859) begin
_T_1829 <= io_in_d_bits_sink;
end
if (_T_1859) begin
_T_1831 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1870 <= 9'h0;
end else begin
if (_T_1860) begin
if (_T_1874) begin
_T_1870 <= 9'h0;
end else begin
_T_1870 <= _T_1873;
end
end
end
if (_T_1915) begin
_T_1885 <= io_in_b_bits_param;
end
if (_T_1915) begin
_T_1891 <= io_in_b_bits_address;
end
if (reset) begin
_T_1925 <= 9'h0;
end else begin
if (_T_1916) begin
if (_T_1929) begin
if (_T_1922) begin
_T_1925 <= _T_1921;
end else begin
_T_1925 <= 9'h0;
end
end else begin
_T_1925 <= _T_1928;
end
end
end
if (_T_1970) begin
_T_1938 <= io_in_c_bits_opcode;
end
if (_T_1970) begin
_T_1940 <= io_in_c_bits_param;
end
if (_T_1970) begin
_T_1942 <= io_in_c_bits_size;
end
if (_T_1970) begin
_T_1944 <= io_in_c_bits_source;
end
if (_T_1970) begin
_T_1946 <= io_in_c_bits_address;
end
if (reset) begin
_T_1972 <= 9'h0;
end else begin
_T_1972 <= _T_2052;
end
if (reset) begin
_T_1983 <= 9'h0;
end else begin
if (_T_1743) begin
if (_T_1987) begin
if (_T_1750) begin
_T_1983 <= _T_1748;
end else begin
_T_1983 <= 9'h0;
end
end else begin
_T_1983 <= _T_1986;
end
end
end
if (reset) begin
_T_2004 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_2008) begin
if (_T_1805) begin
_T_2004 <= _T_1804;
end else begin
_T_2004 <= 9'h0;
end
end else begin
_T_2004 <= _T_2007;
end
end
end
if (reset) begin
_T_2054 <= 32'h0;
end else begin
if (_T_2068) begin
_T_2054 <= 32'h0;
end else begin
_T_2054 <= _T_2065;
end
end
if (reset) begin
_T_2070 <= 4'h0;
end else begin
_T_2070 <= _T_2122;
end
if (reset) begin
_T_2080 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_2084) begin
if (_T_1805) begin
_T_2080 <= _T_1804;
end else begin
_T_2080 <= 9'h0;
end
end else begin
_T_2080 <= _T_2083;
end
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at SystemBus.scala:32:18)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@44.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@45.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@171.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@172.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_199) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@229.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_199) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@230.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_230) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:32:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@259.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_230) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@260.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@266.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_233) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@267.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_237) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@274.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_237) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@275.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@281.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_240) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@282.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_244) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:32:18)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@289.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_244) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@290.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_249) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@298.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_249) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@299.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@306.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_253) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@307.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_199) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@365.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_199) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@366.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_230) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:32:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@395.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_230) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@396.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@402.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_233) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@403.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_237) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@410.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_237) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@411.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@417.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_240) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@418.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_244) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:32:18)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@425.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_244) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@426.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_355) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:32:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@433.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_355) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@434.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_249) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@442.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_249) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@443.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@450.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_253) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@451.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_420) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@512.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_420) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@513.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@519.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_233) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@520.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@526.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_240) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@527.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@534.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_430) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@535.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@542.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_434) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@543.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@550.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_253) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@551.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_501) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@619.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_501) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@620.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@626.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_233) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@627.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@633.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_240) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@634.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@641.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_430) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@642.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@649.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_434) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@650.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_501) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@718.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_501) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@719.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@725.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_233) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@726.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@732.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_240) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@733.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@740.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_430) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@741.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_594) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_594) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_647) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@809.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_647) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@810.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@816.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_233) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@817.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@823.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_240) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@824.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_657) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:32:18)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@831.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_657) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@832.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@839.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_434) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@840.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_647) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@898.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_647) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@899.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@905.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_233) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@906.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@912.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_240) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@913.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_724) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:32:18)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_724) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@928.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_434) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@929.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_781) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@987.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_781) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@988.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@994.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_233) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@995.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@1001.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_240) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@1002.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@1009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_434) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@1010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@1017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_253) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@1018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_799) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:32:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@1028.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_799) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@1029.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1055.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@1056.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@1063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@1064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@1071.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@1072.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@1079.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@1080.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:32:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@1087.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@1088.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@1097.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@1098.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@1104.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@1105.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@1112.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@1113.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:32:18)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@1120.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@1121.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:32:18)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@1128.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@1129.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@1136.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@1137.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at SystemBus.scala:32:18)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@1145.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@1146.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@1155.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@1156.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@1162.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@1163.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@1170.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@1171.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:32:18)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@1178.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@1179.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:32:18)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@1186.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@1187.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@1195.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@1196.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at SystemBus.scala:32:18)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@1204.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@1205.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@1214.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@1215.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@1222.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@1223.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@1230.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@1231.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at SystemBus.scala:32:18)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@1239.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@1240.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@1249.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@1250.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@1257.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@1258.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@1266.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@1267.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at SystemBus.scala:32:18)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@1275.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@1276.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@1285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@1286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@1293.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@1294.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@1301.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@1302.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at SystemBus.scala:32:18)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@1310.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@1311.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel has invalid opcode (connected at SystemBus.scala:32:18)\n at Monitor.scala:122 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 122:12:freechips.rocketchip.system.LowRiscConfig.fir@1321.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 122:12:freechips.rocketchip.system.LowRiscConfig.fir@1322.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:124 assert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 124:12:freechips.rocketchip.system.LowRiscConfig.fir@1361.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 124:12:freechips.rocketchip.system.LowRiscConfig.fir@1362.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Probe type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:133 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n"); // @[Monitor.scala 133:14:freechips.rocketchip.system.LowRiscConfig.fir@1536.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 133:14:freechips.rocketchip.system.LowRiscConfig.fir@1537.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1177) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:134 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n"); // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@1543.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1177) begin
$fatal; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@1544.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:135 assert (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n"); // @[Monitor.scala 135:14:freechips.rocketchip.system.LowRiscConfig.fir@1550.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 135:14:freechips.rocketchip.system.LowRiscConfig.fir@1551.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1183) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:136 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n"); // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@1557.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1183) begin
$fatal; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@1558.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1187) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries invalid cap param (connected at SystemBus.scala:32:18)\n at Monitor.scala:137 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n"); // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@1565.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1187) begin
$fatal; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@1566.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:138 assert (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n"); // @[Monitor.scala 138:14:freechips.rocketchip.system.LowRiscConfig.fir@1573.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 138:14:freechips.rocketchip.system.LowRiscConfig.fir@1574.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:139 assert (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n"); // @[Monitor.scala 139:14:freechips.rocketchip.system.LowRiscConfig.fir@1581.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 139:14:freechips.rocketchip.system.LowRiscConfig.fir@1582.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Get type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:143 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n"); // @[Monitor.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@1591.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@1592.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:144 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n"); // @[Monitor.scala 144:14:freechips.rocketchip.system.LowRiscConfig.fir@1598.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 144:14:freechips.rocketchip.system.LowRiscConfig.fir@1599.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:145 assert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n"); // @[Monitor.scala 145:14:freechips.rocketchip.system.LowRiscConfig.fir@1605.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 145:14:freechips.rocketchip.system.LowRiscConfig.fir@1606.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 146:14:freechips.rocketchip.system.LowRiscConfig.fir@1612.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 146:14:freechips.rocketchip.system.LowRiscConfig.fir@1613.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:147 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 147:14:freechips.rocketchip.system.LowRiscConfig.fir@1620.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 147:14:freechips.rocketchip.system.LowRiscConfig.fir@1621.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 148:14:freechips.rocketchip.system.LowRiscConfig.fir@1628.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 148:14:freechips.rocketchip.system.LowRiscConfig.fir@1629.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:149 assert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 149:14:freechips.rocketchip.system.LowRiscConfig.fir@1636.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 149:14:freechips.rocketchip.system.LowRiscConfig.fir@1637.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:153 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n"); // @[Monitor.scala 153:14:freechips.rocketchip.system.LowRiscConfig.fir@1646.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 153:14:freechips.rocketchip.system.LowRiscConfig.fir@1647.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:154 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n"); // @[Monitor.scala 154:14:freechips.rocketchip.system.LowRiscConfig.fir@1653.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 154:14:freechips.rocketchip.system.LowRiscConfig.fir@1654.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:155 assert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n"); // @[Monitor.scala 155:14:freechips.rocketchip.system.LowRiscConfig.fir@1660.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 155:14:freechips.rocketchip.system.LowRiscConfig.fir@1661.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:156 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 156:14:freechips.rocketchip.system.LowRiscConfig.fir@1667.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 156:14:freechips.rocketchip.system.LowRiscConfig.fir@1668.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:157 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 157:14:freechips.rocketchip.system.LowRiscConfig.fir@1675.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 157:14:freechips.rocketchip.system.LowRiscConfig.fir@1676.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:158 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 158:14:freechips.rocketchip.system.LowRiscConfig.fir@1683.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 158:14:freechips.rocketchip.system.LowRiscConfig.fir@1684.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:162 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n"); // @[Monitor.scala 162:14:freechips.rocketchip.system.LowRiscConfig.fir@1693.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 162:14:freechips.rocketchip.system.LowRiscConfig.fir@1694.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:163 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n"); // @[Monitor.scala 163:14:freechips.rocketchip.system.LowRiscConfig.fir@1700.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 163:14:freechips.rocketchip.system.LowRiscConfig.fir@1701.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:164 assert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n"); // @[Monitor.scala 164:14:freechips.rocketchip.system.LowRiscConfig.fir@1707.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 164:14:freechips.rocketchip.system.LowRiscConfig.fir@1708.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:165 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 165:14:freechips.rocketchip.system.LowRiscConfig.fir@1714.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 165:14:freechips.rocketchip.system.LowRiscConfig.fir@1715.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:166 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 166:14:freechips.rocketchip.system.LowRiscConfig.fir@1722.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 166:14:freechips.rocketchip.system.LowRiscConfig.fir@1723.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:167 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@1732.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@1733.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:171 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n"); // @[Monitor.scala 171:14:freechips.rocketchip.system.LowRiscConfig.fir@1742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 171:14:freechips.rocketchip.system.LowRiscConfig.fir@1743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:172 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n"); // @[Monitor.scala 172:14:freechips.rocketchip.system.LowRiscConfig.fir@1749.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 172:14:freechips.rocketchip.system.LowRiscConfig.fir@1750.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:173 assert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n"); // @[Monitor.scala 173:14:freechips.rocketchip.system.LowRiscConfig.fir@1756.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 173:14:freechips.rocketchip.system.LowRiscConfig.fir@1757.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:174 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 174:14:freechips.rocketchip.system.LowRiscConfig.fir@1763.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 174:14:freechips.rocketchip.system.LowRiscConfig.fir@1764.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:32:18)\n at Monitor.scala:175 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 175:14:freechips.rocketchip.system.LowRiscConfig.fir@1771.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 175:14:freechips.rocketchip.system.LowRiscConfig.fir@1772.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:176 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@1779.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@1780.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Logical type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:180 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n"); // @[Monitor.scala 180:14:freechips.rocketchip.system.LowRiscConfig.fir@1789.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 180:14:freechips.rocketchip.system.LowRiscConfig.fir@1790.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:181 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n"); // @[Monitor.scala 181:14:freechips.rocketchip.system.LowRiscConfig.fir@1796.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 181:14:freechips.rocketchip.system.LowRiscConfig.fir@1797.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:182 assert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n"); // @[Monitor.scala 182:14:freechips.rocketchip.system.LowRiscConfig.fir@1803.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 182:14:freechips.rocketchip.system.LowRiscConfig.fir@1804.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:183 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 183:14:freechips.rocketchip.system.LowRiscConfig.fir@1810.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 183:14:freechips.rocketchip.system.LowRiscConfig.fir@1811.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries invalid opcode param (connected at SystemBus.scala:32:18)\n at Monitor.scala:184 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 184:14:freechips.rocketchip.system.LowRiscConfig.fir@1818.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 184:14:freechips.rocketchip.system.LowRiscConfig.fir@1819.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:185 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 185:14:freechips.rocketchip.system.LowRiscConfig.fir@1826.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 185:14:freechips.rocketchip.system.LowRiscConfig.fir@1827.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Hint type unsupported by client (connected at SystemBus.scala:32:18)\n at Monitor.scala:189 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n"); // @[Monitor.scala 189:14:freechips.rocketchip.system.LowRiscConfig.fir@1836.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 189:14:freechips.rocketchip.system.LowRiscConfig.fir@1837.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:190 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n"); // @[Monitor.scala 190:14:freechips.rocketchip.system.LowRiscConfig.fir@1843.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 190:14:freechips.rocketchip.system.LowRiscConfig.fir@1844.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint carries source that is not first source (connected at SystemBus.scala:32:18)\n at Monitor.scala:191 assert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n"); // @[Monitor.scala 191:14:freechips.rocketchip.system.LowRiscConfig.fir@1850.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 191:14:freechips.rocketchip.system.LowRiscConfig.fir@1851.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:192 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 192:14:freechips.rocketchip.system.LowRiscConfig.fir@1857.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 192:14:freechips.rocketchip.system.LowRiscConfig.fir@1858.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint contains invalid mask (connected at SystemBus.scala:32:18)\n at Monitor.scala:193 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 193:14:freechips.rocketchip.system.LowRiscConfig.fir@1865.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 193:14:freechips.rocketchip.system.LowRiscConfig.fir@1866.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:194 assert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 194:14:freechips.rocketchip.system.LowRiscConfig.fir@1873.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 194:14:freechips.rocketchip.system.LowRiscConfig.fir@1874.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel has invalid opcode (connected at SystemBus.scala:32:18)\n at Monitor.scala:199 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 199:12:freechips.rocketchip.system.LowRiscConfig.fir@1884.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 199:12:freechips.rocketchip.system.LowRiscConfig.fir@1885.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:205 assert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 205:12:freechips.rocketchip.system.LowRiscConfig.fir@1997.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 205:12:freechips.rocketchip.system.LowRiscConfig.fir@1998.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:208 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2006.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1452) begin
$fatal; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@2007.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:209 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@2013.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1455) begin
$fatal; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@2014.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:210 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@2021.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1459) begin
$fatal; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@2022.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:211 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@2028.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1462) begin
$fatal; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@2029.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1466) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at SystemBus.scala:32:18)\n at Monitor.scala:212 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n"); // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@2036.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1466) begin
$fatal; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@2037.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:213 assert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n"); // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@2044.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1470) begin
$fatal; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@2045.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:217 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n"); // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@2054.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1452) begin
$fatal; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@2055.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:218 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 218:14:freechips.rocketchip.system.LowRiscConfig.fir@2061.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1455) begin
$fatal; // @[Monitor.scala 218:14:freechips.rocketchip.system.LowRiscConfig.fir@2062.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:219 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n"); // @[Monitor.scala 219:14:freechips.rocketchip.system.LowRiscConfig.fir@2069.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1459) begin
$fatal; // @[Monitor.scala 219:14:freechips.rocketchip.system.LowRiscConfig.fir@2070.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n"); // @[Monitor.scala 220:14:freechips.rocketchip.system.LowRiscConfig.fir@2076.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1462) begin
$fatal; // @[Monitor.scala 220:14:freechips.rocketchip.system.LowRiscConfig.fir@2077.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1466) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at SystemBus.scala:32:18)\n at Monitor.scala:221 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n"); // @[Monitor.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@2084.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1466) begin
$fatal; // @[Monitor.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@2085.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1541) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:225 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n"); // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2143.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1541) begin
$fatal; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@2144.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1572) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:32:18)\n at Monitor.scala:226 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@2173.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1572) begin
$fatal; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@2174.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:227 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n"); // @[Monitor.scala 227:14:freechips.rocketchip.system.LowRiscConfig.fir@2180.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1455) begin
$fatal; // @[Monitor.scala 227:14:freechips.rocketchip.system.LowRiscConfig.fir@2181.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:228 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n"); // @[Monitor.scala 228:14:freechips.rocketchip.system.LowRiscConfig.fir@2188.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1459) begin
$fatal; // @[Monitor.scala 228:14:freechips.rocketchip.system.LowRiscConfig.fir@2189.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:229 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n"); // @[Monitor.scala 229:14:freechips.rocketchip.system.LowRiscConfig.fir@2195.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1462) begin
$fatal; // @[Monitor.scala 229:14:freechips.rocketchip.system.LowRiscConfig.fir@2196.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1586) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release carries invalid shrink param (connected at SystemBus.scala:32:18)\n at Monitor.scala:230 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n"); // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@2203.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1586) begin
$fatal; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@2204.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:231 assert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n"); // @[Monitor.scala 231:14:freechips.rocketchip.system.LowRiscConfig.fir@2211.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1470) begin
$fatal; // @[Monitor.scala 231:14:freechips.rocketchip.system.LowRiscConfig.fir@2212.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1541) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at SystemBus.scala:32:18)\n at Monitor.scala:235 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n"); // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@2270.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1541) begin
$fatal; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@2271.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1572) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:32:18)\n at Monitor.scala:236 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 236:14:freechips.rocketchip.system.LowRiscConfig.fir@2300.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1572) begin
$fatal; // @[Monitor.scala 236:14:freechips.rocketchip.system.LowRiscConfig.fir@2301.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:237 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 237:14:freechips.rocketchip.system.LowRiscConfig.fir@2307.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1455) begin
$fatal; // @[Monitor.scala 237:14:freechips.rocketchip.system.LowRiscConfig.fir@2308.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at SystemBus.scala:32:18)\n at Monitor.scala:238 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n"); // @[Monitor.scala 238:14:freechips.rocketchip.system.LowRiscConfig.fir@2315.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1459) begin
$fatal; // @[Monitor.scala 238:14:freechips.rocketchip.system.LowRiscConfig.fir@2316.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:239 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n"); // @[Monitor.scala 239:14:freechips.rocketchip.system.LowRiscConfig.fir@2322.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1462) begin
$fatal; // @[Monitor.scala 239:14:freechips.rocketchip.system.LowRiscConfig.fir@2323.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1586) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at SystemBus.scala:32:18)\n at Monitor.scala:240 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n"); // @[Monitor.scala 240:14:freechips.rocketchip.system.LowRiscConfig.fir@2330.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1586) begin
$fatal; // @[Monitor.scala 240:14:freechips.rocketchip.system.LowRiscConfig.fir@2331.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:244 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@2340.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1452) begin
$fatal; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@2341.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:245 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 245:14:freechips.rocketchip.system.LowRiscConfig.fir@2347.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1455) begin
$fatal; // @[Monitor.scala 245:14:freechips.rocketchip.system.LowRiscConfig.fir@2348.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:246 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 246:14:freechips.rocketchip.system.LowRiscConfig.fir@2354.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1462) begin
$fatal; // @[Monitor.scala 246:14:freechips.rocketchip.system.LowRiscConfig.fir@2355.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:247 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@2362.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1702) begin
$fatal; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@2363.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:248 assert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 248:14:freechips.rocketchip.system.LowRiscConfig.fir@2370.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1470) begin
$fatal; // @[Monitor.scala 248:14:freechips.rocketchip.system.LowRiscConfig.fir@2371.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:252 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n"); // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@2380.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1452) begin
$fatal; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@2381.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:253 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 253:14:freechips.rocketchip.system.LowRiscConfig.fir@2387.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1455) begin
$fatal; // @[Monitor.scala 253:14:freechips.rocketchip.system.LowRiscConfig.fir@2388.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:254 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n"); // @[Monitor.scala 254:14:freechips.rocketchip.system.LowRiscConfig.fir@2394.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1462) begin
$fatal; // @[Monitor.scala 254:14:freechips.rocketchip.system.LowRiscConfig.fir@2395.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:255 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 255:14:freechips.rocketchip.system.LowRiscConfig.fir@2402.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1702) begin
$fatal; // @[Monitor.scala 255:14:freechips.rocketchip.system.LowRiscConfig.fir@2403.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries unmanaged address (connected at SystemBus.scala:32:18)\n at Monitor.scala:259 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@2412.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1452) begin
$fatal; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@2413.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries invalid source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:260 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 260:14:freechips.rocketchip.system.LowRiscConfig.fir@2419.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1455) begin
$fatal; // @[Monitor.scala 260:14:freechips.rocketchip.system.LowRiscConfig.fir@2420.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck address not aligned to size (connected at SystemBus.scala:32:18)\n at Monitor.scala:261 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 261:14:freechips.rocketchip.system.LowRiscConfig.fir@2426.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1462) begin
$fatal; // @[Monitor.scala 261:14:freechips.rocketchip.system.LowRiscConfig.fir@2427.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries invalid param (connected at SystemBus.scala:32:18)\n at Monitor.scala:262 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 262:14:freechips.rocketchip.system.LowRiscConfig.fir@2434.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1702) begin
$fatal; // @[Monitor.scala 262:14:freechips.rocketchip.system.LowRiscConfig.fir@2435.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck is corrupt (connected at SystemBus.scala:32:18)\n at Monitor.scala:263 assert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 263:14:freechips.rocketchip.system.LowRiscConfig.fir@2442.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1470) begin
$fatal; // @[Monitor.scala 263:14:freechips.rocketchip.system.LowRiscConfig.fir@2443.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channels carries invalid sink ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:330 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 330:12:freechips.rocketchip.system.LowRiscConfig.fir@2453.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 330:12:freechips.rocketchip.system.LowRiscConfig.fir@2454.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1780) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@2494.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1780) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@2495.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1784) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@2502.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1784) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@2503.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1788) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@2510.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1788) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@2511.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1792) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@2518.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1792) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@2519.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1796) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@2526.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1796) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@2527.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@2576.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1837) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@2577.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@2584.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1841) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@2585.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1845) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@2592.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1845) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@2593.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1849) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@2600.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1849) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@2601.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1853) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@2608.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1853) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@2609.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1857) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@2616.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1857) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@2617.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:378 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 378:14:freechips.rocketchip.system.LowRiscConfig.fir@2667.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 378:14:freechips.rocketchip.system.LowRiscConfig.fir@2668.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1893 & _T_1901) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel param changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:379 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@2675.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1893 & _T_1901) begin
$fatal; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@2676.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel size changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:380 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 380:14:freechips.rocketchip.system.LowRiscConfig.fir@2683.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 380:14:freechips.rocketchip.system.LowRiscConfig.fir@2684.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel source changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:381 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 381:14:freechips.rocketchip.system.LowRiscConfig.fir@2691.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 381:14:freechips.rocketchip.system.LowRiscConfig.fir@2692.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1893 & _T_1913) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel addresss changed with multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:382 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@2699.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1893 & _T_1913) begin
$fatal; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@2700.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1952) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:401 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@2748.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1952) begin
$fatal; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@2749.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1956) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel param changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:402 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@2756.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1956) begin
$fatal; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@2757.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1960) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel size changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:403 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@2764.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1960) begin
$fatal; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@2765.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1964) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel source changed within multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:404 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@2772.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1964) begin
$fatal; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@2773.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1968) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel address changed with multibeat operation (connected at SystemBus.scala:32:18)\n at Monitor.scala:405 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@2780.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1968) begin
$fatal; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@2781.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2019 & _T_2027) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@2857.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2019 & _T_2027) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@2858.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2035 & _T_2042) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:32:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@2880.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2035 & _T_2042) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@2881.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2049) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:32:18)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@2892.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2049) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@2893.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2063) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at SystemBus.scala:32:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@2912.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2063) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@2913.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2100 & _T_2107) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel re-used a sink ID (connected at SystemBus.scala:32:18)\n at Monitor.scala:494 assert(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n"); // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@2968.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2100 & _T_2107) begin
$fatal; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@2969.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_e_valid & _T_2119) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel acknowledged for nothing inflight (connected at SystemBus.scala:32:18)\n at Monitor.scala:500 assert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@2988.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_e_valid & _T_2119) begin
$fatal; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@2989.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@3004.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3005.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3006.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@3007.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@4554.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@3024.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@3025.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@3042.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@3044.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@3045.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@3046.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@3047.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@3047.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@3048.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@3050.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@3051.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@3052.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@3053.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@3054.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@3055.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@3056.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@3057.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3059.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3060.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3062.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3063.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@3064.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@3065.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@3066.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3067.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3068.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3069.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3070.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3071.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3072.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3073.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3074.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3075.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3076.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3077.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3078.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@3079.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@3080.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@3081.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3082.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3083.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3084.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3085.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3086.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3087.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3088.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3089.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3090.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3091.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3092.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3093.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3094.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3095.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3096.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3097.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3098.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3099.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3100.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3101.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3102.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3103.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3104.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3105.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@3112.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3123.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@3151.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3154.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3155.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3156.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3157.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3158.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3159.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3160.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3161.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3162.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3163.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3164.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3165.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3166.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3167.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3168.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3169.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3170.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3171.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3172.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3173.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3176.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3177.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3178.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3179.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3180.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3181.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3182.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3183.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3191.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3194.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3195.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3196.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3197.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3198.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3199.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3203.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3204.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@3211.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@3217.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@3218.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@3225.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@3226.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@3232.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@3233.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@3238.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@3240.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@3241.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@3246.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@3247.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@3249.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@3250.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@3255.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@3257.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@3258.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@3264.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@3359.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@3361.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@3362.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@3385.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3421.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3422.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3423.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3424.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3425.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3426.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3428.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3436.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@3438.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3440.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3441.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@3460.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@3462.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@3463.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@3468.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@3470.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@3471.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@3485.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3518.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3519.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3520.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3521.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3523.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3531.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@3544.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@3545.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3547.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3548.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@3584.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@3674.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@3675.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@3676.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@3678.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@3679.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@3685.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3707.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3730.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3731.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3732.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3733.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3737.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3738.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@3757.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@3759.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@3760.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@3774.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@3846.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@3848.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@3849.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@3863.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3915.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3916.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@3954.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@3956.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@3957.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@3964.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@3965.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@3982.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@3984.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3987.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3988.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@3993.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@3995.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@3996.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@4001.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@4003.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@4004.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@4009.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@4011.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@4012.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@4017.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@4019.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@4020.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@4026.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@4050.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@4052.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@4053.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@4058.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@4060.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@4061.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@4084.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@4125.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@4127.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@4128.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@4143.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@4178.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@4214.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@4274.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4279.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@4280.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@4281.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@4283.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4284.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4285.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4286.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4287.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@4298.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@4299.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@4300.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@4301.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@4302.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@4303.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@4304.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@4306.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@4308.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@4309.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@4314.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@4316.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@4317.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@4322.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@4324.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@4325.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@4330.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@4332.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@4333.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@4338.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@4340.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@4341.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@4348.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@4356.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4358.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4359.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4360.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4361.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4362.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@4364.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4365.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4366.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4367.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4368.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@4379.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@4380.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@4381.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@4382.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@4383.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@4384.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@4385.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@4386.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@4388.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@4390.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@4391.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@4396.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@4398.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@4399.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@4404.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@4406.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@4407.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@4412.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@4414.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@4415.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@4420.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@4422.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@4423.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@4428.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@4430.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@4431.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@4438.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@4447.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@4457.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4458.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4459.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4460.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4461.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@4480.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4481.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4482.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4483.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4484.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@4499.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@4502.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@4504.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@4505.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@4506.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@4508.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@4509.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@4501.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@4520.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@4522.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@4523.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@4525.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@4527.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@4528.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@4529.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@4531.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@4532.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@4524.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@4538.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@4539.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@4540.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@4541.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@4543.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@4544.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@4549.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@4550.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@4551.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@4553.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@4556.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@4557.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@4558.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@4559.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@4560.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@4561.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@4563.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@4564.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@4570.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@4574.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3206.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@3319.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3443.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3550.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@3649.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3740.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@3829.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3918.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3990.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@4032.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@4090.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@4149.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@4184.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@4220.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@4554.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@3024.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@3025.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@3042.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@3044.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@3045.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@3046.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@3047.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@3047.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@3048.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@3050.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@3051.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@3052.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@3053.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@3054.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@3055.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@3056.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@3057.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3059.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3060.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3062.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3063.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@3064.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@3065.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@3066.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3067.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3068.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3069.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3070.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3071.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3072.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3073.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3074.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3075.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3076.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3077.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3078.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@3079.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@3080.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@3081.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3082.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3083.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3084.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3085.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3086.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3087.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3088.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3089.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3090.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3091.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3092.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3093.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3094.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3095.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3096.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3097.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3098.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3099.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3100.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3101.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3102.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@3103.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@3104.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@3105.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@3112.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3123.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@3151.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3154.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3155.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3156.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3157.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3158.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3159.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3160.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3161.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3162.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3163.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3164.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3165.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3166.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3167.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3168.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3169.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3170.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3171.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3172.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3173.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3176.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3177.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3178.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3179.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3180.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3181.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3182.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3183.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3191.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@3194.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@3195.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3196.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@3197.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@3198.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3199.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3203.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3204.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@3211.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@3217.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@3218.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@3225.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@3226.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@3232.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@3233.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@3238.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@3240.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@3241.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@3246.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@3247.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@3249.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@3250.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@3255.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@3257.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@3258.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@3264.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@3359.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@3361.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@3362.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@3385.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3421.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3422.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3423.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3424.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3425.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3426.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3428.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3436.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@3438.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3440.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3441.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@3460.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@3462.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@3463.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@3468.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@3470.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@3471.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@3485.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3518.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3519.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3520.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3521.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3523.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3531.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@3544.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@3545.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3547.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3548.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@3584.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@3674.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@3675.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@3676.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@3678.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@3679.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@3685.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@3707.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3730.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3731.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@3732.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@3733.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3737.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3738.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@3757.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@3759.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@3760.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@3774.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@3846.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@3848.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@3849.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@3863.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3915.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3916.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@3954.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@3956.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@3957.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@3964.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@3965.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@3982.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@3984.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3987.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3988.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@3993.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@3995.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@3996.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@4001.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@4003.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@4004.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@4009.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@4011.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@4012.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@4017.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@4019.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@4020.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@4026.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@4050.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@4052.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@4053.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@4058.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@4060.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@4061.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@4084.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@4125.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@4127.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@4128.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@4143.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@4178.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@4214.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@4274.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4279.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@4280.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@4281.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4284.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4285.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4286.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4287.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@4303.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@4304.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@4306.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@4308.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@4309.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@4314.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@4316.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@4317.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@4322.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@4324.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@4325.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@4330.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@4332.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@4333.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@4338.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@4340.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@4341.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@4348.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@4356.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4358.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4359.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4360.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4361.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4362.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4365.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4366.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4367.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4368.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@4385.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@4386.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@4388.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@4390.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@4391.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@4396.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@4398.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@4399.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@4404.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@4406.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@4407.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@4412.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@4414.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@4415.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@4420.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@4422.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@4423.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@4428.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@4430.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@4431.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@4438.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4458.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4459.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4460.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4461.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4481.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4482.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@4483.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@4484.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@4499.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@4502.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@4504.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@4505.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@4506.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@4508.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@4509.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@4501.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@4520.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@4522.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@4523.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@4525.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@4527.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@4528.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@4529.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@4531.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@4532.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@4524.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@4538.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@4539.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@4540.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@4541.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@4543.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@4544.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@4549.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@4550.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@4551.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@4556.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@4557.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@4558.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@4559.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@4560.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@4561.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@4563.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@4564.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@4570.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@4574.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3206.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@3319.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3443.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3550.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@3649.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3740.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@3829.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3918.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3990.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@4032.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@4090.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@4149.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@4184.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@4220.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:62:9)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@3019.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@3020.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@3148.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@3149.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3206.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@3207.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:62:9)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@3213.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@3214.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@3220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@3221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@3228.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@3229.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@3235.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@3236.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@3243.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@3244.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@3252.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@3253.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@3260.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@3261.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@3319.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@3320.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:62:9)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@3326.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@3327.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@3333.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@3334.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@3341.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@3342.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@3348.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@3349.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@3356.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@3357.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:62:9)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@3364.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@3365.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@3373.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@3374.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@3381.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@3382.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3443.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@3444.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@3450.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@3451.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@3457.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@3458.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@3465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@3466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@3473.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@3474.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@3481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@3482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3550.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@3551.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@3557.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@3558.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@3564.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@3565.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@3572.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@3573.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@3580.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@3581.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@3649.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@3650.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@3656.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@3657.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@3663.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@3664.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@3671.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@3672.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@3681.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@3682.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3740.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@3741.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@3747.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@3748.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@3754.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@3755.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@3762.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@3763.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@3770.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@3771.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@3829.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@3830.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@3836.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@3837.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@3843.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@3844.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@3851.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@3852.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@3859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@3860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:62:9)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3918.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@3919.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@3925.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@3926.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:62:9)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@3932.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@3933.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:62:9)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@3940.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@3941.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@3948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@3949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:62:9)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@3959.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@3960.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3990.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@3991.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@3998.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@3999.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@4006.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@4007.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@4014.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@4015.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@4022.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@4023.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@4032.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@4033.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@4039.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@4040.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@4047.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@4048.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@4055.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@4056.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@4063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@4064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@4071.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@4072.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@4080.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@4081.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@4090.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@4091.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@4097.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@4098.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:62:9)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@4105.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@4106.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@4113.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@4114.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@4121.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@4122.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@4130.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@4131.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@4139.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@4140.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@4149.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@4150.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@4157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@4158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@4165.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@4166.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@4174.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@4175.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@4184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@4185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@4192.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@4193.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@4201.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@4202.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@4210.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@4211.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@4220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@4221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:62:9)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@4228.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@4229.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:62:9)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@4236.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@4237.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:62:9)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@4245.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@4246.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:62:9)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@4255.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@4256.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:62:9)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@4263.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@4264.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:62:9)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@4271.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@4272.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@4311.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@4312.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@4319.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@4320.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@4327.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@4328.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@4335.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@4336.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@4343.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@4344.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@4393.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@4394.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@4401.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@4402.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@4409.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@4410.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@4417.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@4418.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@4425.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@4426.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:62:9)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@4433.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@4434.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:62:9)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@4511.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@4512.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:62:9)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@4534.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@4535.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at BusWrapper.scala:62:9)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@4546.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@4547.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:62:9)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@4566.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@4567.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLXbar( // @[:freechips.rocketchip.system.LowRiscConfig.fir@4579.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4580.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4581.4]
output auto_in_1_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_1_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_in_1_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_in_1_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_in_1_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_in_1_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [31:0] auto_in_1_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [7:0] auto_in_1_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [63:0] auto_in_1_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_1_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_1_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_1_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_in_1_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [1:0] auto_in_1_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [3:0] auto_in_1_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [3:0] auto_in_1_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [1:0] auto_in_1_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_1_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [63:0] auto_in_1_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_1_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_0_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_in_0_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_in_0_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_in_0_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_in_0_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [31:0] auto_in_0_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [7:0] auto_in_0_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [63:0] auto_in_0_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_0_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [1:0] auto_in_0_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [31:0] auto_in_0_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_0_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_in_0_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_in_0_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_in_0_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_in_0_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [31:0] auto_in_0_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [63:0] auto_in_0_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_0_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_in_0_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [1:0] auto_in_0_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [3:0] auto_in_0_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [3:0] auto_in_0_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [1:0] auto_in_0_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_0_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [63:0] auto_in_0_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_in_0_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_in_0_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [1:0] auto_in_0_e_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_2_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_2_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_2_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_2_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [4:0] auto_out_2_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [31:0] auto_out_2_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [7:0] auto_out_2_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [63:0] auto_out_2_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_2_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [1:0] auto_out_2_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [31:0] auto_out_2_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_2_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_2_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_2_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_2_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [4:0] auto_out_2_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [31:0] auto_out_2_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [63:0] auto_out_2_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_2_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_out_2_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [1:0] auto_out_2_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_out_2_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [4:0] auto_out_2_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [1:0] auto_out_2_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_2_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [63:0] auto_out_2_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_2_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_2_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [1:0] auto_out_2_e_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_1_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_1_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_1_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_1_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [3:0] auto_out_1_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [4:0] auto_out_1_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [27:0] auto_out_1_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [7:0] auto_out_1_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [63:0] auto_out_1_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_1_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_1_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_1_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_out_1_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [1:0] auto_out_1_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_out_1_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [4:0] auto_out_1_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_1_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_1_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [63:0] auto_out_1_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_1_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_0_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_0_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_0_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [2:0] auto_out_0_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [3:0] auto_out_0_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [4:0] auto_out_0_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [30:0] auto_out_0_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [7:0] auto_out_0_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output [63:0] auto_out_0_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_0_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
output auto_out_0_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_0_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [2:0] auto_out_0_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [3:0] auto_out_0_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [4:0] auto_out_0_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_0_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input [63:0] auto_out_0_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
input auto_out_0_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@4582.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_b_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_b_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [1:0] TLMonitor_io_in_b_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [31:0] TLMonitor_io_in_b_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_c_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_c_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [2:0] TLMonitor_io_in_c_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [2:0] TLMonitor_io_in_c_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [3:0] TLMonitor_io_in_c_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [3:0] TLMonitor_io_in_c_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [31:0] TLMonitor_io_in_c_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_c_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_io_in_e_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire [1:0] TLMonitor_io_in_e_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
wire TLMonitor_1_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [2:0] TLMonitor_1_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [2:0] TLMonitor_1_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [3:0] TLMonitor_1_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [3:0] TLMonitor_1_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [31:0] TLMonitor_1_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [7:0] TLMonitor_1_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [2:0] TLMonitor_1_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [1:0] TLMonitor_1_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [3:0] TLMonitor_1_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [3:0] TLMonitor_1_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [1:0] TLMonitor_1_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire TLMonitor_1_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
wire [4:0] _GEN_5; // @[Xbar.scala 115:55:freechips.rocketchip.system.LowRiscConfig.fir@4679.4]
wire [4:0] in_0_a_bits_source; // @[Xbar.scala 115:55:freechips.rocketchip.system.LowRiscConfig.fir@4679.4]
wire [4:0] _GEN_6; // @[Xbar.scala 131:55:freechips.rocketchip.system.LowRiscConfig.fir@4685.4]
reg [8:0] _T_2272; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@5660.4]
reg [31:0] _RAND_0;
wire _T_2273; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5661.4]
wire requestDOI_2_0; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@4888.4]
wire _T_1678; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5165.4]
wire requestDOI_1_0; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@4872.4]
wire _T_1643; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5149.4]
wire requestDOI_0_0; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@4856.4]
wire _T_1608; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5133.4]
wire [2:0] _T_2276; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5664.4]
reg [2:0] _T_2284; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@5675.4]
reg [31:0] _RAND_1;
wire [2:0] _T_2285; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5676.4]
wire [2:0] _T_2286; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5677.4]
wire [5:0] _T_2287; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5678.4]
wire [4:0] _T_2288; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5679.4]
wire [5:0] _GEN_7; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5680.4]
wire [5:0] _T_2289; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5680.4]
wire [3:0] _T_2290; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5681.4]
wire [5:0] _GEN_8; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5682.4]
wire [5:0] _T_2291; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5682.4]
wire [4:0] _T_2293; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5684.4]
wire [5:0] _GEN_9; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5685.4]
wire [5:0] _T_2294; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5685.4]
wire [5:0] _GEN_10; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5686.4]
wire [5:0] _T_2295; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5686.4]
wire [2:0] _T_2296; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5687.4]
wire [2:0] _T_2297; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5688.4]
wire [2:0] _T_2298; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5689.4]
wire [2:0] _T_2299; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5690.4]
wire _T_2311; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5705.4]
wire _T_2323; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5713.4]
reg _T_2390_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5771.4]
reg [31:0] _RAND_2;
wire _T_2404_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5772.4]
wire [81:0] _T_2445; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5798.4]
wire [81:0] _T_2446; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5799.4]
wire _T_2312; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5706.4]
wire _T_2324; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5714.4]
reg _T_2390_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5771.4]
reg [31:0] _RAND_3;
wire _T_2404_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5772.4]
wire [1:0] out_1_d_bits_sink; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@4703.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@4720.4 Xbar.scala 181:28:freechips.rocketchip.system.LowRiscConfig.fir@4722.4]
wire [81:0] _T_2453; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5806.4]
wire [81:0] _T_2454; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5807.4]
wire [81:0] _T_2463; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5816.4]
wire _T_2313; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5707.4]
wire _T_2325; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5715.4]
reg _T_2390_2; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5771.4]
reg [31:0] _RAND_4;
wire _T_2404_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5772.4]
wire [3:0] out_2_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@4703.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@4728.4]
wire [81:0] _T_2461; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5814.4]
wire [81:0] _T_2462; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5815.4]
wire [81:0] _T_2464; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5817.4]
wire [4:0] in_0_d_bits_source; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5829.4]
reg [8:0] _T_2478; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@5839.4]
reg [31:0] _RAND_5;
wire _T_2479; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5840.4]
wire requestDOI_2_1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@4897.4]
wire _T_1680; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5169.4]
wire requestDOI_1_1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@4881.4]
wire _T_1645; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5153.4]
wire requestDOI_0_1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@4865.4]
wire _T_1610; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5137.4]
wire [2:0] _T_2482; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5843.4]
reg [2:0] _T_2490; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@5854.4]
reg [31:0] _RAND_6;
wire [2:0] _T_2491; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5855.4]
wire [2:0] _T_2492; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5856.4]
wire [5:0] _T_2493; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5857.4]
wire [4:0] _T_2494; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5858.4]
wire [5:0] _GEN_11; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5859.4]
wire [5:0] _T_2495; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5859.4]
wire [3:0] _T_2496; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5860.4]
wire [5:0] _GEN_12; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5861.4]
wire [5:0] _T_2497; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5861.4]
wire [4:0] _T_2499; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5863.4]
wire [5:0] _GEN_13; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5864.4]
wire [5:0] _T_2500; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5864.4]
wire [5:0] _GEN_14; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5865.4]
wire [5:0] _T_2501; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5865.4]
wire [2:0] _T_2502; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5866.4]
wire [2:0] _T_2503; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5867.4]
wire [2:0] _T_2504; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5868.4]
wire [2:0] _T_2505; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5869.4]
wire _T_2517; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5884.4]
wire _T_2529; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5892.4]
reg _T_2596_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5950.4]
reg [31:0] _RAND_7;
wire _T_2610_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5951.4]
wire [81:0] _T_2652; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5978.4]
wire _T_2518; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5885.4]
wire _T_2530; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5893.4]
reg _T_2596_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5950.4]
reg [31:0] _RAND_8;
wire _T_2610_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5951.4]
wire [81:0] _T_2660; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5986.4]
wire [81:0] _T_2669; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5995.4]
wire _T_2519; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5886.4]
wire _T_2531; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5894.4]
reg _T_2596_2; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5950.4]
reg [31:0] _RAND_9;
wire _T_2610_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5951.4]
wire [81:0] _T_2668; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5994.4]
wire [81:0] _T_2670; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5996.4]
wire [4:0] in_1_d_bits_source; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@6008.4]
wire [31:0] _T_1070; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4734.4]
wire [32:0] _T_1071; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4735.4]
wire [32:0] _T_1072; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4736.4]
wire [32:0] _T_1073; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4737.4]
wire requestAIO_0_0; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4738.4]
wire [32:0] _T_1076; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4741.4]
wire [32:0] _T_1077; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4742.4]
wire [32:0] _T_1078; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4743.4]
wire requestAIO_0_1; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4744.4]
wire [31:0] _T_1080; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4746.4]
wire [32:0] _T_1081; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4747.4]
wire [32:0] _T_1082; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4748.4]
wire [32:0] _T_1083; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4749.4]
wire requestAIO_0_2; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4750.4]
wire [31:0] _T_1085; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4752.4]
wire [32:0] _T_1086; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4753.4]
wire [32:0] _T_1087; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4754.4]
wire [32:0] _T_1088; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4755.4]
wire requestAIO_1_0; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4756.4]
wire [32:0] _T_1091; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4759.4]
wire [32:0] _T_1092; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4760.4]
wire [32:0] _T_1093; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4761.4]
wire requestAIO_1_1; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4762.4]
wire [31:0] _T_1095; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4764.4]
wire [32:0] _T_1096; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4765.4]
wire [32:0] _T_1097; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4766.4]
wire [32:0] _T_1098; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4767.4]
wire requestAIO_1_2; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4768.4]
wire [26:0] _T_1229; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4919.4]
wire [11:0] _T_1230; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4920.4]
wire [11:0] _T_1231; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4921.4]
wire [8:0] _T_1232; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4922.4]
wire _T_1233; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@4923.4]
wire _T_1234; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@4924.4]
wire [8:0] beatsAI_0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4925.4]
wire [26:0] _T_1236; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4927.4]
wire [11:0] _T_1237; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4928.4]
wire [11:0] _T_1238; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4929.4]
wire [8:0] _T_1239; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4930.4]
wire _T_1240; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@4931.4]
wire _T_1241; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@4932.4]
wire [8:0] beatsAI_1; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4933.4]
wire [22:0] _T_1276; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4973.4]
wire [7:0] _T_1277; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4974.4]
wire [7:0] _T_1278; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4975.4]
wire [4:0] _T_1279; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4976.4]
wire _T_1280; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4977.4]
wire [4:0] beatsDO_0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4978.4]
wire [26:0] _T_1282; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4980.4]
wire [11:0] _T_1283; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4981.4]
wire [11:0] _T_1284; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4982.4]
wire [8:0] _T_1285; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4983.4]
wire _T_1286; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4984.4]
wire [8:0] beatsDO_1; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4985.4]
wire [20:0] _T_1288; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4987.4]
wire [5:0] _T_1289; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4988.4]
wire [5:0] _T_1290; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4989.4]
wire [2:0] _T_1291; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4990.4]
wire _T_1292; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4991.4]
wire [2:0] beatsDO_2; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4992.4]
wire _T_1326; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@4997.4]
wire _T_1328; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5001.4]
wire _T_1330; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5005.4]
reg [8:0] _T_1780; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@5221.4]
reg [31:0] _RAND_10;
wire _T_1781; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5222.4]
wire _T_1372; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5019.4]
wire [1:0] _T_1783; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5224.4]
reg [1:0] _T_1791; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@5235.4]
reg [31:0] _RAND_11;
wire [1:0] _T_1792; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5236.4]
wire [1:0] _T_1793; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5237.4]
wire [3:0] _T_1794; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5238.4]
wire [2:0] _T_1795; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5239.4]
wire [3:0] _GEN_15; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5240.4]
wire [3:0] _T_1796; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5240.4]
wire [2:0] _T_1798; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5242.4]
wire [3:0] _GEN_16; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5243.4]
wire [3:0] _T_1799; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5243.4]
wire [3:0] _GEN_17; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5244.4]
wire [3:0] _T_1800; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5244.4]
wire [1:0] _T_1801; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5245.4]
wire [1:0] _T_1802; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5246.4]
wire [1:0] _T_1803; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5247.4]
wire [1:0] _T_1804; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5248.4]
wire _T_1813; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5260.4]
reg _T_1876_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5312.4]
reg [31:0] _RAND_12;
wire _T_1895_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5315.4]
wire _T_1903; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5316.4]
wire _T_1332; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5007.4]
reg [8:0] _T_1944; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@5367.4]
reg [31:0] _RAND_13;
wire _T_1945; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5368.4]
wire _T_1374; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5023.4]
wire [1:0] _T_1947; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5370.4]
reg [1:0] _T_1955; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@5381.4]
reg [31:0] _RAND_14;
wire [1:0] _T_1956; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5382.4]
wire [1:0] _T_1957; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5383.4]
wire [3:0] _T_1958; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5384.4]
wire [2:0] _T_1959; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5385.4]
wire [3:0] _GEN_18; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5386.4]
wire [3:0] _T_1960; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5386.4]
wire [2:0] _T_1962; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5388.4]
wire [3:0] _GEN_19; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5389.4]
wire [3:0] _T_1963; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5389.4]
wire [3:0] _GEN_20; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5390.4]
wire [3:0] _T_1964; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5390.4]
wire [1:0] _T_1965; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5391.4]
wire [1:0] _T_1966; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5392.4]
wire [1:0] _T_1967; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5393.4]
wire [1:0] _T_1968; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5394.4]
wire _T_1977; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5406.4]
reg _T_2040_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5458.4]
reg [31:0] _RAND_15;
wire _T_2059_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5461.4]
wire _T_2067; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5462.4]
wire _T_1333; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5008.4]
reg [8:0] _T_2108; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@5513.4]
reg [31:0] _RAND_16;
wire _T_2109; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5514.4]
wire _T_1376; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5027.4]
wire [1:0] _T_2111; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5516.4]
reg [1:0] _T_2119; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@5527.4]
reg [31:0] _RAND_17;
wire [1:0] _T_2120; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5528.4]
wire [1:0] _T_2121; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5529.4]
wire [3:0] _T_2122; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5530.4]
wire [2:0] _T_2123; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5531.4]
wire [3:0] _GEN_21; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5532.4]
wire [3:0] _T_2124; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5532.4]
wire [2:0] _T_2126; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5534.4]
wire [3:0] _GEN_22; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5535.4]
wire [3:0] _T_2127; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5535.4]
wire [3:0] _GEN_23; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5536.4]
wire [3:0] _T_2128; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5536.4]
wire [1:0] _T_2129; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5537.4]
wire [1:0] _T_2130; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5538.4]
wire [1:0] _T_2131; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5539.4]
wire [1:0] _T_2132; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5540.4]
wire _T_2141; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5552.4]
reg _T_2204_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5604.4]
reg [31:0] _RAND_18;
wire _T_2223_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5607.4]
wire _T_2231; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5608.4]
wire _T_1334; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5009.4]
wire _T_1335; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5010.4]
wire _T_1814; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5261.4]
reg _T_1876_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5312.4]
reg [31:0] _RAND_19;
wire _T_1895_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5315.4]
wire _T_1904; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5318.4]
wire _T_1378; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5029.4]
wire _T_1978; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5407.4]
reg _T_2040_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5458.4]
reg [31:0] _RAND_20;
wire _T_2059_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5461.4]
wire _T_2068; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5464.4]
wire _T_1379; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5030.4]
wire _T_2142; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5553.4]
reg _T_2204_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@5604.4]
reg [31:0] _RAND_21;
wire _T_2223_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5607.4]
wire _T_2232; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5610.4]
wire _T_1380; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5031.4]
wire _T_1381; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5032.4]
wire _T_2414_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5774.4]
wire _T_2424; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5775.4]
wire _T_1612; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5139.4]
wire _T_2620_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5953.4]
wire _T_2630; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5954.4]
wire _T_1613; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5140.4]
wire _T_2414_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5774.4]
wire _T_2425; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5777.4]
wire _T_1647; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5155.4]
wire _T_2620_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5953.4]
wire _T_2631; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5956.4]
wire _T_1648; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5156.4]
wire _T_2414_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5774.4]
wire _T_2426; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5779.4]
wire _T_1682; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5171.4]
wire _T_2620_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5953.4]
wire _T_2632; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5958.4]
wire _T_1683; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5172.4]
wire _T_1782; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5223.4]
wire _T_1785; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5226.4]
wire _T_1787; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5228.4]
wire _T_1788; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5229.4]
wire _T_1805; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5249.4]
wire _T_1806; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5250.4]
wire [1:0] _T_1807; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5252.6]
wire [2:0] _GEN_24; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5253.6]
wire [2:0] _T_1808; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5253.6]
wire [1:0] _T_1809; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5254.6]
wire [1:0] _T_1810; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5255.6]
wire _T_1823; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5266.4]
wire _T_1824; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5267.4]
wire _T_1834; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5273.4]
wire _T_1836; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5275.4]
wire _T_1839; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5278.4]
wire _T_1840; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5279.4]
wire _T_1843; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5282.4]
wire _T_1844; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5283.4]
wire _T_1845; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5288.4]
wire _T_1846; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5289.4]
wire _T_1848; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5291.4]
wire _T_1850; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5293.4]
wire _T_1851; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5294.4]
wire [8:0] _T_1852; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5299.4]
wire [8:0] _T_1853; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5300.4]
wire [8:0] _T_1854; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5301.4]
wire _T_1907; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5321.4]
wire _T_1908; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5322.4]
wire _T_1909; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5323.4]
wire out_0_a_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5326.4]
wire _T_1855; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5302.4]
wire [8:0] _GEN_25; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5303.4]
wire [9:0] _T_1856; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5303.4]
wire [9:0] _T_1857; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5304.4]
wire [8:0] _T_1858; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5305.4]
wire _T_1887_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5313.4]
wire _T_1887_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5313.4]
wire [119:0] _T_1920; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5334.4]
wire [119:0] _T_1921; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5335.4]
wire [4:0] in_1_a_bits_source; // @[Xbar.scala 109:18:freechips.rocketchip.system.LowRiscConfig.fir@4676.4 Xbar.scala 114:17:freechips.rocketchip.system.LowRiscConfig.fir@4691.4 Xbar.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@4693.4]
wire [119:0] _T_1928; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5342.4]
wire [119:0] _T_1929; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5343.4]
wire [119:0] _T_1930; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5344.4]
wire [31:0] out_0_a_bits_address; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5354.4]
wire _T_1946; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5369.4]
wire _T_1949; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5372.4]
wire _T_1951; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5374.4]
wire _T_1952; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5375.4]
wire _T_1969; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5395.4]
wire _T_1970; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5396.4]
wire [1:0] _T_1971; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5398.6]
wire [2:0] _GEN_26; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5399.6]
wire [2:0] _T_1972; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5399.6]
wire [1:0] _T_1973; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5400.6]
wire [1:0] _T_1974; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5401.6]
wire _T_1987; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5412.4]
wire _T_1988; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5413.4]
wire _T_1998; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5419.4]
wire _T_2000; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5421.4]
wire _T_2003; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5424.4]
wire _T_2004; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5425.4]
wire _T_2007; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5428.4]
wire _T_2008; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5429.4]
wire _T_2009; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5434.4]
wire _T_2010; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5435.4]
wire _T_2012; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5437.4]
wire _T_2014; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5439.4]
wire _T_2015; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5440.4]
wire [8:0] _T_2016; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5445.4]
wire [8:0] _T_2017; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5446.4]
wire [8:0] _T_2018; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5447.4]
wire _T_2071; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5467.4]
wire _T_2072; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5468.4]
wire _T_2073; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5469.4]
wire out_1_a_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5472.4]
wire _T_2019; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5448.4]
wire [8:0] _GEN_27; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5449.4]
wire [9:0] _T_2020; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5449.4]
wire [9:0] _T_2021; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5450.4]
wire [8:0] _T_2022; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5451.4]
wire _T_2051_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5459.4]
wire _T_2051_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5459.4]
wire [119:0] _T_2085; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5481.4]
wire [119:0] _T_2093; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5489.4]
wire [119:0] _T_2094; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5490.4]
wire [31:0] out_1_a_bits_address; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5500.4]
wire _T_2110; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5515.4]
wire _T_2113; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5518.4]
wire _T_2115; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5520.4]
wire _T_2116; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5521.4]
wire _T_2133; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5541.4]
wire _T_2134; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5542.4]
wire [1:0] _T_2135; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5544.6]
wire [2:0] _GEN_28; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5545.6]
wire [2:0] _T_2136; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5545.6]
wire [1:0] _T_2137; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5546.6]
wire [1:0] _T_2138; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5547.6]
wire _T_2151; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5558.4]
wire _T_2152; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5559.4]
wire _T_2162; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5565.4]
wire _T_2164; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5567.4]
wire _T_2167; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5570.4]
wire _T_2168; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5571.4]
wire _T_2171; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5574.4]
wire _T_2172; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5575.4]
wire _T_2173; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5580.4]
wire _T_2174; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5581.4]
wire _T_2176; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5583.4]
wire _T_2178; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5585.4]
wire _T_2179; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5586.4]
wire [8:0] _T_2180; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5591.4]
wire [8:0] _T_2181; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5592.4]
wire [8:0] _T_2182; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5593.4]
wire _T_2235; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5613.4]
wire _T_2236; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5614.4]
wire _T_2237; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5615.4]
wire out_2_a_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5618.4]
wire _T_2183; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5594.4]
wire [8:0] _GEN_29; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5595.4]
wire [9:0] _T_2184; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5595.4]
wire [9:0] _T_2185; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5596.4]
wire [8:0] _T_2186; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5597.4]
wire _T_2215_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5605.4]
wire _T_2215_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5605.4]
wire [119:0] _T_2249; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5627.4]
wire [119:0] _T_2257; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5635.4]
wire [119:0] _T_2258; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5636.4]
wire [3:0] out_2_a_bits_size; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5650.4]
wire _T_2274; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5662.4]
wire _T_2278; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5666.4]
wire _T_2280; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5668.4]
wire _T_2281; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5669.4]
wire _T_2300; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5691.4]
wire _T_2301; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5692.4]
wire [2:0] _T_2302; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5694.6]
wire [3:0] _GEN_30; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5695.6]
wire [3:0] _T_2303; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5695.6]
wire [2:0] _T_2304; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5696.6]
wire [2:0] _T_2305; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5697.6]
wire [4:0] _GEN_31; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5698.6]
wire [4:0] _T_2306; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5698.6]
wire [2:0] _T_2307; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5699.6]
wire [2:0] _T_2308; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5700.6]
wire _T_2336; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5722.4]
wire _T_2337; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5723.4]
wire _T_2339; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5725.4]
wire _T_2342; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5728.4]
wire _T_2343; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5729.4]
wire _T_2344; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@5730.4]
wire _T_2345; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5731.4]
wire _T_2346; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5732.4]
wire _T_2348; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@5734.4]
wire _T_2350; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5736.4]
wire _T_2351; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5737.4]
wire _T_2352; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5742.4]
wire _T_2353; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5743.4]
wire _T_2354; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5744.4]
wire _T_2357; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5747.4]
wire _T_2359; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5749.4]
wire _T_2360; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5750.4]
wire [4:0] _T_2361; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5755.4]
wire [8:0] _T_2362; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5756.4]
wire [2:0] _T_2363; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5757.4]
wire [8:0] _GEN_32; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5758.4]
wire [8:0] _T_2364; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5758.4]
wire [8:0] _GEN_33; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5759.4]
wire [8:0] _T_2365; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5759.4]
wire _T_2430; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5783.4]
wire _T_2431; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5784.4]
wire _T_2433; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5786.4]
wire _T_2432; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5785.4]
wire _T_2434; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5787.4]
wire in_0_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5790.4]
wire _T_2366; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5760.4]
wire [8:0] _GEN_34; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5761.4]
wire [9:0] _T_2367; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5761.4]
wire [9:0] _T_2368; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5762.4]
wire [8:0] _T_2369; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5763.4]
wire _T_2480; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5841.4]
wire _T_2484; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5845.4]
wire _T_2486; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5847.4]
wire _T_2487; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5848.4]
wire _T_2506; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5870.4]
wire _T_2507; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5871.4]
wire [2:0] _T_2508; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5873.6]
wire [3:0] _GEN_35; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5874.6]
wire [3:0] _T_2509; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5874.6]
wire [2:0] _T_2510; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5875.6]
wire [2:0] _T_2511; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5876.6]
wire [4:0] _GEN_36; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5877.6]
wire [4:0] _T_2512; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5877.6]
wire [2:0] _T_2513; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5878.6]
wire [2:0] _T_2514; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5879.6]
wire _T_2542; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5901.4]
wire _T_2543; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5902.4]
wire _T_2545; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5904.4]
wire _T_2548; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5907.4]
wire _T_2549; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5908.4]
wire _T_2550; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@5909.4]
wire _T_2551; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5910.4]
wire _T_2552; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5911.4]
wire _T_2554; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@5913.4]
wire _T_2556; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5915.4]
wire _T_2557; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5916.4]
wire _T_2558; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5921.4]
wire _T_2559; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5922.4]
wire _T_2560; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5923.4]
wire _T_2563; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5926.4]
wire _T_2565; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5928.4]
wire _T_2566; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5929.4]
wire [4:0] _T_2567; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5934.4]
wire [8:0] _T_2568; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5935.4]
wire [2:0] _T_2569; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5936.4]
wire [8:0] _GEN_37; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5937.4]
wire [8:0] _T_2570; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5937.4]
wire [8:0] _GEN_38; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5938.4]
wire [8:0] _T_2571; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5938.4]
wire _T_2636; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5962.4]
wire _T_2637; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5963.4]
wire _T_2639; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5965.4]
wire _T_2638; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5964.4]
wire _T_2640; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5966.4]
wire in_1_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5969.4]
wire _T_2572; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5939.4]
wire [8:0] _GEN_39; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5940.4]
wire [9:0] _T_2573; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5940.4]
wire [9:0] _T_2574; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5941.4]
wire [8:0] _T_2575; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5942.4]
TLMonitor TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4591.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_b_ready(TLMonitor_io_in_b_ready),
.io_in_b_valid(TLMonitor_io_in_b_valid),
.io_in_b_bits_param(TLMonitor_io_in_b_bits_param),
.io_in_b_bits_address(TLMonitor_io_in_b_bits_address),
.io_in_c_ready(TLMonitor_io_in_c_ready),
.io_in_c_valid(TLMonitor_io_in_c_valid),
.io_in_c_bits_opcode(TLMonitor_io_in_c_bits_opcode),
.io_in_c_bits_param(TLMonitor_io_in_c_bits_param),
.io_in_c_bits_size(TLMonitor_io_in_c_bits_size),
.io_in_c_bits_source(TLMonitor_io_in_c_bits_source),
.io_in_c_bits_address(TLMonitor_io_in_c_bits_address),
.io_in_c_bits_corrupt(TLMonitor_io_in_c_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt),
.io_in_e_valid(TLMonitor_io_in_e_valid),
.io_in_e_bits_sink(TLMonitor_io_in_e_bits_sink)
);
TLMonitor_1 TLMonitor_1 ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@4628.4]
.clock(TLMonitor_1_clock),
.reset(TLMonitor_1_reset),
.io_in_a_ready(TLMonitor_1_io_in_a_ready),
.io_in_a_valid(TLMonitor_1_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_1_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_1_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_1_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_1_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_1_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_1_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_1_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_1_io_in_d_ready),
.io_in_d_valid(TLMonitor_1_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_1_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_1_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_1_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_1_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_1_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_1_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_1_io_in_d_bits_corrupt)
);
assign _GEN_5 = {{1'd0}, auto_in_0_a_bits_source}; // @[Xbar.scala 115:55:freechips.rocketchip.system.LowRiscConfig.fir@4679.4]
assign in_0_a_bits_source = _GEN_5 | 5'h10; // @[Xbar.scala 115:55:freechips.rocketchip.system.LowRiscConfig.fir@4679.4]
assign _GEN_6 = {{1'd0}, auto_in_0_c_bits_source}; // @[Xbar.scala 131:55:freechips.rocketchip.system.LowRiscConfig.fir@4685.4]
assign _T_2273 = _T_2272 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5661.4]
assign requestDOI_2_0 = auto_out_2_d_bits_source[4:4]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@4888.4]
assign _T_1678 = auto_out_2_d_valid & requestDOI_2_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5165.4]
assign requestDOI_1_0 = auto_out_1_d_bits_source[4:4]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@4872.4]
assign _T_1643 = auto_out_1_d_valid & requestDOI_1_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5149.4]
assign requestDOI_0_0 = auto_out_0_d_bits_source[4:4]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@4856.4]
assign _T_1608 = auto_out_0_d_valid & requestDOI_0_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5133.4]
assign _T_2276 = {_T_1678,_T_1643,_T_1608}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5664.4]
assign _T_2285 = ~ _T_2284; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5676.4]
assign _T_2286 = _T_2276 & _T_2285; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5677.4]
assign _T_2287 = {_T_2286,_T_1678,_T_1643,_T_1608}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5678.4]
assign _T_2288 = _T_2287[5:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5679.4]
assign _GEN_7 = {{1'd0}, _T_2288}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5680.4]
assign _T_2289 = _T_2287 | _GEN_7; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5680.4]
assign _T_2290 = _T_2289[5:2]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5681.4]
assign _GEN_8 = {{2'd0}, _T_2290}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5682.4]
assign _T_2291 = _T_2289 | _GEN_8; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5682.4]
assign _T_2293 = _T_2291[5:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5684.4]
assign _GEN_9 = {{3'd0}, _T_2284}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5685.4]
assign _T_2294 = _GEN_9 << 3; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5685.4]
assign _GEN_10 = {{1'd0}, _T_2293}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5686.4]
assign _T_2295 = _GEN_10 | _T_2294; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5686.4]
assign _T_2296 = _T_2295[5:3]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5687.4]
assign _T_2297 = _T_2295[2:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5688.4]
assign _T_2298 = _T_2296 & _T_2297; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5689.4]
assign _T_2299 = ~ _T_2298; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5690.4]
assign _T_2311 = _T_2299[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5705.4]
assign _T_2323 = _T_2311 & _T_1608; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5713.4]
assign _T_2404_0 = _T_2273 ? _T_2323 : _T_2390_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5772.4]
assign _T_2445 = {auto_out_0_d_bits_opcode,2'h0,auto_out_0_d_bits_size,auto_out_0_d_bits_source,2'h0,auto_out_0_d_bits_denied,auto_out_0_d_bits_data,auto_out_0_d_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5798.4]
assign _T_2446 = _T_2404_0 ? _T_2445 : 82'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5799.4]
assign _T_2312 = _T_2299[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5706.4]
assign _T_2324 = _T_2312 & _T_1643; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5714.4]
assign _T_2404_1 = _T_2273 ? _T_2324 : _T_2390_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5772.4]
assign out_1_d_bits_sink = {{1'd0}, auto_out_1_d_bits_sink}; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@4703.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@4720.4 Xbar.scala 181:28:freechips.rocketchip.system.LowRiscConfig.fir@4722.4]
assign _T_2453 = {auto_out_1_d_bits_opcode,auto_out_1_d_bits_param,auto_out_1_d_bits_size,auto_out_1_d_bits_source,out_1_d_bits_sink,auto_out_1_d_bits_denied,auto_out_1_d_bits_data,auto_out_1_d_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5806.4]
assign _T_2454 = _T_2404_1 ? _T_2453 : 82'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5807.4]
assign _T_2463 = _T_2446 | _T_2454; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5816.4]
assign _T_2313 = _T_2299[2]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5707.4]
assign _T_2325 = _T_2313 & _T_1678; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5715.4]
assign _T_2404_2 = _T_2273 ? _T_2325 : _T_2390_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5772.4]
assign out_2_d_bits_size = {{1'd0}, auto_out_2_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@4703.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@4728.4]
assign _T_2461 = {auto_out_2_d_bits_opcode,auto_out_2_d_bits_param,out_2_d_bits_size,auto_out_2_d_bits_source,auto_out_2_d_bits_sink,auto_out_2_d_bits_denied,auto_out_2_d_bits_data,auto_out_2_d_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5814.4]
assign _T_2462 = _T_2404_2 ? _T_2461 : 82'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5815.4]
assign _T_2464 = _T_2463 | _T_2462; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5817.4]
assign in_0_d_bits_source = _T_2464[72:68]; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5829.4]
assign _T_2479 = _T_2478 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5840.4]
assign requestDOI_2_1 = requestDOI_2_0 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@4897.4]
assign _T_1680 = auto_out_2_d_valid & requestDOI_2_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5169.4]
assign requestDOI_1_1 = requestDOI_1_0 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@4881.4]
assign _T_1645 = auto_out_1_d_valid & requestDOI_1_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5153.4]
assign requestDOI_0_1 = requestDOI_0_0 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@4865.4]
assign _T_1610 = auto_out_0_d_valid & requestDOI_0_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5137.4]
assign _T_2482 = {_T_1680,_T_1645,_T_1610}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5843.4]
assign _T_2491 = ~ _T_2490; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5855.4]
assign _T_2492 = _T_2482 & _T_2491; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5856.4]
assign _T_2493 = {_T_2492,_T_1680,_T_1645,_T_1610}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5857.4]
assign _T_2494 = _T_2493[5:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5858.4]
assign _GEN_11 = {{1'd0}, _T_2494}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5859.4]
assign _T_2495 = _T_2493 | _GEN_11; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5859.4]
assign _T_2496 = _T_2495[5:2]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5860.4]
assign _GEN_12 = {{2'd0}, _T_2496}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5861.4]
assign _T_2497 = _T_2495 | _GEN_12; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5861.4]
assign _T_2499 = _T_2497[5:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5863.4]
assign _GEN_13 = {{3'd0}, _T_2490}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5864.4]
assign _T_2500 = _GEN_13 << 3; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5864.4]
assign _GEN_14 = {{1'd0}, _T_2499}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5865.4]
assign _T_2501 = _GEN_14 | _T_2500; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5865.4]
assign _T_2502 = _T_2501[5:3]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5866.4]
assign _T_2503 = _T_2501[2:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5867.4]
assign _T_2504 = _T_2502 & _T_2503; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5868.4]
assign _T_2505 = ~ _T_2504; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5869.4]
assign _T_2517 = _T_2505[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5884.4]
assign _T_2529 = _T_2517 & _T_1610; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5892.4]
assign _T_2610_0 = _T_2479 ? _T_2529 : _T_2596_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5951.4]
assign _T_2652 = _T_2610_0 ? _T_2445 : 82'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5978.4]
assign _T_2518 = _T_2505[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5885.4]
assign _T_2530 = _T_2518 & _T_1645; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5893.4]
assign _T_2610_1 = _T_2479 ? _T_2530 : _T_2596_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5951.4]
assign _T_2660 = _T_2610_1 ? _T_2453 : 82'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5986.4]
assign _T_2669 = _T_2652 | _T_2660; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5995.4]
assign _T_2519 = _T_2505[2]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5886.4]
assign _T_2531 = _T_2519 & _T_1680; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5894.4]
assign _T_2610_2 = _T_2479 ? _T_2531 : _T_2596_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5951.4]
assign _T_2668 = _T_2610_2 ? _T_2461 : 82'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5994.4]
assign _T_2670 = _T_2669 | _T_2668; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5996.4]
assign in_1_d_bits_source = _T_2670[72:68]; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@6008.4]
assign _T_1070 = auto_in_0_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4734.4]
assign _T_1071 = {1'b0,$signed(_T_1070)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4735.4]
assign _T_1072 = $signed(_T_1071) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4736.4]
assign _T_1073 = $signed(_T_1072); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4737.4]
assign requestAIO_0_0 = $signed(_T_1073) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4738.4]
assign _T_1076 = {1'b0,$signed(auto_in_0_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4741.4]
assign _T_1077 = $signed(_T_1076) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4742.4]
assign _T_1078 = $signed(_T_1077); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4743.4]
assign requestAIO_0_1 = $signed(_T_1078) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4744.4]
assign _T_1080 = auto_in_0_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4746.4]
assign _T_1081 = {1'b0,$signed(_T_1080)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4747.4]
assign _T_1082 = $signed(_T_1081) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4748.4]
assign _T_1083 = $signed(_T_1082); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4749.4]
assign requestAIO_0_2 = $signed(_T_1083) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4750.4]
assign _T_1085 = auto_in_1_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4752.4]
assign _T_1086 = {1'b0,$signed(_T_1085)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4753.4]
assign _T_1087 = $signed(_T_1086) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4754.4]
assign _T_1088 = $signed(_T_1087); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4755.4]
assign requestAIO_1_0 = $signed(_T_1088) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4756.4]
assign _T_1091 = {1'b0,$signed(auto_in_1_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4759.4]
assign _T_1092 = $signed(_T_1091) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4760.4]
assign _T_1093 = $signed(_T_1092); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4761.4]
assign requestAIO_1_1 = $signed(_T_1093) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4762.4]
assign _T_1095 = auto_in_1_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@4764.4]
assign _T_1096 = {1'b0,$signed(_T_1095)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@4765.4]
assign _T_1097 = $signed(_T_1096) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4766.4]
assign _T_1098 = $signed(_T_1097); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@4767.4]
assign requestAIO_1_2 = $signed(_T_1098) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@4768.4]
assign _T_1229 = 27'hfff << auto_in_0_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4919.4]
assign _T_1230 = _T_1229[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4920.4]
assign _T_1231 = ~ _T_1230; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4921.4]
assign _T_1232 = _T_1231[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4922.4]
assign _T_1233 = auto_in_0_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@4923.4]
assign _T_1234 = _T_1233 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@4924.4]
assign beatsAI_0 = _T_1234 ? _T_1232 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4925.4]
assign _T_1236 = 27'hfff << auto_in_1_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4927.4]
assign _T_1237 = _T_1236[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4928.4]
assign _T_1238 = ~ _T_1237; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4929.4]
assign _T_1239 = _T_1238[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4930.4]
assign _T_1240 = auto_in_1_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@4931.4]
assign _T_1241 = _T_1240 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@4932.4]
assign beatsAI_1 = _T_1241 ? _T_1239 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4933.4]
assign _T_1276 = 23'hff << auto_out_0_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4973.4]
assign _T_1277 = _T_1276[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4974.4]
assign _T_1278 = ~ _T_1277; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4975.4]
assign _T_1279 = _T_1278[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4976.4]
assign _T_1280 = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4977.4]
assign beatsDO_0 = _T_1280 ? _T_1279 : 5'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4978.4]
assign _T_1282 = 27'hfff << auto_out_1_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4980.4]
assign _T_1283 = _T_1282[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4981.4]
assign _T_1284 = ~ _T_1283; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4982.4]
assign _T_1285 = _T_1284[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4983.4]
assign _T_1286 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4984.4]
assign beatsDO_1 = _T_1286 ? _T_1285 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4985.4]
assign _T_1288 = 21'h3f << out_2_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@4987.4]
assign _T_1289 = _T_1288[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@4988.4]
assign _T_1290 = ~ _T_1289; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@4989.4]
assign _T_1291 = _T_1290[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@4990.4]
assign _T_1292 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@4991.4]
assign beatsDO_2 = _T_1292 ? _T_1291 : 3'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@4992.4]
assign _T_1326 = auto_in_0_a_valid & requestAIO_0_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@4997.4]
assign _T_1328 = auto_in_0_a_valid & requestAIO_0_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5001.4]
assign _T_1330 = auto_in_0_a_valid & requestAIO_0_2; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5005.4]
assign _T_1781 = _T_1780 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5222.4]
assign _T_1372 = auto_in_1_a_valid & requestAIO_1_0; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5019.4]
assign _T_1783 = {_T_1372,_T_1326}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5224.4]
assign _T_1792 = ~ _T_1791; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5236.4]
assign _T_1793 = _T_1783 & _T_1792; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5237.4]
assign _T_1794 = {_T_1793,_T_1372,_T_1326}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5238.4]
assign _T_1795 = _T_1794[3:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5239.4]
assign _GEN_15 = {{1'd0}, _T_1795}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5240.4]
assign _T_1796 = _T_1794 | _GEN_15; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5240.4]
assign _T_1798 = _T_1796[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5242.4]
assign _GEN_16 = {{2'd0}, _T_1791}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5243.4]
assign _T_1799 = _GEN_16 << 2; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5243.4]
assign _GEN_17 = {{1'd0}, _T_1798}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5244.4]
assign _T_1800 = _GEN_17 | _T_1799; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5244.4]
assign _T_1801 = _T_1800[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5245.4]
assign _T_1802 = _T_1800[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5246.4]
assign _T_1803 = _T_1801 & _T_1802; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5247.4]
assign _T_1804 = ~ _T_1803; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5248.4]
assign _T_1813 = _T_1804[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5260.4]
assign _T_1895_0 = _T_1781 ? _T_1813 : _T_1876_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5315.4]
assign _T_1903 = auto_out_0_a_ready & _T_1895_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5316.4]
assign _T_1332 = requestAIO_0_0 ? _T_1903 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5007.4]
assign _T_1945 = _T_1944 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5368.4]
assign _T_1374 = auto_in_1_a_valid & requestAIO_1_1; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5023.4]
assign _T_1947 = {_T_1374,_T_1328}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5370.4]
assign _T_1956 = ~ _T_1955; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5382.4]
assign _T_1957 = _T_1947 & _T_1956; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5383.4]
assign _T_1958 = {_T_1957,_T_1374,_T_1328}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5384.4]
assign _T_1959 = _T_1958[3:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5385.4]
assign _GEN_18 = {{1'd0}, _T_1959}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5386.4]
assign _T_1960 = _T_1958 | _GEN_18; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5386.4]
assign _T_1962 = _T_1960[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5388.4]
assign _GEN_19 = {{2'd0}, _T_1955}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5389.4]
assign _T_1963 = _GEN_19 << 2; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5389.4]
assign _GEN_20 = {{1'd0}, _T_1962}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5390.4]
assign _T_1964 = _GEN_20 | _T_1963; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5390.4]
assign _T_1965 = _T_1964[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5391.4]
assign _T_1966 = _T_1964[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5392.4]
assign _T_1967 = _T_1965 & _T_1966; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5393.4]
assign _T_1968 = ~ _T_1967; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5394.4]
assign _T_1977 = _T_1968[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5406.4]
assign _T_2059_0 = _T_1945 ? _T_1977 : _T_2040_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5461.4]
assign _T_2067 = auto_out_1_a_ready & _T_2059_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5462.4]
assign _T_1333 = requestAIO_0_1 ? _T_2067 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5008.4]
assign _T_2109 = _T_2108 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@5514.4]
assign _T_1376 = auto_in_1_a_valid & requestAIO_1_2; // @[Xbar.scala 307:40:freechips.rocketchip.system.LowRiscConfig.fir@5027.4]
assign _T_2111 = {_T_1376,_T_1330}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5516.4]
assign _T_2120 = ~ _T_2119; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@5528.4]
assign _T_2121 = _T_2111 & _T_2120; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@5529.4]
assign _T_2122 = {_T_2121,_T_1376,_T_1330}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@5530.4]
assign _T_2123 = _T_2122[3:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@5531.4]
assign _GEN_21 = {{1'd0}, _T_2123}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5532.4]
assign _T_2124 = _T_2122 | _GEN_21; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@5532.4]
assign _T_2126 = _T_2124[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@5534.4]
assign _GEN_22 = {{2'd0}, _T_2119}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5535.4]
assign _T_2127 = _GEN_22 << 2; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@5535.4]
assign _GEN_23 = {{1'd0}, _T_2126}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5536.4]
assign _T_2128 = _GEN_23 | _T_2127; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@5536.4]
assign _T_2129 = _T_2128[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@5537.4]
assign _T_2130 = _T_2128[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@5538.4]
assign _T_2131 = _T_2129 & _T_2130; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@5539.4]
assign _T_2132 = ~ _T_2131; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@5540.4]
assign _T_2141 = _T_2132[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5552.4]
assign _T_2223_0 = _T_2109 ? _T_2141 : _T_2204_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5607.4]
assign _T_2231 = auto_out_2_a_ready & _T_2223_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5608.4]
assign _T_1334 = requestAIO_0_2 ? _T_2231 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5009.4]
assign _T_1335 = _T_1332 | _T_1333; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5010.4]
assign _T_1814 = _T_1804[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5261.4]
assign _T_1895_1 = _T_1781 ? _T_1814 : _T_1876_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5315.4]
assign _T_1904 = auto_out_0_a_ready & _T_1895_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5318.4]
assign _T_1378 = requestAIO_1_0 ? _T_1904 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5029.4]
assign _T_1978 = _T_1968[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5407.4]
assign _T_2059_1 = _T_1945 ? _T_1978 : _T_2040_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5461.4]
assign _T_2068 = auto_out_1_a_ready & _T_2059_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5464.4]
assign _T_1379 = requestAIO_1_1 ? _T_2068 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5030.4]
assign _T_2142 = _T_2132[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@5553.4]
assign _T_2223_1 = _T_2109 ? _T_2142 : _T_2204_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5607.4]
assign _T_2232 = auto_out_2_a_ready & _T_2223_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5610.4]
assign _T_1380 = requestAIO_1_2 ? _T_2232 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5031.4]
assign _T_1381 = _T_1378 | _T_1379; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5032.4]
assign _T_2414_0 = _T_2273 ? _T_2311 : _T_2390_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5774.4]
assign _T_2424 = auto_in_0_d_ready & _T_2414_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5775.4]
assign _T_1612 = requestDOI_0_0 ? _T_2424 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5139.4]
assign _T_2620_0 = _T_2479 ? _T_2517 : _T_2596_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5953.4]
assign _T_2630 = auto_in_1_d_ready & _T_2620_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5954.4]
assign _T_1613 = requestDOI_0_1 ? _T_2630 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5140.4]
assign _T_2414_1 = _T_2273 ? _T_2312 : _T_2390_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5774.4]
assign _T_2425 = auto_in_0_d_ready & _T_2414_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5777.4]
assign _T_1647 = requestDOI_1_0 ? _T_2425 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5155.4]
assign _T_2620_1 = _T_2479 ? _T_2518 : _T_2596_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5953.4]
assign _T_2631 = auto_in_1_d_ready & _T_2620_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5956.4]
assign _T_1648 = requestDOI_1_1 ? _T_2631 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5156.4]
assign _T_2414_2 = _T_2273 ? _T_2313 : _T_2390_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5774.4]
assign _T_2426 = auto_in_0_d_ready & _T_2414_2; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5779.4]
assign _T_1682 = requestDOI_2_0 ? _T_2426 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5171.4]
assign _T_2620_2 = _T_2479 ? _T_2519 : _T_2596_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@5953.4]
assign _T_2632 = auto_in_1_d_ready & _T_2620_2; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@5958.4]
assign _T_1683 = requestDOI_2_1 ? _T_2632 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5172.4]
assign _T_1782 = _T_1781 & auto_out_0_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5223.4]
assign _T_1785 = _T_1783 == _T_1783; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5226.4]
assign _T_1787 = _T_1785 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5228.4]
assign _T_1788 = _T_1787 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5229.4]
assign _T_1805 = _T_1783 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5249.4]
assign _T_1806 = _T_1782 & _T_1805; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5250.4]
assign _T_1807 = _T_1804 & _T_1783; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5252.6]
assign _GEN_24 = {{1'd0}, _T_1807}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5253.6]
assign _T_1808 = _GEN_24 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5253.6]
assign _T_1809 = _T_1808[1:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5254.6]
assign _T_1810 = _T_1807 | _T_1809; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5255.6]
assign _T_1823 = _T_1813 & _T_1326; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5266.4]
assign _T_1824 = _T_1814 & _T_1372; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5267.4]
assign _T_1834 = _T_1823 | _T_1824; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5273.4]
assign _T_1836 = _T_1823 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5275.4]
assign _T_1839 = _T_1824 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5278.4]
assign _T_1840 = _T_1836 | _T_1839; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5279.4]
assign _T_1843 = _T_1840 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5282.4]
assign _T_1844 = _T_1843 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5283.4]
assign _T_1845 = _T_1326 | _T_1372; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5288.4]
assign _T_1846 = _T_1845 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5289.4]
assign _T_1848 = _T_1846 | _T_1834; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5291.4]
assign _T_1850 = _T_1848 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5293.4]
assign _T_1851 = _T_1850 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5294.4]
assign _T_1852 = _T_1823 ? beatsAI_0 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5299.4]
assign _T_1853 = _T_1824 ? beatsAI_1 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5300.4]
assign _T_1854 = _T_1852 | _T_1853; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5301.4]
assign _T_1907 = _T_1876_0 ? _T_1326 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5321.4]
assign _T_1908 = _T_1876_1 ? _T_1372 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5322.4]
assign _T_1909 = _T_1907 | _T_1908; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5323.4]
assign out_0_a_valid = _T_1781 ? _T_1845 : _T_1909; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5326.4]
assign _T_1855 = auto_out_0_a_ready & out_0_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5302.4]
assign _GEN_25 = {{8'd0}, _T_1855}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5303.4]
assign _T_1856 = _T_1780 - _GEN_25; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5303.4]
assign _T_1857 = $unsigned(_T_1856); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5304.4]
assign _T_1858 = _T_1857[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5305.4]
assign _T_1887_0 = _T_1781 ? _T_1823 : _T_1876_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5313.4]
assign _T_1887_1 = _T_1781 ? _T_1824 : _T_1876_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5313.4]
assign _T_1920 = {auto_in_0_a_bits_opcode,auto_in_0_a_bits_param,auto_in_0_a_bits_size,in_0_a_bits_source,auto_in_0_a_bits_address,auto_in_0_a_bits_mask,auto_in_0_a_bits_data,auto_in_0_a_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5334.4]
assign _T_1921 = _T_1887_0 ? _T_1920 : 120'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5335.4]
assign in_1_a_bits_source = {{1'd0}, auto_in_1_a_bits_source}; // @[Xbar.scala 109:18:freechips.rocketchip.system.LowRiscConfig.fir@4676.4 Xbar.scala 114:17:freechips.rocketchip.system.LowRiscConfig.fir@4691.4 Xbar.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@4693.4]
assign _T_1928 = {auto_in_1_a_bits_opcode,auto_in_1_a_bits_param,auto_in_1_a_bits_size,in_1_a_bits_source,auto_in_1_a_bits_address,auto_in_1_a_bits_mask,auto_in_1_a_bits_data,auto_in_1_a_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5342.4]
assign _T_1929 = _T_1887_1 ? _T_1928 : 120'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5343.4]
assign _T_1930 = _T_1921 | _T_1929; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5344.4]
assign out_0_a_bits_address = _T_1930[104:73]; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5354.4]
assign _T_1946 = _T_1945 & auto_out_1_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5369.4]
assign _T_1949 = _T_1947 == _T_1947; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5372.4]
assign _T_1951 = _T_1949 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5374.4]
assign _T_1952 = _T_1951 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5375.4]
assign _T_1969 = _T_1947 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5395.4]
assign _T_1970 = _T_1946 & _T_1969; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5396.4]
assign _T_1971 = _T_1968 & _T_1947; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5398.6]
assign _GEN_26 = {{1'd0}, _T_1971}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5399.6]
assign _T_1972 = _GEN_26 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5399.6]
assign _T_1973 = _T_1972[1:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5400.6]
assign _T_1974 = _T_1971 | _T_1973; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5401.6]
assign _T_1987 = _T_1977 & _T_1328; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5412.4]
assign _T_1988 = _T_1978 & _T_1374; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5413.4]
assign _T_1998 = _T_1987 | _T_1988; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5419.4]
assign _T_2000 = _T_1987 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5421.4]
assign _T_2003 = _T_1988 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5424.4]
assign _T_2004 = _T_2000 | _T_2003; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5425.4]
assign _T_2007 = _T_2004 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5428.4]
assign _T_2008 = _T_2007 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5429.4]
assign _T_2009 = _T_1328 | _T_1374; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5434.4]
assign _T_2010 = _T_2009 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5435.4]
assign _T_2012 = _T_2010 | _T_1998; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5437.4]
assign _T_2014 = _T_2012 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5439.4]
assign _T_2015 = _T_2014 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5440.4]
assign _T_2016 = _T_1987 ? beatsAI_0 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5445.4]
assign _T_2017 = _T_1988 ? beatsAI_1 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5446.4]
assign _T_2018 = _T_2016 | _T_2017; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5447.4]
assign _T_2071 = _T_2040_0 ? _T_1328 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5467.4]
assign _T_2072 = _T_2040_1 ? _T_1374 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5468.4]
assign _T_2073 = _T_2071 | _T_2072; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5469.4]
assign out_1_a_valid = _T_1945 ? _T_2009 : _T_2073; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5472.4]
assign _T_2019 = auto_out_1_a_ready & out_1_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5448.4]
assign _GEN_27 = {{8'd0}, _T_2019}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5449.4]
assign _T_2020 = _T_1944 - _GEN_27; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5449.4]
assign _T_2021 = $unsigned(_T_2020); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5450.4]
assign _T_2022 = _T_2021[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5451.4]
assign _T_2051_0 = _T_1945 ? _T_1987 : _T_2040_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5459.4]
assign _T_2051_1 = _T_1945 ? _T_1988 : _T_2040_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5459.4]
assign _T_2085 = _T_2051_0 ? _T_1920 : 120'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5481.4]
assign _T_2093 = _T_2051_1 ? _T_1928 : 120'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5489.4]
assign _T_2094 = _T_2085 | _T_2093; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5490.4]
assign out_1_a_bits_address = _T_2094[104:73]; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5500.4]
assign _T_2110 = _T_2109 & auto_out_2_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5515.4]
assign _T_2113 = _T_2111 == _T_2111; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5518.4]
assign _T_2115 = _T_2113 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5520.4]
assign _T_2116 = _T_2115 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5521.4]
assign _T_2133 = _T_2111 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5541.4]
assign _T_2134 = _T_2110 & _T_2133; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5542.4]
assign _T_2135 = _T_2132 & _T_2111; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5544.6]
assign _GEN_28 = {{1'd0}, _T_2135}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5545.6]
assign _T_2136 = _GEN_28 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5545.6]
assign _T_2137 = _T_2136[1:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5546.6]
assign _T_2138 = _T_2135 | _T_2137; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5547.6]
assign _T_2151 = _T_2141 & _T_1330; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5558.4]
assign _T_2152 = _T_2142 & _T_1376; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@5559.4]
assign _T_2162 = _T_2151 | _T_2152; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5565.4]
assign _T_2164 = _T_2151 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5567.4]
assign _T_2167 = _T_2152 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5570.4]
assign _T_2168 = _T_2164 | _T_2167; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5571.4]
assign _T_2171 = _T_2168 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5574.4]
assign _T_2172 = _T_2171 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5575.4]
assign _T_2173 = _T_1330 | _T_1376; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5580.4]
assign _T_2174 = _T_2173 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5581.4]
assign _T_2176 = _T_2174 | _T_2162; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5583.4]
assign _T_2178 = _T_2176 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5585.4]
assign _T_2179 = _T_2178 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5586.4]
assign _T_2180 = _T_2151 ? beatsAI_0 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5591.4]
assign _T_2181 = _T_2152 ? beatsAI_1 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5592.4]
assign _T_2182 = _T_2180 | _T_2181; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5593.4]
assign _T_2235 = _T_2204_0 ? _T_1330 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5613.4]
assign _T_2236 = _T_2204_1 ? _T_1376 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5614.4]
assign _T_2237 = _T_2235 | _T_2236; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5615.4]
assign out_2_a_valid = _T_2109 ? _T_2173 : _T_2237; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5618.4]
assign _T_2183 = auto_out_2_a_ready & out_2_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5594.4]
assign _GEN_29 = {{8'd0}, _T_2183}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5595.4]
assign _T_2184 = _T_2108 - _GEN_29; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5595.4]
assign _T_2185 = $unsigned(_T_2184); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5596.4]
assign _T_2186 = _T_2185[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5597.4]
assign _T_2215_0 = _T_2109 ? _T_2151 : _T_2204_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5605.4]
assign _T_2215_1 = _T_2109 ? _T_2152 : _T_2204_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@5605.4]
assign _T_2249 = _T_2215_0 ? _T_1920 : 120'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5627.4]
assign _T_2257 = _T_2215_1 ? _T_1928 : 120'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5635.4]
assign _T_2258 = _T_2249 | _T_2257; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5636.4]
assign out_2_a_bits_size = _T_2258[113:110]; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5650.4]
assign _T_2274 = _T_2273 & auto_in_0_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5662.4]
assign _T_2278 = _T_2276 == _T_2276; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5666.4]
assign _T_2280 = _T_2278 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5668.4]
assign _T_2281 = _T_2280 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5669.4]
assign _T_2300 = _T_2276 != 3'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5691.4]
assign _T_2301 = _T_2274 & _T_2300; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5692.4]
assign _T_2302 = _T_2299 & _T_2276; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5694.6]
assign _GEN_30 = {{1'd0}, _T_2302}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5695.6]
assign _T_2303 = _GEN_30 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5695.6]
assign _T_2304 = _T_2303[2:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5696.6]
assign _T_2305 = _T_2302 | _T_2304; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5697.6]
assign _GEN_31 = {{2'd0}, _T_2305}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5698.6]
assign _T_2306 = _GEN_31 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5698.6]
assign _T_2307 = _T_2306[2:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5699.6]
assign _T_2308 = _T_2305 | _T_2307; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5700.6]
assign _T_2336 = _T_2323 | _T_2324; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5722.4]
assign _T_2337 = _T_2336 | _T_2325; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5723.4]
assign _T_2339 = _T_2323 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5725.4]
assign _T_2342 = _T_2324 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5728.4]
assign _T_2343 = _T_2339 | _T_2342; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5729.4]
assign _T_2344 = _T_2336 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@5730.4]
assign _T_2345 = _T_2325 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5731.4]
assign _T_2346 = _T_2344 | _T_2345; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5732.4]
assign _T_2348 = _T_2343 & _T_2346; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@5734.4]
assign _T_2350 = _T_2348 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5736.4]
assign _T_2351 = _T_2350 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5737.4]
assign _T_2352 = _T_1608 | _T_1643; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5742.4]
assign _T_2353 = _T_2352 | _T_1678; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5743.4]
assign _T_2354 = _T_2353 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5744.4]
assign _T_2357 = _T_2354 | _T_2337; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5747.4]
assign _T_2359 = _T_2357 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5749.4]
assign _T_2360 = _T_2359 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5750.4]
assign _T_2361 = _T_2323 ? beatsDO_0 : 5'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5755.4]
assign _T_2362 = _T_2324 ? beatsDO_1 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5756.4]
assign _T_2363 = _T_2325 ? beatsDO_2 : 3'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5757.4]
assign _GEN_32 = {{4'd0}, _T_2361}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5758.4]
assign _T_2364 = _GEN_32 | _T_2362; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5758.4]
assign _GEN_33 = {{6'd0}, _T_2363}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5759.4]
assign _T_2365 = _T_2364 | _GEN_33; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5759.4]
assign _T_2430 = _T_2390_0 ? _T_1608 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5783.4]
assign _T_2431 = _T_2390_1 ? _T_1643 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5784.4]
assign _T_2433 = _T_2430 | _T_2431; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5786.4]
assign _T_2432 = _T_2390_2 ? _T_1678 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5785.4]
assign _T_2434 = _T_2433 | _T_2432; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5787.4]
assign in_0_d_valid = _T_2273 ? _T_2353 : _T_2434; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5790.4]
assign _T_2366 = auto_in_0_d_ready & in_0_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5760.4]
assign _GEN_34 = {{8'd0}, _T_2366}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5761.4]
assign _T_2367 = _T_2272 - _GEN_34; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5761.4]
assign _T_2368 = $unsigned(_T_2367); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5762.4]
assign _T_2369 = _T_2368[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5763.4]
assign _T_2480 = _T_2479 & auto_in_1_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@5841.4]
assign _T_2484 = _T_2482 == _T_2482; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@5845.4]
assign _T_2486 = _T_2484 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5847.4]
assign _T_2487 = _T_2486 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5848.4]
assign _T_2506 = _T_2482 != 3'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@5870.4]
assign _T_2507 = _T_2480 & _T_2506; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@5871.4]
assign _T_2508 = _T_2505 & _T_2482; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@5873.6]
assign _GEN_35 = {{1'd0}, _T_2508}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5874.6]
assign _T_2509 = _GEN_35 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5874.6]
assign _T_2510 = _T_2509[2:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5875.6]
assign _T_2511 = _T_2508 | _T_2510; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5876.6]
assign _GEN_36 = {{2'd0}, _T_2511}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5877.6]
assign _T_2512 = _GEN_36 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@5877.6]
assign _T_2513 = _T_2512[2:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@5878.6]
assign _T_2514 = _T_2511 | _T_2513; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@5879.6]
assign _T_2542 = _T_2529 | _T_2530; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5901.4]
assign _T_2543 = _T_2542 | _T_2531; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@5902.4]
assign _T_2545 = _T_2529 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5904.4]
assign _T_2548 = _T_2530 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5907.4]
assign _T_2549 = _T_2545 | _T_2548; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5908.4]
assign _T_2550 = _T_2542 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@5909.4]
assign _T_2551 = _T_2531 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@5910.4]
assign _T_2552 = _T_2550 | _T_2551; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@5911.4]
assign _T_2554 = _T_2549 & _T_2552; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@5913.4]
assign _T_2556 = _T_2554 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5915.4]
assign _T_2557 = _T_2556 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5916.4]
assign _T_2558 = _T_1610 | _T_1645; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5921.4]
assign _T_2559 = _T_2558 | _T_1680; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@5922.4]
assign _T_2560 = _T_2559 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@5923.4]
assign _T_2563 = _T_2560 | _T_2543; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@5926.4]
assign _T_2565 = _T_2563 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5928.4]
assign _T_2566 = _T_2565 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5929.4]
assign _T_2567 = _T_2529 ? beatsDO_0 : 5'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5934.4]
assign _T_2568 = _T_2530 ? beatsDO_1 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5935.4]
assign _T_2569 = _T_2531 ? beatsDO_2 : 3'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@5936.4]
assign _GEN_37 = {{4'd0}, _T_2567}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5937.4]
assign _T_2570 = _GEN_37 | _T_2568; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5937.4]
assign _GEN_38 = {{6'd0}, _T_2569}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5938.4]
assign _T_2571 = _T_2570 | _GEN_38; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@5938.4]
assign _T_2636 = _T_2596_0 ? _T_1610 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5962.4]
assign _T_2637 = _T_2596_1 ? _T_1645 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5963.4]
assign _T_2639 = _T_2636 | _T_2637; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5965.4]
assign _T_2638 = _T_2596_2 ? _T_1680 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5964.4]
assign _T_2640 = _T_2639 | _T_2638; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@5966.4]
assign in_1_d_valid = _T_2479 ? _T_2559 : _T_2640; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@5969.4]
assign _T_2572 = auto_in_1_d_ready & in_1_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@5939.4]
assign _GEN_39 = {{8'd0}, _T_2572}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5940.4]
assign _T_2573 = _T_2478 - _GEN_39; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5940.4]
assign _T_2574 = $unsigned(_T_2573); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5941.4]
assign _T_2575 = _T_2574[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@5942.4]
assign auto_in_1_a_ready = _T_1381 | _T_1380; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_valid = _T_2479 ? _T_2559 : _T_2640; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_opcode = _T_2670[81:79]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_param = _T_2670[78:77]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_size = _T_2670[76:73]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_source = in_1_d_bits_source[3:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_sink = _T_2670[67:66]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_denied = _T_2670[65]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_data = _T_2670[64:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_1_d_bits_corrupt = _T_2670[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4675.4]
assign auto_in_0_a_ready = _T_1335 | _T_1334; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_b_valid = auto_out_2_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_b_bits_param = auto_out_2_b_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_b_bits_address = auto_out_2_b_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_c_ready = auto_out_2_c_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_valid = _T_2273 ? _T_2353 : _T_2434; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_opcode = _T_2464[81:79]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_param = _T_2464[78:77]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_size = _T_2464[76:73]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_source = in_0_d_bits_source[3:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_sink = _T_2464[67:66]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_denied = _T_2464[65]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_data = _T_2464[64:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_in_0_d_bits_corrupt = _T_2464[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@4674.4]
assign auto_out_2_a_valid = _T_2109 ? _T_2173 : _T_2237; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_opcode = _T_2258[119:117]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_param = _T_2258[116:114]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_size = out_2_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_source = _T_2258[109:105]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_address = _T_2258[104:73]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_mask = _T_2258[72:65]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_data = _T_2258[64:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_a_bits_corrupt = _T_2258[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_b_ready = auto_in_0_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_valid = auto_in_0_c_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_opcode = auto_in_0_c_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_param = auto_in_0_c_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_size = auto_in_0_c_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_source = _GEN_6 | 5'h10; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_address = auto_in_0_c_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_data = auto_in_0_c_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_c_bits_corrupt = auto_in_0_c_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_d_ready = _T_1682 | _T_1683; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_e_valid = auto_in_0_e_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_2_e_bits_sink = auto_in_0_e_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4673.4]
assign auto_out_1_a_valid = _T_1945 ? _T_2009 : _T_2073; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_opcode = _T_2094[119:117]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_param = _T_2094[116:114]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_size = _T_2094[113:110]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_source = _T_2094[109:105]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_address = out_1_a_bits_address[27:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_mask = _T_2094[72:65]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_data = _T_2094[64:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_a_bits_corrupt = _T_2094[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_1_d_ready = _T_1647 | _T_1648; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4672.4]
assign auto_out_0_a_valid = _T_1781 ? _T_1845 : _T_1909; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_opcode = _T_1930[119:117]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_param = _T_1930[116:114]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_size = _T_1930[113:110]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_source = _T_1930[109:105]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_address = out_0_a_bits_address[30:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_mask = _T_1930[72:65]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_data = _T_1930[64:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_a_bits_corrupt = _T_1930[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign auto_out_0_d_ready = _T_1612 | _T_1613; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@4671.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@4593.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@4594.4]
assign TLMonitor_io_in_a_ready = _T_1335 | _T_1334; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_valid = auto_in_0_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_0_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_param = auto_in_0_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_size = auto_in_0_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_source = auto_in_0_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_address = auto_in_0_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_0_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_0_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_b_ready = auto_in_0_b_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_b_valid = auto_out_2_b_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_b_bits_param = auto_out_2_b_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_b_bits_address = auto_out_2_b_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_ready = auto_out_2_c_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_valid = auto_in_0_c_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_bits_opcode = auto_in_0_c_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_bits_param = auto_in_0_c_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_bits_size = auto_in_0_c_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_bits_source = auto_in_0_c_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_bits_address = auto_in_0_c_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_c_bits_corrupt = auto_in_0_c_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_ready = auto_in_0_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_valid = _T_2273 ? _T_2353 : _T_2434; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_opcode = _T_2464[81:79]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_param = _T_2464[78:77]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_size = _T_2464[76:73]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_source = in_0_d_bits_source[3:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_sink = _T_2464[67:66]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_denied = _T_2464[65]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_d_bits_corrupt = _T_2464[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_e_valid = auto_in_0_e_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_io_in_e_bits_sink = auto_in_0_e_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4627.4]
assign TLMonitor_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@4630.4]
assign TLMonitor_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@4631.4]
assign TLMonitor_1_io_in_a_ready = _T_1381 | _T_1380; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_valid = auto_in_1_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_opcode = auto_in_1_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_param = auto_in_1_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_size = auto_in_1_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_source = auto_in_1_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_address = auto_in_1_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_mask = auto_in_1_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_a_bits_corrupt = auto_in_1_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_ready = auto_in_1_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_valid = _T_2479 ? _T_2559 : _T_2640; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_opcode = _T_2670[81:79]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_param = _T_2670[78:77]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_size = _T_2670[76:73]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_source = in_1_d_bits_source[3:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_sink = _T_2670[67:66]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_denied = _T_2670[65]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
assign TLMonitor_1_io_in_d_bits_corrupt = _T_2670[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@4664.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_2272 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_2284 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_2390_0 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_2390_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_2390_2 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_2478 = _RAND_5[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_2490 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_2596_0 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_2596_1 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_2596_2 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1780 = _RAND_10[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1791 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1876_0 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1944 = _RAND_13[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1955 = _RAND_14[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_2040_0 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_2108 = _RAND_16[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_2119 = _RAND_17[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_2204_0 = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_1876_1 = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_2040_1 = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_2204_1 = _RAND_21[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_2272 <= 9'h0;
end else begin
if (_T_2274) begin
_T_2272 <= _T_2365;
end else begin
_T_2272 <= _T_2369;
end
end
if (reset) begin
_T_2284 <= 3'h7;
end else begin
if (_T_2301) begin
_T_2284 <= _T_2308;
end
end
if (reset) begin
_T_2390_0 <= 1'h0;
end else begin
if (_T_2273) begin
_T_2390_0 <= _T_2323;
end
end
if (reset) begin
_T_2390_1 <= 1'h0;
end else begin
if (_T_2273) begin
_T_2390_1 <= _T_2324;
end
end
if (reset) begin
_T_2390_2 <= 1'h0;
end else begin
if (_T_2273) begin
_T_2390_2 <= _T_2325;
end
end
if (reset) begin
_T_2478 <= 9'h0;
end else begin
if (_T_2480) begin
_T_2478 <= _T_2571;
end else begin
_T_2478 <= _T_2575;
end
end
if (reset) begin
_T_2490 <= 3'h7;
end else begin
if (_T_2507) begin
_T_2490 <= _T_2514;
end
end
if (reset) begin
_T_2596_0 <= 1'h0;
end else begin
if (_T_2479) begin
_T_2596_0 <= _T_2529;
end
end
if (reset) begin
_T_2596_1 <= 1'h0;
end else begin
if (_T_2479) begin
_T_2596_1 <= _T_2530;
end
end
if (reset) begin
_T_2596_2 <= 1'h0;
end else begin
if (_T_2479) begin
_T_2596_2 <= _T_2531;
end
end
if (reset) begin
_T_1780 <= 9'h0;
end else begin
if (_T_1782) begin
_T_1780 <= _T_1854;
end else begin
_T_1780 <= _T_1858;
end
end
if (reset) begin
_T_1791 <= 2'h3;
end else begin
if (_T_1806) begin
_T_1791 <= _T_1810;
end
end
if (reset) begin
_T_1876_0 <= 1'h0;
end else begin
if (_T_1781) begin
_T_1876_0 <= _T_1823;
end
end
if (reset) begin
_T_1944 <= 9'h0;
end else begin
if (_T_1946) begin
_T_1944 <= _T_2018;
end else begin
_T_1944 <= _T_2022;
end
end
if (reset) begin
_T_1955 <= 2'h3;
end else begin
if (_T_1970) begin
_T_1955 <= _T_1974;
end
end
if (reset) begin
_T_2040_0 <= 1'h0;
end else begin
if (_T_1945) begin
_T_2040_0 <= _T_1987;
end
end
if (reset) begin
_T_2108 <= 9'h0;
end else begin
if (_T_2110) begin
_T_2108 <= _T_2182;
end else begin
_T_2108 <= _T_2186;
end
end
if (reset) begin
_T_2119 <= 2'h3;
end else begin
if (_T_2134) begin
_T_2119 <= _T_2138;
end
end
if (reset) begin
_T_2204_0 <= 1'h0;
end else begin
if (_T_2109) begin
_T_2204_0 <= _T_2151;
end
end
if (reset) begin
_T_1876_1 <= 1'h0;
end else begin
if (_T_1781) begin
_T_1876_1 <= _T_1824;
end
end
if (reset) begin
_T_2040_1 <= 1'h0;
end else begin
if (_T_1945) begin
_T_2040_1 <= _T_1988;
end
end
if (reset) begin
_T_2204_1 <= 1'h0;
end else begin
if (_T_2109) begin
_T_2204_1 <= _T_2152;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1788) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5231.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1788) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5232.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1844) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5285.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1844) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5286.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1851) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5296.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1851) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5297.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1952) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5377.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1952) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5378.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2008) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5431.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2008) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5432.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2015) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5442.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2015) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5443.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2116) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5523.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2116) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5524.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2172) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5577.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2172) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5578.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2179) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5588.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2179) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5589.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2281) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5671.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2281) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5672.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2351) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5739.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2351) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5740.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2360) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5752.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2360) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5753.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2487) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5850.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2487) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@5851.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2557) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5918.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2557) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@5919.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2566) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5931.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2566) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@5932.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@6025.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6026.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6027.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [1:0] io_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [31:0] io_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [2:0] io_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [2:0] io_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [3:0] io_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [3:0] io_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [31:0] io_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input io_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
input [1:0] io_in_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@6028.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@8896.4]
wire [1:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@6045.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@6046.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@6051.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@6052.6]
wire _T_39; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@6058.6]
wire _T_40; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@6059.6]
wire [26:0] _T_42; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@6061.6]
wire [11:0] _T_43; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@6062.6]
wire [11:0] _T_44; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@6063.6]
wire [31:0] _GEN_33; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@6064.6]
wire [31:0] _T_45; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@6064.6]
wire _T_46; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@6065.6]
wire [1:0] _T_48; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@6067.6]
wire [3:0] _T_49; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@6068.6]
wire [2:0] _T_50; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@6069.6]
wire [2:0] _T_51; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@6070.6]
wire _T_52; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@6071.6]
wire _T_53; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@6072.6]
wire _T_54; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@6073.6]
wire _T_55; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@6074.6]
wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6076.6]
wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6077.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6079.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6080.6]
wire _T_62; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@6081.6]
wire _T_63; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@6082.6]
wire _T_64; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@6083.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6084.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6085.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6086.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6087.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6088.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6089.6]
wire _T_71; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6090.6]
wire _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6091.6]
wire _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6092.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6093.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6094.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6095.6]
wire _T_77; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@6096.6]
wire _T_78; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@6097.6]
wire _T_79; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@6098.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6099.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6100.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6101.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6102.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6103.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6104.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6105.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6106.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6107.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6108.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6109.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6110.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6111.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6112.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6113.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6114.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6115.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6116.6]
wire _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6117.6]
wire _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6118.6]
wire _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6119.6]
wire _T_101; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6120.6]
wire _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6121.6]
wire _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6122.6]
wire [7:0] _T_110; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@6129.6]
wire [32:0] _T_121; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6140.6]
wire _T_147; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@6170.6]
wire [31:0] _T_149; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6173.8]
wire [32:0] _T_150; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6174.8]
wire [32:0] _T_151; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6175.8]
wire [32:0] _T_152; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6176.8]
wire _T_153; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6177.8]
wire [31:0] _T_154; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6178.8]
wire [32:0] _T_155; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6179.8]
wire [32:0] _T_156; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6180.8]
wire [32:0] _T_157; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6181.8]
wire _T_158; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6182.8]
wire [31:0] _T_159; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6183.8]
wire [32:0] _T_160; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6184.8]
wire [32:0] _T_161; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6185.8]
wire [32:0] _T_162; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6186.8]
wire _T_163; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6187.8]
wire [31:0] _T_164; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6188.8]
wire [32:0] _T_165; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6189.8]
wire [32:0] _T_166; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6190.8]
wire [32:0] _T_167; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6191.8]
wire _T_168; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6192.8]
wire [32:0] _T_171; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6195.8]
wire [32:0] _T_172; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6196.8]
wire _T_173; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6197.8]
wire [31:0] _T_174; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6198.8]
wire [32:0] _T_175; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6199.8]
wire [32:0] _T_176; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6200.8]
wire [32:0] _T_177; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6201.8]
wire _T_178; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6202.8]
wire _T_186; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6210.8]
wire [31:0] _T_189; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6213.8]
wire [32:0] _T_190; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6214.8]
wire [32:0] _T_191; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6215.8]
wire [32:0] _T_192; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6216.8]
wire _T_193; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6217.8]
wire _T_194; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6218.8]
wire _T_198; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6222.8]
wire _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6223.8]
wire _T_219; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@6243.8]
wire _T_221; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@6244.8]
wire _T_229; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@6252.8]
wire _T_230; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@6253.8]
wire _T_232; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@6259.8]
wire _T_233; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@6260.8]
wire _T_236; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@6267.8]
wire _T_237; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@6268.8]
wire _T_239; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@6274.8]
wire _T_240; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@6275.8]
wire _T_241; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@6280.8]
wire _T_243; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@6282.8]
wire _T_244; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@6283.8]
wire [7:0] _T_245; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@6288.8]
wire _T_246; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@6289.8]
wire _T_248; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@6291.8]
wire _T_249; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@6292.8]
wire _T_250; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@6297.8]
wire _T_252; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@6299.8]
wire _T_253; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@6300.8]
wire _T_254; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@6306.6]
wire _T_352; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@6424.8]
wire _T_354; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@6426.8]
wire _T_355; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@6427.8]
wire _T_365; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@6450.6]
wire _T_400; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6486.8]
wire _T_401; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6487.8]
wire _T_402; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6488.8]
wire _T_403; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6489.8]
wire _T_404; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6490.8]
wire _T_405; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6491.8]
wire _T_407; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6493.8]
wire _T_415; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6501.8]
wire _T_417; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@6503.8]
wire _T_419; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6505.8]
wire _T_420; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6506.8]
wire _T_427; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@6525.8]
wire _T_429; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@6527.8]
wire _T_430; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@6528.8]
wire _T_431; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@6533.8]
wire _T_433; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@6535.8]
wire _T_434; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@6536.8]
wire _T_439; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@6550.6]
wire _T_471; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6583.8]
wire _T_472; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6584.8]
wire _T_473; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6585.8]
wire _T_474; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6586.8]
wire _T_476; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6588.8]
wire _T_484; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6596.8]
wire _T_497; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@6609.8]
wire _T_498; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@6610.8]
wire _T_500; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6612.8]
wire _T_501; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6613.8]
wire _T_516; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@6649.6]
wire [7:0] _T_589; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@6739.8]
wire [7:0] _T_590; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@6740.8]
wire _T_591; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@6741.8]
wire _T_593; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@6743.8]
wire _T_594; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@6744.8]
wire _T_595; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@6750.6]
wire _T_616; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6772.8]
wire _T_639; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6795.8]
wire _T_640; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6796.8]
wire _T_641; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6797.8]
wire _T_642; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6798.8]
wire _T_646; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6802.8]
wire _T_647; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6803.8]
wire _T_654; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@6822.8]
wire _T_656; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@6824.8]
wire _T_657; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@6825.8]
wire _T_662; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@6839.6]
wire _T_721; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@6911.8]
wire _T_723; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@6913.8]
wire _T_724; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@6914.8]
wire _T_729; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@6928.6]
wire _T_780; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6980.8]
wire _T_781; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6981.8]
wire _T_796; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@7019.6]
wire _T_798; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@7021.6]
wire _T_799; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@7022.6]
wire [1:0] _T_802; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@7029.6]
wire _T_803; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@7030.6]
wire _T_808; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7035.6]
wire _T_809; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7036.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7042.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7043.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@7045.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7048.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7049.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@7054.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@7056.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@7057.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@7062.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@7064.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@7065.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@7070.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@7072.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@7073.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@7078.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@7080.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@7081.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@7087.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@7111.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@7113.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@7114.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@7119.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@7121.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@7122.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@7145.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@7186.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@7188.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@7189.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@7204.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@7239.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@7275.6]
wire [32:0] _T_965; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7330.6]
wire [31:0] _T_991; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7360.6]
wire [32:0] _T_992; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7361.6]
wire [32:0] _T_993; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7362.6]
wire [32:0] _T_994; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7363.6]
wire _T_995; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7364.6]
wire [31:0] _T_996; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7365.6]
wire [32:0] _T_997; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7366.6]
wire [32:0] _T_998; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7367.6]
wire [32:0] _T_999; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7368.6]
wire _T_1000; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7369.6]
wire [31:0] _T_1001; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7370.6]
wire [32:0] _T_1002; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7371.6]
wire [32:0] _T_1003; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7372.6]
wire [32:0] _T_1004; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7373.6]
wire _T_1005; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7374.6]
wire [31:0] _T_1006; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7375.6]
wire [32:0] _T_1007; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7376.6]
wire [32:0] _T_1008; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7377.6]
wire [32:0] _T_1009; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7378.6]
wire _T_1010; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7379.6]
wire [32:0] _T_1013; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7382.6]
wire [32:0] _T_1014; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7383.6]
wire _T_1015; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7384.6]
wire [31:0] _T_1016; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7385.6]
wire [32:0] _T_1017; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7386.6]
wire [32:0] _T_1018; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7387.6]
wire [32:0] _T_1019; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7388.6]
wire _T_1020; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7389.6]
wire [31:0] _T_1021; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7390.6]
wire [32:0] _T_1022; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7391.6]
wire [32:0] _T_1023; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7392.6]
wire [32:0] _T_1024; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7393.6]
wire _T_1025; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7394.6]
wire _T_1039; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7404.6]
wire _T_1040; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7405.6]
wire _T_1041; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7406.6]
wire _T_1042; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7407.6]
wire _T_1043; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7408.6]
wire _T_1044; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7409.6]
wire [26:0] _T_1046; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@7411.6]
wire [11:0] _T_1047; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@7412.6]
wire [11:0] _T_1048; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@7413.6]
wire [31:0] _GEN_34; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7414.6]
wire [31:0] _T_1049; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7414.6]
wire _T_1050; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@7415.6]
wire _T_1176; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@7536.8]
wire _T_1177; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@7537.8]
wire _T_1182; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@7550.8]
wire _T_1183; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@7551.8]
wire _T_1184; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@7556.8]
wire _T_1186; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@7558.8]
wire _T_1187; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@7559.8]
wire [1:0] _T_1334; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@7885.6]
wire _T_1335; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@7886.6]
wire _T_1340; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7891.6]
wire _T_1341; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7892.6]
wire _T_1351; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7898.6]
wire _T_1352; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7899.6]
wire [26:0] _T_1354; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@7901.6]
wire [11:0] _T_1355; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@7902.6]
wire [11:0] _T_1356; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@7903.6]
wire [31:0] _GEN_35; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7904.6]
wire [31:0] _T_1357; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7904.6]
wire _T_1358; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@7905.6]
wire [31:0] _T_1359; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7906.6]
wire [32:0] _T_1360; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7907.6]
wire [32:0] _T_1361; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7908.6]
wire [32:0] _T_1362; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7909.6]
wire _T_1363; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7910.6]
wire [31:0] _T_1364; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7911.6]
wire [32:0] _T_1365; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7912.6]
wire [32:0] _T_1366; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7913.6]
wire [32:0] _T_1367; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7914.6]
wire _T_1368; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7915.6]
wire [31:0] _T_1369; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7916.6]
wire [32:0] _T_1370; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7917.6]
wire [32:0] _T_1371; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7918.6]
wire [32:0] _T_1372; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7919.6]
wire _T_1373; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7920.6]
wire [31:0] _T_1374; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7921.6]
wire [32:0] _T_1375; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7922.6]
wire [32:0] _T_1376; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7923.6]
wire [32:0] _T_1377; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7924.6]
wire _T_1378; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7925.6]
wire [32:0] _T_1380; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7927.6]
wire [32:0] _T_1381; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7928.6]
wire [32:0] _T_1382; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7929.6]
wire _T_1383; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7930.6]
wire [31:0] _T_1384; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7931.6]
wire [32:0] _T_1385; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7932.6]
wire [32:0] _T_1386; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7933.6]
wire [32:0] _T_1387; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7934.6]
wire _T_1388; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7935.6]
wire [31:0] _T_1389; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7936.6]
wire [32:0] _T_1390; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7937.6]
wire [32:0] _T_1391; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7938.6]
wire [32:0] _T_1392; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7939.6]
wire _T_1393; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7940.6]
wire _T_1407; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7950.6]
wire _T_1408; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7951.6]
wire _T_1409; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7952.6]
wire _T_1410; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7953.6]
wire _T_1411; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7954.6]
wire _T_1412; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7955.6]
wire _T_1449; // @[Monitor.scala 207:25:freechips.rocketchip.system.LowRiscConfig.fir@7996.6]
wire _T_1451; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@7999.8]
wire _T_1452; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@8000.8]
wire _T_1454; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@8006.8]
wire _T_1455; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@8007.8]
wire _T_1456; // @[Monitor.scala 210:27:freechips.rocketchip.system.LowRiscConfig.fir@8012.8]
wire _T_1458; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@8014.8]
wire _T_1459; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@8015.8]
wire _T_1461; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@8021.8]
wire _T_1462; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@8022.8]
wire _T_1463; // @[Bundles.scala 121:29:freechips.rocketchip.system.LowRiscConfig.fir@8027.8]
wire _T_1465; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@8029.8]
wire _T_1466; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@8030.8]
wire _T_1467; // @[Monitor.scala 213:15:freechips.rocketchip.system.LowRiscConfig.fir@8035.8]
wire _T_1469; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@8037.8]
wire _T_1470; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@8038.8]
wire _T_1471; // @[Monitor.scala 216:25:freechips.rocketchip.system.LowRiscConfig.fir@8044.6]
wire _T_1489; // @[Monitor.scala 224:25:freechips.rocketchip.system.LowRiscConfig.fir@8084.6]
wire _T_1528; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@8124.8]
wire _T_1536; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@8132.8]
wire _T_1540; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8136.8]
wire _T_1541; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8137.8]
wire _T_1561; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@8157.8]
wire _T_1563; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@8158.8]
wire _T_1571; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@8166.8]
wire _T_1572; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@8167.8]
wire _T_1583; // @[Bundles.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@8194.8]
wire _T_1585; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@8196.8]
wire _T_1586; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@8197.8]
wire _T_1591; // @[Monitor.scala 234:25:freechips.rocketchip.system.LowRiscConfig.fir@8211.6]
wire _T_1689; // @[Monitor.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@8330.6]
wire _T_1699; // @[Monitor.scala 247:28:freechips.rocketchip.system.LowRiscConfig.fir@8353.8]
wire _T_1701; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@8355.8]
wire _T_1702; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@8356.8]
wire _T_1707; // @[Monitor.scala 251:25:freechips.rocketchip.system.LowRiscConfig.fir@8370.6]
wire _T_1721; // @[Monitor.scala 258:25:freechips.rocketchip.system.LowRiscConfig.fir@8402.6]
wire _T_1743; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8453.4]
wire [8:0] _T_1748; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@8458.4]
wire _T_1749; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@8459.4]
wire _T_1750; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@8460.4]
reg [8:0] _T_1753; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8462.4]
reg [31:0] _RAND_0;
wire [9:0] _T_1754; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8463.4]
wire [9:0] _T_1755; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8464.4]
wire [8:0] _T_1756; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8465.4]
wire _T_1757; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8466.4]
reg [2:0] _T_1766; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@8477.4]
reg [31:0] _RAND_1;
reg [2:0] _T_1768; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@8478.4]
reg [31:0] _RAND_2;
reg [3:0] _T_1770; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@8479.4]
reg [31:0] _RAND_3;
reg [3:0] _T_1772; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@8480.4]
reg [31:0] _RAND_4;
reg [31:0] _T_1774; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@8481.4]
reg [31:0] _RAND_5;
wire _T_1775; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@8482.4]
wire _T_1776; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@8483.4]
wire _T_1777; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@8485.6]
wire _T_1779; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@8487.6]
wire _T_1780; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@8488.6]
wire _T_1781; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@8493.6]
wire _T_1783; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@8495.6]
wire _T_1784; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@8496.6]
wire _T_1785; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@8501.6]
wire _T_1787; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@8503.6]
wire _T_1788; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@8504.6]
wire _T_1789; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@8509.6]
wire _T_1791; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@8511.6]
wire _T_1792; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@8512.6]
wire _T_1793; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@8517.6]
wire _T_1795; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@8519.6]
wire _T_1796; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@8520.6]
wire _T_1798; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@8527.4]
wire _T_1799; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8535.4]
wire [26:0] _T_1801; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@8537.4]
wire [11:0] _T_1802; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@8538.4]
wire [11:0] _T_1803; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@8539.4]
wire [8:0] _T_1804; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@8540.4]
wire _T_1805; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@8541.4]
reg [8:0] _T_1808; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8543.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1809; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8544.4]
wire [9:0] _T_1810; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8545.4]
wire [8:0] _T_1811; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8546.4]
wire _T_1812; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8547.4]
reg [2:0] _T_1821; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@8558.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1823; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@8559.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1825; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@8560.4]
reg [31:0] _RAND_9;
reg [3:0] _T_1827; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@8561.4]
reg [31:0] _RAND_10;
reg [1:0] _T_1829; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@8562.4]
reg [31:0] _RAND_11;
reg _T_1831; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@8563.4]
reg [31:0] _RAND_12;
wire _T_1832; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@8564.4]
wire _T_1833; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@8565.4]
wire _T_1834; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@8567.6]
wire _T_1836; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@8569.6]
wire _T_1837; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@8570.6]
wire _T_1838; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@8575.6]
wire _T_1840; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@8577.6]
wire _T_1841; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@8578.6]
wire _T_1842; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@8583.6]
wire _T_1844; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@8585.6]
wire _T_1845; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@8586.6]
wire _T_1846; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@8591.6]
wire _T_1848; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@8593.6]
wire _T_1849; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@8594.6]
wire _T_1850; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@8599.6]
wire _T_1852; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@8601.6]
wire _T_1853; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@8602.6]
wire _T_1854; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@8607.6]
wire _T_1856; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@8609.6]
wire _T_1857; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@8610.6]
wire _T_1859; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@8617.4]
wire _T_1860; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8626.4]
reg [8:0] _T_1870; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8635.4]
reg [31:0] _RAND_13;
wire [9:0] _T_1871; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8636.4]
wire [9:0] _T_1872; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8637.4]
wire [8:0] _T_1873; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8638.4]
wire _T_1874; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8639.4]
reg [1:0] _T_1885; // @[Monitor.scala 373:22:freechips.rocketchip.system.LowRiscConfig.fir@8651.4]
reg [31:0] _RAND_14;
reg [31:0] _T_1891; // @[Monitor.scala 376:22:freechips.rocketchip.system.LowRiscConfig.fir@8654.4]
reg [31:0] _RAND_15;
wire _T_1892; // @[Monitor.scala 377:22:freechips.rocketchip.system.LowRiscConfig.fir@8655.4]
wire _T_1893; // @[Monitor.scala 377:19:freechips.rocketchip.system.LowRiscConfig.fir@8656.4]
wire _T_1898; // @[Monitor.scala 379:29:freechips.rocketchip.system.LowRiscConfig.fir@8666.6]
wire _T_1900; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@8668.6]
wire _T_1901; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@8669.6]
wire _T_1910; // @[Monitor.scala 382:29:freechips.rocketchip.system.LowRiscConfig.fir@8690.6]
wire _T_1912; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@8692.6]
wire _T_1913; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@8693.6]
wire _T_1915; // @[Monitor.scala 384:20:freechips.rocketchip.system.LowRiscConfig.fir@8700.4]
wire _T_1916; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8708.4]
wire [8:0] _T_1921; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@8713.4]
wire _T_1922; // @[Edges.scala 102:36:freechips.rocketchip.system.LowRiscConfig.fir@8714.4]
reg [8:0] _T_1925; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8716.4]
reg [31:0] _RAND_16;
wire [9:0] _T_1926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8717.4]
wire [9:0] _T_1927; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8718.4]
wire [8:0] _T_1928; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8719.4]
wire _T_1929; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8720.4]
reg [2:0] _T_1938; // @[Monitor.scala 395:22:freechips.rocketchip.system.LowRiscConfig.fir@8731.4]
reg [31:0] _RAND_17;
reg [2:0] _T_1940; // @[Monitor.scala 396:22:freechips.rocketchip.system.LowRiscConfig.fir@8732.4]
reg [31:0] _RAND_18;
reg [3:0] _T_1942; // @[Monitor.scala 397:22:freechips.rocketchip.system.LowRiscConfig.fir@8733.4]
reg [31:0] _RAND_19;
reg [3:0] _T_1944; // @[Monitor.scala 398:22:freechips.rocketchip.system.LowRiscConfig.fir@8734.4]
reg [31:0] _RAND_20;
reg [31:0] _T_1946; // @[Monitor.scala 399:22:freechips.rocketchip.system.LowRiscConfig.fir@8735.4]
reg [31:0] _RAND_21;
wire _T_1947; // @[Monitor.scala 400:22:freechips.rocketchip.system.LowRiscConfig.fir@8736.4]
wire _T_1948; // @[Monitor.scala 400:19:freechips.rocketchip.system.LowRiscConfig.fir@8737.4]
wire _T_1949; // @[Monitor.scala 401:29:freechips.rocketchip.system.LowRiscConfig.fir@8739.6]
wire _T_1951; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@8741.6]
wire _T_1952; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@8742.6]
wire _T_1953; // @[Monitor.scala 402:29:freechips.rocketchip.system.LowRiscConfig.fir@8747.6]
wire _T_1955; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@8749.6]
wire _T_1956; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@8750.6]
wire _T_1957; // @[Monitor.scala 403:29:freechips.rocketchip.system.LowRiscConfig.fir@8755.6]
wire _T_1959; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@8757.6]
wire _T_1960; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@8758.6]
wire _T_1961; // @[Monitor.scala 404:29:freechips.rocketchip.system.LowRiscConfig.fir@8763.6]
wire _T_1963; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@8765.6]
wire _T_1964; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@8766.6]
wire _T_1965; // @[Monitor.scala 405:29:freechips.rocketchip.system.LowRiscConfig.fir@8771.6]
wire _T_1967; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@8773.6]
wire _T_1968; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@8774.6]
wire _T_1970; // @[Monitor.scala 407:20:freechips.rocketchip.system.LowRiscConfig.fir@8781.4]
reg [8:0] _T_1972; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@8789.4]
reg [31:0] _RAND_22;
reg [8:0] _T_1983; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8799.4]
reg [31:0] _RAND_23;
wire [9:0] _T_1984; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8800.4]
wire [9:0] _T_1985; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8801.4]
wire [8:0] _T_1986; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8802.4]
wire _T_1987; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8803.4]
reg [8:0] _T_2004; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8822.4]
reg [31:0] _RAND_24;
wire [9:0] _T_2005; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8823.4]
wire [9:0] _T_2006; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8824.4]
wire [8:0] _T_2007; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8825.4]
wire _T_2008; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8826.4]
wire _T_2019; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@8841.4]
wire [15:0] _T_2021; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8844.6]
wire [8:0] _T_2022; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@8846.6]
wire _T_2023; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@8847.6]
wire _T_2024; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@8848.6]
wire _T_2026; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@8850.6]
wire _T_2027; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@8851.6]
wire [15:0] _GEN_27; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@8843.4]
wire _T_2032; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@8862.4]
wire _T_2034; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@8864.4]
wire _T_2035; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@8865.4]
wire [15:0] _T_2036; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8867.6]
wire [8:0] _T_2017; // @[:freechips.rocketchip.system.LowRiscConfig.fir@8837.4 :freechips.rocketchip.system.LowRiscConfig.fir@8839.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@8845.6]
wire [8:0] _T_2037; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@8869.6]
wire [8:0] _T_2038; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@8870.6]
wire _T_2039; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@8871.6]
wire _T_2041; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@8873.6]
wire _T_2042; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@8874.6]
wire [15:0] _GEN_28; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@8866.4]
wire [8:0] _T_2029; // @[:freechips.rocketchip.system.LowRiscConfig.fir@8857.4 :freechips.rocketchip.system.LowRiscConfig.fir@8859.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@8868.6]
wire _T_2043; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@8880.4]
wire _T_2044; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@8881.4]
wire _T_2045; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@8882.4]
wire _T_2046; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@8883.4]
wire _T_2048; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@8885.4]
wire _T_2049; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@8886.4]
wire [8:0] _T_2050; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@8891.4]
wire [8:0] _T_2051; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@8892.4]
wire [8:0] _T_2052; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@8893.4]
reg [31:0] _T_2054; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@8895.4]
reg [31:0] _RAND_25;
wire _T_2055; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@8898.4]
wire _T_2056; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@8899.4]
wire _T_2057; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@8900.4]
wire _T_2058; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@8901.4]
wire _T_2059; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@8902.4]
wire _T_2060; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@8903.4]
wire _T_2062; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@8905.4]
wire _T_2063; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@8906.4]
wire [31:0] _T_2065; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@8912.4]
wire _T_2068; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@8916.4]
reg [3:0] _T_2070; // @[Monitor.scala 486:27:freechips.rocketchip.system.LowRiscConfig.fir@8920.4]
reg [31:0] _RAND_26;
reg [8:0] _T_2080; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@8929.4]
reg [31:0] _RAND_27;
wire [9:0] _T_2081; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8930.4]
wire [9:0] _T_2082; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8931.4]
wire [8:0] _T_2083; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8932.4]
wire _T_2084; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8933.4]
wire _T_2095; // @[Monitor.scala 492:27:freechips.rocketchip.system.LowRiscConfig.fir@8948.4]
wire _T_2096; // @[Edges.scala 71:36:freechips.rocketchip.system.LowRiscConfig.fir@8949.4]
wire _T_2097; // @[Edges.scala 71:52:freechips.rocketchip.system.LowRiscConfig.fir@8950.4]
wire _T_2098; // @[Edges.scala 71:43:freechips.rocketchip.system.LowRiscConfig.fir@8951.4]
wire _T_2099; // @[Edges.scala 71:40:freechips.rocketchip.system.LowRiscConfig.fir@8952.4]
wire _T_2100; // @[Monitor.scala 492:38:freechips.rocketchip.system.LowRiscConfig.fir@8953.4]
wire [3:0] _T_2101; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8955.6]
wire [3:0] _T_2102; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@8957.6]
wire _T_2103; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@8958.6]
wire _T_2104; // @[Monitor.scala 494:14:freechips.rocketchip.system.LowRiscConfig.fir@8959.6]
wire _T_2106; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@8961.6]
wire _T_2107; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@8962.6]
wire [3:0] _GEN_31; // @[Monitor.scala 492:72:freechips.rocketchip.system.LowRiscConfig.fir@8954.4]
wire [3:0] _T_2113; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8975.6]
wire [3:0] _T_2114; // @[Monitor.scala 500:21:freechips.rocketchip.system.LowRiscConfig.fir@8977.6]
wire [3:0] _T_2115; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@8978.6]
wire _T_2116; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@8979.6]
wire _T_2118; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@8981.6]
wire _T_2119; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@8982.6]
wire [3:0] _GEN_32; // @[Monitor.scala 498:73:freechips.rocketchip.system.LowRiscConfig.fir@8974.4]
wire [3:0] _T_2120; // @[Monitor.scala 505:27:freechips.rocketchip.system.LowRiscConfig.fir@8988.4]
wire [3:0] _T_2121; // @[Monitor.scala 505:38:freechips.rocketchip.system.LowRiscConfig.fir@8989.4]
wire [3:0] _T_2122; // @[Monitor.scala 505:36:freechips.rocketchip.system.LowRiscConfig.fir@8990.4]
wire _GEN_36; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6225.10]
wire _GEN_52; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@6361.10]
wire _GEN_70; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6508.10]
wire _GEN_82; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6615.10]
wire _GEN_92; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@6714.10]
wire _GEN_102; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6805.10]
wire _GEN_112; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@6894.10]
wire _GEN_122; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6983.10]
wire _GEN_132; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7051.10]
wire _GEN_142; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@7093.10]
wire _GEN_152; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@7151.10]
wire _GEN_162; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@7210.10]
wire _GEN_168; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@7245.10]
wire _GEN_174; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@7281.10]
wire _GEN_180; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@8002.10]
wire _GEN_192; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@8050.10]
wire _GEN_202; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8139.10]
wire _GEN_216; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@8266.10]
wire _GEN_228; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@8336.10]
wire _GEN_238; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@8376.10]
wire _GEN_246; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@8408.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@8896.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@6045.6]
assign _T_23 = _T_22 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@6046.6]
assign _T_28 = io_in_a_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@6051.6]
assign _T_29 = io_in_a_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@6052.6]
assign _T_39 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@6058.6]
assign _T_40 = _T_39 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@6059.6]
assign _T_42 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@6061.6]
assign _T_43 = _T_42[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@6062.6]
assign _T_44 = ~ _T_43; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@6063.6]
assign _GEN_33 = {{20'd0}, _T_44}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@6064.6]
assign _T_45 = io_in_a_bits_address & _GEN_33; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@6064.6]
assign _T_46 = _T_45 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@6065.6]
assign _T_48 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@6067.6]
assign _T_49 = 4'h1 << _T_48; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@6068.6]
assign _T_50 = _T_49[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@6069.6]
assign _T_51 = _T_50 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@6070.6]
assign _T_52 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@6071.6]
assign _T_53 = _T_51[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@6072.6]
assign _T_54 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@6073.6]
assign _T_55 = _T_54 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@6074.6]
assign _T_57 = _T_53 & _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6076.6]
assign _T_58 = _T_52 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6077.6]
assign _T_60 = _T_53 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6079.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6080.6]
assign _T_62 = _T_51[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@6081.6]
assign _T_63 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@6082.6]
assign _T_64 = _T_63 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@6083.6]
assign _T_65 = _T_55 & _T_64; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6084.6]
assign _T_66 = _T_62 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6085.6]
assign _T_67 = _T_58 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6086.6]
assign _T_68 = _T_55 & _T_63; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6087.6]
assign _T_69 = _T_62 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6088.6]
assign _T_70 = _T_58 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6089.6]
assign _T_71 = _T_54 & _T_64; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6090.6]
assign _T_72 = _T_62 & _T_71; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6091.6]
assign _T_73 = _T_61 | _T_72; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6092.6]
assign _T_74 = _T_54 & _T_63; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6093.6]
assign _T_75 = _T_62 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6094.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6095.6]
assign _T_77 = _T_51[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@6096.6]
assign _T_78 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@6097.6]
assign _T_79 = _T_78 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@6098.6]
assign _T_80 = _T_65 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6099.6]
assign _T_81 = _T_77 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6100.6]
assign _T_82 = _T_67 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6101.6]
assign _T_83 = _T_65 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6102.6]
assign _T_84 = _T_77 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6103.6]
assign _T_85 = _T_67 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6104.6]
assign _T_86 = _T_68 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6105.6]
assign _T_87 = _T_77 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6106.6]
assign _T_88 = _T_70 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6107.6]
assign _T_89 = _T_68 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6108.6]
assign _T_90 = _T_77 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6109.6]
assign _T_91 = _T_70 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6110.6]
assign _T_92 = _T_71 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6111.6]
assign _T_93 = _T_77 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6112.6]
assign _T_94 = _T_73 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6113.6]
assign _T_95 = _T_71 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6114.6]
assign _T_96 = _T_77 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6115.6]
assign _T_97 = _T_73 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6116.6]
assign _T_98 = _T_74 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6117.6]
assign _T_99 = _T_77 & _T_98; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6118.6]
assign _T_100 = _T_76 | _T_99; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6119.6]
assign _T_101 = _T_74 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@6120.6]
assign _T_102 = _T_77 & _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@6121.6]
assign _T_103 = _T_76 | _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@6122.6]
assign _T_110 = {_T_103,_T_100,_T_97,_T_94,_T_91,_T_88,_T_85,_T_82}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@6129.6]
assign _T_121 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6140.6]
assign _T_147 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@6170.6]
assign _T_149 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6173.8]
assign _T_150 = {1'b0,$signed(_T_149)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6174.8]
assign _T_151 = $signed(_T_150) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6175.8]
assign _T_152 = $signed(_T_151); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6176.8]
assign _T_153 = $signed(_T_152) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6177.8]
assign _T_154 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6178.8]
assign _T_155 = {1'b0,$signed(_T_154)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6179.8]
assign _T_156 = $signed(_T_155) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6180.8]
assign _T_157 = $signed(_T_156); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6181.8]
assign _T_158 = $signed(_T_157) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6182.8]
assign _T_159 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6183.8]
assign _T_160 = {1'b0,$signed(_T_159)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6184.8]
assign _T_161 = $signed(_T_160) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6185.8]
assign _T_162 = $signed(_T_161); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6186.8]
assign _T_163 = $signed(_T_162) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6187.8]
assign _T_164 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6188.8]
assign _T_165 = {1'b0,$signed(_T_164)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6189.8]
assign _T_166 = $signed(_T_165) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6190.8]
assign _T_167 = $signed(_T_166); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6191.8]
assign _T_168 = $signed(_T_167) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6192.8]
assign _T_171 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6195.8]
assign _T_172 = $signed(_T_171); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6196.8]
assign _T_173 = $signed(_T_172) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6197.8]
assign _T_174 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6198.8]
assign _T_175 = {1'b0,$signed(_T_174)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6199.8]
assign _T_176 = $signed(_T_175) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6200.8]
assign _T_177 = $signed(_T_176); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6201.8]
assign _T_178 = $signed(_T_177) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6202.8]
assign _T_186 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6210.8]
assign _T_189 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@6213.8]
assign _T_190 = {1'b0,$signed(_T_189)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@6214.8]
assign _T_191 = $signed(_T_190) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6215.8]
assign _T_192 = $signed(_T_191); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@6216.8]
assign _T_193 = $signed(_T_192) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@6217.8]
assign _T_194 = _T_186 & _T_193; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6218.8]
assign _T_198 = _T_194 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6222.8]
assign _T_199 = _T_198 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6223.8]
assign _T_219 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@6243.8]
assign _T_221 = _T_23 ? _T_219 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@6244.8]
assign _T_229 = _T_221 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@6252.8]
assign _T_230 = _T_229 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@6253.8]
assign _T_232 = _T_40 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@6259.8]
assign _T_233 = _T_232 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@6260.8]
assign _T_236 = _T_52 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@6267.8]
assign _T_237 = _T_236 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@6268.8]
assign _T_239 = _T_46 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@6274.8]
assign _T_240 = _T_239 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@6275.8]
assign _T_241 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@6280.8]
assign _T_243 = _T_241 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@6282.8]
assign _T_244 = _T_243 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@6283.8]
assign _T_245 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@6288.8]
assign _T_246 = _T_245 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@6289.8]
assign _T_248 = _T_246 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@6291.8]
assign _T_249 = _T_248 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@6292.8]
assign _T_250 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@6297.8]
assign _T_252 = _T_250 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@6299.8]
assign _T_253 = _T_252 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@6300.8]
assign _T_254 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@6306.6]
assign _T_352 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@6424.8]
assign _T_354 = _T_352 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@6426.8]
assign _T_355 = _T_354 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@6427.8]
assign _T_365 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@6450.6]
assign _T_400 = _T_153 | _T_163; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6486.8]
assign _T_401 = _T_400 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6487.8]
assign _T_402 = _T_401 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6488.8]
assign _T_403 = _T_402 | _T_178; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6489.8]
assign _T_404 = _T_403 | _T_193; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6490.8]
assign _T_405 = _T_186 & _T_404; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6491.8]
assign _T_407 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6493.8]
assign _T_415 = _T_407 & _T_158; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6501.8]
assign _T_417 = _T_405 | _T_415; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@6503.8]
assign _T_419 = _T_417 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6505.8]
assign _T_420 = _T_419 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6506.8]
assign _T_427 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@6525.8]
assign _T_429 = _T_427 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@6527.8]
assign _T_430 = _T_429 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@6528.8]
assign _T_431 = io_in_a_bits_mask == _T_110; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@6533.8]
assign _T_433 = _T_431 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@6535.8]
assign _T_434 = _T_433 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@6536.8]
assign _T_439 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@6550.6]
assign _T_471 = _T_163 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6583.8]
assign _T_472 = _T_471 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6584.8]
assign _T_473 = _T_472 | _T_193; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6585.8]
assign _T_474 = _T_186 & _T_473; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6586.8]
assign _T_476 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6588.8]
assign _T_484 = _T_476 & _T_153; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6596.8]
assign _T_497 = _T_474 | _T_484; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@6609.8]
assign _T_498 = _T_497 | _T_415; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@6610.8]
assign _T_500 = _T_498 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6612.8]
assign _T_501 = _T_500 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6613.8]
assign _T_516 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@6649.6]
assign _T_589 = ~ _T_110; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@6739.8]
assign _T_590 = io_in_a_bits_mask & _T_589; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@6740.8]
assign _T_591 = _T_590 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@6741.8]
assign _T_593 = _T_591 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@6743.8]
assign _T_594 = _T_593 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@6744.8]
assign _T_595 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@6750.6]
assign _T_616 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@6772.8]
assign _T_639 = _T_158 | _T_163; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6795.8]
assign _T_640 = _T_639 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6796.8]
assign _T_641 = _T_640 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@6797.8]
assign _T_642 = _T_616 & _T_641; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@6798.8]
assign _T_646 = _T_642 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6802.8]
assign _T_647 = _T_646 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6803.8]
assign _T_654 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@6822.8]
assign _T_656 = _T_654 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@6824.8]
assign _T_657 = _T_656 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@6825.8]
assign _T_662 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@6839.6]
assign _T_721 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@6911.8]
assign _T_723 = _T_721 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@6913.8]
assign _T_724 = _T_723 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@6914.8]
assign _T_729 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@6928.6]
assign _T_780 = _T_415 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6980.8]
assign _T_781 = _T_780 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6981.8]
assign _T_796 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@7019.6]
assign _T_798 = _T_796 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@7021.6]
assign _T_799 = _T_798 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@7022.6]
assign _T_802 = io_in_d_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@7029.6]
assign _T_803 = _T_802 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@7030.6]
assign _T_808 = io_in_d_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7035.6]
assign _T_809 = io_in_d_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7036.6]
assign _T_819 = _T_803 | _T_808; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7042.6]
assign _T_820 = _T_819 | _T_809; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7043.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@7045.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7048.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7049.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@7054.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@7056.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@7057.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@7062.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@7064.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@7065.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@7070.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@7072.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@7073.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@7078.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@7080.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@7081.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@7087.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@7111.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@7113.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@7114.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@7119.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@7121.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@7122.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@7145.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@7186.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@7188.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@7189.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@7204.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@7239.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@7275.6]
assign _T_965 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7330.6]
assign _T_991 = io_in_b_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7360.6]
assign _T_992 = {1'b0,$signed(_T_991)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7361.6]
assign _T_993 = $signed(_T_992) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7362.6]
assign _T_994 = $signed(_T_993); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7363.6]
assign _T_995 = $signed(_T_994) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7364.6]
assign _T_996 = io_in_b_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7365.6]
assign _T_997 = {1'b0,$signed(_T_996)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7366.6]
assign _T_998 = $signed(_T_997) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7367.6]
assign _T_999 = $signed(_T_998); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7368.6]
assign _T_1000 = $signed(_T_999) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7369.6]
assign _T_1001 = io_in_b_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7370.6]
assign _T_1002 = {1'b0,$signed(_T_1001)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7371.6]
assign _T_1003 = $signed(_T_1002) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7372.6]
assign _T_1004 = $signed(_T_1003); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7373.6]
assign _T_1005 = $signed(_T_1004) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7374.6]
assign _T_1006 = io_in_b_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7375.6]
assign _T_1007 = {1'b0,$signed(_T_1006)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7376.6]
assign _T_1008 = $signed(_T_1007) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7377.6]
assign _T_1009 = $signed(_T_1008); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7378.6]
assign _T_1010 = $signed(_T_1009) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7379.6]
assign _T_1013 = $signed(_T_965) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7382.6]
assign _T_1014 = $signed(_T_1013); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7383.6]
assign _T_1015 = $signed(_T_1014) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7384.6]
assign _T_1016 = io_in_b_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7385.6]
assign _T_1017 = {1'b0,$signed(_T_1016)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7386.6]
assign _T_1018 = $signed(_T_1017) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7387.6]
assign _T_1019 = $signed(_T_1018); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7388.6]
assign _T_1020 = $signed(_T_1019) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7389.6]
assign _T_1021 = io_in_b_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7390.6]
assign _T_1022 = {1'b0,$signed(_T_1021)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7391.6]
assign _T_1023 = $signed(_T_1022) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7392.6]
assign _T_1024 = $signed(_T_1023); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7393.6]
assign _T_1025 = $signed(_T_1024) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7394.6]
assign _T_1039 = _T_995 | _T_1000; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7404.6]
assign _T_1040 = _T_1039 | _T_1005; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7405.6]
assign _T_1041 = _T_1040 | _T_1010; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7406.6]
assign _T_1042 = _T_1041 | _T_1015; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7407.6]
assign _T_1043 = _T_1042 | _T_1020; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7408.6]
assign _T_1044 = _T_1043 | _T_1025; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7409.6]
assign _T_1046 = 27'hfff << 4'h6; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@7411.6]
assign _T_1047 = _T_1046[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@7412.6]
assign _T_1048 = ~ _T_1047; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@7413.6]
assign _GEN_34 = {{20'd0}, _T_1048}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7414.6]
assign _T_1049 = io_in_b_bits_address & _GEN_34; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7414.6]
assign _T_1050 = _T_1049 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@7415.6]
assign _T_1176 = _T_1044 | reset; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@7536.8]
assign _T_1177 = _T_1176 == 1'h0; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@7537.8]
assign _T_1182 = _T_1050 | reset; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@7550.8]
assign _T_1183 = _T_1182 == 1'h0; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@7551.8]
assign _T_1184 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@7556.8]
assign _T_1186 = _T_1184 | reset; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@7558.8]
assign _T_1187 = _T_1186 == 1'h0; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@7559.8]
assign _T_1334 = io_in_c_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@7885.6]
assign _T_1335 = _T_1334 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@7886.6]
assign _T_1340 = io_in_c_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7891.6]
assign _T_1341 = io_in_c_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@7892.6]
assign _T_1351 = _T_1335 | _T_1340; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7898.6]
assign _T_1352 = _T_1351 | _T_1341; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@7899.6]
assign _T_1354 = 27'hfff << io_in_c_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@7901.6]
assign _T_1355 = _T_1354[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@7902.6]
assign _T_1356 = ~ _T_1355; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@7903.6]
assign _GEN_35 = {{20'd0}, _T_1356}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7904.6]
assign _T_1357 = io_in_c_bits_address & _GEN_35; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@7904.6]
assign _T_1358 = _T_1357 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@7905.6]
assign _T_1359 = io_in_c_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7906.6]
assign _T_1360 = {1'b0,$signed(_T_1359)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7907.6]
assign _T_1361 = $signed(_T_1360) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7908.6]
assign _T_1362 = $signed(_T_1361); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7909.6]
assign _T_1363 = $signed(_T_1362) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7910.6]
assign _T_1364 = io_in_c_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7911.6]
assign _T_1365 = {1'b0,$signed(_T_1364)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7912.6]
assign _T_1366 = $signed(_T_1365) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7913.6]
assign _T_1367 = $signed(_T_1366); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7914.6]
assign _T_1368 = $signed(_T_1367) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7915.6]
assign _T_1369 = io_in_c_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7916.6]
assign _T_1370 = {1'b0,$signed(_T_1369)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7917.6]
assign _T_1371 = $signed(_T_1370) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7918.6]
assign _T_1372 = $signed(_T_1371); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7919.6]
assign _T_1373 = $signed(_T_1372) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7920.6]
assign _T_1374 = io_in_c_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7921.6]
assign _T_1375 = {1'b0,$signed(_T_1374)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7922.6]
assign _T_1376 = $signed(_T_1375) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7923.6]
assign _T_1377 = $signed(_T_1376); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7924.6]
assign _T_1378 = $signed(_T_1377) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7925.6]
assign _T_1380 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7927.6]
assign _T_1381 = $signed(_T_1380) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7928.6]
assign _T_1382 = $signed(_T_1381); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7929.6]
assign _T_1383 = $signed(_T_1382) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7930.6]
assign _T_1384 = io_in_c_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7931.6]
assign _T_1385 = {1'b0,$signed(_T_1384)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7932.6]
assign _T_1386 = $signed(_T_1385) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7933.6]
assign _T_1387 = $signed(_T_1386); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7934.6]
assign _T_1388 = $signed(_T_1387) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7935.6]
assign _T_1389 = io_in_c_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@7936.6]
assign _T_1390 = {1'b0,$signed(_T_1389)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@7937.6]
assign _T_1391 = $signed(_T_1390) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7938.6]
assign _T_1392 = $signed(_T_1391); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@7939.6]
assign _T_1393 = $signed(_T_1392) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@7940.6]
assign _T_1407 = _T_1363 | _T_1368; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7950.6]
assign _T_1408 = _T_1407 | _T_1373; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7951.6]
assign _T_1409 = _T_1408 | _T_1378; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7952.6]
assign _T_1410 = _T_1409 | _T_1383; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7953.6]
assign _T_1411 = _T_1410 | _T_1388; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7954.6]
assign _T_1412 = _T_1411 | _T_1393; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@7955.6]
assign _T_1449 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 207:25:freechips.rocketchip.system.LowRiscConfig.fir@7996.6]
assign _T_1451 = _T_1412 | reset; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@7999.8]
assign _T_1452 = _T_1451 == 1'h0; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@8000.8]
assign _T_1454 = _T_1352 | reset; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@8006.8]
assign _T_1455 = _T_1454 == 1'h0; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@8007.8]
assign _T_1456 = io_in_c_bits_size >= 4'h3; // @[Monitor.scala 210:27:freechips.rocketchip.system.LowRiscConfig.fir@8012.8]
assign _T_1458 = _T_1456 | reset; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@8014.8]
assign _T_1459 = _T_1458 == 1'h0; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@8015.8]
assign _T_1461 = _T_1358 | reset; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@8021.8]
assign _T_1462 = _T_1461 == 1'h0; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@8022.8]
assign _T_1463 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 121:29:freechips.rocketchip.system.LowRiscConfig.fir@8027.8]
assign _T_1465 = _T_1463 | reset; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@8029.8]
assign _T_1466 = _T_1465 == 1'h0; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@8030.8]
assign _T_1467 = io_in_c_bits_corrupt == 1'h0; // @[Monitor.scala 213:15:freechips.rocketchip.system.LowRiscConfig.fir@8035.8]
assign _T_1469 = _T_1467 | reset; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@8037.8]
assign _T_1470 = _T_1469 == 1'h0; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@8038.8]
assign _T_1471 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 216:25:freechips.rocketchip.system.LowRiscConfig.fir@8044.6]
assign _T_1489 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 224:25:freechips.rocketchip.system.LowRiscConfig.fir@8084.6]
assign _T_1528 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@8124.8]
assign _T_1536 = _T_1528 & _T_1393; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@8132.8]
assign _T_1540 = _T_1536 | reset; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8136.8]
assign _T_1541 = _T_1540 == 1'h0; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8137.8]
assign _T_1561 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@8157.8]
assign _T_1563 = _T_1335 ? _T_1561 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@8158.8]
assign _T_1571 = _T_1563 | reset; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@8166.8]
assign _T_1572 = _T_1571 == 1'h0; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@8167.8]
assign _T_1583 = io_in_c_bits_param <= 3'h2; // @[Bundles.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@8194.8]
assign _T_1585 = _T_1583 | reset; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@8196.8]
assign _T_1586 = _T_1585 == 1'h0; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@8197.8]
assign _T_1591 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 234:25:freechips.rocketchip.system.LowRiscConfig.fir@8211.6]
assign _T_1689 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@8330.6]
assign _T_1699 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 247:28:freechips.rocketchip.system.LowRiscConfig.fir@8353.8]
assign _T_1701 = _T_1699 | reset; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@8355.8]
assign _T_1702 = _T_1701 == 1'h0; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@8356.8]
assign _T_1707 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 251:25:freechips.rocketchip.system.LowRiscConfig.fir@8370.6]
assign _T_1721 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 258:25:freechips.rocketchip.system.LowRiscConfig.fir@8402.6]
assign _T_1743 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8453.4]
assign _T_1748 = _T_44[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@8458.4]
assign _T_1749 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@8459.4]
assign _T_1750 = _T_1749 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@8460.4]
assign _T_1754 = _T_1753 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8463.4]
assign _T_1755 = $unsigned(_T_1754); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8464.4]
assign _T_1756 = _T_1755[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8465.4]
assign _T_1757 = _T_1753 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8466.4]
assign _T_1775 = _T_1757 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@8482.4]
assign _T_1776 = io_in_a_valid & _T_1775; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@8483.4]
assign _T_1777 = io_in_a_bits_opcode == _T_1766; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@8485.6]
assign _T_1779 = _T_1777 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@8487.6]
assign _T_1780 = _T_1779 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@8488.6]
assign _T_1781 = io_in_a_bits_param == _T_1768; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@8493.6]
assign _T_1783 = _T_1781 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@8495.6]
assign _T_1784 = _T_1783 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@8496.6]
assign _T_1785 = io_in_a_bits_size == _T_1770; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@8501.6]
assign _T_1787 = _T_1785 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@8503.6]
assign _T_1788 = _T_1787 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@8504.6]
assign _T_1789 = io_in_a_bits_source == _T_1772; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@8509.6]
assign _T_1791 = _T_1789 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@8511.6]
assign _T_1792 = _T_1791 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@8512.6]
assign _T_1793 = io_in_a_bits_address == _T_1774; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@8517.6]
assign _T_1795 = _T_1793 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@8519.6]
assign _T_1796 = _T_1795 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@8520.6]
assign _T_1798 = _T_1743 & _T_1757; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@8527.4]
assign _T_1799 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8535.4]
assign _T_1801 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@8537.4]
assign _T_1802 = _T_1801[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@8538.4]
assign _T_1803 = ~ _T_1802; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@8539.4]
assign _T_1804 = _T_1803[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@8540.4]
assign _T_1805 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@8541.4]
assign _T_1809 = _T_1808 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8544.4]
assign _T_1810 = $unsigned(_T_1809); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8545.4]
assign _T_1811 = _T_1810[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8546.4]
assign _T_1812 = _T_1808 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8547.4]
assign _T_1832 = _T_1812 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@8564.4]
assign _T_1833 = io_in_d_valid & _T_1832; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@8565.4]
assign _T_1834 = io_in_d_bits_opcode == _T_1821; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@8567.6]
assign _T_1836 = _T_1834 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@8569.6]
assign _T_1837 = _T_1836 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@8570.6]
assign _T_1838 = io_in_d_bits_param == _T_1823; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@8575.6]
assign _T_1840 = _T_1838 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@8577.6]
assign _T_1841 = _T_1840 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@8578.6]
assign _T_1842 = io_in_d_bits_size == _T_1825; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@8583.6]
assign _T_1844 = _T_1842 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@8585.6]
assign _T_1845 = _T_1844 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@8586.6]
assign _T_1846 = io_in_d_bits_source == _T_1827; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@8591.6]
assign _T_1848 = _T_1846 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@8593.6]
assign _T_1849 = _T_1848 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@8594.6]
assign _T_1850 = io_in_d_bits_sink == _T_1829; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@8599.6]
assign _T_1852 = _T_1850 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@8601.6]
assign _T_1853 = _T_1852 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@8602.6]
assign _T_1854 = io_in_d_bits_denied == _T_1831; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@8607.6]
assign _T_1856 = _T_1854 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@8609.6]
assign _T_1857 = _T_1856 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@8610.6]
assign _T_1859 = _T_1799 & _T_1812; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@8617.4]
assign _T_1860 = io_in_b_ready & io_in_b_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8626.4]
assign _T_1871 = _T_1870 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8636.4]
assign _T_1872 = $unsigned(_T_1871); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8637.4]
assign _T_1873 = _T_1872[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8638.4]
assign _T_1874 = _T_1870 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8639.4]
assign _T_1892 = _T_1874 == 1'h0; // @[Monitor.scala 377:22:freechips.rocketchip.system.LowRiscConfig.fir@8655.4]
assign _T_1893 = io_in_b_valid & _T_1892; // @[Monitor.scala 377:19:freechips.rocketchip.system.LowRiscConfig.fir@8656.4]
assign _T_1898 = io_in_b_bits_param == _T_1885; // @[Monitor.scala 379:29:freechips.rocketchip.system.LowRiscConfig.fir@8666.6]
assign _T_1900 = _T_1898 | reset; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@8668.6]
assign _T_1901 = _T_1900 == 1'h0; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@8669.6]
assign _T_1910 = io_in_b_bits_address == _T_1891; // @[Monitor.scala 382:29:freechips.rocketchip.system.LowRiscConfig.fir@8690.6]
assign _T_1912 = _T_1910 | reset; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@8692.6]
assign _T_1913 = _T_1912 == 1'h0; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@8693.6]
assign _T_1915 = _T_1860 & _T_1874; // @[Monitor.scala 384:20:freechips.rocketchip.system.LowRiscConfig.fir@8700.4]
assign _T_1916 = io_in_c_ready & io_in_c_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@8708.4]
assign _T_1921 = _T_1356[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@8713.4]
assign _T_1922 = io_in_c_bits_opcode[0]; // @[Edges.scala 102:36:freechips.rocketchip.system.LowRiscConfig.fir@8714.4]
assign _T_1926 = _T_1925 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8717.4]
assign _T_1927 = $unsigned(_T_1926); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8718.4]
assign _T_1928 = _T_1927[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8719.4]
assign _T_1929 = _T_1925 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8720.4]
assign _T_1947 = _T_1929 == 1'h0; // @[Monitor.scala 400:22:freechips.rocketchip.system.LowRiscConfig.fir@8736.4]
assign _T_1948 = io_in_c_valid & _T_1947; // @[Monitor.scala 400:19:freechips.rocketchip.system.LowRiscConfig.fir@8737.4]
assign _T_1949 = io_in_c_bits_opcode == _T_1938; // @[Monitor.scala 401:29:freechips.rocketchip.system.LowRiscConfig.fir@8739.6]
assign _T_1951 = _T_1949 | reset; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@8741.6]
assign _T_1952 = _T_1951 == 1'h0; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@8742.6]
assign _T_1953 = io_in_c_bits_param == _T_1940; // @[Monitor.scala 402:29:freechips.rocketchip.system.LowRiscConfig.fir@8747.6]
assign _T_1955 = _T_1953 | reset; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@8749.6]
assign _T_1956 = _T_1955 == 1'h0; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@8750.6]
assign _T_1957 = io_in_c_bits_size == _T_1942; // @[Monitor.scala 403:29:freechips.rocketchip.system.LowRiscConfig.fir@8755.6]
assign _T_1959 = _T_1957 | reset; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@8757.6]
assign _T_1960 = _T_1959 == 1'h0; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@8758.6]
assign _T_1961 = io_in_c_bits_source == _T_1944; // @[Monitor.scala 404:29:freechips.rocketchip.system.LowRiscConfig.fir@8763.6]
assign _T_1963 = _T_1961 | reset; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@8765.6]
assign _T_1964 = _T_1963 == 1'h0; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@8766.6]
assign _T_1965 = io_in_c_bits_address == _T_1946; // @[Monitor.scala 405:29:freechips.rocketchip.system.LowRiscConfig.fir@8771.6]
assign _T_1967 = _T_1965 | reset; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@8773.6]
assign _T_1968 = _T_1967 == 1'h0; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@8774.6]
assign _T_1970 = _T_1916 & _T_1929; // @[Monitor.scala 407:20:freechips.rocketchip.system.LowRiscConfig.fir@8781.4]
assign _T_1984 = _T_1983 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8800.4]
assign _T_1985 = $unsigned(_T_1984); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8801.4]
assign _T_1986 = _T_1985[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8802.4]
assign _T_1987 = _T_1983 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8803.4]
assign _T_2005 = _T_2004 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8823.4]
assign _T_2006 = $unsigned(_T_2005); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8824.4]
assign _T_2007 = _T_2006[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8825.4]
assign _T_2008 = _T_2004 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8826.4]
assign _T_2019 = _T_1743 & _T_1987; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@8841.4]
assign _T_2021 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8844.6]
assign _T_2022 = _T_1972 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@8846.6]
assign _T_2023 = _T_2022[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@8847.6]
assign _T_2024 = _T_2023 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@8848.6]
assign _T_2026 = _T_2024 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@8850.6]
assign _T_2027 = _T_2026 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@8851.6]
assign _GEN_27 = _T_2019 ? _T_2021 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@8843.4]
assign _T_2032 = _T_1799 & _T_2008; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@8862.4]
assign _T_2034 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@8864.4]
assign _T_2035 = _T_2032 & _T_2034; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@8865.4]
assign _T_2036 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8867.6]
assign _T_2017 = _GEN_27[8:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@8837.4 :freechips.rocketchip.system.LowRiscConfig.fir@8839.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@8845.6]
assign _T_2037 = _T_2017 | _T_1972; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@8869.6]
assign _T_2038 = _T_2037 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@8870.6]
assign _T_2039 = _T_2038[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@8871.6]
assign _T_2041 = _T_2039 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@8873.6]
assign _T_2042 = _T_2041 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@8874.6]
assign _GEN_28 = _T_2035 ? _T_2036 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@8866.4]
assign _T_2029 = _GEN_28[8:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@8857.4 :freechips.rocketchip.system.LowRiscConfig.fir@8859.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@8868.6]
assign _T_2043 = _T_2017 != _T_2029; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@8880.4]
assign _T_2044 = _T_2017 != 9'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@8881.4]
assign _T_2045 = _T_2044 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@8882.4]
assign _T_2046 = _T_2043 | _T_2045; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@8883.4]
assign _T_2048 = _T_2046 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@8885.4]
assign _T_2049 = _T_2048 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@8886.4]
assign _T_2050 = _T_1972 | _T_2017; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@8891.4]
assign _T_2051 = ~ _T_2029; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@8892.4]
assign _T_2052 = _T_2050 & _T_2051; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@8893.4]
assign _T_2055 = _T_1972 != 9'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@8898.4]
assign _T_2056 = _T_2055 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@8899.4]
assign _T_2057 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@8900.4]
assign _T_2058 = _T_2056 | _T_2057; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@8901.4]
assign _T_2059 = _T_2054 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@8902.4]
assign _T_2060 = _T_2058 | _T_2059; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@8903.4]
assign _T_2062 = _T_2060 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@8905.4]
assign _T_2063 = _T_2062 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@8906.4]
assign _T_2065 = _T_2054 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@8912.4]
assign _T_2068 = _T_1743 | _T_1799; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@8916.4]
assign _T_2081 = _T_2080 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8930.4]
assign _T_2082 = $unsigned(_T_2081); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8931.4]
assign _T_2083 = _T_2082[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@8932.4]
assign _T_2084 = _T_2080 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@8933.4]
assign _T_2095 = _T_1799 & _T_2084; // @[Monitor.scala 492:27:freechips.rocketchip.system.LowRiscConfig.fir@8948.4]
assign _T_2096 = io_in_d_bits_opcode[2]; // @[Edges.scala 71:36:freechips.rocketchip.system.LowRiscConfig.fir@8949.4]
assign _T_2097 = io_in_d_bits_opcode[1]; // @[Edges.scala 71:52:freechips.rocketchip.system.LowRiscConfig.fir@8950.4]
assign _T_2098 = _T_2097 == 1'h0; // @[Edges.scala 71:43:freechips.rocketchip.system.LowRiscConfig.fir@8951.4]
assign _T_2099 = _T_2096 & _T_2098; // @[Edges.scala 71:40:freechips.rocketchip.system.LowRiscConfig.fir@8952.4]
assign _T_2100 = _T_2095 & _T_2099; // @[Monitor.scala 492:38:freechips.rocketchip.system.LowRiscConfig.fir@8953.4]
assign _T_2101 = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8955.6]
assign _T_2102 = _T_2070 >> io_in_d_bits_sink; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@8957.6]
assign _T_2103 = _T_2102[0]; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@8958.6]
assign _T_2104 = _T_2103 == 1'h0; // @[Monitor.scala 494:14:freechips.rocketchip.system.LowRiscConfig.fir@8959.6]
assign _T_2106 = _T_2104 | reset; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@8961.6]
assign _T_2107 = _T_2106 == 1'h0; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@8962.6]
assign _GEN_31 = _T_2100 ? _T_2101 : 4'h0; // @[Monitor.scala 492:72:freechips.rocketchip.system.LowRiscConfig.fir@8954.4]
assign _T_2113 = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@8975.6]
assign _T_2114 = _GEN_31 | _T_2070; // @[Monitor.scala 500:21:freechips.rocketchip.system.LowRiscConfig.fir@8977.6]
assign _T_2115 = _T_2114 >> io_in_e_bits_sink; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@8978.6]
assign _T_2116 = _T_2115[0]; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@8979.6]
assign _T_2118 = _T_2116 | reset; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@8981.6]
assign _T_2119 = _T_2118 == 1'h0; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@8982.6]
assign _GEN_32 = io_in_e_valid ? _T_2113 : 4'h0; // @[Monitor.scala 498:73:freechips.rocketchip.system.LowRiscConfig.fir@8974.4]
assign _T_2120 = _T_2070 | _GEN_31; // @[Monitor.scala 505:27:freechips.rocketchip.system.LowRiscConfig.fir@8988.4]
assign _T_2121 = ~ _GEN_32; // @[Monitor.scala 505:38:freechips.rocketchip.system.LowRiscConfig.fir@8989.4]
assign _T_2122 = _T_2120 & _T_2121; // @[Monitor.scala 505:36:freechips.rocketchip.system.LowRiscConfig.fir@8990.4]
assign _GEN_36 = io_in_a_valid & _T_147; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6225.10]
assign _GEN_52 = io_in_a_valid & _T_254; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@6361.10]
assign _GEN_70 = io_in_a_valid & _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6508.10]
assign _GEN_82 = io_in_a_valid & _T_439; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6615.10]
assign _GEN_92 = io_in_a_valid & _T_516; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@6714.10]
assign _GEN_102 = io_in_a_valid & _T_595; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6805.10]
assign _GEN_112 = io_in_a_valid & _T_662; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@6894.10]
assign _GEN_122 = io_in_a_valid & _T_729; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6983.10]
assign _GEN_132 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7051.10]
assign _GEN_142 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@7093.10]
assign _GEN_152 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@7151.10]
assign _GEN_162 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@7210.10]
assign _GEN_168 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@7245.10]
assign _GEN_174 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@7281.10]
assign _GEN_180 = io_in_c_valid & _T_1449; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@8002.10]
assign _GEN_192 = io_in_c_valid & _T_1471; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@8050.10]
assign _GEN_202 = io_in_c_valid & _T_1489; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8139.10]
assign _GEN_216 = io_in_c_valid & _T_1591; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@8266.10]
assign _GEN_228 = io_in_c_valid & _T_1689; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@8336.10]
assign _GEN_238 = io_in_c_valid & _T_1707; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@8376.10]
assign _GEN_246 = io_in_c_valid & _T_1721; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@8408.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1753 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1766 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1768 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1770 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_1772 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_1774 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1808 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1821 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1823 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1825 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1827 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1829 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1831 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1870 = _RAND_13[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1885 = _RAND_14[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1891 = _RAND_15[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1925 = _RAND_16[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_1938 = _RAND_17[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_1940 = _RAND_18[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_1942 = _RAND_19[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_1944 = _RAND_20[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_1946 = _RAND_21[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_22 = {1{`RANDOM}};
_T_1972 = _RAND_22[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_23 = {1{`RANDOM}};
_T_1983 = _RAND_23[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_24 = {1{`RANDOM}};
_T_2004 = _RAND_24[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_25 = {1{`RANDOM}};
_T_2054 = _RAND_25[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_26 = {1{`RANDOM}};
_T_2070 = _RAND_26[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_27 = {1{`RANDOM}};
_T_2080 = _RAND_27[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_1753 <= 9'h0;
end else begin
if (_T_1743) begin
if (_T_1757) begin
if (_T_1750) begin
_T_1753 <= _T_1748;
end else begin
_T_1753 <= 9'h0;
end
end else begin
_T_1753 <= _T_1756;
end
end
end
if (_T_1798) begin
_T_1766 <= io_in_a_bits_opcode;
end
if (_T_1798) begin
_T_1768 <= io_in_a_bits_param;
end
if (_T_1798) begin
_T_1770 <= io_in_a_bits_size;
end
if (_T_1798) begin
_T_1772 <= io_in_a_bits_source;
end
if (_T_1798) begin
_T_1774 <= io_in_a_bits_address;
end
if (reset) begin
_T_1808 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_1812) begin
if (_T_1805) begin
_T_1808 <= _T_1804;
end else begin
_T_1808 <= 9'h0;
end
end else begin
_T_1808 <= _T_1811;
end
end
end
if (_T_1859) begin
_T_1821 <= io_in_d_bits_opcode;
end
if (_T_1859) begin
_T_1823 <= io_in_d_bits_param;
end
if (_T_1859) begin
_T_1825 <= io_in_d_bits_size;
end
if (_T_1859) begin
_T_1827 <= io_in_d_bits_source;
end
if (_T_1859) begin
_T_1829 <= io_in_d_bits_sink;
end
if (_T_1859) begin
_T_1831 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1870 <= 9'h0;
end else begin
if (_T_1860) begin
if (_T_1874) begin
_T_1870 <= 9'h0;
end else begin
_T_1870 <= _T_1873;
end
end
end
if (_T_1915) begin
_T_1885 <= io_in_b_bits_param;
end
if (_T_1915) begin
_T_1891 <= io_in_b_bits_address;
end
if (reset) begin
_T_1925 <= 9'h0;
end else begin
if (_T_1916) begin
if (_T_1929) begin
if (_T_1922) begin
_T_1925 <= _T_1921;
end else begin
_T_1925 <= 9'h0;
end
end else begin
_T_1925 <= _T_1928;
end
end
end
if (_T_1970) begin
_T_1938 <= io_in_c_bits_opcode;
end
if (_T_1970) begin
_T_1940 <= io_in_c_bits_param;
end
if (_T_1970) begin
_T_1942 <= io_in_c_bits_size;
end
if (_T_1970) begin
_T_1944 <= io_in_c_bits_source;
end
if (_T_1970) begin
_T_1946 <= io_in_c_bits_address;
end
if (reset) begin
_T_1972 <= 9'h0;
end else begin
_T_1972 <= _T_2052;
end
if (reset) begin
_T_1983 <= 9'h0;
end else begin
if (_T_1743) begin
if (_T_1987) begin
if (_T_1750) begin
_T_1983 <= _T_1748;
end else begin
_T_1983 <= 9'h0;
end
end else begin
_T_1983 <= _T_1986;
end
end
end
if (reset) begin
_T_2004 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_2008) begin
if (_T_1805) begin
_T_2004 <= _T_1804;
end else begin
_T_2004 <= 9'h0;
end
end else begin
_T_2004 <= _T_2007;
end
end
end
if (reset) begin
_T_2054 <= 32'h0;
end else begin
if (_T_2068) begin
_T_2054 <= 32'h0;
end else begin
_T_2054 <= _T_2065;
end
end
if (reset) begin
_T_2070 <= 4'h0;
end else begin
_T_2070 <= _T_2122;
end
if (reset) begin
_T_2080 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_2084) begin
if (_T_1805) begin
_T_2080 <= _T_1804;
end else begin
_T_2080 <= 9'h0;
end
end else begin
_T_2080 <= _T_2083;
end
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at SystemBus.scala:32:39)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@6040.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@6041.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@6167.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@6168.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_199) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6225.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_199) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@6226.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_230) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:32:39)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@6255.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_230) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@6256.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@6262.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_233) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@6263.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_237) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@6270.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_237) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@6271.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@6277.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_240) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@6278.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_244) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:32:39)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@6285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_244) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@6286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_249) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@6294.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_249) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@6295.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@6302.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_253) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@6303.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_199) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@6361.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_199) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@6362.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_230) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:32:39)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@6391.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_230) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@6392.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@6398.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_233) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@6399.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_237) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@6406.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_237) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@6407.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@6413.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_240) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@6414.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_244) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:32:39)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@6421.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_244) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@6422.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_355) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:32:39)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@6429.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_355) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@6430.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_249) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@6438.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_249) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@6439.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@6446.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_253) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@6447.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_420) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6508.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_420) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@6509.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@6515.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_233) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@6516.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@6522.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_240) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@6523.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@6530.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_430) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@6531.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@6538.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_434) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@6539.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@6546.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_253) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@6547.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_501) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6615.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_501) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@6616.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@6622.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_233) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@6623.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@6629.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_240) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@6630.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@6637.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_430) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@6638.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@6645.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_434) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@6646.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_501) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@6714.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_501) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@6715.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@6721.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_233) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@6722.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@6728.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_240) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@6729.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@6736.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_430) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@6737.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_594) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@6746.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_594) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@6747.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_647) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6805.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_647) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@6806.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@6812.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_233) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@6813.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@6819.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_240) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@6820.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_657) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:32:39)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@6827.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_657) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@6828.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@6835.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_434) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@6836.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_647) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@6894.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_647) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@6895.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@6901.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_233) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@6902.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@6908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_240) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@6909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_724) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:32:39)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@6916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_724) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@6917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@6924.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_434) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@6925.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_781) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6983.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_781) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@6984.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@6990.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_233) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@6991.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@6997.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_240) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@6998.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@7005.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_434) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@7006.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@7013.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_253) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@7014.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_799) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:32:39)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@7024.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_799) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@7025.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7051.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@7052.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@7059.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@7060.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@7067.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@7068.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@7075.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@7076.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:32:39)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@7083.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@7084.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@7093.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@7094.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@7100.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@7101.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@7108.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@7109.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:32:39)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@7116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@7117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:32:39)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@7124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@7125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@7132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@7133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at SystemBus.scala:32:39)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@7141.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@7142.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@7151.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@7152.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@7158.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@7159.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@7166.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@7167.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:32:39)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@7174.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@7175.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:32:39)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@7182.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@7183.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@7191.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@7192.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at SystemBus.scala:32:39)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@7200.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@7201.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@7210.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@7211.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@7218.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@7219.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@7226.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@7227.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at SystemBus.scala:32:39)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@7235.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@7236.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@7245.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@7246.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@7253.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@7254.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@7262.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@7263.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at SystemBus.scala:32:39)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@7271.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@7272.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@7281.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@7282.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@7289.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@7290.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@7297.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@7298.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at SystemBus.scala:32:39)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@7306.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@7307.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel has invalid opcode (connected at SystemBus.scala:32:39)\n at Monitor.scala:122 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 122:12:freechips.rocketchip.system.LowRiscConfig.fir@7317.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 122:12:freechips.rocketchip.system.LowRiscConfig.fir@7318.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:124 assert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 124:12:freechips.rocketchip.system.LowRiscConfig.fir@7357.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 124:12:freechips.rocketchip.system.LowRiscConfig.fir@7358.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Probe type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:133 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n"); // @[Monitor.scala 133:14:freechips.rocketchip.system.LowRiscConfig.fir@7532.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 133:14:freechips.rocketchip.system.LowRiscConfig.fir@7533.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1177) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:134 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n"); // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@7539.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1177) begin
$fatal; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@7540.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:135 assert (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n"); // @[Monitor.scala 135:14:freechips.rocketchip.system.LowRiscConfig.fir@7546.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 135:14:freechips.rocketchip.system.LowRiscConfig.fir@7547.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1183) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:136 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n"); // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@7553.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1183) begin
$fatal; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@7554.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1187) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries invalid cap param (connected at SystemBus.scala:32:39)\n at Monitor.scala:137 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n"); // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@7561.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1187) begin
$fatal; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@7562.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:138 assert (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n"); // @[Monitor.scala 138:14:freechips.rocketchip.system.LowRiscConfig.fir@7569.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 138:14:freechips.rocketchip.system.LowRiscConfig.fir@7570.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:139 assert (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n"); // @[Monitor.scala 139:14:freechips.rocketchip.system.LowRiscConfig.fir@7577.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 139:14:freechips.rocketchip.system.LowRiscConfig.fir@7578.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Get type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:143 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n"); // @[Monitor.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@7587.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@7588.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:144 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n"); // @[Monitor.scala 144:14:freechips.rocketchip.system.LowRiscConfig.fir@7594.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 144:14:freechips.rocketchip.system.LowRiscConfig.fir@7595.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:145 assert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n"); // @[Monitor.scala 145:14:freechips.rocketchip.system.LowRiscConfig.fir@7601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 145:14:freechips.rocketchip.system.LowRiscConfig.fir@7602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 146:14:freechips.rocketchip.system.LowRiscConfig.fir@7608.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 146:14:freechips.rocketchip.system.LowRiscConfig.fir@7609.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:147 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 147:14:freechips.rocketchip.system.LowRiscConfig.fir@7616.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 147:14:freechips.rocketchip.system.LowRiscConfig.fir@7617.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 148:14:freechips.rocketchip.system.LowRiscConfig.fir@7624.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 148:14:freechips.rocketchip.system.LowRiscConfig.fir@7625.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:149 assert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 149:14:freechips.rocketchip.system.LowRiscConfig.fir@7632.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 149:14:freechips.rocketchip.system.LowRiscConfig.fir@7633.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:153 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n"); // @[Monitor.scala 153:14:freechips.rocketchip.system.LowRiscConfig.fir@7642.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 153:14:freechips.rocketchip.system.LowRiscConfig.fir@7643.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:154 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n"); // @[Monitor.scala 154:14:freechips.rocketchip.system.LowRiscConfig.fir@7649.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 154:14:freechips.rocketchip.system.LowRiscConfig.fir@7650.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:155 assert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n"); // @[Monitor.scala 155:14:freechips.rocketchip.system.LowRiscConfig.fir@7656.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 155:14:freechips.rocketchip.system.LowRiscConfig.fir@7657.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:156 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 156:14:freechips.rocketchip.system.LowRiscConfig.fir@7663.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 156:14:freechips.rocketchip.system.LowRiscConfig.fir@7664.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:157 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 157:14:freechips.rocketchip.system.LowRiscConfig.fir@7671.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 157:14:freechips.rocketchip.system.LowRiscConfig.fir@7672.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:158 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 158:14:freechips.rocketchip.system.LowRiscConfig.fir@7679.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 158:14:freechips.rocketchip.system.LowRiscConfig.fir@7680.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:162 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n"); // @[Monitor.scala 162:14:freechips.rocketchip.system.LowRiscConfig.fir@7689.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 162:14:freechips.rocketchip.system.LowRiscConfig.fir@7690.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:163 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n"); // @[Monitor.scala 163:14:freechips.rocketchip.system.LowRiscConfig.fir@7696.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 163:14:freechips.rocketchip.system.LowRiscConfig.fir@7697.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:164 assert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n"); // @[Monitor.scala 164:14:freechips.rocketchip.system.LowRiscConfig.fir@7703.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 164:14:freechips.rocketchip.system.LowRiscConfig.fir@7704.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:165 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 165:14:freechips.rocketchip.system.LowRiscConfig.fir@7710.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 165:14:freechips.rocketchip.system.LowRiscConfig.fir@7711.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:166 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 166:14:freechips.rocketchip.system.LowRiscConfig.fir@7718.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 166:14:freechips.rocketchip.system.LowRiscConfig.fir@7719.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:167 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@7728.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@7729.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:171 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n"); // @[Monitor.scala 171:14:freechips.rocketchip.system.LowRiscConfig.fir@7738.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 171:14:freechips.rocketchip.system.LowRiscConfig.fir@7739.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:172 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n"); // @[Monitor.scala 172:14:freechips.rocketchip.system.LowRiscConfig.fir@7745.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 172:14:freechips.rocketchip.system.LowRiscConfig.fir@7746.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:173 assert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n"); // @[Monitor.scala 173:14:freechips.rocketchip.system.LowRiscConfig.fir@7752.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 173:14:freechips.rocketchip.system.LowRiscConfig.fir@7753.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:174 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 174:14:freechips.rocketchip.system.LowRiscConfig.fir@7759.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 174:14:freechips.rocketchip.system.LowRiscConfig.fir@7760.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:32:39)\n at Monitor.scala:175 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 175:14:freechips.rocketchip.system.LowRiscConfig.fir@7767.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 175:14:freechips.rocketchip.system.LowRiscConfig.fir@7768.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:176 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@7775.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@7776.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Logical type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:180 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n"); // @[Monitor.scala 180:14:freechips.rocketchip.system.LowRiscConfig.fir@7785.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 180:14:freechips.rocketchip.system.LowRiscConfig.fir@7786.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:181 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n"); // @[Monitor.scala 181:14:freechips.rocketchip.system.LowRiscConfig.fir@7792.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 181:14:freechips.rocketchip.system.LowRiscConfig.fir@7793.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:182 assert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n"); // @[Monitor.scala 182:14:freechips.rocketchip.system.LowRiscConfig.fir@7799.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 182:14:freechips.rocketchip.system.LowRiscConfig.fir@7800.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:183 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 183:14:freechips.rocketchip.system.LowRiscConfig.fir@7806.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 183:14:freechips.rocketchip.system.LowRiscConfig.fir@7807.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries invalid opcode param (connected at SystemBus.scala:32:39)\n at Monitor.scala:184 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 184:14:freechips.rocketchip.system.LowRiscConfig.fir@7814.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 184:14:freechips.rocketchip.system.LowRiscConfig.fir@7815.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:185 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 185:14:freechips.rocketchip.system.LowRiscConfig.fir@7822.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 185:14:freechips.rocketchip.system.LowRiscConfig.fir@7823.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Hint type unsupported by client (connected at SystemBus.scala:32:39)\n at Monitor.scala:189 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n"); // @[Monitor.scala 189:14:freechips.rocketchip.system.LowRiscConfig.fir@7832.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 189:14:freechips.rocketchip.system.LowRiscConfig.fir@7833.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:190 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n"); // @[Monitor.scala 190:14:freechips.rocketchip.system.LowRiscConfig.fir@7839.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 190:14:freechips.rocketchip.system.LowRiscConfig.fir@7840.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint carries source that is not first source (connected at SystemBus.scala:32:39)\n at Monitor.scala:191 assert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n"); // @[Monitor.scala 191:14:freechips.rocketchip.system.LowRiscConfig.fir@7846.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 191:14:freechips.rocketchip.system.LowRiscConfig.fir@7847.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:192 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 192:14:freechips.rocketchip.system.LowRiscConfig.fir@7853.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 192:14:freechips.rocketchip.system.LowRiscConfig.fir@7854.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint contains invalid mask (connected at SystemBus.scala:32:39)\n at Monitor.scala:193 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 193:14:freechips.rocketchip.system.LowRiscConfig.fir@7861.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 193:14:freechips.rocketchip.system.LowRiscConfig.fir@7862.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:194 assert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 194:14:freechips.rocketchip.system.LowRiscConfig.fir@7869.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 194:14:freechips.rocketchip.system.LowRiscConfig.fir@7870.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel has invalid opcode (connected at SystemBus.scala:32:39)\n at Monitor.scala:199 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 199:12:freechips.rocketchip.system.LowRiscConfig.fir@7880.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 199:12:freechips.rocketchip.system.LowRiscConfig.fir@7881.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:205 assert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 205:12:freechips.rocketchip.system.LowRiscConfig.fir@7993.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 205:12:freechips.rocketchip.system.LowRiscConfig.fir@7994.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:208 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@8002.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1452) begin
$fatal; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@8003.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:209 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@8009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1455) begin
$fatal; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@8010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:210 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@8017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1459) begin
$fatal; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@8018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:211 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@8024.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1462) begin
$fatal; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@8025.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1466) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at SystemBus.scala:32:39)\n at Monitor.scala:212 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n"); // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@8032.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1466) begin
$fatal; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@8033.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:213 assert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n"); // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@8040.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1470) begin
$fatal; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@8041.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:217 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n"); // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@8050.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1452) begin
$fatal; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@8051.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:218 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 218:14:freechips.rocketchip.system.LowRiscConfig.fir@8057.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1455) begin
$fatal; // @[Monitor.scala 218:14:freechips.rocketchip.system.LowRiscConfig.fir@8058.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:219 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n"); // @[Monitor.scala 219:14:freechips.rocketchip.system.LowRiscConfig.fir@8065.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1459) begin
$fatal; // @[Monitor.scala 219:14:freechips.rocketchip.system.LowRiscConfig.fir@8066.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n"); // @[Monitor.scala 220:14:freechips.rocketchip.system.LowRiscConfig.fir@8072.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1462) begin
$fatal; // @[Monitor.scala 220:14:freechips.rocketchip.system.LowRiscConfig.fir@8073.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1466) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at SystemBus.scala:32:39)\n at Monitor.scala:221 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n"); // @[Monitor.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@8080.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1466) begin
$fatal; // @[Monitor.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@8081.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1541) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:225 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n"); // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8139.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1541) begin
$fatal; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@8140.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1572) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:32:39)\n at Monitor.scala:226 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@8169.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1572) begin
$fatal; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@8170.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:227 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n"); // @[Monitor.scala 227:14:freechips.rocketchip.system.LowRiscConfig.fir@8176.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1455) begin
$fatal; // @[Monitor.scala 227:14:freechips.rocketchip.system.LowRiscConfig.fir@8177.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:228 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n"); // @[Monitor.scala 228:14:freechips.rocketchip.system.LowRiscConfig.fir@8184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1459) begin
$fatal; // @[Monitor.scala 228:14:freechips.rocketchip.system.LowRiscConfig.fir@8185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:229 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n"); // @[Monitor.scala 229:14:freechips.rocketchip.system.LowRiscConfig.fir@8191.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1462) begin
$fatal; // @[Monitor.scala 229:14:freechips.rocketchip.system.LowRiscConfig.fir@8192.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1586) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release carries invalid shrink param (connected at SystemBus.scala:32:39)\n at Monitor.scala:230 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n"); // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@8199.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1586) begin
$fatal; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@8200.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:231 assert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n"); // @[Monitor.scala 231:14:freechips.rocketchip.system.LowRiscConfig.fir@8207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1470) begin
$fatal; // @[Monitor.scala 231:14:freechips.rocketchip.system.LowRiscConfig.fir@8208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1541) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at SystemBus.scala:32:39)\n at Monitor.scala:235 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n"); // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@8266.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1541) begin
$fatal; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@8267.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1572) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:32:39)\n at Monitor.scala:236 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 236:14:freechips.rocketchip.system.LowRiscConfig.fir@8296.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1572) begin
$fatal; // @[Monitor.scala 236:14:freechips.rocketchip.system.LowRiscConfig.fir@8297.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:237 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 237:14:freechips.rocketchip.system.LowRiscConfig.fir@8303.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1455) begin
$fatal; // @[Monitor.scala 237:14:freechips.rocketchip.system.LowRiscConfig.fir@8304.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at SystemBus.scala:32:39)\n at Monitor.scala:238 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n"); // @[Monitor.scala 238:14:freechips.rocketchip.system.LowRiscConfig.fir@8311.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1459) begin
$fatal; // @[Monitor.scala 238:14:freechips.rocketchip.system.LowRiscConfig.fir@8312.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:239 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n"); // @[Monitor.scala 239:14:freechips.rocketchip.system.LowRiscConfig.fir@8318.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1462) begin
$fatal; // @[Monitor.scala 239:14:freechips.rocketchip.system.LowRiscConfig.fir@8319.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1586) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at SystemBus.scala:32:39)\n at Monitor.scala:240 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n"); // @[Monitor.scala 240:14:freechips.rocketchip.system.LowRiscConfig.fir@8326.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1586) begin
$fatal; // @[Monitor.scala 240:14:freechips.rocketchip.system.LowRiscConfig.fir@8327.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:244 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@8336.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1452) begin
$fatal; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@8337.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:245 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 245:14:freechips.rocketchip.system.LowRiscConfig.fir@8343.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1455) begin
$fatal; // @[Monitor.scala 245:14:freechips.rocketchip.system.LowRiscConfig.fir@8344.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:246 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 246:14:freechips.rocketchip.system.LowRiscConfig.fir@8350.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1462) begin
$fatal; // @[Monitor.scala 246:14:freechips.rocketchip.system.LowRiscConfig.fir@8351.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:247 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@8358.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1702) begin
$fatal; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@8359.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:248 assert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 248:14:freechips.rocketchip.system.LowRiscConfig.fir@8366.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1470) begin
$fatal; // @[Monitor.scala 248:14:freechips.rocketchip.system.LowRiscConfig.fir@8367.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:252 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n"); // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@8376.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1452) begin
$fatal; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@8377.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:253 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 253:14:freechips.rocketchip.system.LowRiscConfig.fir@8383.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1455) begin
$fatal; // @[Monitor.scala 253:14:freechips.rocketchip.system.LowRiscConfig.fir@8384.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:254 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n"); // @[Monitor.scala 254:14:freechips.rocketchip.system.LowRiscConfig.fir@8390.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1462) begin
$fatal; // @[Monitor.scala 254:14:freechips.rocketchip.system.LowRiscConfig.fir@8391.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:255 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 255:14:freechips.rocketchip.system.LowRiscConfig.fir@8398.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1702) begin
$fatal; // @[Monitor.scala 255:14:freechips.rocketchip.system.LowRiscConfig.fir@8399.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries unmanaged address (connected at SystemBus.scala:32:39)\n at Monitor.scala:259 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@8408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1452) begin
$fatal; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@8409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries invalid source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:260 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 260:14:freechips.rocketchip.system.LowRiscConfig.fir@8415.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1455) begin
$fatal; // @[Monitor.scala 260:14:freechips.rocketchip.system.LowRiscConfig.fir@8416.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck address not aligned to size (connected at SystemBus.scala:32:39)\n at Monitor.scala:261 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 261:14:freechips.rocketchip.system.LowRiscConfig.fir@8422.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1462) begin
$fatal; // @[Monitor.scala 261:14:freechips.rocketchip.system.LowRiscConfig.fir@8423.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries invalid param (connected at SystemBus.scala:32:39)\n at Monitor.scala:262 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 262:14:freechips.rocketchip.system.LowRiscConfig.fir@8430.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1702) begin
$fatal; // @[Monitor.scala 262:14:freechips.rocketchip.system.LowRiscConfig.fir@8431.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck is corrupt (connected at SystemBus.scala:32:39)\n at Monitor.scala:263 assert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 263:14:freechips.rocketchip.system.LowRiscConfig.fir@8438.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1470) begin
$fatal; // @[Monitor.scala 263:14:freechips.rocketchip.system.LowRiscConfig.fir@8439.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channels carries invalid sink ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:330 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 330:12:freechips.rocketchip.system.LowRiscConfig.fir@8449.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 330:12:freechips.rocketchip.system.LowRiscConfig.fir@8450.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1780) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@8490.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1780) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@8491.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1784) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@8498.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1784) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@8499.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1788) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@8506.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1788) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@8507.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1792) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@8514.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1792) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@8515.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1796) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@8522.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1796) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@8523.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@8572.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1837) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@8573.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@8580.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1841) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@8581.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1845) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@8588.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1845) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@8589.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1849) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@8596.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1849) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@8597.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1853) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@8604.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1853) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@8605.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1857) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@8612.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1857) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@8613.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:378 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 378:14:freechips.rocketchip.system.LowRiscConfig.fir@8663.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 378:14:freechips.rocketchip.system.LowRiscConfig.fir@8664.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1893 & _T_1901) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel param changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:379 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@8671.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1893 & _T_1901) begin
$fatal; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@8672.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel size changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:380 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 380:14:freechips.rocketchip.system.LowRiscConfig.fir@8679.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 380:14:freechips.rocketchip.system.LowRiscConfig.fir@8680.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel source changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:381 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 381:14:freechips.rocketchip.system.LowRiscConfig.fir@8687.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 381:14:freechips.rocketchip.system.LowRiscConfig.fir@8688.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1893 & _T_1913) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel addresss changed with multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:382 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@8695.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1893 & _T_1913) begin
$fatal; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@8696.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1952) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:401 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@8744.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1952) begin
$fatal; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@8745.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1956) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel param changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:402 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@8752.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1956) begin
$fatal; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@8753.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1960) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel size changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:403 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@8760.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1960) begin
$fatal; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@8761.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1964) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel source changed within multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:404 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@8768.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1964) begin
$fatal; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@8769.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1968) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel address changed with multibeat operation (connected at SystemBus.scala:32:39)\n at Monitor.scala:405 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@8776.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1968) begin
$fatal; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@8777.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2019 & _T_2027) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@8853.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2019 & _T_2027) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@8854.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2035 & _T_2042) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:32:39)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@8876.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2035 & _T_2042) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@8877.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2049) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:32:39)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@8888.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2049) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@8889.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2063) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at SystemBus.scala:32:39)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@8908.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2063) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@8909.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2100 & _T_2107) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel re-used a sink ID (connected at SystemBus.scala:32:39)\n at Monitor.scala:494 assert(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n"); // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@8964.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2100 & _T_2107) begin
$fatal; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@8965.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_e_valid & _T_2119) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel acknowledged for nothing inflight (connected at SystemBus.scala:32:39)\n at Monitor.scala:500 assert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@8984.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_e_valid & _T_2119) begin
$fatal; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@8985.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLBuffer( // @[:freechips.rocketchip.system.LowRiscConfig.fir@8993.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8994.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8995.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [1:0] auto_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [31:0] auto_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [2:0] auto_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [2:0] auto_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [3:0] auto_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [3:0] auto_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [31:0] auto_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [63:0] auto_in_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [1:0] auto_in_e_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [1:0] auto_out_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [31:0] auto_out_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_out_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [2:0] auto_out_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [2:0] auto_out_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [3:0] auto_out_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [3:0] auto_out_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [31:0] auto_out_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [63:0] auto_out_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
input auto_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output auto_out_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
output [1:0] auto_out_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@8996.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_b_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_b_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [1:0] TLMonitor_io_in_b_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [31:0] TLMonitor_io_in_b_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_c_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_c_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [2:0] TLMonitor_io_in_c_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [2:0] TLMonitor_io_in_c_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [3:0] TLMonitor_io_in_c_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [3:0] TLMonitor_io_in_c_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [31:0] TLMonitor_io_in_c_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_c_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire TLMonitor_io_in_e_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
wire [1:0] TLMonitor_io_in_e_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
TLMonitor_2 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@9003.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_b_ready(TLMonitor_io_in_b_ready),
.io_in_b_valid(TLMonitor_io_in_b_valid),
.io_in_b_bits_param(TLMonitor_io_in_b_bits_param),
.io_in_b_bits_address(TLMonitor_io_in_b_bits_address),
.io_in_c_ready(TLMonitor_io_in_c_ready),
.io_in_c_valid(TLMonitor_io_in_c_valid),
.io_in_c_bits_opcode(TLMonitor_io_in_c_bits_opcode),
.io_in_c_bits_param(TLMonitor_io_in_c_bits_param),
.io_in_c_bits_size(TLMonitor_io_in_c_bits_size),
.io_in_c_bits_source(TLMonitor_io_in_c_bits_source),
.io_in_c_bits_address(TLMonitor_io_in_c_bits_address),
.io_in_c_bits_corrupt(TLMonitor_io_in_c_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt),
.io_in_e_valid(TLMonitor_io_in_e_valid),
.io_in_e_bits_sink(TLMonitor_io_in_e_bits_sink)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_b_bits_param = auto_out_b_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_b_bits_address = auto_out_b_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_c_ready = auto_out_c_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@9043.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_valid = auto_in_c_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_opcode = auto_in_c_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_param = auto_in_c_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_size = auto_in_c_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_source = auto_in_c_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_address = auto_in_c_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_data = auto_in_c_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_c_bits_corrupt = auto_in_c_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_e_valid = auto_in_e_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign auto_out_e_bits_sink = auto_in_e_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@9042.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@9005.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@9006.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_b_valid = auto_out_b_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_ready = auto_out_c_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
assign TLMonitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@9039.4]
endmodule
module TLMonitor_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@9057.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9058.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9059.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [1:0] io_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [31:0] io_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [2:0] io_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [2:0] io_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [3:0] io_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [3:0] io_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [31:0] io_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input io_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
input [1:0] io_in_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@9060.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@11928.4]
wire [1:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@9077.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@9078.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@9083.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@9084.6]
wire _T_39; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@9090.6]
wire _T_40; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@9091.6]
wire [26:0] _T_42; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@9093.6]
wire [11:0] _T_43; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@9094.6]
wire [11:0] _T_44; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@9095.6]
wire [31:0] _GEN_33; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@9096.6]
wire [31:0] _T_45; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@9096.6]
wire _T_46; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@9097.6]
wire [1:0] _T_48; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@9099.6]
wire [3:0] _T_49; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@9100.6]
wire [2:0] _T_50; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@9101.6]
wire [2:0] _T_51; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@9102.6]
wire _T_52; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@9103.6]
wire _T_53; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@9104.6]
wire _T_54; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@9105.6]
wire _T_55; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@9106.6]
wire _T_57; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9108.6]
wire _T_58; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9109.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9111.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9112.6]
wire _T_62; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@9113.6]
wire _T_63; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@9114.6]
wire _T_64; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@9115.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9116.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9117.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9118.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9119.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9120.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9121.6]
wire _T_71; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9122.6]
wire _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9123.6]
wire _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9124.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9125.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9126.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9127.6]
wire _T_77; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@9128.6]
wire _T_78; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@9129.6]
wire _T_79; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@9130.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9131.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9132.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9133.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9134.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9135.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9136.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9137.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9138.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9139.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9140.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9141.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9142.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9143.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9144.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9145.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9146.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9147.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9148.6]
wire _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9149.6]
wire _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9150.6]
wire _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9151.6]
wire _T_101; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9152.6]
wire _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9153.6]
wire _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9154.6]
wire [7:0] _T_110; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@9161.6]
wire [32:0] _T_121; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9172.6]
wire _T_147; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@9202.6]
wire [31:0] _T_149; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9205.8]
wire [32:0] _T_150; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9206.8]
wire [32:0] _T_151; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9207.8]
wire [32:0] _T_152; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9208.8]
wire _T_153; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9209.8]
wire [31:0] _T_154; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9210.8]
wire [32:0] _T_155; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9211.8]
wire [32:0] _T_156; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9212.8]
wire [32:0] _T_157; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9213.8]
wire _T_158; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9214.8]
wire [31:0] _T_159; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9215.8]
wire [32:0] _T_160; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9216.8]
wire [32:0] _T_161; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9217.8]
wire [32:0] _T_162; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9218.8]
wire _T_163; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9219.8]
wire [31:0] _T_164; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9220.8]
wire [32:0] _T_165; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9221.8]
wire [32:0] _T_166; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9222.8]
wire [32:0] _T_167; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9223.8]
wire _T_168; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9224.8]
wire [32:0] _T_171; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9227.8]
wire [32:0] _T_172; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9228.8]
wire _T_173; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9229.8]
wire [31:0] _T_174; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9230.8]
wire [32:0] _T_175; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9231.8]
wire [32:0] _T_176; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9232.8]
wire [32:0] _T_177; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9233.8]
wire _T_178; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9234.8]
wire _T_186; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9242.8]
wire [31:0] _T_189; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9245.8]
wire [32:0] _T_190; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9246.8]
wire [32:0] _T_191; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9247.8]
wire [32:0] _T_192; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9248.8]
wire _T_193; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9249.8]
wire _T_194; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9250.8]
wire _T_198; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9254.8]
wire _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9255.8]
wire _T_219; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@9275.8]
wire _T_221; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@9276.8]
wire _T_229; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@9284.8]
wire _T_230; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@9285.8]
wire _T_232; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@9291.8]
wire _T_233; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@9292.8]
wire _T_236; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@9299.8]
wire _T_237; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@9300.8]
wire _T_239; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@9306.8]
wire _T_240; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@9307.8]
wire _T_241; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@9312.8]
wire _T_243; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@9314.8]
wire _T_244; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@9315.8]
wire [7:0] _T_245; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@9320.8]
wire _T_246; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@9321.8]
wire _T_248; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@9323.8]
wire _T_249; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@9324.8]
wire _T_250; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@9329.8]
wire _T_252; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@9331.8]
wire _T_253; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@9332.8]
wire _T_254; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@9338.6]
wire _T_352; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@9456.8]
wire _T_354; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@9458.8]
wire _T_355; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@9459.8]
wire _T_365; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@9482.6]
wire _T_400; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9518.8]
wire _T_401; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9519.8]
wire _T_402; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9520.8]
wire _T_403; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9521.8]
wire _T_404; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9522.8]
wire _T_405; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9523.8]
wire _T_407; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9525.8]
wire _T_415; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9533.8]
wire _T_417; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@9535.8]
wire _T_419; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9537.8]
wire _T_420; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9538.8]
wire _T_427; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@9557.8]
wire _T_429; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@9559.8]
wire _T_430; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@9560.8]
wire _T_431; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@9565.8]
wire _T_433; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@9567.8]
wire _T_434; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@9568.8]
wire _T_439; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@9582.6]
wire _T_471; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9615.8]
wire _T_472; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9616.8]
wire _T_473; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9617.8]
wire _T_474; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9618.8]
wire _T_476; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9620.8]
wire _T_484; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9628.8]
wire _T_497; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@9641.8]
wire _T_498; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@9642.8]
wire _T_500; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9644.8]
wire _T_501; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9645.8]
wire _T_516; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@9681.6]
wire [7:0] _T_589; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@9771.8]
wire [7:0] _T_590; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@9772.8]
wire _T_591; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@9773.8]
wire _T_593; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@9775.8]
wire _T_594; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@9776.8]
wire _T_595; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@9782.6]
wire _T_616; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9804.8]
wire _T_639; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9827.8]
wire _T_640; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9828.8]
wire _T_641; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9829.8]
wire _T_642; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9830.8]
wire _T_646; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9834.8]
wire _T_647; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9835.8]
wire _T_654; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@9854.8]
wire _T_656; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@9856.8]
wire _T_657; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@9857.8]
wire _T_662; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@9871.6]
wire _T_721; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@9943.8]
wire _T_723; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@9945.8]
wire _T_724; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@9946.8]
wire _T_729; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@9960.6]
wire _T_780; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10012.8]
wire _T_781; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10013.8]
wire _T_796; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@10051.6]
wire _T_798; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@10053.6]
wire _T_799; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@10054.6]
wire [1:0] _T_802; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@10061.6]
wire _T_803; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@10062.6]
wire _T_808; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10067.6]
wire _T_809; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10068.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10074.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10075.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@10077.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10080.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10081.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@10086.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@10088.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@10089.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@10094.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@10096.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@10097.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@10102.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@10104.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@10105.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@10110.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@10112.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@10113.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@10119.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@10143.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@10145.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@10146.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@10151.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@10153.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@10154.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@10177.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@10218.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@10220.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@10221.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@10236.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@10271.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@10307.6]
wire [32:0] _T_965; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10362.6]
wire [31:0] _T_991; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10392.6]
wire [32:0] _T_992; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10393.6]
wire [32:0] _T_993; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10394.6]
wire [32:0] _T_994; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10395.6]
wire _T_995; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10396.6]
wire [31:0] _T_996; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10397.6]
wire [32:0] _T_997; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10398.6]
wire [32:0] _T_998; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10399.6]
wire [32:0] _T_999; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10400.6]
wire _T_1000; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10401.6]
wire [31:0] _T_1001; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10402.6]
wire [32:0] _T_1002; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10403.6]
wire [32:0] _T_1003; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10404.6]
wire [32:0] _T_1004; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10405.6]
wire _T_1005; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10406.6]
wire [31:0] _T_1006; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10407.6]
wire [32:0] _T_1007; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10408.6]
wire [32:0] _T_1008; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10409.6]
wire [32:0] _T_1009; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10410.6]
wire _T_1010; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10411.6]
wire [32:0] _T_1013; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10414.6]
wire [32:0] _T_1014; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10415.6]
wire _T_1015; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10416.6]
wire [31:0] _T_1016; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10417.6]
wire [32:0] _T_1017; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10418.6]
wire [32:0] _T_1018; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10419.6]
wire [32:0] _T_1019; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10420.6]
wire _T_1020; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10421.6]
wire [31:0] _T_1021; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10422.6]
wire [32:0] _T_1022; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10423.6]
wire [32:0] _T_1023; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10424.6]
wire [32:0] _T_1024; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10425.6]
wire _T_1025; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10426.6]
wire _T_1039; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10436.6]
wire _T_1040; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10437.6]
wire _T_1041; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10438.6]
wire _T_1042; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10439.6]
wire _T_1043; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10440.6]
wire _T_1044; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10441.6]
wire [26:0] _T_1046; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@10443.6]
wire [11:0] _T_1047; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@10444.6]
wire [11:0] _T_1048; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@10445.6]
wire [31:0] _GEN_34; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10446.6]
wire [31:0] _T_1049; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10446.6]
wire _T_1050; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@10447.6]
wire _T_1176; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@10568.8]
wire _T_1177; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@10569.8]
wire _T_1182; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@10582.8]
wire _T_1183; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@10583.8]
wire _T_1184; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@10588.8]
wire _T_1186; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@10590.8]
wire _T_1187; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@10591.8]
wire [1:0] _T_1334; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@10917.6]
wire _T_1335; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@10918.6]
wire _T_1340; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10923.6]
wire _T_1341; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10924.6]
wire _T_1351; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10930.6]
wire _T_1352; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10931.6]
wire [26:0] _T_1354; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@10933.6]
wire [11:0] _T_1355; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@10934.6]
wire [11:0] _T_1356; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@10935.6]
wire [31:0] _GEN_35; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10936.6]
wire [31:0] _T_1357; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10936.6]
wire _T_1358; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@10937.6]
wire [31:0] _T_1359; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10938.6]
wire [32:0] _T_1360; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10939.6]
wire [32:0] _T_1361; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10940.6]
wire [32:0] _T_1362; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10941.6]
wire _T_1363; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10942.6]
wire [31:0] _T_1364; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10943.6]
wire [32:0] _T_1365; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10944.6]
wire [32:0] _T_1366; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10945.6]
wire [32:0] _T_1367; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10946.6]
wire _T_1368; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10947.6]
wire [31:0] _T_1369; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10948.6]
wire [32:0] _T_1370; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10949.6]
wire [32:0] _T_1371; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10950.6]
wire [32:0] _T_1372; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10951.6]
wire _T_1373; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10952.6]
wire [31:0] _T_1374; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10953.6]
wire [32:0] _T_1375; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10954.6]
wire [32:0] _T_1376; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10955.6]
wire [32:0] _T_1377; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10956.6]
wire _T_1378; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10957.6]
wire [32:0] _T_1380; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10959.6]
wire [32:0] _T_1381; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10960.6]
wire [32:0] _T_1382; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10961.6]
wire _T_1383; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10962.6]
wire [31:0] _T_1384; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10963.6]
wire [32:0] _T_1385; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10964.6]
wire [32:0] _T_1386; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10965.6]
wire [32:0] _T_1387; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10966.6]
wire _T_1388; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10967.6]
wire [31:0] _T_1389; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10968.6]
wire [32:0] _T_1390; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10969.6]
wire [32:0] _T_1391; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10970.6]
wire [32:0] _T_1392; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10971.6]
wire _T_1393; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10972.6]
wire _T_1407; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10982.6]
wire _T_1408; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10983.6]
wire _T_1409; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10984.6]
wire _T_1410; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10985.6]
wire _T_1411; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10986.6]
wire _T_1412; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10987.6]
wire _T_1449; // @[Monitor.scala 207:25:freechips.rocketchip.system.LowRiscConfig.fir@11028.6]
wire _T_1451; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11031.8]
wire _T_1452; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11032.8]
wire _T_1454; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@11038.8]
wire _T_1455; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@11039.8]
wire _T_1456; // @[Monitor.scala 210:27:freechips.rocketchip.system.LowRiscConfig.fir@11044.8]
wire _T_1458; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@11046.8]
wire _T_1459; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@11047.8]
wire _T_1461; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@11053.8]
wire _T_1462; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@11054.8]
wire _T_1463; // @[Bundles.scala 121:29:freechips.rocketchip.system.LowRiscConfig.fir@11059.8]
wire _T_1465; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@11061.8]
wire _T_1466; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@11062.8]
wire _T_1467; // @[Monitor.scala 213:15:freechips.rocketchip.system.LowRiscConfig.fir@11067.8]
wire _T_1469; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@11069.8]
wire _T_1470; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@11070.8]
wire _T_1471; // @[Monitor.scala 216:25:freechips.rocketchip.system.LowRiscConfig.fir@11076.6]
wire _T_1489; // @[Monitor.scala 224:25:freechips.rocketchip.system.LowRiscConfig.fir@11116.6]
wire _T_1528; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@11156.8]
wire _T_1536; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@11164.8]
wire _T_1540; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11168.8]
wire _T_1541; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11169.8]
wire _T_1561; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@11189.8]
wire _T_1563; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@11190.8]
wire _T_1571; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@11198.8]
wire _T_1572; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@11199.8]
wire _T_1583; // @[Bundles.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@11226.8]
wire _T_1585; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@11228.8]
wire _T_1586; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@11229.8]
wire _T_1591; // @[Monitor.scala 234:25:freechips.rocketchip.system.LowRiscConfig.fir@11243.6]
wire _T_1689; // @[Monitor.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@11362.6]
wire _T_1699; // @[Monitor.scala 247:28:freechips.rocketchip.system.LowRiscConfig.fir@11385.8]
wire _T_1701; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@11387.8]
wire _T_1702; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@11388.8]
wire _T_1707; // @[Monitor.scala 251:25:freechips.rocketchip.system.LowRiscConfig.fir@11402.6]
wire _T_1721; // @[Monitor.scala 258:25:freechips.rocketchip.system.LowRiscConfig.fir@11434.6]
wire _T_1743; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11485.4]
wire [8:0] _T_1748; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@11490.4]
wire _T_1749; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@11491.4]
wire _T_1750; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@11492.4]
reg [8:0] _T_1753; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11494.4]
reg [31:0] _RAND_0;
wire [9:0] _T_1754; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11495.4]
wire [9:0] _T_1755; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11496.4]
wire [8:0] _T_1756; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11497.4]
wire _T_1757; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11498.4]
reg [2:0] _T_1766; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@11509.4]
reg [31:0] _RAND_1;
reg [2:0] _T_1768; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@11510.4]
reg [31:0] _RAND_2;
reg [3:0] _T_1770; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@11511.4]
reg [31:0] _RAND_3;
reg [3:0] _T_1772; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@11512.4]
reg [31:0] _RAND_4;
reg [31:0] _T_1774; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@11513.4]
reg [31:0] _RAND_5;
wire _T_1775; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@11514.4]
wire _T_1776; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@11515.4]
wire _T_1777; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@11517.6]
wire _T_1779; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@11519.6]
wire _T_1780; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@11520.6]
wire _T_1781; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@11525.6]
wire _T_1783; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@11527.6]
wire _T_1784; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@11528.6]
wire _T_1785; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@11533.6]
wire _T_1787; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@11535.6]
wire _T_1788; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@11536.6]
wire _T_1789; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@11541.6]
wire _T_1791; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@11543.6]
wire _T_1792; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@11544.6]
wire _T_1793; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@11549.6]
wire _T_1795; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@11551.6]
wire _T_1796; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@11552.6]
wire _T_1798; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@11559.4]
wire _T_1799; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11567.4]
wire [26:0] _T_1801; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@11569.4]
wire [11:0] _T_1802; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@11570.4]
wire [11:0] _T_1803; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@11571.4]
wire [8:0] _T_1804; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@11572.4]
wire _T_1805; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@11573.4]
reg [8:0] _T_1808; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11575.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1809; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11576.4]
wire [9:0] _T_1810; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11577.4]
wire [8:0] _T_1811; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11578.4]
wire _T_1812; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11579.4]
reg [2:0] _T_1821; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@11590.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1823; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@11591.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1825; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@11592.4]
reg [31:0] _RAND_9;
reg [3:0] _T_1827; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@11593.4]
reg [31:0] _RAND_10;
reg [1:0] _T_1829; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@11594.4]
reg [31:0] _RAND_11;
reg _T_1831; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@11595.4]
reg [31:0] _RAND_12;
wire _T_1832; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@11596.4]
wire _T_1833; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@11597.4]
wire _T_1834; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@11599.6]
wire _T_1836; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@11601.6]
wire _T_1837; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@11602.6]
wire _T_1838; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@11607.6]
wire _T_1840; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@11609.6]
wire _T_1841; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@11610.6]
wire _T_1842; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@11615.6]
wire _T_1844; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@11617.6]
wire _T_1845; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@11618.6]
wire _T_1846; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@11623.6]
wire _T_1848; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@11625.6]
wire _T_1849; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@11626.6]
wire _T_1850; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@11631.6]
wire _T_1852; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@11633.6]
wire _T_1853; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@11634.6]
wire _T_1854; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@11639.6]
wire _T_1856; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@11641.6]
wire _T_1857; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@11642.6]
wire _T_1859; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@11649.4]
wire _T_1860; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11658.4]
reg [8:0] _T_1870; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11667.4]
reg [31:0] _RAND_13;
wire [9:0] _T_1871; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11668.4]
wire [9:0] _T_1872; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11669.4]
wire [8:0] _T_1873; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11670.4]
wire _T_1874; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11671.4]
reg [1:0] _T_1885; // @[Monitor.scala 373:22:freechips.rocketchip.system.LowRiscConfig.fir@11683.4]
reg [31:0] _RAND_14;
reg [31:0] _T_1891; // @[Monitor.scala 376:22:freechips.rocketchip.system.LowRiscConfig.fir@11686.4]
reg [31:0] _RAND_15;
wire _T_1892; // @[Monitor.scala 377:22:freechips.rocketchip.system.LowRiscConfig.fir@11687.4]
wire _T_1893; // @[Monitor.scala 377:19:freechips.rocketchip.system.LowRiscConfig.fir@11688.4]
wire _T_1898; // @[Monitor.scala 379:29:freechips.rocketchip.system.LowRiscConfig.fir@11698.6]
wire _T_1900; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@11700.6]
wire _T_1901; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@11701.6]
wire _T_1910; // @[Monitor.scala 382:29:freechips.rocketchip.system.LowRiscConfig.fir@11722.6]
wire _T_1912; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@11724.6]
wire _T_1913; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@11725.6]
wire _T_1915; // @[Monitor.scala 384:20:freechips.rocketchip.system.LowRiscConfig.fir@11732.4]
wire _T_1916; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11740.4]
wire [8:0] _T_1921; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@11745.4]
wire _T_1922; // @[Edges.scala 102:36:freechips.rocketchip.system.LowRiscConfig.fir@11746.4]
reg [8:0] _T_1925; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11748.4]
reg [31:0] _RAND_16;
wire [9:0] _T_1926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11749.4]
wire [9:0] _T_1927; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11750.4]
wire [8:0] _T_1928; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11751.4]
wire _T_1929; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11752.4]
reg [2:0] _T_1938; // @[Monitor.scala 395:22:freechips.rocketchip.system.LowRiscConfig.fir@11763.4]
reg [31:0] _RAND_17;
reg [2:0] _T_1940; // @[Monitor.scala 396:22:freechips.rocketchip.system.LowRiscConfig.fir@11764.4]
reg [31:0] _RAND_18;
reg [3:0] _T_1942; // @[Monitor.scala 397:22:freechips.rocketchip.system.LowRiscConfig.fir@11765.4]
reg [31:0] _RAND_19;
reg [3:0] _T_1944; // @[Monitor.scala 398:22:freechips.rocketchip.system.LowRiscConfig.fir@11766.4]
reg [31:0] _RAND_20;
reg [31:0] _T_1946; // @[Monitor.scala 399:22:freechips.rocketchip.system.LowRiscConfig.fir@11767.4]
reg [31:0] _RAND_21;
wire _T_1947; // @[Monitor.scala 400:22:freechips.rocketchip.system.LowRiscConfig.fir@11768.4]
wire _T_1948; // @[Monitor.scala 400:19:freechips.rocketchip.system.LowRiscConfig.fir@11769.4]
wire _T_1949; // @[Monitor.scala 401:29:freechips.rocketchip.system.LowRiscConfig.fir@11771.6]
wire _T_1951; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@11773.6]
wire _T_1952; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@11774.6]
wire _T_1953; // @[Monitor.scala 402:29:freechips.rocketchip.system.LowRiscConfig.fir@11779.6]
wire _T_1955; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@11781.6]
wire _T_1956; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@11782.6]
wire _T_1957; // @[Monitor.scala 403:29:freechips.rocketchip.system.LowRiscConfig.fir@11787.6]
wire _T_1959; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@11789.6]
wire _T_1960; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@11790.6]
wire _T_1961; // @[Monitor.scala 404:29:freechips.rocketchip.system.LowRiscConfig.fir@11795.6]
wire _T_1963; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@11797.6]
wire _T_1964; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@11798.6]
wire _T_1965; // @[Monitor.scala 405:29:freechips.rocketchip.system.LowRiscConfig.fir@11803.6]
wire _T_1967; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@11805.6]
wire _T_1968; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@11806.6]
wire _T_1970; // @[Monitor.scala 407:20:freechips.rocketchip.system.LowRiscConfig.fir@11813.4]
reg [8:0] _T_1972; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@11821.4]
reg [31:0] _RAND_22;
reg [8:0] _T_1983; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11831.4]
reg [31:0] _RAND_23;
wire [9:0] _T_1984; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11832.4]
wire [9:0] _T_1985; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11833.4]
wire [8:0] _T_1986; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11834.4]
wire _T_1987; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11835.4]
reg [8:0] _T_2004; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11854.4]
reg [31:0] _RAND_24;
wire [9:0] _T_2005; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11855.4]
wire [9:0] _T_2006; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11856.4]
wire [8:0] _T_2007; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11857.4]
wire _T_2008; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11858.4]
wire _T_2019; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@11873.4]
wire [15:0] _T_2021; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@11876.6]
wire [8:0] _T_2022; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@11878.6]
wire _T_2023; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@11879.6]
wire _T_2024; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@11880.6]
wire _T_2026; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@11882.6]
wire _T_2027; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@11883.6]
wire [15:0] _GEN_27; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@11875.4]
wire _T_2032; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@11894.4]
wire _T_2034; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@11896.4]
wire _T_2035; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@11897.4]
wire [15:0] _T_2036; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@11899.6]
wire [8:0] _T_2017; // @[:freechips.rocketchip.system.LowRiscConfig.fir@11869.4 :freechips.rocketchip.system.LowRiscConfig.fir@11871.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@11877.6]
wire [8:0] _T_2037; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@11901.6]
wire [8:0] _T_2038; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@11902.6]
wire _T_2039; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@11903.6]
wire _T_2041; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@11905.6]
wire _T_2042; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@11906.6]
wire [15:0] _GEN_28; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@11898.4]
wire [8:0] _T_2029; // @[:freechips.rocketchip.system.LowRiscConfig.fir@11889.4 :freechips.rocketchip.system.LowRiscConfig.fir@11891.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@11900.6]
wire _T_2043; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@11912.4]
wire _T_2044; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@11913.4]
wire _T_2045; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@11914.4]
wire _T_2046; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@11915.4]
wire _T_2048; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@11917.4]
wire _T_2049; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@11918.4]
wire [8:0] _T_2050; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@11923.4]
wire [8:0] _T_2051; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@11924.4]
wire [8:0] _T_2052; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@11925.4]
reg [31:0] _T_2054; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@11927.4]
reg [31:0] _RAND_25;
wire _T_2055; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@11930.4]
wire _T_2056; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@11931.4]
wire _T_2057; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@11932.4]
wire _T_2058; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@11933.4]
wire _T_2059; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@11934.4]
wire _T_2060; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@11935.4]
wire _T_2062; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@11937.4]
wire _T_2063; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@11938.4]
wire [31:0] _T_2065; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@11944.4]
wire _T_2068; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@11948.4]
reg [3:0] _T_2070; // @[Monitor.scala 486:27:freechips.rocketchip.system.LowRiscConfig.fir@11952.4]
reg [31:0] _RAND_26;
reg [8:0] _T_2080; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@11961.4]
reg [31:0] _RAND_27;
wire [9:0] _T_2081; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11962.4]
wire [9:0] _T_2082; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11963.4]
wire [8:0] _T_2083; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11964.4]
wire _T_2084; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11965.4]
wire _T_2095; // @[Monitor.scala 492:27:freechips.rocketchip.system.LowRiscConfig.fir@11980.4]
wire _T_2096; // @[Edges.scala 71:36:freechips.rocketchip.system.LowRiscConfig.fir@11981.4]
wire _T_2097; // @[Edges.scala 71:52:freechips.rocketchip.system.LowRiscConfig.fir@11982.4]
wire _T_2098; // @[Edges.scala 71:43:freechips.rocketchip.system.LowRiscConfig.fir@11983.4]
wire _T_2099; // @[Edges.scala 71:40:freechips.rocketchip.system.LowRiscConfig.fir@11984.4]
wire _T_2100; // @[Monitor.scala 492:38:freechips.rocketchip.system.LowRiscConfig.fir@11985.4]
wire [3:0] _T_2101; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@11987.6]
wire [3:0] _T_2102; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@11989.6]
wire _T_2103; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@11990.6]
wire _T_2104; // @[Monitor.scala 494:14:freechips.rocketchip.system.LowRiscConfig.fir@11991.6]
wire _T_2106; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@11993.6]
wire _T_2107; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@11994.6]
wire [3:0] _GEN_31; // @[Monitor.scala 492:72:freechips.rocketchip.system.LowRiscConfig.fir@11986.4]
wire [3:0] _T_2113; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@12007.6]
wire [3:0] _T_2114; // @[Monitor.scala 500:21:freechips.rocketchip.system.LowRiscConfig.fir@12009.6]
wire [3:0] _T_2115; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@12010.6]
wire _T_2116; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@12011.6]
wire _T_2118; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@12013.6]
wire _T_2119; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@12014.6]
wire [3:0] _GEN_32; // @[Monitor.scala 498:73:freechips.rocketchip.system.LowRiscConfig.fir@12006.4]
wire [3:0] _T_2120; // @[Monitor.scala 505:27:freechips.rocketchip.system.LowRiscConfig.fir@12020.4]
wire [3:0] _T_2121; // @[Monitor.scala 505:38:freechips.rocketchip.system.LowRiscConfig.fir@12021.4]
wire [3:0] _T_2122; // @[Monitor.scala 505:36:freechips.rocketchip.system.LowRiscConfig.fir@12022.4]
wire _GEN_36; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9257.10]
wire _GEN_52; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@9393.10]
wire _GEN_70; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9540.10]
wire _GEN_82; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9647.10]
wire _GEN_92; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@9746.10]
wire _GEN_102; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9837.10]
wire _GEN_112; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@9926.10]
wire _GEN_122; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10015.10]
wire _GEN_132; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10083.10]
wire _GEN_142; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@10125.10]
wire _GEN_152; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@10183.10]
wire _GEN_162; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@10242.10]
wire _GEN_168; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@10277.10]
wire _GEN_174; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@10313.10]
wire _GEN_180; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11034.10]
wire _GEN_192; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@11082.10]
wire _GEN_202; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11171.10]
wire _GEN_216; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@11298.10]
wire _GEN_228; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@11368.10]
wire _GEN_238; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@11408.10]
wire _GEN_246; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@11440.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@11928.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@9077.6]
assign _T_23 = _T_22 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@9078.6]
assign _T_28 = io_in_a_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@9083.6]
assign _T_29 = io_in_a_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@9084.6]
assign _T_39 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@9090.6]
assign _T_40 = _T_39 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@9091.6]
assign _T_42 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@9093.6]
assign _T_43 = _T_42[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@9094.6]
assign _T_44 = ~ _T_43; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@9095.6]
assign _GEN_33 = {{20'd0}, _T_44}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@9096.6]
assign _T_45 = io_in_a_bits_address & _GEN_33; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@9096.6]
assign _T_46 = _T_45 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@9097.6]
assign _T_48 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@9099.6]
assign _T_49 = 4'h1 << _T_48; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@9100.6]
assign _T_50 = _T_49[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@9101.6]
assign _T_51 = _T_50 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@9102.6]
assign _T_52 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@9103.6]
assign _T_53 = _T_51[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@9104.6]
assign _T_54 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@9105.6]
assign _T_55 = _T_54 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@9106.6]
assign _T_57 = _T_53 & _T_55; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9108.6]
assign _T_58 = _T_52 | _T_57; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9109.6]
assign _T_60 = _T_53 & _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9111.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9112.6]
assign _T_62 = _T_51[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@9113.6]
assign _T_63 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@9114.6]
assign _T_64 = _T_63 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@9115.6]
assign _T_65 = _T_55 & _T_64; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9116.6]
assign _T_66 = _T_62 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9117.6]
assign _T_67 = _T_58 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9118.6]
assign _T_68 = _T_55 & _T_63; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9119.6]
assign _T_69 = _T_62 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9120.6]
assign _T_70 = _T_58 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9121.6]
assign _T_71 = _T_54 & _T_64; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9122.6]
assign _T_72 = _T_62 & _T_71; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9123.6]
assign _T_73 = _T_61 | _T_72; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9124.6]
assign _T_74 = _T_54 & _T_63; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9125.6]
assign _T_75 = _T_62 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9126.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9127.6]
assign _T_77 = _T_51[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@9128.6]
assign _T_78 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@9129.6]
assign _T_79 = _T_78 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@9130.6]
assign _T_80 = _T_65 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9131.6]
assign _T_81 = _T_77 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9132.6]
assign _T_82 = _T_67 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9133.6]
assign _T_83 = _T_65 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9134.6]
assign _T_84 = _T_77 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9135.6]
assign _T_85 = _T_67 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9136.6]
assign _T_86 = _T_68 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9137.6]
assign _T_87 = _T_77 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9138.6]
assign _T_88 = _T_70 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9139.6]
assign _T_89 = _T_68 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9140.6]
assign _T_90 = _T_77 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9141.6]
assign _T_91 = _T_70 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9142.6]
assign _T_92 = _T_71 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9143.6]
assign _T_93 = _T_77 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9144.6]
assign _T_94 = _T_73 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9145.6]
assign _T_95 = _T_71 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9146.6]
assign _T_96 = _T_77 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9147.6]
assign _T_97 = _T_73 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9148.6]
assign _T_98 = _T_74 & _T_79; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9149.6]
assign _T_99 = _T_77 & _T_98; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9150.6]
assign _T_100 = _T_76 | _T_99; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9151.6]
assign _T_101 = _T_74 & _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@9152.6]
assign _T_102 = _T_77 & _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@9153.6]
assign _T_103 = _T_76 | _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@9154.6]
assign _T_110 = {_T_103,_T_100,_T_97,_T_94,_T_91,_T_88,_T_85,_T_82}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@9161.6]
assign _T_121 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9172.6]
assign _T_147 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@9202.6]
assign _T_149 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9205.8]
assign _T_150 = {1'b0,$signed(_T_149)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9206.8]
assign _T_151 = $signed(_T_150) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9207.8]
assign _T_152 = $signed(_T_151); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9208.8]
assign _T_153 = $signed(_T_152) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9209.8]
assign _T_154 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9210.8]
assign _T_155 = {1'b0,$signed(_T_154)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9211.8]
assign _T_156 = $signed(_T_155) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9212.8]
assign _T_157 = $signed(_T_156); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9213.8]
assign _T_158 = $signed(_T_157) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9214.8]
assign _T_159 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9215.8]
assign _T_160 = {1'b0,$signed(_T_159)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9216.8]
assign _T_161 = $signed(_T_160) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9217.8]
assign _T_162 = $signed(_T_161); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9218.8]
assign _T_163 = $signed(_T_162) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9219.8]
assign _T_164 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9220.8]
assign _T_165 = {1'b0,$signed(_T_164)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9221.8]
assign _T_166 = $signed(_T_165) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9222.8]
assign _T_167 = $signed(_T_166); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9223.8]
assign _T_168 = $signed(_T_167) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9224.8]
assign _T_171 = $signed(_T_121) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9227.8]
assign _T_172 = $signed(_T_171); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9228.8]
assign _T_173 = $signed(_T_172) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9229.8]
assign _T_174 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9230.8]
assign _T_175 = {1'b0,$signed(_T_174)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9231.8]
assign _T_176 = $signed(_T_175) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9232.8]
assign _T_177 = $signed(_T_176); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9233.8]
assign _T_178 = $signed(_T_177) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9234.8]
assign _T_186 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9242.8]
assign _T_189 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@9245.8]
assign _T_190 = {1'b0,$signed(_T_189)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@9246.8]
assign _T_191 = $signed(_T_190) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9247.8]
assign _T_192 = $signed(_T_191); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@9248.8]
assign _T_193 = $signed(_T_192) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@9249.8]
assign _T_194 = _T_186 & _T_193; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9250.8]
assign _T_198 = _T_194 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9254.8]
assign _T_199 = _T_198 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9255.8]
assign _T_219 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@9275.8]
assign _T_221 = _T_23 ? _T_219 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@9276.8]
assign _T_229 = _T_221 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@9284.8]
assign _T_230 = _T_229 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@9285.8]
assign _T_232 = _T_40 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@9291.8]
assign _T_233 = _T_232 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@9292.8]
assign _T_236 = _T_52 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@9299.8]
assign _T_237 = _T_236 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@9300.8]
assign _T_239 = _T_46 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@9306.8]
assign _T_240 = _T_239 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@9307.8]
assign _T_241 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@9312.8]
assign _T_243 = _T_241 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@9314.8]
assign _T_244 = _T_243 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@9315.8]
assign _T_245 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@9320.8]
assign _T_246 = _T_245 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@9321.8]
assign _T_248 = _T_246 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@9323.8]
assign _T_249 = _T_248 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@9324.8]
assign _T_250 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@9329.8]
assign _T_252 = _T_250 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@9331.8]
assign _T_253 = _T_252 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@9332.8]
assign _T_254 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@9338.6]
assign _T_352 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@9456.8]
assign _T_354 = _T_352 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@9458.8]
assign _T_355 = _T_354 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@9459.8]
assign _T_365 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@9482.6]
assign _T_400 = _T_153 | _T_163; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9518.8]
assign _T_401 = _T_400 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9519.8]
assign _T_402 = _T_401 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9520.8]
assign _T_403 = _T_402 | _T_178; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9521.8]
assign _T_404 = _T_403 | _T_193; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9522.8]
assign _T_405 = _T_186 & _T_404; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9523.8]
assign _T_407 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9525.8]
assign _T_415 = _T_407 & _T_158; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9533.8]
assign _T_417 = _T_405 | _T_415; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@9535.8]
assign _T_419 = _T_417 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9537.8]
assign _T_420 = _T_419 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9538.8]
assign _T_427 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@9557.8]
assign _T_429 = _T_427 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@9559.8]
assign _T_430 = _T_429 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@9560.8]
assign _T_431 = io_in_a_bits_mask == _T_110; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@9565.8]
assign _T_433 = _T_431 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@9567.8]
assign _T_434 = _T_433 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@9568.8]
assign _T_439 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@9582.6]
assign _T_471 = _T_163 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9615.8]
assign _T_472 = _T_471 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9616.8]
assign _T_473 = _T_472 | _T_193; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9617.8]
assign _T_474 = _T_186 & _T_473; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9618.8]
assign _T_476 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9620.8]
assign _T_484 = _T_476 & _T_153; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9628.8]
assign _T_497 = _T_474 | _T_484; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@9641.8]
assign _T_498 = _T_497 | _T_415; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@9642.8]
assign _T_500 = _T_498 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9644.8]
assign _T_501 = _T_500 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9645.8]
assign _T_516 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@9681.6]
assign _T_589 = ~ _T_110; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@9771.8]
assign _T_590 = io_in_a_bits_mask & _T_589; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@9772.8]
assign _T_591 = _T_590 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@9773.8]
assign _T_593 = _T_591 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@9775.8]
assign _T_594 = _T_593 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@9776.8]
assign _T_595 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@9782.6]
assign _T_616 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@9804.8]
assign _T_639 = _T_158 | _T_163; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9827.8]
assign _T_640 = _T_639 | _T_168; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9828.8]
assign _T_641 = _T_640 | _T_173; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@9829.8]
assign _T_642 = _T_616 & _T_641; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@9830.8]
assign _T_646 = _T_642 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9834.8]
assign _T_647 = _T_646 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9835.8]
assign _T_654 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@9854.8]
assign _T_656 = _T_654 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@9856.8]
assign _T_657 = _T_656 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@9857.8]
assign _T_662 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@9871.6]
assign _T_721 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@9943.8]
assign _T_723 = _T_721 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@9945.8]
assign _T_724 = _T_723 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@9946.8]
assign _T_729 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@9960.6]
assign _T_780 = _T_415 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10012.8]
assign _T_781 = _T_780 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10013.8]
assign _T_796 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@10051.6]
assign _T_798 = _T_796 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@10053.6]
assign _T_799 = _T_798 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@10054.6]
assign _T_802 = io_in_d_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@10061.6]
assign _T_803 = _T_802 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@10062.6]
assign _T_808 = io_in_d_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10067.6]
assign _T_809 = io_in_d_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10068.6]
assign _T_819 = _T_803 | _T_808; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10074.6]
assign _T_820 = _T_819 | _T_809; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10075.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@10077.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10080.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10081.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@10086.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@10088.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@10089.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@10094.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@10096.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@10097.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@10102.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@10104.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@10105.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@10110.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@10112.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@10113.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@10119.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@10143.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@10145.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@10146.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@10151.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@10153.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@10154.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@10177.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@10218.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@10220.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@10221.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@10236.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@10271.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@10307.6]
assign _T_965 = {1'b0,$signed(io_in_b_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10362.6]
assign _T_991 = io_in_b_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10392.6]
assign _T_992 = {1'b0,$signed(_T_991)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10393.6]
assign _T_993 = $signed(_T_992) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10394.6]
assign _T_994 = $signed(_T_993); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10395.6]
assign _T_995 = $signed(_T_994) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10396.6]
assign _T_996 = io_in_b_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10397.6]
assign _T_997 = {1'b0,$signed(_T_996)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10398.6]
assign _T_998 = $signed(_T_997) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10399.6]
assign _T_999 = $signed(_T_998); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10400.6]
assign _T_1000 = $signed(_T_999) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10401.6]
assign _T_1001 = io_in_b_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10402.6]
assign _T_1002 = {1'b0,$signed(_T_1001)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10403.6]
assign _T_1003 = $signed(_T_1002) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10404.6]
assign _T_1004 = $signed(_T_1003); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10405.6]
assign _T_1005 = $signed(_T_1004) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10406.6]
assign _T_1006 = io_in_b_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10407.6]
assign _T_1007 = {1'b0,$signed(_T_1006)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10408.6]
assign _T_1008 = $signed(_T_1007) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10409.6]
assign _T_1009 = $signed(_T_1008); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10410.6]
assign _T_1010 = $signed(_T_1009) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10411.6]
assign _T_1013 = $signed(_T_965) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10414.6]
assign _T_1014 = $signed(_T_1013); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10415.6]
assign _T_1015 = $signed(_T_1014) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10416.6]
assign _T_1016 = io_in_b_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10417.6]
assign _T_1017 = {1'b0,$signed(_T_1016)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10418.6]
assign _T_1018 = $signed(_T_1017) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10419.6]
assign _T_1019 = $signed(_T_1018); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10420.6]
assign _T_1020 = $signed(_T_1019) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10421.6]
assign _T_1021 = io_in_b_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10422.6]
assign _T_1022 = {1'b0,$signed(_T_1021)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10423.6]
assign _T_1023 = $signed(_T_1022) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10424.6]
assign _T_1024 = $signed(_T_1023); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10425.6]
assign _T_1025 = $signed(_T_1024) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10426.6]
assign _T_1039 = _T_995 | _T_1000; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10436.6]
assign _T_1040 = _T_1039 | _T_1005; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10437.6]
assign _T_1041 = _T_1040 | _T_1010; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10438.6]
assign _T_1042 = _T_1041 | _T_1015; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10439.6]
assign _T_1043 = _T_1042 | _T_1020; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10440.6]
assign _T_1044 = _T_1043 | _T_1025; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10441.6]
assign _T_1046 = 27'hfff << 4'h6; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@10443.6]
assign _T_1047 = _T_1046[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@10444.6]
assign _T_1048 = ~ _T_1047; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@10445.6]
assign _GEN_34 = {{20'd0}, _T_1048}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10446.6]
assign _T_1049 = io_in_b_bits_address & _GEN_34; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10446.6]
assign _T_1050 = _T_1049 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@10447.6]
assign _T_1176 = _T_1044 | reset; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@10568.8]
assign _T_1177 = _T_1176 == 1'h0; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@10569.8]
assign _T_1182 = _T_1050 | reset; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@10582.8]
assign _T_1183 = _T_1182 == 1'h0; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@10583.8]
assign _T_1184 = io_in_b_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@10588.8]
assign _T_1186 = _T_1184 | reset; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@10590.8]
assign _T_1187 = _T_1186 == 1'h0; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@10591.8]
assign _T_1334 = io_in_c_bits_source[3:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@10917.6]
assign _T_1335 = _T_1334 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@10918.6]
assign _T_1340 = io_in_c_bits_source == 4'h4; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10923.6]
assign _T_1341 = io_in_c_bits_source == 4'h8; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@10924.6]
assign _T_1351 = _T_1335 | _T_1340; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10930.6]
assign _T_1352 = _T_1351 | _T_1341; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@10931.6]
assign _T_1354 = 27'hfff << io_in_c_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@10933.6]
assign _T_1355 = _T_1354[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@10934.6]
assign _T_1356 = ~ _T_1355; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@10935.6]
assign _GEN_35 = {{20'd0}, _T_1356}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10936.6]
assign _T_1357 = io_in_c_bits_address & _GEN_35; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@10936.6]
assign _T_1358 = _T_1357 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@10937.6]
assign _T_1359 = io_in_c_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10938.6]
assign _T_1360 = {1'b0,$signed(_T_1359)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10939.6]
assign _T_1361 = $signed(_T_1360) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10940.6]
assign _T_1362 = $signed(_T_1361); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10941.6]
assign _T_1363 = $signed(_T_1362) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10942.6]
assign _T_1364 = io_in_c_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10943.6]
assign _T_1365 = {1'b0,$signed(_T_1364)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10944.6]
assign _T_1366 = $signed(_T_1365) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10945.6]
assign _T_1367 = $signed(_T_1366); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10946.6]
assign _T_1368 = $signed(_T_1367) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10947.6]
assign _T_1369 = io_in_c_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10948.6]
assign _T_1370 = {1'b0,$signed(_T_1369)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10949.6]
assign _T_1371 = $signed(_T_1370) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10950.6]
assign _T_1372 = $signed(_T_1371); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10951.6]
assign _T_1373 = $signed(_T_1372) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10952.6]
assign _T_1374 = io_in_c_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10953.6]
assign _T_1375 = {1'b0,$signed(_T_1374)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10954.6]
assign _T_1376 = $signed(_T_1375) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10955.6]
assign _T_1377 = $signed(_T_1376); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10956.6]
assign _T_1378 = $signed(_T_1377) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10957.6]
assign _T_1380 = {1'b0,$signed(io_in_c_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10959.6]
assign _T_1381 = $signed(_T_1380) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10960.6]
assign _T_1382 = $signed(_T_1381); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10961.6]
assign _T_1383 = $signed(_T_1382) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10962.6]
assign _T_1384 = io_in_c_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10963.6]
assign _T_1385 = {1'b0,$signed(_T_1384)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10964.6]
assign _T_1386 = $signed(_T_1385) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10965.6]
assign _T_1387 = $signed(_T_1386); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10966.6]
assign _T_1388 = $signed(_T_1387) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10967.6]
assign _T_1389 = io_in_c_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@10968.6]
assign _T_1390 = {1'b0,$signed(_T_1389)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@10969.6]
assign _T_1391 = $signed(_T_1390) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10970.6]
assign _T_1392 = $signed(_T_1391); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@10971.6]
assign _T_1393 = $signed(_T_1392) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@10972.6]
assign _T_1407 = _T_1363 | _T_1368; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10982.6]
assign _T_1408 = _T_1407 | _T_1373; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10983.6]
assign _T_1409 = _T_1408 | _T_1378; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10984.6]
assign _T_1410 = _T_1409 | _T_1383; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10985.6]
assign _T_1411 = _T_1410 | _T_1388; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10986.6]
assign _T_1412 = _T_1411 | _T_1393; // @[Parameters.scala 156:64:freechips.rocketchip.system.LowRiscConfig.fir@10987.6]
assign _T_1449 = io_in_c_bits_opcode == 3'h4; // @[Monitor.scala 207:25:freechips.rocketchip.system.LowRiscConfig.fir@11028.6]
assign _T_1451 = _T_1412 | reset; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11031.8]
assign _T_1452 = _T_1451 == 1'h0; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11032.8]
assign _T_1454 = _T_1352 | reset; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@11038.8]
assign _T_1455 = _T_1454 == 1'h0; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@11039.8]
assign _T_1456 = io_in_c_bits_size >= 4'h3; // @[Monitor.scala 210:27:freechips.rocketchip.system.LowRiscConfig.fir@11044.8]
assign _T_1458 = _T_1456 | reset; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@11046.8]
assign _T_1459 = _T_1458 == 1'h0; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@11047.8]
assign _T_1461 = _T_1358 | reset; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@11053.8]
assign _T_1462 = _T_1461 == 1'h0; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@11054.8]
assign _T_1463 = io_in_c_bits_param <= 3'h5; // @[Bundles.scala 121:29:freechips.rocketchip.system.LowRiscConfig.fir@11059.8]
assign _T_1465 = _T_1463 | reset; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@11061.8]
assign _T_1466 = _T_1465 == 1'h0; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@11062.8]
assign _T_1467 = io_in_c_bits_corrupt == 1'h0; // @[Monitor.scala 213:15:freechips.rocketchip.system.LowRiscConfig.fir@11067.8]
assign _T_1469 = _T_1467 | reset; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@11069.8]
assign _T_1470 = _T_1469 == 1'h0; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@11070.8]
assign _T_1471 = io_in_c_bits_opcode == 3'h5; // @[Monitor.scala 216:25:freechips.rocketchip.system.LowRiscConfig.fir@11076.6]
assign _T_1489 = io_in_c_bits_opcode == 3'h6; // @[Monitor.scala 224:25:freechips.rocketchip.system.LowRiscConfig.fir@11116.6]
assign _T_1528 = io_in_c_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@11156.8]
assign _T_1536 = _T_1528 & _T_1393; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@11164.8]
assign _T_1540 = _T_1536 | reset; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11168.8]
assign _T_1541 = _T_1540 == 1'h0; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11169.8]
assign _T_1561 = 4'h6 == io_in_c_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@11189.8]
assign _T_1563 = _T_1335 ? _T_1561 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@11190.8]
assign _T_1571 = _T_1563 | reset; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@11198.8]
assign _T_1572 = _T_1571 == 1'h0; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@11199.8]
assign _T_1583 = io_in_c_bits_param <= 3'h2; // @[Bundles.scala 115:29:freechips.rocketchip.system.LowRiscConfig.fir@11226.8]
assign _T_1585 = _T_1583 | reset; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@11228.8]
assign _T_1586 = _T_1585 == 1'h0; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@11229.8]
assign _T_1591 = io_in_c_bits_opcode == 3'h7; // @[Monitor.scala 234:25:freechips.rocketchip.system.LowRiscConfig.fir@11243.6]
assign _T_1689 = io_in_c_bits_opcode == 3'h0; // @[Monitor.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@11362.6]
assign _T_1699 = io_in_c_bits_param == 3'h0; // @[Monitor.scala 247:28:freechips.rocketchip.system.LowRiscConfig.fir@11385.8]
assign _T_1701 = _T_1699 | reset; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@11387.8]
assign _T_1702 = _T_1701 == 1'h0; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@11388.8]
assign _T_1707 = io_in_c_bits_opcode == 3'h1; // @[Monitor.scala 251:25:freechips.rocketchip.system.LowRiscConfig.fir@11402.6]
assign _T_1721 = io_in_c_bits_opcode == 3'h2; // @[Monitor.scala 258:25:freechips.rocketchip.system.LowRiscConfig.fir@11434.6]
assign _T_1743 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11485.4]
assign _T_1748 = _T_44[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@11490.4]
assign _T_1749 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@11491.4]
assign _T_1750 = _T_1749 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@11492.4]
assign _T_1754 = _T_1753 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11495.4]
assign _T_1755 = $unsigned(_T_1754); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11496.4]
assign _T_1756 = _T_1755[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11497.4]
assign _T_1757 = _T_1753 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11498.4]
assign _T_1775 = _T_1757 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@11514.4]
assign _T_1776 = io_in_a_valid & _T_1775; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@11515.4]
assign _T_1777 = io_in_a_bits_opcode == _T_1766; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@11517.6]
assign _T_1779 = _T_1777 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@11519.6]
assign _T_1780 = _T_1779 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@11520.6]
assign _T_1781 = io_in_a_bits_param == _T_1768; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@11525.6]
assign _T_1783 = _T_1781 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@11527.6]
assign _T_1784 = _T_1783 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@11528.6]
assign _T_1785 = io_in_a_bits_size == _T_1770; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@11533.6]
assign _T_1787 = _T_1785 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@11535.6]
assign _T_1788 = _T_1787 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@11536.6]
assign _T_1789 = io_in_a_bits_source == _T_1772; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@11541.6]
assign _T_1791 = _T_1789 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@11543.6]
assign _T_1792 = _T_1791 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@11544.6]
assign _T_1793 = io_in_a_bits_address == _T_1774; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@11549.6]
assign _T_1795 = _T_1793 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@11551.6]
assign _T_1796 = _T_1795 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@11552.6]
assign _T_1798 = _T_1743 & _T_1757; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@11559.4]
assign _T_1799 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11567.4]
assign _T_1801 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@11569.4]
assign _T_1802 = _T_1801[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@11570.4]
assign _T_1803 = ~ _T_1802; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@11571.4]
assign _T_1804 = _T_1803[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@11572.4]
assign _T_1805 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@11573.4]
assign _T_1809 = _T_1808 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11576.4]
assign _T_1810 = $unsigned(_T_1809); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11577.4]
assign _T_1811 = _T_1810[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11578.4]
assign _T_1812 = _T_1808 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11579.4]
assign _T_1832 = _T_1812 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@11596.4]
assign _T_1833 = io_in_d_valid & _T_1832; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@11597.4]
assign _T_1834 = io_in_d_bits_opcode == _T_1821; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@11599.6]
assign _T_1836 = _T_1834 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@11601.6]
assign _T_1837 = _T_1836 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@11602.6]
assign _T_1838 = io_in_d_bits_param == _T_1823; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@11607.6]
assign _T_1840 = _T_1838 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@11609.6]
assign _T_1841 = _T_1840 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@11610.6]
assign _T_1842 = io_in_d_bits_size == _T_1825; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@11615.6]
assign _T_1844 = _T_1842 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@11617.6]
assign _T_1845 = _T_1844 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@11618.6]
assign _T_1846 = io_in_d_bits_source == _T_1827; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@11623.6]
assign _T_1848 = _T_1846 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@11625.6]
assign _T_1849 = _T_1848 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@11626.6]
assign _T_1850 = io_in_d_bits_sink == _T_1829; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@11631.6]
assign _T_1852 = _T_1850 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@11633.6]
assign _T_1853 = _T_1852 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@11634.6]
assign _T_1854 = io_in_d_bits_denied == _T_1831; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@11639.6]
assign _T_1856 = _T_1854 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@11641.6]
assign _T_1857 = _T_1856 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@11642.6]
assign _T_1859 = _T_1799 & _T_1812; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@11649.4]
assign _T_1860 = io_in_b_ready & io_in_b_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11658.4]
assign _T_1871 = _T_1870 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11668.4]
assign _T_1872 = $unsigned(_T_1871); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11669.4]
assign _T_1873 = _T_1872[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11670.4]
assign _T_1874 = _T_1870 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11671.4]
assign _T_1892 = _T_1874 == 1'h0; // @[Monitor.scala 377:22:freechips.rocketchip.system.LowRiscConfig.fir@11687.4]
assign _T_1893 = io_in_b_valid & _T_1892; // @[Monitor.scala 377:19:freechips.rocketchip.system.LowRiscConfig.fir@11688.4]
assign _T_1898 = io_in_b_bits_param == _T_1885; // @[Monitor.scala 379:29:freechips.rocketchip.system.LowRiscConfig.fir@11698.6]
assign _T_1900 = _T_1898 | reset; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@11700.6]
assign _T_1901 = _T_1900 == 1'h0; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@11701.6]
assign _T_1910 = io_in_b_bits_address == _T_1891; // @[Monitor.scala 382:29:freechips.rocketchip.system.LowRiscConfig.fir@11722.6]
assign _T_1912 = _T_1910 | reset; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@11724.6]
assign _T_1913 = _T_1912 == 1'h0; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@11725.6]
assign _T_1915 = _T_1860 & _T_1874; // @[Monitor.scala 384:20:freechips.rocketchip.system.LowRiscConfig.fir@11732.4]
assign _T_1916 = io_in_c_ready & io_in_c_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@11740.4]
assign _T_1921 = _T_1356[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@11745.4]
assign _T_1922 = io_in_c_bits_opcode[0]; // @[Edges.scala 102:36:freechips.rocketchip.system.LowRiscConfig.fir@11746.4]
assign _T_1926 = _T_1925 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11749.4]
assign _T_1927 = $unsigned(_T_1926); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11750.4]
assign _T_1928 = _T_1927[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11751.4]
assign _T_1929 = _T_1925 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11752.4]
assign _T_1947 = _T_1929 == 1'h0; // @[Monitor.scala 400:22:freechips.rocketchip.system.LowRiscConfig.fir@11768.4]
assign _T_1948 = io_in_c_valid & _T_1947; // @[Monitor.scala 400:19:freechips.rocketchip.system.LowRiscConfig.fir@11769.4]
assign _T_1949 = io_in_c_bits_opcode == _T_1938; // @[Monitor.scala 401:29:freechips.rocketchip.system.LowRiscConfig.fir@11771.6]
assign _T_1951 = _T_1949 | reset; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@11773.6]
assign _T_1952 = _T_1951 == 1'h0; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@11774.6]
assign _T_1953 = io_in_c_bits_param == _T_1940; // @[Monitor.scala 402:29:freechips.rocketchip.system.LowRiscConfig.fir@11779.6]
assign _T_1955 = _T_1953 | reset; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@11781.6]
assign _T_1956 = _T_1955 == 1'h0; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@11782.6]
assign _T_1957 = io_in_c_bits_size == _T_1942; // @[Monitor.scala 403:29:freechips.rocketchip.system.LowRiscConfig.fir@11787.6]
assign _T_1959 = _T_1957 | reset; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@11789.6]
assign _T_1960 = _T_1959 == 1'h0; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@11790.6]
assign _T_1961 = io_in_c_bits_source == _T_1944; // @[Monitor.scala 404:29:freechips.rocketchip.system.LowRiscConfig.fir@11795.6]
assign _T_1963 = _T_1961 | reset; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@11797.6]
assign _T_1964 = _T_1963 == 1'h0; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@11798.6]
assign _T_1965 = io_in_c_bits_address == _T_1946; // @[Monitor.scala 405:29:freechips.rocketchip.system.LowRiscConfig.fir@11803.6]
assign _T_1967 = _T_1965 | reset; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@11805.6]
assign _T_1968 = _T_1967 == 1'h0; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@11806.6]
assign _T_1970 = _T_1916 & _T_1929; // @[Monitor.scala 407:20:freechips.rocketchip.system.LowRiscConfig.fir@11813.4]
assign _T_1984 = _T_1983 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11832.4]
assign _T_1985 = $unsigned(_T_1984); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11833.4]
assign _T_1986 = _T_1985[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11834.4]
assign _T_1987 = _T_1983 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11835.4]
assign _T_2005 = _T_2004 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11855.4]
assign _T_2006 = $unsigned(_T_2005); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11856.4]
assign _T_2007 = _T_2006[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11857.4]
assign _T_2008 = _T_2004 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11858.4]
assign _T_2019 = _T_1743 & _T_1987; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@11873.4]
assign _T_2021 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@11876.6]
assign _T_2022 = _T_1972 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@11878.6]
assign _T_2023 = _T_2022[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@11879.6]
assign _T_2024 = _T_2023 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@11880.6]
assign _T_2026 = _T_2024 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@11882.6]
assign _T_2027 = _T_2026 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@11883.6]
assign _GEN_27 = _T_2019 ? _T_2021 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@11875.4]
assign _T_2032 = _T_1799 & _T_2008; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@11894.4]
assign _T_2034 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@11896.4]
assign _T_2035 = _T_2032 & _T_2034; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@11897.4]
assign _T_2036 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@11899.6]
assign _T_2017 = _GEN_27[8:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@11869.4 :freechips.rocketchip.system.LowRiscConfig.fir@11871.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@11877.6]
assign _T_2037 = _T_2017 | _T_1972; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@11901.6]
assign _T_2038 = _T_2037 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@11902.6]
assign _T_2039 = _T_2038[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@11903.6]
assign _T_2041 = _T_2039 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@11905.6]
assign _T_2042 = _T_2041 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@11906.6]
assign _GEN_28 = _T_2035 ? _T_2036 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@11898.4]
assign _T_2029 = _GEN_28[8:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@11889.4 :freechips.rocketchip.system.LowRiscConfig.fir@11891.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@11900.6]
assign _T_2043 = _T_2017 != _T_2029; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@11912.4]
assign _T_2044 = _T_2017 != 9'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@11913.4]
assign _T_2045 = _T_2044 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@11914.4]
assign _T_2046 = _T_2043 | _T_2045; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@11915.4]
assign _T_2048 = _T_2046 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@11917.4]
assign _T_2049 = _T_2048 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@11918.4]
assign _T_2050 = _T_1972 | _T_2017; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@11923.4]
assign _T_2051 = ~ _T_2029; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@11924.4]
assign _T_2052 = _T_2050 & _T_2051; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@11925.4]
assign _T_2055 = _T_1972 != 9'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@11930.4]
assign _T_2056 = _T_2055 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@11931.4]
assign _T_2057 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@11932.4]
assign _T_2058 = _T_2056 | _T_2057; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@11933.4]
assign _T_2059 = _T_2054 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@11934.4]
assign _T_2060 = _T_2058 | _T_2059; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@11935.4]
assign _T_2062 = _T_2060 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@11937.4]
assign _T_2063 = _T_2062 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@11938.4]
assign _T_2065 = _T_2054 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@11944.4]
assign _T_2068 = _T_1743 | _T_1799; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@11948.4]
assign _T_2081 = _T_2080 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11962.4]
assign _T_2082 = $unsigned(_T_2081); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11963.4]
assign _T_2083 = _T_2082[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@11964.4]
assign _T_2084 = _T_2080 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@11965.4]
assign _T_2095 = _T_1799 & _T_2084; // @[Monitor.scala 492:27:freechips.rocketchip.system.LowRiscConfig.fir@11980.4]
assign _T_2096 = io_in_d_bits_opcode[2]; // @[Edges.scala 71:36:freechips.rocketchip.system.LowRiscConfig.fir@11981.4]
assign _T_2097 = io_in_d_bits_opcode[1]; // @[Edges.scala 71:52:freechips.rocketchip.system.LowRiscConfig.fir@11982.4]
assign _T_2098 = _T_2097 == 1'h0; // @[Edges.scala 71:43:freechips.rocketchip.system.LowRiscConfig.fir@11983.4]
assign _T_2099 = _T_2096 & _T_2098; // @[Edges.scala 71:40:freechips.rocketchip.system.LowRiscConfig.fir@11984.4]
assign _T_2100 = _T_2095 & _T_2099; // @[Monitor.scala 492:38:freechips.rocketchip.system.LowRiscConfig.fir@11985.4]
assign _T_2101 = 4'h1 << io_in_d_bits_sink; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@11987.6]
assign _T_2102 = _T_2070 >> io_in_d_bits_sink; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@11989.6]
assign _T_2103 = _T_2102[0]; // @[Monitor.scala 494:23:freechips.rocketchip.system.LowRiscConfig.fir@11990.6]
assign _T_2104 = _T_2103 == 1'h0; // @[Monitor.scala 494:14:freechips.rocketchip.system.LowRiscConfig.fir@11991.6]
assign _T_2106 = _T_2104 | reset; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@11993.6]
assign _T_2107 = _T_2106 == 1'h0; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@11994.6]
assign _GEN_31 = _T_2100 ? _T_2101 : 4'h0; // @[Monitor.scala 492:72:freechips.rocketchip.system.LowRiscConfig.fir@11986.4]
assign _T_2113 = 4'h1 << io_in_e_bits_sink; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@12007.6]
assign _T_2114 = _GEN_31 | _T_2070; // @[Monitor.scala 500:21:freechips.rocketchip.system.LowRiscConfig.fir@12009.6]
assign _T_2115 = _T_2114 >> io_in_e_bits_sink; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@12010.6]
assign _T_2116 = _T_2115[0]; // @[Monitor.scala 500:32:freechips.rocketchip.system.LowRiscConfig.fir@12011.6]
assign _T_2118 = _T_2116 | reset; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@12013.6]
assign _T_2119 = _T_2118 == 1'h0; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@12014.6]
assign _GEN_32 = io_in_e_valid ? _T_2113 : 4'h0; // @[Monitor.scala 498:73:freechips.rocketchip.system.LowRiscConfig.fir@12006.4]
assign _T_2120 = _T_2070 | _GEN_31; // @[Monitor.scala 505:27:freechips.rocketchip.system.LowRiscConfig.fir@12020.4]
assign _T_2121 = ~ _GEN_32; // @[Monitor.scala 505:38:freechips.rocketchip.system.LowRiscConfig.fir@12021.4]
assign _T_2122 = _T_2120 & _T_2121; // @[Monitor.scala 505:36:freechips.rocketchip.system.LowRiscConfig.fir@12022.4]
assign _GEN_36 = io_in_a_valid & _T_147; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9257.10]
assign _GEN_52 = io_in_a_valid & _T_254; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@9393.10]
assign _GEN_70 = io_in_a_valid & _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9540.10]
assign _GEN_82 = io_in_a_valid & _T_439; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9647.10]
assign _GEN_92 = io_in_a_valid & _T_516; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@9746.10]
assign _GEN_102 = io_in_a_valid & _T_595; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9837.10]
assign _GEN_112 = io_in_a_valid & _T_662; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@9926.10]
assign _GEN_122 = io_in_a_valid & _T_729; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10015.10]
assign _GEN_132 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10083.10]
assign _GEN_142 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@10125.10]
assign _GEN_152 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@10183.10]
assign _GEN_162 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@10242.10]
assign _GEN_168 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@10277.10]
assign _GEN_174 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@10313.10]
assign _GEN_180 = io_in_c_valid & _T_1449; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11034.10]
assign _GEN_192 = io_in_c_valid & _T_1471; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@11082.10]
assign _GEN_202 = io_in_c_valid & _T_1489; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11171.10]
assign _GEN_216 = io_in_c_valid & _T_1591; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@11298.10]
assign _GEN_228 = io_in_c_valid & _T_1689; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@11368.10]
assign _GEN_238 = io_in_c_valid & _T_1707; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@11408.10]
assign _GEN_246 = io_in_c_valid & _T_1721; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@11440.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1753 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1766 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1768 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1770 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_1772 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_1774 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1808 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1821 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1823 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1825 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1827 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1829 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1831 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1870 = _RAND_13[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1885 = _RAND_14[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1891 = _RAND_15[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1925 = _RAND_16[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_1938 = _RAND_17[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_1940 = _RAND_18[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_1942 = _RAND_19[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_1944 = _RAND_20[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_1946 = _RAND_21[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_22 = {1{`RANDOM}};
_T_1972 = _RAND_22[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_23 = {1{`RANDOM}};
_T_1983 = _RAND_23[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_24 = {1{`RANDOM}};
_T_2004 = _RAND_24[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_25 = {1{`RANDOM}};
_T_2054 = _RAND_25[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_26 = {1{`RANDOM}};
_T_2070 = _RAND_26[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_27 = {1{`RANDOM}};
_T_2080 = _RAND_27[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_1753 <= 9'h0;
end else begin
if (_T_1743) begin
if (_T_1757) begin
if (_T_1750) begin
_T_1753 <= _T_1748;
end else begin
_T_1753 <= 9'h0;
end
end else begin
_T_1753 <= _T_1756;
end
end
end
if (_T_1798) begin
_T_1766 <= io_in_a_bits_opcode;
end
if (_T_1798) begin
_T_1768 <= io_in_a_bits_param;
end
if (_T_1798) begin
_T_1770 <= io_in_a_bits_size;
end
if (_T_1798) begin
_T_1772 <= io_in_a_bits_source;
end
if (_T_1798) begin
_T_1774 <= io_in_a_bits_address;
end
if (reset) begin
_T_1808 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_1812) begin
if (_T_1805) begin
_T_1808 <= _T_1804;
end else begin
_T_1808 <= 9'h0;
end
end else begin
_T_1808 <= _T_1811;
end
end
end
if (_T_1859) begin
_T_1821 <= io_in_d_bits_opcode;
end
if (_T_1859) begin
_T_1823 <= io_in_d_bits_param;
end
if (_T_1859) begin
_T_1825 <= io_in_d_bits_size;
end
if (_T_1859) begin
_T_1827 <= io_in_d_bits_source;
end
if (_T_1859) begin
_T_1829 <= io_in_d_bits_sink;
end
if (_T_1859) begin
_T_1831 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1870 <= 9'h0;
end else begin
if (_T_1860) begin
if (_T_1874) begin
_T_1870 <= 9'h0;
end else begin
_T_1870 <= _T_1873;
end
end
end
if (_T_1915) begin
_T_1885 <= io_in_b_bits_param;
end
if (_T_1915) begin
_T_1891 <= io_in_b_bits_address;
end
if (reset) begin
_T_1925 <= 9'h0;
end else begin
if (_T_1916) begin
if (_T_1929) begin
if (_T_1922) begin
_T_1925 <= _T_1921;
end else begin
_T_1925 <= 9'h0;
end
end else begin
_T_1925 <= _T_1928;
end
end
end
if (_T_1970) begin
_T_1938 <= io_in_c_bits_opcode;
end
if (_T_1970) begin
_T_1940 <= io_in_c_bits_param;
end
if (_T_1970) begin
_T_1942 <= io_in_c_bits_size;
end
if (_T_1970) begin
_T_1944 <= io_in_c_bits_source;
end
if (_T_1970) begin
_T_1946 <= io_in_c_bits_address;
end
if (reset) begin
_T_1972 <= 9'h0;
end else begin
_T_1972 <= _T_2052;
end
if (reset) begin
_T_1983 <= 9'h0;
end else begin
if (_T_1743) begin
if (_T_1987) begin
if (_T_1750) begin
_T_1983 <= _T_1748;
end else begin
_T_1983 <= 9'h0;
end
end else begin
_T_1983 <= _T_1986;
end
end
end
if (reset) begin
_T_2004 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_2008) begin
if (_T_1805) begin
_T_2004 <= _T_1804;
end else begin
_T_2004 <= 9'h0;
end
end else begin
_T_2004 <= _T_2007;
end
end
end
if (reset) begin
_T_2054 <= 32'h0;
end else begin
if (_T_2068) begin
_T_2054 <= 32'h0;
end else begin
_T_2054 <= _T_2065;
end
end
if (reset) begin
_T_2070 <= 4'h0;
end else begin
_T_2070 <= _T_2122;
end
if (reset) begin
_T_2080 <= 9'h0;
end else begin
if (_T_1799) begin
if (_T_2084) begin
if (_T_1805) begin
_T_2080 <= _T_1804;
end else begin
_T_2080 <= 9'h0;
end
end else begin
_T_2080 <= _T_2083;
end
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at SystemBus.scala:32:83)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@9072.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@9073.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@9199.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@9200.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_199) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9257.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_199) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@9258.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_230) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at SystemBus.scala:32:83)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@9287.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_230) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@9288.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@9294.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_233) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@9295.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_237) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@9302.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_237) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@9303.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@9309.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_240) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@9310.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_244) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at SystemBus.scala:32:83)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@9317.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_244) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@9318.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_249) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@9326.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_249) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@9327.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_36 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@9334.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_36 & _T_253) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@9335.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_199) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@9393.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_199) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@9394.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_230) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at SystemBus.scala:32:83)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@9423.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_230) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@9424.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@9430.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_233) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@9431.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_237) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@9438.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_237) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@9439.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@9445.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_240) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@9446.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_244) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at SystemBus.scala:32:83)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@9453.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_244) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@9454.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_355) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at SystemBus.scala:32:83)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@9461.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_355) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@9462.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_249) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@9470.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_249) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@9471.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_52 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@9478.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_52 & _T_253) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@9479.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_420) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9540.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_420) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@9541.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@9547.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_233) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@9548.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@9554.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_240) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@9555.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@9562.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_430) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@9563.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@9570.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_434) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@9571.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_70 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@9578.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_70 & _T_253) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@9579.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_501) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9647.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_501) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@9648.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@9654.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_233) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@9655.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@9661.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_240) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@9662.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@9669.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_430) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@9670.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_82 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@9677.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_82 & _T_434) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@9678.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_501) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@9746.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_501) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@9747.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@9753.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_233) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@9754.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@9760.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_240) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@9761.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_430) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@9768.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_430) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@9769.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_92 & _T_594) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@9778.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_92 & _T_594) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@9779.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_647) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9837.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_647) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@9838.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@9844.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_233) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@9845.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@9851.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_240) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@9852.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_657) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:32:83)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@9859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_657) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@9860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_102 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@9867.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_102 & _T_434) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@9868.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_647) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@9926.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_647) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@9927.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@9933.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_233) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@9934.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@9940.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_240) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@9941.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_724) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at SystemBus.scala:32:83)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@9948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_724) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@9949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_112 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@9956.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_112 & _T_434) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@9957.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_781) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10015.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_781) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@10016.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_233) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@10022.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_233) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@10023.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_240) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@10029.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_240) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@10030.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_434) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@10037.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_434) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@10038.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_122 & _T_253) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@10045.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_122 & _T_253) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@10046.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_799) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at SystemBus.scala:32:83)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@10056.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_799) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@10057.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10083.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@10084.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@10091.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@10092.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@10099.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@10100.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@10107.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@10108.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_132 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at SystemBus.scala:32:83)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@10115.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_132 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@10116.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@10125.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@10126.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@10132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@10133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@10140.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@10141.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at SystemBus.scala:32:83)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@10148.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@10149.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at SystemBus.scala:32:83)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@10156.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@10157.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_142 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@10164.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_142 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@10165.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at SystemBus.scala:32:83)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@10173.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@10174.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@10183.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@10184.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@10190.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@10191.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@10198.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@10199.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at SystemBus.scala:32:83)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@10206.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@10207.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at SystemBus.scala:32:83)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@10214.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@10215.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_152 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@10223.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_152 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@10224.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at SystemBus.scala:32:83)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@10232.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@10233.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@10242.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@10243.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@10250.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@10251.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_162 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@10258.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_162 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@10259.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at SystemBus.scala:32:83)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@10267.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@10268.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@10277.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@10278.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@10285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@10286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_168 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@10294.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_168 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@10295.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at SystemBus.scala:32:83)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@10303.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@10304.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@10313.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@10314.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@10321.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@10322.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_174 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@10329.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_174 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@10330.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at SystemBus.scala:32:83)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@10338.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@10339.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel has invalid opcode (connected at SystemBus.scala:32:83)\n at Monitor.scala:122 assert (TLMessages.isB(bundle.opcode), \"'B' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 122:12:freechips.rocketchip.system.LowRiscConfig.fir@10349.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 122:12:freechips.rocketchip.system.LowRiscConfig.fir@10350.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:124 assert (visible(edge.address(bundle), bundle.source, edge), \"'B' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 124:12:freechips.rocketchip.system.LowRiscConfig.fir@10389.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 124:12:freechips.rocketchip.system.LowRiscConfig.fir@10390.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Probe type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:133 assert (edge.client.supportsProbe(bundle.source, bundle.size), \"'B' channel carries Probe type unsupported by client\" + extra)\n"); // @[Monitor.scala 133:14:freechips.rocketchip.system.LowRiscConfig.fir@10564.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 133:14:freechips.rocketchip.system.LowRiscConfig.fir@10565.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1177) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:134 assert (address_ok, \"'B' channel Probe carries unmanaged address\" + extra)\n"); // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@10571.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1177) begin
$fatal; // @[Monitor.scala 134:14:freechips.rocketchip.system.LowRiscConfig.fir@10572.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:135 assert (legal_source, \"'B' channel Probe carries source that is not first source\" + extra)\n"); // @[Monitor.scala 135:14:freechips.rocketchip.system.LowRiscConfig.fir@10578.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 135:14:freechips.rocketchip.system.LowRiscConfig.fir@10579.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1183) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:136 assert (is_aligned, \"'B' channel Probe address not aligned to size\" + extra)\n"); // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@10585.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1183) begin
$fatal; // @[Monitor.scala 136:14:freechips.rocketchip.system.LowRiscConfig.fir@10586.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_b_valid & _T_1187) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe carries invalid cap param (connected at SystemBus.scala:32:83)\n at Monitor.scala:137 assert (TLPermissions.isCap(bundle.param), \"'B' channel Probe carries invalid cap param\" + extra)\n"); // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@10593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_b_valid & _T_1187) begin
$fatal; // @[Monitor.scala 137:14:freechips.rocketchip.system.LowRiscConfig.fir@10594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:138 assert (bundle.mask === mask, \"'B' channel Probe contains invalid mask\" + extra)\n"); // @[Monitor.scala 138:14:freechips.rocketchip.system.LowRiscConfig.fir@10601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 138:14:freechips.rocketchip.system.LowRiscConfig.fir@10602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Probe is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:139 assert (!bundle.corrupt, \"'B' channel Probe is corrupt\" + extra)\n"); // @[Monitor.scala 139:14:freechips.rocketchip.system.LowRiscConfig.fir@10609.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 139:14:freechips.rocketchip.system.LowRiscConfig.fir@10610.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Get type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:143 assert (edge.client.supportsGet(bundle.source, bundle.size), \"'B' channel carries Get type unsupported by client\" + extra)\n"); // @[Monitor.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@10619.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@10620.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:144 assert (address_ok, \"'B' channel Get carries unmanaged address\" + extra)\n"); // @[Monitor.scala 144:14:freechips.rocketchip.system.LowRiscConfig.fir@10626.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 144:14:freechips.rocketchip.system.LowRiscConfig.fir@10627.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:145 assert (legal_source, \"'B' channel Get carries source that is not first source\" + extra)\n"); // @[Monitor.scala 145:14:freechips.rocketchip.system.LowRiscConfig.fir@10633.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 145:14:freechips.rocketchip.system.LowRiscConfig.fir@10634.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:146 assert (is_aligned, \"'B' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 146:14:freechips.rocketchip.system.LowRiscConfig.fir@10640.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 146:14:freechips.rocketchip.system.LowRiscConfig.fir@10641.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:147 assert (bundle.param === UInt(0), \"'B' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 147:14:freechips.rocketchip.system.LowRiscConfig.fir@10648.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 147:14:freechips.rocketchip.system.LowRiscConfig.fir@10649.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:148 assert (bundle.mask === mask, \"'B' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 148:14:freechips.rocketchip.system.LowRiscConfig.fir@10656.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 148:14:freechips.rocketchip.system.LowRiscConfig.fir@10657.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Get is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:149 assert (!bundle.corrupt, \"'B' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 149:14:freechips.rocketchip.system.LowRiscConfig.fir@10664.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 149:14:freechips.rocketchip.system.LowRiscConfig.fir@10665.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries PutFull type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:153 assert (edge.client.supportsPutFull(bundle.source, bundle.size), \"'B' channel carries PutFull type unsupported by client\" + extra)\n"); // @[Monitor.scala 153:14:freechips.rocketchip.system.LowRiscConfig.fir@10674.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 153:14:freechips.rocketchip.system.LowRiscConfig.fir@10675.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:154 assert (address_ok, \"'B' channel PutFull carries unmanaged address\" + extra)\n"); // @[Monitor.scala 154:14:freechips.rocketchip.system.LowRiscConfig.fir@10681.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 154:14:freechips.rocketchip.system.LowRiscConfig.fir@10682.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:155 assert (legal_source, \"'B' channel PutFull carries source that is not first source\" + extra)\n"); // @[Monitor.scala 155:14:freechips.rocketchip.system.LowRiscConfig.fir@10688.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 155:14:freechips.rocketchip.system.LowRiscConfig.fir@10689.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:156 assert (is_aligned, \"'B' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 156:14:freechips.rocketchip.system.LowRiscConfig.fir@10695.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 156:14:freechips.rocketchip.system.LowRiscConfig.fir@10696.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:157 assert (bundle.param === UInt(0), \"'B' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 157:14:freechips.rocketchip.system.LowRiscConfig.fir@10703.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 157:14:freechips.rocketchip.system.LowRiscConfig.fir@10704.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutFull contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:158 assert (bundle.mask === mask, \"'B' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 158:14:freechips.rocketchip.system.LowRiscConfig.fir@10711.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 158:14:freechips.rocketchip.system.LowRiscConfig.fir@10712.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries PutPartial type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:162 assert (edge.client.supportsPutPartial(bundle.source, bundle.size), \"'B' channel carries PutPartial type unsupported by client\" + extra)\n"); // @[Monitor.scala 162:14:freechips.rocketchip.system.LowRiscConfig.fir@10721.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 162:14:freechips.rocketchip.system.LowRiscConfig.fir@10722.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:163 assert (address_ok, \"'B' channel PutPartial carries unmanaged address\" + extra)\n"); // @[Monitor.scala 163:14:freechips.rocketchip.system.LowRiscConfig.fir@10728.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 163:14:freechips.rocketchip.system.LowRiscConfig.fir@10729.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:164 assert (legal_source, \"'B' channel PutPartial carries source that is not first source\" + extra)\n"); // @[Monitor.scala 164:14:freechips.rocketchip.system.LowRiscConfig.fir@10735.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 164:14:freechips.rocketchip.system.LowRiscConfig.fir@10736.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:165 assert (is_aligned, \"'B' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 165:14:freechips.rocketchip.system.LowRiscConfig.fir@10742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 165:14:freechips.rocketchip.system.LowRiscConfig.fir@10743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:166 assert (bundle.param === UInt(0), \"'B' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 166:14:freechips.rocketchip.system.LowRiscConfig.fir@10750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 166:14:freechips.rocketchip.system.LowRiscConfig.fir@10751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel PutPartial contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:167 assert ((bundle.mask & ~mask) === UInt(0), \"'B' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@10760.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@10761.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Arithmetic type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:171 assert (edge.client.supportsArithmetic(bundle.source, bundle.size), \"'B' channel carries Arithmetic type unsupported by client\" + extra)\n"); // @[Monitor.scala 171:14:freechips.rocketchip.system.LowRiscConfig.fir@10770.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 171:14:freechips.rocketchip.system.LowRiscConfig.fir@10771.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:172 assert (address_ok, \"'B' channel Arithmetic carries unmanaged address\" + extra)\n"); // @[Monitor.scala 172:14:freechips.rocketchip.system.LowRiscConfig.fir@10777.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 172:14:freechips.rocketchip.system.LowRiscConfig.fir@10778.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:173 assert (legal_source, \"'B' channel Arithmetic carries source that is not first source\" + extra)\n"); // @[Monitor.scala 173:14:freechips.rocketchip.system.LowRiscConfig.fir@10784.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 173:14:freechips.rocketchip.system.LowRiscConfig.fir@10785.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:174 assert (is_aligned, \"'B' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 174:14:freechips.rocketchip.system.LowRiscConfig.fir@10791.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 174:14:freechips.rocketchip.system.LowRiscConfig.fir@10792.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at SystemBus.scala:32:83)\n at Monitor.scala:175 assert (TLAtomics.isArithmetic(bundle.param), \"'B' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 175:14:freechips.rocketchip.system.LowRiscConfig.fir@10799.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 175:14:freechips.rocketchip.system.LowRiscConfig.fir@10800.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:176 assert (bundle.mask === mask, \"'B' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@10807.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@10808.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Logical type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:180 assert (edge.client.supportsLogical(bundle.source, bundle.size), \"'B' channel carries Logical type unsupported by client\" + extra)\n"); // @[Monitor.scala 180:14:freechips.rocketchip.system.LowRiscConfig.fir@10817.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 180:14:freechips.rocketchip.system.LowRiscConfig.fir@10818.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:181 assert (address_ok, \"'B' channel Logical carries unmanaged address\" + extra)\n"); // @[Monitor.scala 181:14:freechips.rocketchip.system.LowRiscConfig.fir@10824.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 181:14:freechips.rocketchip.system.LowRiscConfig.fir@10825.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:182 assert (legal_source, \"'B' channel Logical carries source that is not first source\" + extra)\n"); // @[Monitor.scala 182:14:freechips.rocketchip.system.LowRiscConfig.fir@10831.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 182:14:freechips.rocketchip.system.LowRiscConfig.fir@10832.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:183 assert (is_aligned, \"'B' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 183:14:freechips.rocketchip.system.LowRiscConfig.fir@10838.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 183:14:freechips.rocketchip.system.LowRiscConfig.fir@10839.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical carries invalid opcode param (connected at SystemBus.scala:32:83)\n at Monitor.scala:184 assert (TLAtomics.isLogical(bundle.param), \"'B' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 184:14:freechips.rocketchip.system.LowRiscConfig.fir@10846.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 184:14:freechips.rocketchip.system.LowRiscConfig.fir@10847.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Logical contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:185 assert (bundle.mask === mask, \"'B' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 185:14:freechips.rocketchip.system.LowRiscConfig.fir@10854.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 185:14:freechips.rocketchip.system.LowRiscConfig.fir@10855.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel carries Hint type unsupported by client (connected at SystemBus.scala:32:83)\n at Monitor.scala:189 assert (edge.client.supportsHint(bundle.source, bundle.size), \"'B' channel carries Hint type unsupported by client\" + extra)\n"); // @[Monitor.scala 189:14:freechips.rocketchip.system.LowRiscConfig.fir@10864.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 189:14:freechips.rocketchip.system.LowRiscConfig.fir@10865.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:190 assert (address_ok, \"'B' channel Hint carries unmanaged address\" + extra)\n"); // @[Monitor.scala 190:14:freechips.rocketchip.system.LowRiscConfig.fir@10871.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 190:14:freechips.rocketchip.system.LowRiscConfig.fir@10872.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint carries source that is not first source (connected at SystemBus.scala:32:83)\n at Monitor.scala:191 assert (legal_source, \"'B' channel Hint carries source that is not first source\" + extra)\n"); // @[Monitor.scala 191:14:freechips.rocketchip.system.LowRiscConfig.fir@10878.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 191:14:freechips.rocketchip.system.LowRiscConfig.fir@10879.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:192 assert (is_aligned, \"'B' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 192:14:freechips.rocketchip.system.LowRiscConfig.fir@10885.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 192:14:freechips.rocketchip.system.LowRiscConfig.fir@10886.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint contains invalid mask (connected at SystemBus.scala:32:83)\n at Monitor.scala:193 assert (bundle.mask === mask, \"'B' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 193:14:freechips.rocketchip.system.LowRiscConfig.fir@10893.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 193:14:freechips.rocketchip.system.LowRiscConfig.fir@10894.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel Hint is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:194 assert (!bundle.corrupt, \"'B' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 194:14:freechips.rocketchip.system.LowRiscConfig.fir@10901.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 194:14:freechips.rocketchip.system.LowRiscConfig.fir@10902.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel has invalid opcode (connected at SystemBus.scala:32:83)\n at Monitor.scala:199 assert (TLMessages.isC(bundle.opcode), \"'C' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 199:12:freechips.rocketchip.system.LowRiscConfig.fir@10912.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 199:12:freechips.rocketchip.system.LowRiscConfig.fir@10913.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:205 assert (visible(edge.address(bundle), bundle.source, edge), \"'C' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 205:12:freechips.rocketchip.system.LowRiscConfig.fir@11025.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 205:12:freechips.rocketchip.system.LowRiscConfig.fir@11026.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:208 assert (address_ok, \"'C' channel ProbeAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11034.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1452) begin
$fatal; // @[Monitor.scala 208:14:freechips.rocketchip.system.LowRiscConfig.fir@11035.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:209 assert (source_ok, \"'C' channel ProbeAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@11041.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1455) begin
$fatal; // @[Monitor.scala 209:14:freechips.rocketchip.system.LowRiscConfig.fir@11042.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:210 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@11049.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1459) begin
$fatal; // @[Monitor.scala 210:14:freechips.rocketchip.system.LowRiscConfig.fir@11050.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:211 assert (is_aligned, \"'C' channel ProbeAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@11056.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1462) begin
$fatal; // @[Monitor.scala 211:14:freechips.rocketchip.system.LowRiscConfig.fir@11057.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1466) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at SystemBus.scala:32:83)\n at Monitor.scala:212 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAck carries invalid report param\" + extra)\n"); // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@11064.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1466) begin
$fatal; // @[Monitor.scala 212:14:freechips.rocketchip.system.LowRiscConfig.fir@11065.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_180 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAck is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:213 assert (!bundle.corrupt, \"'C' channel ProbeAck is corrupt\" + extra)\n"); // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@11072.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_180 & _T_1470) begin
$fatal; // @[Monitor.scala 213:14:freechips.rocketchip.system.LowRiscConfig.fir@11073.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:217 assert (address_ok, \"'C' channel ProbeAckData carries unmanaged address\" + extra)\n"); // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@11082.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1452) begin
$fatal; // @[Monitor.scala 217:14:freechips.rocketchip.system.LowRiscConfig.fir@11083.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:218 assert (source_ok, \"'C' channel ProbeAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 218:14:freechips.rocketchip.system.LowRiscConfig.fir@11089.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1455) begin
$fatal; // @[Monitor.scala 218:14:freechips.rocketchip.system.LowRiscConfig.fir@11090.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:219 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ProbeAckData smaller than a beat\" + extra)\n"); // @[Monitor.scala 219:14:freechips.rocketchip.system.LowRiscConfig.fir@11097.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1459) begin
$fatal; // @[Monitor.scala 219:14:freechips.rocketchip.system.LowRiscConfig.fir@11098.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:220 assert (is_aligned, \"'C' channel ProbeAckData address not aligned to size\" + extra)\n"); // @[Monitor.scala 220:14:freechips.rocketchip.system.LowRiscConfig.fir@11104.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1462) begin
$fatal; // @[Monitor.scala 220:14:freechips.rocketchip.system.LowRiscConfig.fir@11105.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_192 & _T_1466) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at SystemBus.scala:32:83)\n at Monitor.scala:221 assert (TLPermissions.isReport(bundle.param), \"'C' channel ProbeAckData carries invalid report param\" + extra)\n"); // @[Monitor.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@11112.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_192 & _T_1466) begin
$fatal; // @[Monitor.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@11113.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1541) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:225 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries Release type unsupported by manager\" + extra)\n"); // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11171.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1541) begin
$fatal; // @[Monitor.scala 225:14:freechips.rocketchip.system.LowRiscConfig.fir@11172.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1572) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:32:83)\n at Monitor.scala:226 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@11201.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1572) begin
$fatal; // @[Monitor.scala 226:14:freechips.rocketchip.system.LowRiscConfig.fir@11202.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:227 assert (source_ok, \"'C' channel Release carries invalid source ID\" + extra)\n"); // @[Monitor.scala 227:14:freechips.rocketchip.system.LowRiscConfig.fir@11208.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1455) begin
$fatal; // @[Monitor.scala 227:14:freechips.rocketchip.system.LowRiscConfig.fir@11209.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:228 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel Release smaller than a beat\" + extra)\n"); // @[Monitor.scala 228:14:freechips.rocketchip.system.LowRiscConfig.fir@11216.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1459) begin
$fatal; // @[Monitor.scala 228:14:freechips.rocketchip.system.LowRiscConfig.fir@11217.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:229 assert (is_aligned, \"'C' channel Release address not aligned to size\" + extra)\n"); // @[Monitor.scala 229:14:freechips.rocketchip.system.LowRiscConfig.fir@11223.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1462) begin
$fatal; // @[Monitor.scala 229:14:freechips.rocketchip.system.LowRiscConfig.fir@11224.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1586) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release carries invalid shrink param (connected at SystemBus.scala:32:83)\n at Monitor.scala:230 assert (TLPermissions.isShrink(bundle.param), \"'C' channel Release carries invalid shrink param\" + extra)\n"); // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@11231.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1586) begin
$fatal; // @[Monitor.scala 230:14:freechips.rocketchip.system.LowRiscConfig.fir@11232.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_202 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel Release is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:231 assert (!bundle.corrupt, \"'C' channel Release is corrupt\" + extra)\n"); // @[Monitor.scala 231:14:freechips.rocketchip.system.LowRiscConfig.fir@11239.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_202 & _T_1470) begin
$fatal; // @[Monitor.scala 231:14:freechips.rocketchip.system.LowRiscConfig.fir@11240.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1541) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at SystemBus.scala:32:83)\n at Monitor.scala:235 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'C' channel carries ReleaseData type unsupported by manager\" + extra)\n"); // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@11298.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1541) begin
$fatal; // @[Monitor.scala 235:14:freechips.rocketchip.system.LowRiscConfig.fir@11299.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1572) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at SystemBus.scala:32:83)\n at Monitor.scala:236 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'C' channel carries Release from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 236:14:freechips.rocketchip.system.LowRiscConfig.fir@11328.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1572) begin
$fatal; // @[Monitor.scala 236:14:freechips.rocketchip.system.LowRiscConfig.fir@11329.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:237 assert (source_ok, \"'C' channel ReleaseData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 237:14:freechips.rocketchip.system.LowRiscConfig.fir@11335.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1455) begin
$fatal; // @[Monitor.scala 237:14:freechips.rocketchip.system.LowRiscConfig.fir@11336.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1459) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at SystemBus.scala:32:83)\n at Monitor.scala:238 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'C' channel ReleaseData smaller than a beat\" + extra)\n"); // @[Monitor.scala 238:14:freechips.rocketchip.system.LowRiscConfig.fir@11343.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1459) begin
$fatal; // @[Monitor.scala 238:14:freechips.rocketchip.system.LowRiscConfig.fir@11344.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:239 assert (is_aligned, \"'C' channel ReleaseData address not aligned to size\" + extra)\n"); // @[Monitor.scala 239:14:freechips.rocketchip.system.LowRiscConfig.fir@11350.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1462) begin
$fatal; // @[Monitor.scala 239:14:freechips.rocketchip.system.LowRiscConfig.fir@11351.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_216 & _T_1586) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel ReleaseData carries invalid shrink param (connected at SystemBus.scala:32:83)\n at Monitor.scala:240 assert (TLPermissions.isShrink(bundle.param), \"'C' channel ReleaseData carries invalid shrink param\" + extra)\n"); // @[Monitor.scala 240:14:freechips.rocketchip.system.LowRiscConfig.fir@11358.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_216 & _T_1586) begin
$fatal; // @[Monitor.scala 240:14:freechips.rocketchip.system.LowRiscConfig.fir@11359.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:244 assert (address_ok, \"'C' channel AccessAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@11368.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1452) begin
$fatal; // @[Monitor.scala 244:14:freechips.rocketchip.system.LowRiscConfig.fir@11369.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:245 assert (source_ok, \"'C' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 245:14:freechips.rocketchip.system.LowRiscConfig.fir@11375.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1455) begin
$fatal; // @[Monitor.scala 245:14:freechips.rocketchip.system.LowRiscConfig.fir@11376.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:246 assert (is_aligned, \"'C' channel AccessAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 246:14:freechips.rocketchip.system.LowRiscConfig.fir@11382.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1462) begin
$fatal; // @[Monitor.scala 246:14:freechips.rocketchip.system.LowRiscConfig.fir@11383.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:247 assert (bundle.param === UInt(0), \"'C' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@11390.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1702) begin
$fatal; // @[Monitor.scala 247:14:freechips.rocketchip.system.LowRiscConfig.fir@11391.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_228 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAck is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:248 assert (!bundle.corrupt, \"'C' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 248:14:freechips.rocketchip.system.LowRiscConfig.fir@11398.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_228 & _T_1470) begin
$fatal; // @[Monitor.scala 248:14:freechips.rocketchip.system.LowRiscConfig.fir@11399.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:252 assert (address_ok, \"'C' channel AccessAckData carries unmanaged address\" + extra)\n"); // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@11408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1452) begin
$fatal; // @[Monitor.scala 252:14:freechips.rocketchip.system.LowRiscConfig.fir@11409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:253 assert (source_ok, \"'C' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 253:14:freechips.rocketchip.system.LowRiscConfig.fir@11415.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1455) begin
$fatal; // @[Monitor.scala 253:14:freechips.rocketchip.system.LowRiscConfig.fir@11416.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:254 assert (is_aligned, \"'C' channel AccessAckData address not aligned to size\" + extra)\n"); // @[Monitor.scala 254:14:freechips.rocketchip.system.LowRiscConfig.fir@11422.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1462) begin
$fatal; // @[Monitor.scala 254:14:freechips.rocketchip.system.LowRiscConfig.fir@11423.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_238 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel AccessAckData carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:255 assert (bundle.param === UInt(0), \"'C' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 255:14:freechips.rocketchip.system.LowRiscConfig.fir@11430.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_238 & _T_1702) begin
$fatal; // @[Monitor.scala 255:14:freechips.rocketchip.system.LowRiscConfig.fir@11431.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1452) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries unmanaged address (connected at SystemBus.scala:32:83)\n at Monitor.scala:259 assert (address_ok, \"'C' channel HintAck carries unmanaged address\" + extra)\n"); // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@11440.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1452) begin
$fatal; // @[Monitor.scala 259:14:freechips.rocketchip.system.LowRiscConfig.fir@11441.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1455) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries invalid source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:260 assert (source_ok, \"'C' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 260:14:freechips.rocketchip.system.LowRiscConfig.fir@11447.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1455) begin
$fatal; // @[Monitor.scala 260:14:freechips.rocketchip.system.LowRiscConfig.fir@11448.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1462) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck address not aligned to size (connected at SystemBus.scala:32:83)\n at Monitor.scala:261 assert (is_aligned, \"'C' channel HintAck address not aligned to size\" + extra)\n"); // @[Monitor.scala 261:14:freechips.rocketchip.system.LowRiscConfig.fir@11454.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1462) begin
$fatal; // @[Monitor.scala 261:14:freechips.rocketchip.system.LowRiscConfig.fir@11455.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1702) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck carries invalid param (connected at SystemBus.scala:32:83)\n at Monitor.scala:262 assert (bundle.param === UInt(0), \"'C' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 262:14:freechips.rocketchip.system.LowRiscConfig.fir@11462.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1702) begin
$fatal; // @[Monitor.scala 262:14:freechips.rocketchip.system.LowRiscConfig.fir@11463.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_246 & _T_1470) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel HintAck is corrupt (connected at SystemBus.scala:32:83)\n at Monitor.scala:263 assert (!bundle.corrupt, \"'C' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 263:14:freechips.rocketchip.system.LowRiscConfig.fir@11470.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_246 & _T_1470) begin
$fatal; // @[Monitor.scala 263:14:freechips.rocketchip.system.LowRiscConfig.fir@11471.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channels carries invalid sink ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:330 assert (sink_ok, \"'E' channels carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 330:12:freechips.rocketchip.system.LowRiscConfig.fir@11481.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 330:12:freechips.rocketchip.system.LowRiscConfig.fir@11482.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1780) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@11522.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1780) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@11523.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1784) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@11530.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1784) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@11531.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1788) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@11538.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1788) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@11539.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1792) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@11546.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1792) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@11547.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1776 & _T_1796) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@11554.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1776 & _T_1796) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@11555.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@11604.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1837) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@11605.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@11612.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1841) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@11613.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1845) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@11620.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1845) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@11621.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1849) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@11628.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1849) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@11629.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1853) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@11636.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1853) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@11637.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1833 & _T_1857) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@11644.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1833 & _T_1857) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@11645.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:378 assert (b.bits.opcode === opcode, \"'B' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 378:14:freechips.rocketchip.system.LowRiscConfig.fir@11695.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 378:14:freechips.rocketchip.system.LowRiscConfig.fir@11696.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1893 & _T_1901) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel param changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:379 assert (b.bits.param === param, \"'B' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@11703.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1893 & _T_1901) begin
$fatal; // @[Monitor.scala 379:14:freechips.rocketchip.system.LowRiscConfig.fir@11704.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel size changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:380 assert (b.bits.size === size, \"'B' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 380:14:freechips.rocketchip.system.LowRiscConfig.fir@11711.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 380:14:freechips.rocketchip.system.LowRiscConfig.fir@11712.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel source changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:381 assert (b.bits.source === source, \"'B' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 381:14:freechips.rocketchip.system.LowRiscConfig.fir@11719.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 381:14:freechips.rocketchip.system.LowRiscConfig.fir@11720.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1893 & _T_1913) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel addresss changed with multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:382 assert (b.bits.address=== address,\"'B' channel addresss changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@11727.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1893 & _T_1913) begin
$fatal; // @[Monitor.scala 382:14:freechips.rocketchip.system.LowRiscConfig.fir@11728.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1952) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel opcode changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:401 assert (c.bits.opcode === opcode, \"'C' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@11776.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1952) begin
$fatal; // @[Monitor.scala 401:14:freechips.rocketchip.system.LowRiscConfig.fir@11777.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1956) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel param changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:402 assert (c.bits.param === param, \"'C' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@11784.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1956) begin
$fatal; // @[Monitor.scala 402:14:freechips.rocketchip.system.LowRiscConfig.fir@11785.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1960) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel size changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:403 assert (c.bits.size === size, \"'C' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@11792.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1960) begin
$fatal; // @[Monitor.scala 403:14:freechips.rocketchip.system.LowRiscConfig.fir@11793.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1964) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel source changed within multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:404 assert (c.bits.source === source, \"'C' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@11800.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1964) begin
$fatal; // @[Monitor.scala 404:14:freechips.rocketchip.system.LowRiscConfig.fir@11801.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1948 & _T_1968) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel address changed with multibeat operation (connected at SystemBus.scala:32:83)\n at Monitor.scala:405 assert (c.bits.address=== address,\"'C' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@11808.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1948 & _T_1968) begin
$fatal; // @[Monitor.scala 405:14:freechips.rocketchip.system.LowRiscConfig.fir@11809.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2019 & _T_2027) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@11885.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2019 & _T_2027) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@11886.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2035 & _T_2042) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at SystemBus.scala:32:83)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@11908.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2035 & _T_2042) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@11909.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2049) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at SystemBus.scala:32:83)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@11920.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2049) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@11921.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2063) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at SystemBus.scala:32:83)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@11940.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2063) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@11941.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2100 & _T_2107) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel re-used a sink ID (connected at SystemBus.scala:32:83)\n at Monitor.scala:494 assert(!inflight(bundle.d.bits.sink), \"'D' channel re-used a sink ID\" + extra)\n"); // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@11996.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2100 & _T_2107) begin
$fatal; // @[Monitor.scala 494:13:freechips.rocketchip.system.LowRiscConfig.fir@11997.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_e_valid & _T_2119) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel acknowledged for nothing inflight (connected at SystemBus.scala:32:83)\n at Monitor.scala:500 assert((d_set | inflight)(bundle.e.bits.sink), \"'E' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@12016.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_e_valid & _T_2119) begin
$fatal; // @[Monitor.scala 500:13:freechips.rocketchip.system.LowRiscConfig.fir@12017.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLFIFOFixer( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12025.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12026.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12027.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [1:0] auto_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [31:0] auto_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [2:0] auto_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [2:0] auto_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [3:0] auto_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [3:0] auto_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [31:0] auto_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [63:0] auto_in_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [1:0] auto_in_e_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [1:0] auto_out_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [31:0] auto_out_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_out_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [2:0] auto_out_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [2:0] auto_out_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [3:0] auto_out_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [3:0] auto_out_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [31:0] auto_out_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [63:0] auto_out_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
input auto_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output auto_out_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
output [1:0] auto_out_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@12028.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_b_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_b_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [1:0] TLMonitor_io_in_b_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [31:0] TLMonitor_io_in_b_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_c_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_c_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [2:0] TLMonitor_io_in_c_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [2:0] TLMonitor_io_in_c_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [3:0] TLMonitor_io_in_c_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [3:0] TLMonitor_io_in_c_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [31:0] TLMonitor_io_in_c_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_c_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire TLMonitor_io_in_e_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
wire [1:0] TLMonitor_io_in_e_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
TLMonitor_3 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@12035.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_b_ready(TLMonitor_io_in_b_ready),
.io_in_b_valid(TLMonitor_io_in_b_valid),
.io_in_b_bits_param(TLMonitor_io_in_b_bits_param),
.io_in_b_bits_address(TLMonitor_io_in_b_bits_address),
.io_in_c_ready(TLMonitor_io_in_c_ready),
.io_in_c_valid(TLMonitor_io_in_c_valid),
.io_in_c_bits_opcode(TLMonitor_io_in_c_bits_opcode),
.io_in_c_bits_param(TLMonitor_io_in_c_bits_param),
.io_in_c_bits_size(TLMonitor_io_in_c_bits_size),
.io_in_c_bits_source(TLMonitor_io_in_c_bits_source),
.io_in_c_bits_address(TLMonitor_io_in_c_bits_address),
.io_in_c_bits_corrupt(TLMonitor_io_in_c_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt),
.io_in_e_valid(TLMonitor_io_in_e_valid),
.io_in_e_bits_sink(TLMonitor_io_in_e_bits_sink)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_b_bits_param = auto_out_b_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_b_bits_address = auto_out_b_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_c_ready = auto_out_c_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12075.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_valid = auto_in_c_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_opcode = auto_in_c_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_param = auto_in_c_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_size = auto_in_c_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_source = auto_in_c_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_address = auto_in_c_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_data = auto_in_c_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_c_bits_corrupt = auto_in_c_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_e_valid = auto_in_e_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign auto_out_e_bits_sink = auto_in_e_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12074.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12037.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12038.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_b_ready = auto_in_b_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_b_valid = auto_out_b_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_b_bits_param = auto_out_b_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_b_bits_address = auto_out_b_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_ready = auto_out_c_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_valid = auto_in_c_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_bits_opcode = auto_in_c_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_bits_param = auto_in_c_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_bits_size = auto_in_c_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_bits_source = auto_in_c_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_bits_address = auto_in_c_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_c_bits_corrupt = auto_in_c_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_e_valid = auto_in_e_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
assign TLMonitor_io_in_e_bits_sink = auto_in_e_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@12071.4]
endmodule
module SimpleLazyModule( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12230.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12231.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12232.4]
input auto_buffer_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [2:0] auto_buffer_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [2:0] auto_buffer_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [3:0] auto_buffer_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [3:0] auto_buffer_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [31:0] auto_buffer_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [7:0] auto_buffer_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [63:0] auto_buffer_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_buffer_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [1:0] auto_buffer_out_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [31:0] auto_buffer_out_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_buffer_out_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [2:0] auto_buffer_out_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [2:0] auto_buffer_out_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [3:0] auto_buffer_out_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [3:0] auto_buffer_out_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [31:0] auto_buffer_out_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [63:0] auto_buffer_out_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_buffer_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [2:0] auto_buffer_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [1:0] auto_buffer_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [3:0] auto_buffer_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [3:0] auto_buffer_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [1:0] auto_buffer_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_buffer_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [63:0] auto_buffer_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_buffer_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_buffer_out_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [1:0] auto_buffer_out_e_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_tl_master_xing_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [2:0] auto_tl_master_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [2:0] auto_tl_master_xing_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [3:0] auto_tl_master_xing_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [3:0] auto_tl_master_xing_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [31:0] auto_tl_master_xing_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [7:0] auto_tl_master_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [63:0] auto_tl_master_xing_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_tl_master_xing_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [1:0] auto_tl_master_xing_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [31:0] auto_tl_master_xing_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_tl_master_xing_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [2:0] auto_tl_master_xing_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [2:0] auto_tl_master_xing_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [3:0] auto_tl_master_xing_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [3:0] auto_tl_master_xing_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [31:0] auto_tl_master_xing_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [63:0] auto_tl_master_xing_in_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_tl_master_xing_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [2:0] auto_tl_master_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [1:0] auto_tl_master_xing_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [3:0] auto_tl_master_xing_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [3:0] auto_tl_master_xing_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [1:0] auto_tl_master_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_tl_master_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output [63:0] auto_tl_master_xing_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
output auto_tl_master_xing_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input auto_tl_master_xing_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
input [1:0] auto_tl_master_xing_in_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@12233.4]
);
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_b_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_b_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_c_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_c_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_in_c_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [63:0] buffer_auto_in_c_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_c_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_in_e_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_b_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_b_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_out_b_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [31:0] buffer_auto_out_b_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_c_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_c_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_out_c_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [63:0] buffer_auto_out_c_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_c_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire buffer_auto_out_e_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire [1:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
wire fixer_clock; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_reset; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [31:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [7:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [63:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_b_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_b_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_in_b_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [31:0] fixer_auto_in_b_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_c_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_c_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_in_c_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_in_c_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_in_c_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_in_c_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [31:0] fixer_auto_in_c_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [63:0] fixer_auto_in_c_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_c_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_in_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_in_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [63:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_in_e_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_in_e_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [31:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [7:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [63:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_b_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_b_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_out_b_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [31:0] fixer_auto_out_b_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_c_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_c_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_out_c_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_out_c_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_out_c_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_out_c_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [31:0] fixer_auto_out_c_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [63:0] fixer_auto_out_c_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_c_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_out_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [3:0] fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_out_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [63:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire fixer_auto_out_e_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
wire [1:0] fixer_auto_out_e_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
TLBuffer buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@12238.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_b_ready(buffer_auto_in_b_ready),
.auto_in_b_valid(buffer_auto_in_b_valid),
.auto_in_b_bits_param(buffer_auto_in_b_bits_param),
.auto_in_b_bits_address(buffer_auto_in_b_bits_address),
.auto_in_c_ready(buffer_auto_in_c_ready),
.auto_in_c_valid(buffer_auto_in_c_valid),
.auto_in_c_bits_opcode(buffer_auto_in_c_bits_opcode),
.auto_in_c_bits_param(buffer_auto_in_c_bits_param),
.auto_in_c_bits_size(buffer_auto_in_c_bits_size),
.auto_in_c_bits_source(buffer_auto_in_c_bits_source),
.auto_in_c_bits_address(buffer_auto_in_c_bits_address),
.auto_in_c_bits_data(buffer_auto_in_c_bits_data),
.auto_in_c_bits_corrupt(buffer_auto_in_c_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(buffer_auto_in_d_bits_param),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_in_e_valid(buffer_auto_in_e_valid),
.auto_in_e_bits_sink(buffer_auto_in_e_bits_sink),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_b_ready(buffer_auto_out_b_ready),
.auto_out_b_valid(buffer_auto_out_b_valid),
.auto_out_b_bits_param(buffer_auto_out_b_bits_param),
.auto_out_b_bits_address(buffer_auto_out_b_bits_address),
.auto_out_c_ready(buffer_auto_out_c_ready),
.auto_out_c_valid(buffer_auto_out_c_valid),
.auto_out_c_bits_opcode(buffer_auto_out_c_bits_opcode),
.auto_out_c_bits_param(buffer_auto_out_c_bits_param),
.auto_out_c_bits_size(buffer_auto_out_c_bits_size),
.auto_out_c_bits_source(buffer_auto_out_c_bits_source),
.auto_out_c_bits_address(buffer_auto_out_c_bits_address),
.auto_out_c_bits_data(buffer_auto_out_c_bits_data),
.auto_out_c_bits_corrupt(buffer_auto_out_c_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(buffer_auto_out_d_bits_param),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt),
.auto_out_e_valid(buffer_auto_out_e_valid),
.auto_out_e_bits_sink(buffer_auto_out_e_bits_sink)
);
TLFIFOFixer fixer ( // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@12244.4]
.clock(fixer_clock),
.reset(fixer_reset),
.auto_in_a_ready(fixer_auto_in_a_ready),
.auto_in_a_valid(fixer_auto_in_a_valid),
.auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fixer_auto_in_a_bits_param),
.auto_in_a_bits_size(fixer_auto_in_a_bits_size),
.auto_in_a_bits_source(fixer_auto_in_a_bits_source),
.auto_in_a_bits_address(fixer_auto_in_a_bits_address),
.auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
.auto_in_a_bits_data(fixer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
.auto_in_b_ready(fixer_auto_in_b_ready),
.auto_in_b_valid(fixer_auto_in_b_valid),
.auto_in_b_bits_param(fixer_auto_in_b_bits_param),
.auto_in_b_bits_address(fixer_auto_in_b_bits_address),
.auto_in_c_ready(fixer_auto_in_c_ready),
.auto_in_c_valid(fixer_auto_in_c_valid),
.auto_in_c_bits_opcode(fixer_auto_in_c_bits_opcode),
.auto_in_c_bits_param(fixer_auto_in_c_bits_param),
.auto_in_c_bits_size(fixer_auto_in_c_bits_size),
.auto_in_c_bits_source(fixer_auto_in_c_bits_source),
.auto_in_c_bits_address(fixer_auto_in_c_bits_address),
.auto_in_c_bits_data(fixer_auto_in_c_bits_data),
.auto_in_c_bits_corrupt(fixer_auto_in_c_bits_corrupt),
.auto_in_d_ready(fixer_auto_in_d_ready),
.auto_in_d_valid(fixer_auto_in_d_valid),
.auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(fixer_auto_in_d_bits_param),
.auto_in_d_bits_size(fixer_auto_in_d_bits_size),
.auto_in_d_bits_source(fixer_auto_in_d_bits_source),
.auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
.auto_in_d_bits_data(fixer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
.auto_in_e_valid(fixer_auto_in_e_valid),
.auto_in_e_bits_sink(fixer_auto_in_e_bits_sink),
.auto_out_a_ready(fixer_auto_out_a_ready),
.auto_out_a_valid(fixer_auto_out_a_valid),
.auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fixer_auto_out_a_bits_param),
.auto_out_a_bits_size(fixer_auto_out_a_bits_size),
.auto_out_a_bits_source(fixer_auto_out_a_bits_source),
.auto_out_a_bits_address(fixer_auto_out_a_bits_address),
.auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
.auto_out_a_bits_data(fixer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
.auto_out_b_ready(fixer_auto_out_b_ready),
.auto_out_b_valid(fixer_auto_out_b_valid),
.auto_out_b_bits_param(fixer_auto_out_b_bits_param),
.auto_out_b_bits_address(fixer_auto_out_b_bits_address),
.auto_out_c_ready(fixer_auto_out_c_ready),
.auto_out_c_valid(fixer_auto_out_c_valid),
.auto_out_c_bits_opcode(fixer_auto_out_c_bits_opcode),
.auto_out_c_bits_param(fixer_auto_out_c_bits_param),
.auto_out_c_bits_size(fixer_auto_out_c_bits_size),
.auto_out_c_bits_source(fixer_auto_out_c_bits_source),
.auto_out_c_bits_address(fixer_auto_out_c_bits_address),
.auto_out_c_bits_data(fixer_auto_out_c_bits_data),
.auto_out_c_bits_corrupt(fixer_auto_out_c_bits_corrupt),
.auto_out_d_ready(fixer_auto_out_d_ready),
.auto_out_d_valid(fixer_auto_out_d_valid),
.auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(fixer_auto_out_d_bits_param),
.auto_out_d_bits_size(fixer_auto_out_d_bits_size),
.auto_out_d_bits_source(fixer_auto_out_d_bits_source),
.auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
.auto_out_d_bits_data(fixer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt),
.auto_out_e_valid(fixer_auto_out_e_valid),
.auto_out_e_bits_sink(fixer_auto_out_e_bits_sink)
);
assign auto_buffer_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_b_ready = buffer_auto_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_valid = buffer_auto_out_c_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_opcode = buffer_auto_out_c_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_param = buffer_auto_out_c_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_size = buffer_auto_out_c_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_source = buffer_auto_out_c_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_address = buffer_auto_out_c_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_data = buffer_auto_out_c_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_c_bits_corrupt = buffer_auto_out_c_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_e_valid = buffer_auto_out_e_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_buffer_out_e_bits_sink = buffer_auto_out_e_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign auto_tl_master_xing_in_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_b_valid = fixer_auto_in_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_b_bits_param = fixer_auto_in_b_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_b_bits_address = fixer_auto_in_b_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_c_ready = fixer_auto_in_c_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign auto_tl_master_xing_in_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12257.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12242.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12243.4]
assign buffer_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_b_ready = fixer_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_valid = fixer_auto_out_c_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_opcode = fixer_auto_out_c_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_param = fixer_auto_out_c_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_size = fixer_auto_out_c_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_source = fixer_auto_out_c_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_address = fixer_auto_out_c_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_data = fixer_auto_out_c_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_c_bits_corrupt = fixer_auto_out_c_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_e_valid = fixer_auto_out_e_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_in_e_bits_sink = fixer_auto_out_e_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign buffer_auto_out_a_ready = auto_buffer_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_b_valid = auto_buffer_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_c_ready = auto_buffer_out_c_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_valid = auto_buffer_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12258.4]
assign fixer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12248.4]
assign fixer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12249.4]
assign fixer_auto_in_a_valid = auto_tl_master_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_opcode = auto_tl_master_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_param = auto_tl_master_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_size = auto_tl_master_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_source = auto_tl_master_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_address = auto_tl_master_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_mask = auto_tl_master_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_data = auto_tl_master_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_a_bits_corrupt = auto_tl_master_xing_in_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_b_ready = auto_tl_master_xing_in_b_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_valid = auto_tl_master_xing_in_c_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_opcode = auto_tl_master_xing_in_c_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_param = auto_tl_master_xing_in_c_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_size = auto_tl_master_xing_in_c_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_source = auto_tl_master_xing_in_c_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_address = auto_tl_master_xing_in_c_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_data = auto_tl_master_xing_in_c_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_c_bits_corrupt = auto_tl_master_xing_in_c_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_d_ready = auto_tl_master_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_e_valid = auto_tl_master_xing_in_e_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_in_e_bits_sink = auto_tl_master_xing_in_e_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@12256.4]
assign fixer_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_b_valid = buffer_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_b_bits_param = buffer_auto_in_b_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_b_bits_address = buffer_auto_in_b_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_c_ready = buffer_auto_in_c_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
assign fixer_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@12255.4]
endmodule
module Queue( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12260.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12261.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12262.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [30:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [1:0] io_enq_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input io_enq_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [3:0] io_enq_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [2:0] io_enq_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input [3:0] io_enq_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [30:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output io_deq_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [3:0] io_deq_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [2:0] io_deq_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
output [3:0] io_deq_bits_qos // @[:freechips.rocketchip.system.LowRiscConfig.fir@12263.4]
);
reg [3:0] _T_35_id [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_0;
wire [3:0] _T_35_id__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_id__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [3:0] _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_id__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_id__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_id__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [30:0] _T_35_addr [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_1;
wire [30:0] _T_35_addr__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_addr__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [30:0] _T_35_addr__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_addr__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_addr__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_addr__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [7:0] _T_35_len [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_2;
wire [7:0] _T_35_len__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_len__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [7:0] _T_35_len__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_len__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_len__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_len__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [2:0] _T_35_size [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_3;
wire [2:0] _T_35_size__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_size__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [2:0] _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_size__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_size__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_size__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [1:0] _T_35_burst [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_4;
wire [1:0] _T_35_burst__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_burst__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [1:0] _T_35_burst__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_burst__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_burst__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_burst__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg _T_35_lock [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_5;
wire _T_35_lock__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_lock__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_lock__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_lock__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_lock__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_lock__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [3:0] _T_35_cache [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_6;
wire [3:0] _T_35_cache__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_cache__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [3:0] _T_35_cache__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_cache__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_cache__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_cache__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [2:0] _T_35_prot [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_7;
wire [2:0] _T_35_prot__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_prot__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [2:0] _T_35_prot__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_prot__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_prot__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_prot__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [3:0] _T_35_qos [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg [31:0] _RAND_8;
wire [3:0] _T_35_qos__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_qos__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire [3:0] _T_35_qos__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_qos__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_qos__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
wire _T_35_qos__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12266.4]
reg [31:0] _RAND_9;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12267.4]
reg [31:0] _RAND_10;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@12268.4]
reg [31:0] _RAND_11;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12269.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12270.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12271.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12272.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12273.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12276.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12292.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12298.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12301.4]
assign _T_35_id__T_58_addr = value_1;
assign _T_35_id__T_58_data = _T_35_id[_T_35_id__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_id__T_50_data = io_enq_bits_id;
assign _T_35_id__T_50_addr = value;
assign _T_35_id__T_50_mask = 1'h1;
assign _T_35_id__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_addr__T_58_addr = value_1;
assign _T_35_addr__T_58_data = _T_35_addr[_T_35_addr__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_addr__T_50_data = io_enq_bits_addr;
assign _T_35_addr__T_50_addr = value;
assign _T_35_addr__T_50_mask = 1'h1;
assign _T_35_addr__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_len__T_58_addr = value_1;
assign _T_35_len__T_58_data = _T_35_len[_T_35_len__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_len__T_50_data = io_enq_bits_len;
assign _T_35_len__T_50_addr = value;
assign _T_35_len__T_50_mask = 1'h1;
assign _T_35_len__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_58_addr = value_1;
assign _T_35_size__T_58_data = _T_35_size[_T_35_size__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_size__T_50_data = io_enq_bits_size;
assign _T_35_size__T_50_addr = value;
assign _T_35_size__T_50_mask = 1'h1;
assign _T_35_size__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_burst__T_58_addr = value_1;
assign _T_35_burst__T_58_data = _T_35_burst[_T_35_burst__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_burst__T_50_data = io_enq_bits_burst;
assign _T_35_burst__T_50_addr = value;
assign _T_35_burst__T_50_mask = 1'h1;
assign _T_35_burst__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_lock__T_58_addr = value_1;
assign _T_35_lock__T_58_data = _T_35_lock[_T_35_lock__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_lock__T_50_data = io_enq_bits_lock;
assign _T_35_lock__T_50_addr = value;
assign _T_35_lock__T_50_mask = 1'h1;
assign _T_35_lock__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_cache__T_58_addr = value_1;
assign _T_35_cache__T_58_data = _T_35_cache[_T_35_cache__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_cache__T_50_data = io_enq_bits_cache;
assign _T_35_cache__T_50_addr = value;
assign _T_35_cache__T_50_mask = 1'h1;
assign _T_35_cache__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_prot__T_58_addr = value_1;
assign _T_35_prot__T_58_data = _T_35_prot[_T_35_prot__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_prot__T_50_data = io_enq_bits_prot;
assign _T_35_prot__T_50_addr = value;
assign _T_35_prot__T_50_mask = 1'h1;
assign _T_35_prot__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_qos__T_58_addr = value_1;
assign _T_35_qos__T_58_data = _T_35_qos[_T_35_qos__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
assign _T_35_qos__T_50_data = io_enq_bits_qos;
assign _T_35_qos__T_50_addr = value;
assign _T_35_qos__T_50_mask = 1'h1;
assign _T_35_qos__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12269.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12270.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12271.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12272.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12273.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12276.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12292.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12298.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12301.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@12308.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@12306.4]
assign io_deq_bits_id = _T_35_id__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12318.4]
assign io_deq_bits_addr = _T_35_addr__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12317.4]
assign io_deq_bits_len = _T_35_len__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12316.4]
assign io_deq_bits_size = _T_35_size__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12315.4]
assign io_deq_bits_burst = _T_35_burst__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12314.4]
assign io_deq_bits_lock = _T_35_lock__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12313.4]
assign io_deq_bits_cache = _T_35_cache__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12312.4]
assign io_deq_bits_prot = _T_35_prot__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12311.4]
assign io_deq_bits_qos = _T_35_qos__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12310.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_addr[initvar] = _RAND_1[30:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_len[initvar] = _RAND_2[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_size[initvar] = _RAND_3[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_burst[initvar] = _RAND_4[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_lock[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_cache[initvar] = _RAND_6[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_prot[initvar] = _RAND_7[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_8 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_qos[initvar] = _RAND_8[3:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
value_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_39 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_50_en & _T_35_id__T_50_mask) begin
_T_35_id[_T_35_id__T_50_addr] <= _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_addr__T_50_en & _T_35_addr__T_50_mask) begin
_T_35_addr[_T_35_addr__T_50_addr] <= _T_35_addr__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_len__T_50_en & _T_35_len__T_50_mask) begin
_T_35_len[_T_35_len__T_50_addr] <= _T_35_len__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_size__T_50_en & _T_35_size__T_50_mask) begin
_T_35_size[_T_35_size__T_50_addr] <= _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_burst__T_50_en & _T_35_burst__T_50_mask) begin
_T_35_burst[_T_35_burst__T_50_addr] <= _T_35_burst__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_lock__T_50_en & _T_35_lock__T_50_mask) begin
_T_35_lock[_T_35_lock__T_50_addr] <= _T_35_lock__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_cache__T_50_en & _T_35_cache__T_50_mask) begin
_T_35_cache[_T_35_cache__T_50_addr] <= _T_35_cache__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_prot__T_50_en & _T_35_prot__T_50_mask) begin
_T_35_prot[_T_35_prot__T_50_addr] <= _T_35_prot__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if(_T_35_qos__T_50_en & _T_35_qos__T_50_mask) begin
_T_35_qos[_T_35_qos__T_50_addr] <= _T_35_qos__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12265.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module Queue_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12326.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12327.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12328.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
input [7:0] io_enq_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
input io_enq_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
output [7:0] io_deq_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
output io_deq_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@12329.4]
);
reg [63:0] _T_35_data [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
reg [63:0] _RAND_0;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
reg [7:0] _T_35_strb [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
reg [31:0] _RAND_1;
wire [7:0] _T_35_strb__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_strb__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire [7:0] _T_35_strb__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_strb__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_strb__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_strb__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
reg _T_35_last [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
reg [31:0] _RAND_2;
wire _T_35_last__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_last__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_last__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_last__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_last__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
wire _T_35_last__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12332.4]
reg [31:0] _RAND_3;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12333.4]
reg [31:0] _RAND_4;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@12334.4]
reg [31:0] _RAND_5;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12335.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12336.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12337.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12338.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12339.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12342.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12352.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12358.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12361.4]
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_strb__T_58_addr = value_1;
assign _T_35_strb__T_58_data = _T_35_strb[_T_35_strb__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
assign _T_35_strb__T_50_data = io_enq_bits_strb;
assign _T_35_strb__T_50_addr = value;
assign _T_35_strb__T_50_mask = 1'h1;
assign _T_35_strb__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_last__T_58_addr = value_1;
assign _T_35_last__T_58_data = _T_35_last[_T_35_last__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
assign _T_35_last__T_50_data = io_enq_bits_last;
assign _T_35_last__T_50_addr = value;
assign _T_35_last__T_50_mask = 1'h1;
assign _T_35_last__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12335.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12336.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12337.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12338.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12339.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12342.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12352.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12358.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12361.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@12368.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@12366.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12372.4]
assign io_deq_bits_strb = _T_35_strb__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12371.4]
assign io_deq_bits_last = _T_35_last__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12370.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_data[initvar] = _RAND_0[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_strb[initvar] = _RAND_1[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_last[initvar] = _RAND_2[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
value = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
value_1 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_39 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
end
if(_T_35_strb__T_50_en & _T_35_strb__T_50_mask) begin
_T_35_strb[_T_35_strb__T_50_addr] <= _T_35_strb__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
end
if(_T_35_last__T_50_en & _T_35_last__T_50_mask) begin
_T_35_last[_T_35_last__T_50_addr] <= _T_35_last__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12331.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module Queue_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12380.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12381.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12382.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
output [1:0] io_deq_bits_resp // @[:freechips.rocketchip.system.LowRiscConfig.fir@12383.4]
);
reg [3:0] _T_35_id [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
reg [31:0] _RAND_0;
wire [3:0] _T_35_id__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_id__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire [3:0] _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_id__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_id__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_id__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
reg [1:0] _T_35_resp [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
reg [31:0] _RAND_1;
wire [1:0] _T_35_resp__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_resp__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire [1:0] _T_35_resp__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_resp__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_resp__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
wire _T_35_resp__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12386.4]
reg [31:0] _RAND_2;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12387.4]
reg [31:0] _RAND_3;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@12388.4]
reg [31:0] _RAND_4;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12389.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12390.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12391.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12392.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12393.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12396.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12405.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12411.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12414.4]
assign _T_35_id__T_58_addr = value_1;
assign _T_35_id__T_58_data = _T_35_id[_T_35_id__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
assign _T_35_id__T_50_data = io_enq_bits_id;
assign _T_35_id__T_50_addr = value;
assign _T_35_id__T_50_mask = 1'h1;
assign _T_35_id__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_resp__T_58_addr = value_1;
assign _T_35_resp__T_58_data = _T_35_resp[_T_35_resp__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
assign _T_35_resp__T_50_data = io_enq_bits_resp;
assign _T_35_resp__T_50_addr = value;
assign _T_35_resp__T_50_mask = 1'h1;
assign _T_35_resp__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12389.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12390.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12391.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12392.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12393.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12396.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12405.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12411.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12414.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@12421.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@12419.4]
assign io_deq_bits_id = _T_35_id__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12424.4]
assign io_deq_bits_resp = _T_35_resp__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12423.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_resp[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
value = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
value_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_39 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_50_en & _T_35_id__T_50_mask) begin
_T_35_id[_T_35_id__T_50_addr] <= _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
end
if(_T_35_resp__T_50_en & _T_35_resp__T_50_mask) begin
_T_35_resp[_T_35_resp__T_50_addr] <= _T_35_resp__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12385.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module Queue_4( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12498.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12499.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12500.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
input io_enq_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
output io_deq_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@12501.4]
);
reg [3:0] _T_35_id [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg [31:0] _RAND_0;
wire [3:0] _T_35_id__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_id__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire [3:0] _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_id__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_id__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_id__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg [63:0] _T_35_data [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg [63:0] _RAND_1;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg [1:0] _T_35_resp [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg [31:0] _RAND_2;
wire [1:0] _T_35_resp__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_resp__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire [1:0] _T_35_resp__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_resp__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_resp__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_resp__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg _T_35_last [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg [31:0] _RAND_3;
wire _T_35_last__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_last__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_last__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_last__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_last__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
wire _T_35_last__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12504.4]
reg [31:0] _RAND_4;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12505.4]
reg [31:0] _RAND_5;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@12506.4]
reg [31:0] _RAND_6;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12507.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12508.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12509.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12510.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12511.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12514.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12525.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12531.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12534.4]
assign _T_35_id__T_58_addr = value_1;
assign _T_35_id__T_58_data = _T_35_id[_T_35_id__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
assign _T_35_id__T_50_data = io_enq_bits_id;
assign _T_35_id__T_50_addr = value;
assign _T_35_id__T_50_mask = 1'h1;
assign _T_35_id__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_resp__T_58_addr = value_1;
assign _T_35_resp__T_58_data = _T_35_resp[_T_35_resp__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
assign _T_35_resp__T_50_data = io_enq_bits_resp;
assign _T_35_resp__T_50_addr = value;
assign _T_35_resp__T_50_mask = 1'h1;
assign _T_35_resp__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_last__T_58_addr = value_1;
assign _T_35_last__T_58_data = _T_35_last[_T_35_last__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
assign _T_35_last__T_50_data = io_enq_bits_last;
assign _T_35_last__T_50_addr = value;
assign _T_35_last__T_50_mask = 1'h1;
assign _T_35_last__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12507.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12508.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12509.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12510.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12511.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12514.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12525.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12531.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12534.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@12541.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@12539.4]
assign io_deq_bits_id = _T_35_id__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12546.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12545.4]
assign io_deq_bits_resp = _T_35_resp__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12544.4]
assign io_deq_bits_last = _T_35_last__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12543.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_data[initvar] = _RAND_1[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_resp[initvar] = _RAND_2[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_last[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
value = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
value_1 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_39 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_50_en & _T_35_id__T_50_mask) begin
_T_35_id[_T_35_id__T_50_addr] <= _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
end
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
end
if(_T_35_resp__T_50_en & _T_35_resp__T_50_mask) begin
_T_35_resp[_T_35_resp__T_50_addr] <= _T_35_resp__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
end
if(_T_35_last__T_50_en & _T_35_last__T_50_mask) begin
_T_35_last[_T_35_last__T_50_addr] <= _T_35_last__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12503.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module AXI4Buffer( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12554.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12555.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12556.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@12557.4]
);
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [3:0] Queue_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [30:0] Queue_io_enq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [7:0] Queue_io_enq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [2:0] Queue_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [1:0] Queue_io_enq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_io_enq_bits_lock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [3:0] Queue_io_enq_bits_cache; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [2:0] Queue_io_enq_bits_prot; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [3:0] Queue_io_enq_bits_qos; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [3:0] Queue_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [30:0] Queue_io_deq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [7:0] Queue_io_deq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [2:0] Queue_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [1:0] Queue_io_deq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_io_deq_bits_lock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [3:0] Queue_io_deq_bits_cache; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [2:0] Queue_io_deq_bits_prot; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire [3:0] Queue_io_deq_bits_qos; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire [63:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire [7:0] Queue_1_io_enq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_io_enq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire [63:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire [7:0] Queue_1_io_deq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_1_io_deq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
wire Queue_2_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire Queue_2_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire Queue_2_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire Queue_2_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire [3:0] Queue_2_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire [1:0] Queue_2_io_enq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire Queue_2_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire Queue_2_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire [3:0] Queue_2_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire [1:0] Queue_2_io_deq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
wire Queue_3_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [3:0] Queue_3_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [30:0] Queue_3_io_enq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [7:0] Queue_3_io_enq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [2:0] Queue_3_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [1:0] Queue_3_io_enq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_io_enq_bits_lock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [3:0] Queue_3_io_enq_bits_cache; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [2:0] Queue_3_io_enq_bits_prot; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [3:0] Queue_3_io_enq_bits_qos; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [3:0] Queue_3_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [30:0] Queue_3_io_deq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [7:0] Queue_3_io_deq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [2:0] Queue_3_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [1:0] Queue_3_io_deq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_3_io_deq_bits_lock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [3:0] Queue_3_io_deq_bits_cache; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [2:0] Queue_3_io_deq_bits_prot; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire [3:0] Queue_3_io_deq_bits_qos; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
wire Queue_4_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire [3:0] Queue_4_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire [63:0] Queue_4_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire [1:0] Queue_4_io_enq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_io_enq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire [3:0] Queue_4_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire [63:0] Queue_4_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire [1:0] Queue_4_io_deq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
wire Queue_4_io_deq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
Queue Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12568.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_id(Queue_io_enq_bits_id),
.io_enq_bits_addr(Queue_io_enq_bits_addr),
.io_enq_bits_len(Queue_io_enq_bits_len),
.io_enq_bits_size(Queue_io_enq_bits_size),
.io_enq_bits_burst(Queue_io_enq_bits_burst),
.io_enq_bits_lock(Queue_io_enq_bits_lock),
.io_enq_bits_cache(Queue_io_enq_bits_cache),
.io_enq_bits_prot(Queue_io_enq_bits_prot),
.io_enq_bits_qos(Queue_io_enq_bits_qos),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_id(Queue_io_deq_bits_id),
.io_deq_bits_addr(Queue_io_deq_bits_addr),
.io_deq_bits_len(Queue_io_deq_bits_len),
.io_deq_bits_size(Queue_io_deq_bits_size),
.io_deq_bits_burst(Queue_io_deq_bits_burst),
.io_deq_bits_lock(Queue_io_deq_bits_lock),
.io_deq_bits_cache(Queue_io_deq_bits_cache),
.io_deq_bits_prot(Queue_io_deq_bits_prot),
.io_deq_bits_qos(Queue_io_deq_bits_qos)
);
Queue_1 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12595.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_strb(Queue_1_io_enq_bits_strb),
.io_enq_bits_last(Queue_1_io_enq_bits_last),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_strb(Queue_1_io_deq_bits_strb),
.io_deq_bits_last(Queue_1_io_deq_bits_last)
);
Queue_2 Queue_2 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12610.4]
.clock(Queue_2_clock),
.reset(Queue_2_reset),
.io_enq_ready(Queue_2_io_enq_ready),
.io_enq_valid(Queue_2_io_enq_valid),
.io_enq_bits_id(Queue_2_io_enq_bits_id),
.io_enq_bits_resp(Queue_2_io_enq_bits_resp),
.io_deq_ready(Queue_2_io_deq_ready),
.io_deq_valid(Queue_2_io_deq_valid),
.io_deq_bits_id(Queue_2_io_deq_bits_id),
.io_deq_bits_resp(Queue_2_io_deq_bits_resp)
);
Queue Queue_3 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12623.4]
.clock(Queue_3_clock),
.reset(Queue_3_reset),
.io_enq_ready(Queue_3_io_enq_ready),
.io_enq_valid(Queue_3_io_enq_valid),
.io_enq_bits_id(Queue_3_io_enq_bits_id),
.io_enq_bits_addr(Queue_3_io_enq_bits_addr),
.io_enq_bits_len(Queue_3_io_enq_bits_len),
.io_enq_bits_size(Queue_3_io_enq_bits_size),
.io_enq_bits_burst(Queue_3_io_enq_bits_burst),
.io_enq_bits_lock(Queue_3_io_enq_bits_lock),
.io_enq_bits_cache(Queue_3_io_enq_bits_cache),
.io_enq_bits_prot(Queue_3_io_enq_bits_prot),
.io_enq_bits_qos(Queue_3_io_enq_bits_qos),
.io_deq_ready(Queue_3_io_deq_ready),
.io_deq_valid(Queue_3_io_deq_valid),
.io_deq_bits_id(Queue_3_io_deq_bits_id),
.io_deq_bits_addr(Queue_3_io_deq_bits_addr),
.io_deq_bits_len(Queue_3_io_deq_bits_len),
.io_deq_bits_size(Queue_3_io_deq_bits_size),
.io_deq_bits_burst(Queue_3_io_deq_bits_burst),
.io_deq_bits_lock(Queue_3_io_deq_bits_lock),
.io_deq_bits_cache(Queue_3_io_deq_bits_cache),
.io_deq_bits_prot(Queue_3_io_deq_bits_prot),
.io_deq_bits_qos(Queue_3_io_deq_bits_qos)
);
Queue_4 Queue_4 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@12650.4]
.clock(Queue_4_clock),
.reset(Queue_4_reset),
.io_enq_ready(Queue_4_io_enq_ready),
.io_enq_valid(Queue_4_io_enq_valid),
.io_enq_bits_id(Queue_4_io_enq_bits_id),
.io_enq_bits_data(Queue_4_io_enq_bits_data),
.io_enq_bits_resp(Queue_4_io_enq_bits_resp),
.io_enq_bits_last(Queue_4_io_enq_bits_last),
.io_deq_ready(Queue_4_io_deq_ready),
.io_deq_valid(Queue_4_io_deq_valid),
.io_deq_bits_id(Queue_4_io_deq_bits_id),
.io_deq_bits_data(Queue_4_io_deq_bits_data),
.io_deq_bits_resp(Queue_4_io_deq_bits_resp),
.io_deq_bits_last(Queue_4_io_deq_bits_last)
);
assign auto_in_aw_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_w_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_b_valid = Queue_2_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_b_bits_id = Queue_2_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_b_bits_resp = Queue_2_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_ar_ready = Queue_3_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_r_valid = Queue_4_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_r_bits_id = Queue_4_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_r_bits_data = Queue_4_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_r_bits_resp = Queue_4_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_in_r_bits_last = Queue_4_io_deq_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@12567.4]
assign auto_out_aw_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_addr = Queue_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_len = Queue_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_burst = Queue_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_lock = Queue_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_cache = Queue_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_prot = Queue_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_aw_bits_qos = Queue_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_w_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_w_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_w_bits_strb = Queue_1_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_w_bits_last = Queue_1_io_deq_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_b_ready = Queue_2_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_valid = Queue_3_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_id = Queue_3_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_addr = Queue_3_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_len = Queue_3_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_size = Queue_3_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_burst = Queue_3_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_lock = Queue_3_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_cache = Queue_3_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_prot = Queue_3_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_ar_bits_qos = Queue_3_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign auto_out_r_ready = Queue_4_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@12566.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12569.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12570.4]
assign Queue_io_enq_valid = auto_in_aw_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@12571.4]
assign Queue_io_enq_bits_id = auto_in_aw_bits_id; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12580.4]
assign Queue_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12579.4]
assign Queue_io_enq_bits_len = auto_in_aw_bits_len; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12578.4]
assign Queue_io_enq_bits_size = auto_in_aw_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12577.4]
assign Queue_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12576.4]
assign Queue_io_enq_bits_lock = auto_in_aw_bits_lock; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12575.4]
assign Queue_io_enq_bits_cache = auto_in_aw_bits_cache; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12574.4]
assign Queue_io_enq_bits_prot = auto_in_aw_bits_prot; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12573.4]
assign Queue_io_enq_bits_qos = auto_in_aw_bits_qos; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12572.4]
assign Queue_io_deq_ready = auto_out_aw_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@12593.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12596.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12597.4]
assign Queue_1_io_enq_valid = auto_in_w_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@12598.4]
assign Queue_1_io_enq_bits_data = auto_in_w_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12601.4]
assign Queue_1_io_enq_bits_strb = auto_in_w_bits_strb; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12600.4]
assign Queue_1_io_enq_bits_last = auto_in_w_bits_last; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12599.4]
assign Queue_1_io_deq_ready = auto_out_w_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@12608.4]
assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12611.4]
assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12612.4]
assign Queue_2_io_enq_valid = auto_out_b_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@12613.4]
assign Queue_2_io_enq_bits_id = auto_out_b_bits_id; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12615.4]
assign Queue_2_io_enq_bits_resp = auto_out_b_bits_resp; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12614.4]
assign Queue_2_io_deq_ready = auto_in_b_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@12621.4]
assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12624.4]
assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12625.4]
assign Queue_3_io_enq_valid = auto_in_ar_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@12626.4]
assign Queue_3_io_enq_bits_id = auto_in_ar_bits_id; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12635.4]
assign Queue_3_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12634.4]
assign Queue_3_io_enq_bits_len = auto_in_ar_bits_len; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12633.4]
assign Queue_3_io_enq_bits_size = auto_in_ar_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12632.4]
assign Queue_3_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12631.4]
assign Queue_3_io_enq_bits_lock = auto_in_ar_bits_lock; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12630.4]
assign Queue_3_io_enq_bits_cache = auto_in_ar_bits_cache; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12629.4]
assign Queue_3_io_enq_bits_prot = auto_in_ar_bits_prot; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12628.4]
assign Queue_3_io_enq_bits_qos = auto_in_ar_bits_qos; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12627.4]
assign Queue_3_io_deq_ready = auto_out_ar_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@12648.4]
assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12651.4]
assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@12652.4]
assign Queue_4_io_enq_valid = auto_out_r_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@12653.4]
assign Queue_4_io_enq_bits_id = auto_out_r_bits_id; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12657.4]
assign Queue_4_io_enq_bits_data = auto_out_r_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12656.4]
assign Queue_4_io_enq_bits_resp = auto_out_r_bits_resp; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12655.4]
assign Queue_4_io_enq_bits_last = auto_out_r_bits_last; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@12654.4]
assign Queue_4_io_deq_ready = auto_in_r_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@12665.4]
endmodule
module Queue_5( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12668.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12669.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12670.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12671.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12671.4]
input [8:0] io_enq_bits, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12671.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12671.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12671.4]
output [8:0] io_deq_bits // @[:freechips.rocketchip.system.LowRiscConfig.fir@12671.4]
);
reg [8:0] _T_35 [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
reg [31:0] _RAND_0;
wire [8:0] _T_35__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
wire _T_35__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
wire [8:0] _T_35__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
wire _T_35__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
wire _T_35__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
wire _T_35__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@12677.4]
reg [31:0] _RAND_1;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12679.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12682.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12686.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12696.4]
assign _T_35__T_52_addr = 1'h0;
assign _T_35__T_52_data = _T_35[_T_35__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
assign _T_35__T_48_data = io_enq_bits;
assign _T_35__T_48_addr = 1'h0;
assign _T_35__T_48_mask = 1'h1;
assign _T_35__T_48_en = io_enq_ready & io_enq_valid;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12679.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12682.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12686.4]
assign _T_49 = _T_42 != _T_45; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12696.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@12703.4]
assign io_deq_valid = _T_39 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@12701.4]
assign io_deq_bits = _T_35__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12705.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35[initvar] = _RAND_0[8:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_37 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35__T_48_en & _T_35__T_48_mask) begin
_T_35[_T_35__T_48_addr] <= _T_35__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12676.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
_T_37 <= _T_42;
end
end
end
endmodule
module Queue_7( // @[:freechips.rocketchip.system.LowRiscConfig.fir@12758.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12759.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12760.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12761.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12761.4]
input [8:0] io_enq_bits, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12761.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12761.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@12761.4]
output [8:0] io_deq_bits // @[:freechips.rocketchip.system.LowRiscConfig.fir@12761.4]
);
reg [8:0] _T_35 [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
reg [31:0] _RAND_0;
wire [8:0] _T_35__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
wire [2:0] _T_35__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
wire [8:0] _T_35__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
wire [2:0] _T_35__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
wire _T_35__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
wire _T_35__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
reg [2:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12767.4]
reg [31:0] _RAND_1;
reg [2:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@12768.4]
reg [31:0] _RAND_2;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@12769.4]
reg [31:0] _RAND_3;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12770.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12771.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12772.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12773.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12774.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12778.4]
wire [2:0] _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12787.6]
wire [2:0] _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12793.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12796.4]
assign _T_35__T_58_addr = value_1;
assign _T_35__T_58_data = _T_35[_T_35__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
assign _T_35__T_50_data = io_enq_bits;
assign _T_35__T_50_addr = value;
assign _T_35__T_50_mask = 1'h1;
assign _T_35__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@12770.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@12771.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@12772.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@12773.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12774.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@12778.4]
assign _T_52 = value + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12787.6]
assign _T_54 = value_1 + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@12793.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@12796.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@12803.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@12801.4]
assign io_deq_bits = _T_35__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@12805.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35[initvar] = _RAND_0[8:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
value = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
value_1 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_39 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35__T_50_en & _T_35__T_50_mask) begin
_T_35[_T_35__T_50_addr] <= _T_35__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@12766.4]
end
if (reset) begin
value <= 3'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 3'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module AXI4UserYanker( // @[:freechips.rocketchip.system.LowRiscConfig.fir@13428.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13429.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13430.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [8:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [8:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [8:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [8:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@13431.4]
);
wire Queue_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire Queue_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire Queue_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire Queue_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire [8:0] Queue_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire Queue_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire Queue_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire [8:0] Queue_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
wire Queue_1_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire Queue_1_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire Queue_1_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire Queue_1_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire [8:0] Queue_1_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire Queue_1_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire Queue_1_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire [8:0] Queue_1_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
wire Queue_2_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire Queue_2_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire Queue_2_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire Queue_2_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire [8:0] Queue_2_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire Queue_2_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire Queue_2_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire [8:0] Queue_2_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
wire Queue_3_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire Queue_3_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire Queue_3_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire Queue_3_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire [8:0] Queue_3_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire Queue_3_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire Queue_3_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire [8:0] Queue_3_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
wire Queue_4_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire Queue_4_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire Queue_4_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire Queue_4_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire [8:0] Queue_4_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire Queue_4_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire Queue_4_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire [8:0] Queue_4_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
wire Queue_5_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire Queue_5_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire Queue_5_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire Queue_5_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire [8:0] Queue_5_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire Queue_5_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire Queue_5_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire [8:0] Queue_5_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
wire Queue_6_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire Queue_6_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire Queue_6_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire Queue_6_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire [8:0] Queue_6_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire Queue_6_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire Queue_6_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire [8:0] Queue_6_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
wire Queue_7_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire Queue_7_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire Queue_7_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire Queue_7_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire [8:0] Queue_7_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire Queue_7_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire Queue_7_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire [8:0] Queue_7_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
wire Queue_8_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire Queue_8_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire Queue_8_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire Queue_8_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire [8:0] Queue_8_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire Queue_8_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire Queue_8_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire [8:0] Queue_8_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
wire Queue_9_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire Queue_9_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire Queue_9_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire Queue_9_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire [8:0] Queue_9_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire Queue_9_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire Queue_9_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire [8:0] Queue_9_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
wire Queue_10_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire Queue_10_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire Queue_10_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire Queue_10_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire [8:0] Queue_10_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire Queue_10_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire Queue_10_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire [8:0] Queue_10_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
wire Queue_11_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire Queue_11_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire Queue_11_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire Queue_11_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire [8:0] Queue_11_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire Queue_11_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire Queue_11_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire [8:0] Queue_11_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
wire Queue_12_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire Queue_12_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire Queue_12_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire Queue_12_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire [8:0] Queue_12_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire Queue_12_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire Queue_12_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire [8:0] Queue_12_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
wire Queue_13_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire Queue_13_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire Queue_13_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire Queue_13_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire [8:0] Queue_13_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire Queue_13_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire Queue_13_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire [8:0] Queue_13_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
wire Queue_14_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire Queue_14_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire Queue_14_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire Queue_14_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire [8:0] Queue_14_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire Queue_14_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire Queue_14_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire [8:0] Queue_14_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
wire Queue_15_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire Queue_15_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire Queue_15_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire Queue_15_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire [8:0] Queue_15_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire Queue_15_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire Queue_15_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire [8:0] Queue_15_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
wire _T_736_0; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13540.4]
wire _T_736_1; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13541.4]
wire _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_736_2; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13542.4]
wire _GEN_2; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_736_3; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13543.4]
wire _GEN_3; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_736_4; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13544.4]
wire _GEN_4; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_736_5; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13545.4]
wire _GEN_5; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_736_6; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13546.4]
wire _GEN_6; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_736_7; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13547.4]
wire _GEN_7; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_8; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_9; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_10; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_11; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_12; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_13; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_14; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _GEN_15; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
wire _T_804; // @[UserYanker.scala 54:15:freechips.rocketchip.system.LowRiscConfig.fir@13597.4]
wire _T_761_0; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13563.4]
wire _T_761_1; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13564.4]
wire _GEN_17; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_761_2; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13565.4]
wire _GEN_18; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_761_3; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13566.4]
wire _GEN_19; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_761_4; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13567.4]
wire _GEN_20; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_761_5; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13568.4]
wire _GEN_21; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_761_6; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13569.4]
wire _GEN_22; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_761_7; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13570.4]
wire _GEN_23; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_24; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_25; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_26; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_27; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_28; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_29; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_30; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _GEN_31; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_805; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
wire _T_807; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@13600.4]
wire _T_808; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@13601.4]
wire [8:0] _T_784_0; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13581.4]
wire [8:0] _T_784_1; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13582.4]
wire [8:0] _GEN_33; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _T_784_2; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13583.4]
wire [8:0] _GEN_34; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _T_784_3; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13584.4]
wire [8:0] _GEN_35; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _T_784_4; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13585.4]
wire [8:0] _GEN_36; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _T_784_5; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13586.4]
wire [8:0] _GEN_37; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _T_784_6; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13587.4]
wire [8:0] _GEN_38; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _T_784_7; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13588.4]
wire [8:0] _GEN_39; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_40; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_41; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_42; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_43; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_44; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_45; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [8:0] _GEN_46; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
wire [15:0] _T_810; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13609.4]
wire _T_812; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13611.4]
wire _T_813; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13612.4]
wire _T_814; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13613.4]
wire _T_815; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13614.4]
wire _T_816; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13615.4]
wire _T_817; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13616.4]
wire _T_818; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13617.4]
wire _T_819; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13618.4]
wire [15:0] _T_829; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13628.4]
wire _T_831; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13630.4]
wire _T_832; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13631.4]
wire _T_833; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13632.4]
wire _T_834; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13633.4]
wire _T_835; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13634.4]
wire _T_836; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13635.4]
wire _T_837; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13636.4]
wire _T_838; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13637.4]
wire _T_847; // @[UserYanker.scala 61:37:freechips.rocketchip.system.LowRiscConfig.fir@13646.4]
wire _T_848; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13647.4]
wire _T_850; // @[UserYanker.scala 62:37:freechips.rocketchip.system.LowRiscConfig.fir@13650.4]
wire _T_853; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13655.4]
wire _T_858; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13663.4]
wire _T_863; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13671.4]
wire _T_868; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13679.4]
wire _T_873; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13687.4]
wire _T_878; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13695.4]
wire _T_883; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13703.4]
wire _T_930_0; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13776.4]
wire _T_930_1; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13777.4]
wire _GEN_49; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_930_2; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13778.4]
wire _GEN_50; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_930_3; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13779.4]
wire _GEN_51; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_930_4; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13780.4]
wire _GEN_52; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_930_5; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13781.4]
wire _GEN_53; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_930_6; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13782.4]
wire _GEN_54; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_930_7; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13783.4]
wire _GEN_55; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_56; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_57; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_58; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_59; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_60; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_61; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_62; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _GEN_63; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
wire _T_998; // @[UserYanker.scala 75:15:freechips.rocketchip.system.LowRiscConfig.fir@13833.4]
wire _T_955_0; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13799.4]
wire _T_955_1; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13800.4]
wire _GEN_65; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_955_2; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13801.4]
wire _GEN_66; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_955_3; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13802.4]
wire _GEN_67; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_955_4; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13803.4]
wire _GEN_68; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_955_5; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13804.4]
wire _GEN_69; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_955_6; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13805.4]
wire _GEN_70; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_955_7; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13806.4]
wire _GEN_71; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_72; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_73; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_74; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_75; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_76; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_77; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_78; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _GEN_79; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_999; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
wire _T_1001; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@13836.4]
wire _T_1002; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@13837.4]
wire [8:0] _T_978_0; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13817.4]
wire [8:0] _T_978_1; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13818.4]
wire [8:0] _GEN_81; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _T_978_2; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13819.4]
wire [8:0] _GEN_82; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _T_978_3; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13820.4]
wire [8:0] _GEN_83; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _T_978_4; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13821.4]
wire [8:0] _GEN_84; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _T_978_5; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13822.4]
wire [8:0] _GEN_85; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _T_978_6; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13823.4]
wire [8:0] _GEN_86; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _T_978_7; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13824.4]
wire [8:0] _GEN_87; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_88; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_89; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_90; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_91; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_92; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_93; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [8:0] _GEN_94; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
wire [15:0] _T_1004; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13845.4]
wire _T_1006; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13847.4]
wire _T_1007; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13848.4]
wire _T_1008; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13849.4]
wire _T_1009; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13850.4]
wire _T_1010; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13851.4]
wire _T_1011; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13852.4]
wire _T_1012; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13853.4]
wire _T_1013; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13854.4]
wire [15:0] _T_1023; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13864.4]
wire _T_1025; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13866.4]
wire _T_1026; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13867.4]
wire _T_1027; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13868.4]
wire _T_1028; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13869.4]
wire _T_1029; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13870.4]
wire _T_1030; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13871.4]
wire _T_1031; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13872.4]
wire _T_1032; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13873.4]
wire _T_1041; // @[UserYanker.scala 82:37:freechips.rocketchip.system.LowRiscConfig.fir@13882.4]
wire _T_1043; // @[UserYanker.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@13885.4]
Queue_5 Queue ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13442.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits(Queue_io_enq_bits),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits(Queue_io_deq_bits)
);
Queue_5 Queue_1 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13446.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits(Queue_1_io_enq_bits),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits(Queue_1_io_deq_bits)
);
Queue_7 Queue_2 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13450.4]
.clock(Queue_2_clock),
.reset(Queue_2_reset),
.io_enq_ready(Queue_2_io_enq_ready),
.io_enq_valid(Queue_2_io_enq_valid),
.io_enq_bits(Queue_2_io_enq_bits),
.io_deq_ready(Queue_2_io_deq_ready),
.io_deq_valid(Queue_2_io_deq_valid),
.io_deq_bits(Queue_2_io_deq_bits)
);
Queue_7 Queue_3 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13454.4]
.clock(Queue_3_clock),
.reset(Queue_3_reset),
.io_enq_ready(Queue_3_io_enq_ready),
.io_enq_valid(Queue_3_io_enq_valid),
.io_enq_bits(Queue_3_io_enq_bits),
.io_deq_ready(Queue_3_io_deq_ready),
.io_deq_valid(Queue_3_io_deq_valid),
.io_deq_bits(Queue_3_io_deq_bits)
);
Queue_5 Queue_4 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13458.4]
.clock(Queue_4_clock),
.reset(Queue_4_reset),
.io_enq_ready(Queue_4_io_enq_ready),
.io_enq_valid(Queue_4_io_enq_valid),
.io_enq_bits(Queue_4_io_enq_bits),
.io_deq_ready(Queue_4_io_deq_ready),
.io_deq_valid(Queue_4_io_deq_valid),
.io_deq_bits(Queue_4_io_deq_bits)
);
Queue_5 Queue_5 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13462.4]
.clock(Queue_5_clock),
.reset(Queue_5_reset),
.io_enq_ready(Queue_5_io_enq_ready),
.io_enq_valid(Queue_5_io_enq_valid),
.io_enq_bits(Queue_5_io_enq_bits),
.io_deq_ready(Queue_5_io_deq_ready),
.io_deq_valid(Queue_5_io_deq_valid),
.io_deq_bits(Queue_5_io_deq_bits)
);
Queue_5 Queue_6 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13466.4]
.clock(Queue_6_clock),
.reset(Queue_6_reset),
.io_enq_ready(Queue_6_io_enq_ready),
.io_enq_valid(Queue_6_io_enq_valid),
.io_enq_bits(Queue_6_io_enq_bits),
.io_deq_ready(Queue_6_io_deq_ready),
.io_deq_valid(Queue_6_io_deq_valid),
.io_deq_bits(Queue_6_io_deq_bits)
);
Queue_5 Queue_7 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13470.4]
.clock(Queue_7_clock),
.reset(Queue_7_reset),
.io_enq_ready(Queue_7_io_enq_ready),
.io_enq_valid(Queue_7_io_enq_valid),
.io_enq_bits(Queue_7_io_enq_bits),
.io_deq_ready(Queue_7_io_deq_ready),
.io_deq_valid(Queue_7_io_deq_valid),
.io_deq_bits(Queue_7_io_deq_bits)
);
Queue_5 Queue_8 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13490.4]
.clock(Queue_8_clock),
.reset(Queue_8_reset),
.io_enq_ready(Queue_8_io_enq_ready),
.io_enq_valid(Queue_8_io_enq_valid),
.io_enq_bits(Queue_8_io_enq_bits),
.io_deq_ready(Queue_8_io_deq_ready),
.io_deq_valid(Queue_8_io_deq_valid),
.io_deq_bits(Queue_8_io_deq_bits)
);
Queue_5 Queue_9 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13494.4]
.clock(Queue_9_clock),
.reset(Queue_9_reset),
.io_enq_ready(Queue_9_io_enq_ready),
.io_enq_valid(Queue_9_io_enq_valid),
.io_enq_bits(Queue_9_io_enq_bits),
.io_deq_ready(Queue_9_io_deq_ready),
.io_deq_valid(Queue_9_io_deq_valid),
.io_deq_bits(Queue_9_io_deq_bits)
);
Queue_7 Queue_10 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13498.4]
.clock(Queue_10_clock),
.reset(Queue_10_reset),
.io_enq_ready(Queue_10_io_enq_ready),
.io_enq_valid(Queue_10_io_enq_valid),
.io_enq_bits(Queue_10_io_enq_bits),
.io_deq_ready(Queue_10_io_deq_ready),
.io_deq_valid(Queue_10_io_deq_valid),
.io_deq_bits(Queue_10_io_deq_bits)
);
Queue_7 Queue_11 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13502.4]
.clock(Queue_11_clock),
.reset(Queue_11_reset),
.io_enq_ready(Queue_11_io_enq_ready),
.io_enq_valid(Queue_11_io_enq_valid),
.io_enq_bits(Queue_11_io_enq_bits),
.io_deq_ready(Queue_11_io_deq_ready),
.io_deq_valid(Queue_11_io_deq_valid),
.io_deq_bits(Queue_11_io_deq_bits)
);
Queue_5 Queue_12 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13506.4]
.clock(Queue_12_clock),
.reset(Queue_12_reset),
.io_enq_ready(Queue_12_io_enq_ready),
.io_enq_valid(Queue_12_io_enq_valid),
.io_enq_bits(Queue_12_io_enq_bits),
.io_deq_ready(Queue_12_io_deq_ready),
.io_deq_valid(Queue_12_io_deq_valid),
.io_deq_bits(Queue_12_io_deq_bits)
);
Queue_5 Queue_13 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13510.4]
.clock(Queue_13_clock),
.reset(Queue_13_reset),
.io_enq_ready(Queue_13_io_enq_ready),
.io_enq_valid(Queue_13_io_enq_valid),
.io_enq_bits(Queue_13_io_enq_bits),
.io_deq_ready(Queue_13_io_deq_ready),
.io_deq_valid(Queue_13_io_deq_valid),
.io_deq_bits(Queue_13_io_deq_bits)
);
Queue_5 Queue_14 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13514.4]
.clock(Queue_14_clock),
.reset(Queue_14_reset),
.io_enq_ready(Queue_14_io_enq_ready),
.io_enq_valid(Queue_14_io_enq_valid),
.io_enq_bits(Queue_14_io_enq_bits),
.io_deq_ready(Queue_14_io_deq_ready),
.io_deq_valid(Queue_14_io_deq_valid),
.io_deq_bits(Queue_14_io_deq_bits)
);
Queue_5 Queue_15 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@13518.4]
.clock(Queue_15_clock),
.reset(Queue_15_reset),
.io_enq_ready(Queue_15_io_enq_ready),
.io_enq_valid(Queue_15_io_enq_valid),
.io_enq_bits(Queue_15_io_enq_bits),
.io_deq_ready(Queue_15_io_deq_ready),
.io_deq_valid(Queue_15_io_deq_valid),
.io_deq_bits(Queue_15_io_deq_bits)
);
assign _T_736_0 = Queue_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13540.4]
assign _T_736_1 = Queue_1_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13541.4]
assign _GEN_1 = 4'h1 == auto_in_ar_bits_id ? _T_736_1 : _T_736_0; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_736_2 = Queue_2_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13542.4]
assign _GEN_2 = 4'h2 == auto_in_ar_bits_id ? _T_736_2 : _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_736_3 = Queue_3_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13543.4]
assign _GEN_3 = 4'h3 == auto_in_ar_bits_id ? _T_736_3 : _GEN_2; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_736_4 = Queue_4_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13544.4]
assign _GEN_4 = 4'h4 == auto_in_ar_bits_id ? _T_736_4 : _GEN_3; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_736_5 = Queue_5_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13545.4]
assign _GEN_5 = 4'h5 == auto_in_ar_bits_id ? _T_736_5 : _GEN_4; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_736_6 = Queue_6_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13546.4]
assign _GEN_6 = 4'h6 == auto_in_ar_bits_id ? _T_736_6 : _GEN_5; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_736_7 = Queue_7_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13538.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@13547.4]
assign _GEN_7 = 4'h7 == auto_in_ar_bits_id ? _T_736_7 : _GEN_6; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_8 = 4'h8 == auto_in_ar_bits_id ? 1'h0 : _GEN_7; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_9 = 4'h9 == auto_in_ar_bits_id ? 1'h0 : _GEN_8; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_10 = 4'ha == auto_in_ar_bits_id ? 1'h0 : _GEN_9; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_11 = 4'hb == auto_in_ar_bits_id ? 1'h0 : _GEN_10; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_12 = 4'hc == auto_in_ar_bits_id ? 1'h0 : _GEN_11; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_13 = 4'hd == auto_in_ar_bits_id ? 1'h0 : _GEN_12; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_14 = 4'he == auto_in_ar_bits_id ? 1'h0 : _GEN_13; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _GEN_15 = 4'hf == auto_in_ar_bits_id ? 1'h0 : _GEN_14; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@13556.4]
assign _T_804 = auto_out_r_valid == 1'h0; // @[UserYanker.scala 54:15:freechips.rocketchip.system.LowRiscConfig.fir@13597.4]
assign _T_761_0 = Queue_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13563.4]
assign _T_761_1 = Queue_1_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13564.4]
assign _GEN_17 = 4'h1 == auto_out_r_bits_id ? _T_761_1 : _T_761_0; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_761_2 = Queue_2_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13565.4]
assign _GEN_18 = 4'h2 == auto_out_r_bits_id ? _T_761_2 : _GEN_17; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_761_3 = Queue_3_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13566.4]
assign _GEN_19 = 4'h3 == auto_out_r_bits_id ? _T_761_3 : _GEN_18; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_761_4 = Queue_4_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13567.4]
assign _GEN_20 = 4'h4 == auto_out_r_bits_id ? _T_761_4 : _GEN_19; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_761_5 = Queue_5_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13568.4]
assign _GEN_21 = 4'h5 == auto_out_r_bits_id ? _T_761_5 : _GEN_20; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_761_6 = Queue_6_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13569.4]
assign _GEN_22 = 4'h6 == auto_out_r_bits_id ? _T_761_6 : _GEN_21; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_761_7 = Queue_7_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13561.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@13570.4]
assign _GEN_23 = 4'h7 == auto_out_r_bits_id ? _T_761_7 : _GEN_22; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_24 = 4'h8 == auto_out_r_bits_id ? 1'h0 : _GEN_23; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_25 = 4'h9 == auto_out_r_bits_id ? 1'h0 : _GEN_24; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_26 = 4'ha == auto_out_r_bits_id ? 1'h0 : _GEN_25; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_27 = 4'hb == auto_out_r_bits_id ? 1'h0 : _GEN_26; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_28 = 4'hc == auto_out_r_bits_id ? 1'h0 : _GEN_27; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_29 = 4'hd == auto_out_r_bits_id ? 1'h0 : _GEN_28; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_30 = 4'he == auto_out_r_bits_id ? 1'h0 : _GEN_29; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _GEN_31 = 4'hf == auto_out_r_bits_id ? 1'h0 : _GEN_30; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_805 = _T_804 | _GEN_31; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@13598.4]
assign _T_807 = _T_805 | reset; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@13600.4]
assign _T_808 = _T_807 == 1'h0; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@13601.4]
assign _T_784_0 = Queue_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13581.4]
assign _T_784_1 = Queue_1_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13582.4]
assign _GEN_33 = 4'h1 == auto_out_r_bits_id ? _T_784_1 : _T_784_0; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_784_2 = Queue_2_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13583.4]
assign _GEN_34 = 4'h2 == auto_out_r_bits_id ? _T_784_2 : _GEN_33; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_784_3 = Queue_3_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13584.4]
assign _GEN_35 = 4'h3 == auto_out_r_bits_id ? _T_784_3 : _GEN_34; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_784_4 = Queue_4_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13585.4]
assign _GEN_36 = 4'h4 == auto_out_r_bits_id ? _T_784_4 : _GEN_35; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_784_5 = Queue_5_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13586.4]
assign _GEN_37 = 4'h5 == auto_out_r_bits_id ? _T_784_5 : _GEN_36; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_784_6 = Queue_6_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13587.4]
assign _GEN_38 = 4'h6 == auto_out_r_bits_id ? _T_784_6 : _GEN_37; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_784_7 = Queue_7_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13579.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@13588.4]
assign _GEN_39 = 4'h7 == auto_out_r_bits_id ? _T_784_7 : _GEN_38; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_40 = 4'h8 == auto_out_r_bits_id ? 9'h0 : _GEN_39; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_41 = 4'h9 == auto_out_r_bits_id ? 9'h0 : _GEN_40; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_42 = 4'ha == auto_out_r_bits_id ? 9'h0 : _GEN_41; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_43 = 4'hb == auto_out_r_bits_id ? 9'h0 : _GEN_42; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_44 = 4'hc == auto_out_r_bits_id ? 9'h0 : _GEN_43; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_45 = 4'hd == auto_out_r_bits_id ? 9'h0 : _GEN_44; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _GEN_46 = 4'he == auto_out_r_bits_id ? 9'h0 : _GEN_45; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@13607.4]
assign _T_810 = 16'h1 << auto_in_ar_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13609.4]
assign _T_812 = _T_810[0]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13611.4]
assign _T_813 = _T_810[1]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13612.4]
assign _T_814 = _T_810[2]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13613.4]
assign _T_815 = _T_810[3]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13614.4]
assign _T_816 = _T_810[4]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13615.4]
assign _T_817 = _T_810[5]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13616.4]
assign _T_818 = _T_810[6]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13617.4]
assign _T_819 = _T_810[7]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@13618.4]
assign _T_829 = 16'h1 << auto_out_r_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13628.4]
assign _T_831 = _T_829[0]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13630.4]
assign _T_832 = _T_829[1]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13631.4]
assign _T_833 = _T_829[2]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13632.4]
assign _T_834 = _T_829[3]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13633.4]
assign _T_835 = _T_829[4]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13634.4]
assign _T_836 = _T_829[5]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13635.4]
assign _T_837 = _T_829[6]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13636.4]
assign _T_838 = _T_829[7]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@13637.4]
assign _T_847 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala 61:37:freechips.rocketchip.system.LowRiscConfig.fir@13646.4]
assign _T_848 = _T_847 & _T_831; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13647.4]
assign _T_850 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala 62:37:freechips.rocketchip.system.LowRiscConfig.fir@13650.4]
assign _T_853 = _T_847 & _T_832; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13655.4]
assign _T_858 = _T_847 & _T_833; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13663.4]
assign _T_863 = _T_847 & _T_834; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13671.4]
assign _T_868 = _T_847 & _T_835; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13679.4]
assign _T_873 = _T_847 & _T_836; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13687.4]
assign _T_878 = _T_847 & _T_837; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13695.4]
assign _T_883 = _T_847 & _T_838; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@13703.4]
assign _T_930_0 = Queue_8_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13776.4]
assign _T_930_1 = Queue_9_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13777.4]
assign _GEN_49 = 4'h1 == auto_in_aw_bits_id ? _T_930_1 : _T_930_0; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_930_2 = Queue_10_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13778.4]
assign _GEN_50 = 4'h2 == auto_in_aw_bits_id ? _T_930_2 : _GEN_49; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_930_3 = Queue_11_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13779.4]
assign _GEN_51 = 4'h3 == auto_in_aw_bits_id ? _T_930_3 : _GEN_50; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_930_4 = Queue_12_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13780.4]
assign _GEN_52 = 4'h4 == auto_in_aw_bits_id ? _T_930_4 : _GEN_51; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_930_5 = Queue_13_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13781.4]
assign _GEN_53 = 4'h5 == auto_in_aw_bits_id ? _T_930_5 : _GEN_52; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_930_6 = Queue_14_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13782.4]
assign _GEN_54 = 4'h6 == auto_in_aw_bits_id ? _T_930_6 : _GEN_53; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_930_7 = Queue_15_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13774.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@13783.4]
assign _GEN_55 = 4'h7 == auto_in_aw_bits_id ? _T_930_7 : _GEN_54; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_56 = 4'h8 == auto_in_aw_bits_id ? 1'h0 : _GEN_55; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_57 = 4'h9 == auto_in_aw_bits_id ? 1'h0 : _GEN_56; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_58 = 4'ha == auto_in_aw_bits_id ? 1'h0 : _GEN_57; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_59 = 4'hb == auto_in_aw_bits_id ? 1'h0 : _GEN_58; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_60 = 4'hc == auto_in_aw_bits_id ? 1'h0 : _GEN_59; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_61 = 4'hd == auto_in_aw_bits_id ? 1'h0 : _GEN_60; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_62 = 4'he == auto_in_aw_bits_id ? 1'h0 : _GEN_61; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _GEN_63 = 4'hf == auto_in_aw_bits_id ? 1'h0 : _GEN_62; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@13792.4]
assign _T_998 = auto_out_b_valid == 1'h0; // @[UserYanker.scala 75:15:freechips.rocketchip.system.LowRiscConfig.fir@13833.4]
assign _T_955_0 = Queue_8_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13799.4]
assign _T_955_1 = Queue_9_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13800.4]
assign _GEN_65 = 4'h1 == auto_out_b_bits_id ? _T_955_1 : _T_955_0; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_955_2 = Queue_10_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13801.4]
assign _GEN_66 = 4'h2 == auto_out_b_bits_id ? _T_955_2 : _GEN_65; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_955_3 = Queue_11_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13802.4]
assign _GEN_67 = 4'h3 == auto_out_b_bits_id ? _T_955_3 : _GEN_66; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_955_4 = Queue_12_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13803.4]
assign _GEN_68 = 4'h4 == auto_out_b_bits_id ? _T_955_4 : _GEN_67; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_955_5 = Queue_13_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13804.4]
assign _GEN_69 = 4'h5 == auto_out_b_bits_id ? _T_955_5 : _GEN_68; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_955_6 = Queue_14_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13805.4]
assign _GEN_70 = 4'h6 == auto_out_b_bits_id ? _T_955_6 : _GEN_69; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_955_7 = Queue_15_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13797.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@13806.4]
assign _GEN_71 = 4'h7 == auto_out_b_bits_id ? _T_955_7 : _GEN_70; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_72 = 4'h8 == auto_out_b_bits_id ? 1'h0 : _GEN_71; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_73 = 4'h9 == auto_out_b_bits_id ? 1'h0 : _GEN_72; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_74 = 4'ha == auto_out_b_bits_id ? 1'h0 : _GEN_73; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_75 = 4'hb == auto_out_b_bits_id ? 1'h0 : _GEN_74; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_76 = 4'hc == auto_out_b_bits_id ? 1'h0 : _GEN_75; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_77 = 4'hd == auto_out_b_bits_id ? 1'h0 : _GEN_76; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_78 = 4'he == auto_out_b_bits_id ? 1'h0 : _GEN_77; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _GEN_79 = 4'hf == auto_out_b_bits_id ? 1'h0 : _GEN_78; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_999 = _T_998 | _GEN_79; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@13834.4]
assign _T_1001 = _T_999 | reset; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@13836.4]
assign _T_1002 = _T_1001 == 1'h0; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@13837.4]
assign _T_978_0 = Queue_8_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13817.4]
assign _T_978_1 = Queue_9_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13818.4]
assign _GEN_81 = 4'h1 == auto_out_b_bits_id ? _T_978_1 : _T_978_0; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_978_2 = Queue_10_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13819.4]
assign _GEN_82 = 4'h2 == auto_out_b_bits_id ? _T_978_2 : _GEN_81; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_978_3 = Queue_11_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13820.4]
assign _GEN_83 = 4'h3 == auto_out_b_bits_id ? _T_978_3 : _GEN_82; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_978_4 = Queue_12_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13821.4]
assign _GEN_84 = 4'h4 == auto_out_b_bits_id ? _T_978_4 : _GEN_83; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_978_5 = Queue_13_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13822.4]
assign _GEN_85 = 4'h5 == auto_out_b_bits_id ? _T_978_5 : _GEN_84; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_978_6 = Queue_14_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13823.4]
assign _GEN_86 = 4'h6 == auto_out_b_bits_id ? _T_978_6 : _GEN_85; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_978_7 = Queue_15_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13815.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@13824.4]
assign _GEN_87 = 4'h7 == auto_out_b_bits_id ? _T_978_7 : _GEN_86; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_88 = 4'h8 == auto_out_b_bits_id ? 9'h0 : _GEN_87; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_89 = 4'h9 == auto_out_b_bits_id ? 9'h0 : _GEN_88; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_90 = 4'ha == auto_out_b_bits_id ? 9'h0 : _GEN_89; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_91 = 4'hb == auto_out_b_bits_id ? 9'h0 : _GEN_90; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_92 = 4'hc == auto_out_b_bits_id ? 9'h0 : _GEN_91; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_93 = 4'hd == auto_out_b_bits_id ? 9'h0 : _GEN_92; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _GEN_94 = 4'he == auto_out_b_bits_id ? 9'h0 : _GEN_93; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@13843.4]
assign _T_1004 = 16'h1 << auto_in_aw_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13845.4]
assign _T_1006 = _T_1004[0]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13847.4]
assign _T_1007 = _T_1004[1]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13848.4]
assign _T_1008 = _T_1004[2]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13849.4]
assign _T_1009 = _T_1004[3]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13850.4]
assign _T_1010 = _T_1004[4]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13851.4]
assign _T_1011 = _T_1004[5]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13852.4]
assign _T_1012 = _T_1004[6]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13853.4]
assign _T_1013 = _T_1004[7]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@13854.4]
assign _T_1023 = 16'h1 << auto_out_b_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@13864.4]
assign _T_1025 = _T_1023[0]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13866.4]
assign _T_1026 = _T_1023[1]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13867.4]
assign _T_1027 = _T_1023[2]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13868.4]
assign _T_1028 = _T_1023[3]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13869.4]
assign _T_1029 = _T_1023[4]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13870.4]
assign _T_1030 = _T_1023[5]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13871.4]
assign _T_1031 = _T_1023[6]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13872.4]
assign _T_1032 = _T_1023[7]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@13873.4]
assign _T_1041 = auto_out_b_valid & auto_in_b_ready; // @[UserYanker.scala 82:37:freechips.rocketchip.system.LowRiscConfig.fir@13882.4]
assign _T_1043 = auto_in_aw_valid & auto_out_aw_ready; // @[UserYanker.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@13885.4]
assign auto_in_aw_ready = auto_out_aw_ready & _GEN_63; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_b_bits_user = 4'hf == auto_out_b_bits_id ? 9'h0 : _GEN_94; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_ar_ready = auto_out_ar_ready & _GEN_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_r_bits_user = 4'hf == auto_out_r_bits_id ? 9'h0 : _GEN_46; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@13441.4]
assign auto_out_aw_valid = auto_in_aw_valid & _GEN_63; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_valid = auto_in_ar_valid & _GEN_15; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@13440.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13444.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13445.4]
assign Queue_io_enq_valid = _T_850 & _T_812; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13652.4]
assign Queue_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13653.4]
assign Queue_io_deq_ready = _T_848 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13649.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13448.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13449.4]
assign Queue_1_io_enq_valid = _T_850 & _T_813; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13660.4]
assign Queue_1_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13661.4]
assign Queue_1_io_deq_ready = _T_853 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13657.4]
assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13452.4]
assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13453.4]
assign Queue_2_io_enq_valid = _T_850 & _T_814; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13668.4]
assign Queue_2_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13669.4]
assign Queue_2_io_deq_ready = _T_858 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13665.4]
assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13456.4]
assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13457.4]
assign Queue_3_io_enq_valid = _T_850 & _T_815; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13676.4]
assign Queue_3_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13677.4]
assign Queue_3_io_deq_ready = _T_863 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13673.4]
assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13460.4]
assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13461.4]
assign Queue_4_io_enq_valid = _T_850 & _T_816; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13684.4]
assign Queue_4_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13685.4]
assign Queue_4_io_deq_ready = _T_868 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13681.4]
assign Queue_5_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13464.4]
assign Queue_5_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13465.4]
assign Queue_5_io_enq_valid = _T_850 & _T_817; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13692.4]
assign Queue_5_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13693.4]
assign Queue_5_io_deq_ready = _T_873 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13689.4]
assign Queue_6_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13468.4]
assign Queue_6_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13469.4]
assign Queue_6_io_enq_valid = _T_850 & _T_818; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13700.4]
assign Queue_6_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13701.4]
assign Queue_6_io_deq_ready = _T_878 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13697.4]
assign Queue_7_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13472.4]
assign Queue_7_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13473.4]
assign Queue_7_io_enq_valid = _T_850 & _T_819; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@13708.4]
assign Queue_7_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@13709.4]
assign Queue_7_io_deq_ready = _T_883 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@13705.4]
assign Queue_8_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13492.4]
assign Queue_8_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13493.4]
assign Queue_8_io_enq_valid = _T_1043 & _T_1006; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13887.4]
assign Queue_8_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13888.4]
assign Queue_8_io_deq_ready = _T_1041 & _T_1025; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13884.4]
assign Queue_9_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13496.4]
assign Queue_9_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13497.4]
assign Queue_9_io_enq_valid = _T_1043 & _T_1007; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13894.4]
assign Queue_9_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13895.4]
assign Queue_9_io_deq_ready = _T_1041 & _T_1026; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13891.4]
assign Queue_10_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13500.4]
assign Queue_10_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13501.4]
assign Queue_10_io_enq_valid = _T_1043 & _T_1008; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13901.4]
assign Queue_10_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13902.4]
assign Queue_10_io_deq_ready = _T_1041 & _T_1027; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13898.4]
assign Queue_11_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13504.4]
assign Queue_11_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13505.4]
assign Queue_11_io_enq_valid = _T_1043 & _T_1009; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13908.4]
assign Queue_11_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13909.4]
assign Queue_11_io_deq_ready = _T_1041 & _T_1028; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13905.4]
assign Queue_12_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13508.4]
assign Queue_12_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13509.4]
assign Queue_12_io_enq_valid = _T_1043 & _T_1010; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13915.4]
assign Queue_12_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13916.4]
assign Queue_12_io_deq_ready = _T_1041 & _T_1029; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13912.4]
assign Queue_13_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13512.4]
assign Queue_13_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13513.4]
assign Queue_13_io_enq_valid = _T_1043 & _T_1011; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13922.4]
assign Queue_13_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13923.4]
assign Queue_13_io_deq_ready = _T_1041 & _T_1030; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13919.4]
assign Queue_14_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13516.4]
assign Queue_14_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13517.4]
assign Queue_14_io_enq_valid = _T_1043 & _T_1012; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13929.4]
assign Queue_14_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13930.4]
assign Queue_14_io_deq_ready = _T_1041 & _T_1031; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13926.4]
assign Queue_15_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13520.4]
assign Queue_15_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@13521.4]
assign Queue_15_io_enq_valid = _T_1043 & _T_1013; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@13936.4]
assign Queue_15_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@13937.4]
assign Queue_15_io_deq_ready = _T_1041 & _T_1032; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@13933.4]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_808) begin
$fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:54 assert (!out.r.valid || r_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@13603.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_808) begin
$fatal; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@13604.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1002) begin
$fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:75 assert (!out.b.valid || b_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@13839.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1002) begin
$fatal; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@13840.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_21( // @[:freechips.rocketchip.system.LowRiscConfig.fir@13996.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13997.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13998.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input [3:0] io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input [8:0] io_enq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input io_enq_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
output [3:0] io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
output [8:0] io_deq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
output io_deq_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@13999.4]
);
reg [3:0] _T_35_id [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [31:0] _RAND_0;
wire [3:0] _T_35_id__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_id__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [3:0] _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_id__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_id__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_id__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [63:0] _T_35_data [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [63:0] _RAND_1;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [1:0] _T_35_resp [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [31:0] _RAND_2;
wire [1:0] _T_35_resp__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_resp__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [1:0] _T_35_resp__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_resp__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_resp__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_resp__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [8:0] _T_35_user [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [31:0] _RAND_3;
wire [8:0] _T_35_user__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_user__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [8:0] _T_35_user__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_user__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_user__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_user__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg _T_35_last [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [31:0] _RAND_4;
wire _T_35_last__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_last__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_last__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire [2:0] _T_35_last__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_last__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
wire _T_35_last__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
reg [2:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@14005.4]
reg [31:0] _RAND_5;
reg [2:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@14006.4]
reg [31:0] _RAND_6;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@14007.4]
reg [31:0] _RAND_7;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@14008.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@14009.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@14010.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@14011.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14012.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14016.4]
wire [2:0] _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@14025.6]
wire [2:0] _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@14031.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@14034.4]
assign _T_35_id__T_58_addr = value_1;
assign _T_35_id__T_58_data = _T_35_id[_T_35_id__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
assign _T_35_id__T_50_data = io_enq_bits_id;
assign _T_35_id__T_50_addr = value;
assign _T_35_id__T_50_mask = 1'h1;
assign _T_35_id__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_resp__T_58_addr = value_1;
assign _T_35_resp__T_58_data = _T_35_resp[_T_35_resp__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
assign _T_35_resp__T_50_data = io_enq_bits_resp;
assign _T_35_resp__T_50_addr = value;
assign _T_35_resp__T_50_mask = 1'h1;
assign _T_35_resp__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_user__T_58_addr = value_1;
assign _T_35_user__T_58_data = _T_35_user[_T_35_user__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
assign _T_35_user__T_50_data = io_enq_bits_user;
assign _T_35_user__T_50_addr = value;
assign _T_35_user__T_50_mask = 1'h1;
assign _T_35_user__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_last__T_58_addr = value_1;
assign _T_35_last__T_58_data = _T_35_last[_T_35_last__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
assign _T_35_last__T_50_data = io_enq_bits_last;
assign _T_35_last__T_50_addr = value;
assign _T_35_last__T_50_mask = 1'h1;
assign _T_35_last__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@14008.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@14009.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@14010.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@14011.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14012.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14016.4]
assign _T_52 = value + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@14025.6]
assign _T_54 = value_1 + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@14031.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@14034.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@14041.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@14039.4]
assign io_deq_bits_id = _T_35_id__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@14043.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@14043.4]
assign io_deq_bits_resp = _T_35_resp__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@14043.4]
assign io_deq_bits_user = _T_35_user__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@14043.4]
assign io_deq_bits_last = _T_35_last__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@14043.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35_data[initvar] = _RAND_1[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35_resp[initvar] = _RAND_2[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35_user[initvar] = _RAND_3[8:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35_last[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
value = _RAND_5[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
value_1 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_39 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_50_en & _T_35_id__T_50_mask) begin
_T_35_id[_T_35_id__T_50_addr] <= _T_35_id__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
end
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
end
if(_T_35_resp__T_50_en & _T_35_resp__T_50_mask) begin
_T_35_resp[_T_35_resp__T_50_addr] <= _T_35_resp__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
end
if(_T_35_user__T_50_en & _T_35_user__T_50_mask) begin
_T_35_user[_T_35_user__T_50_addr] <= _T_35_user__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
end
if(_T_35_last__T_50_en & _T_35_last__T_50_mask) begin
_T_35_last[_T_35_last__T_50_addr] <= _T_35_last__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@14004.4]
end
if (reset) begin
value <= 3'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 3'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module AXI4Deinterleaver( // @[:freechips.rocketchip.system.LowRiscConfig.fir@14436.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14437.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14438.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [8:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [8:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [8:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [8:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [8:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [8:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output [8:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input [8:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@14439.4]
);
wire Queue_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [3:0] Queue_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [63:0] Queue_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [1:0] Queue_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [8:0] Queue_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [3:0] Queue_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [63:0] Queue_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [1:0] Queue_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire [8:0] Queue_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
wire Queue_1_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [3:0] Queue_1_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [63:0] Queue_1_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [1:0] Queue_1_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [8:0] Queue_1_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [3:0] Queue_1_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [63:0] Queue_1_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [1:0] Queue_1_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire [8:0] Queue_1_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_1_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
wire Queue_2_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [3:0] Queue_2_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [63:0] Queue_2_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [1:0] Queue_2_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [8:0] Queue_2_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [3:0] Queue_2_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [63:0] Queue_2_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [1:0] Queue_2_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire [8:0] Queue_2_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_2_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
wire Queue_3_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [3:0] Queue_3_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [63:0] Queue_3_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [1:0] Queue_3_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [8:0] Queue_3_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [3:0] Queue_3_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [63:0] Queue_3_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [1:0] Queue_3_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire [8:0] Queue_3_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_3_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
wire Queue_4_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [3:0] Queue_4_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [63:0] Queue_4_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [1:0] Queue_4_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [8:0] Queue_4_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [3:0] Queue_4_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [63:0] Queue_4_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [1:0] Queue_4_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire [8:0] Queue_4_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_4_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
wire Queue_5_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [3:0] Queue_5_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [63:0] Queue_5_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [1:0] Queue_5_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [8:0] Queue_5_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [3:0] Queue_5_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [63:0] Queue_5_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [1:0] Queue_5_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire [8:0] Queue_5_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_5_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
wire Queue_6_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [3:0] Queue_6_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [63:0] Queue_6_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [1:0] Queue_6_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [8:0] Queue_6_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [3:0] Queue_6_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [63:0] Queue_6_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [1:0] Queue_6_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire [8:0] Queue_6_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_6_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
wire Queue_7_clock; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_reset; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_io_enq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_io_enq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [3:0] Queue_7_io_enq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [63:0] Queue_7_io_enq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [1:0] Queue_7_io_enq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [8:0] Queue_7_io_enq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_io_enq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_io_deq_ready; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_io_deq_valid; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [3:0] Queue_7_io_deq_bits_id; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [63:0] Queue_7_io_deq_bits_data; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [1:0] Queue_7_io_deq_bits_resp; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire [8:0] Queue_7_io_deq_bits_user; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
wire Queue_7_io_deq_bits_last; // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
reg _T_478; // @[Deinterleaver.scala 50:29:freechips.rocketchip.system.LowRiscConfig.fir@14502.4]
reg [31:0] _RAND_0;
reg [3:0] _T_480; // @[Deinterleaver.scala 51:25:freechips.rocketchip.system.LowRiscConfig.fir@14503.4]
reg [31:0] _RAND_1;
wire [15:0] _T_482; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@14505.4]
wire [15:0] _T_485; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@14508.4]
reg [3:0] _T_488; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14510.4]
reg [31:0] _RAND_2;
wire _T_490; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14513.4]
wire _T_850_7; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14976.4]
wire _T_850_6; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14975.4]
wire _T_850_5; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14974.4]
wire _T_850_4; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14973.4]
wire _T_850_3; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14972.4]
wire _T_850_2; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14971.4]
wire _T_850_1; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14970.4]
wire _T_850_0; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14969.4]
wire _GEN_83; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_84; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_85; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_86; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_87; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_88; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_89; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_90; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_91; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_92; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_93; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_94; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_95; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_96; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _GEN_97; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
wire _T_491; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14514.4]
wire _T_492; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14515.4]
wire _T_493; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14516.4]
wire _T_494; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14517.4]
wire _T_495; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14518.4]
wire _T_496; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14519.4]
wire _T_779_7_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
wire _T_779_6_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
wire _T_779_5_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
wire _T_779_4_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
wire _T_779_3_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
wire _T_779_2_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
wire _T_779_1_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
wire _T_779_0_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
wire _GEN_11; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_16; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_21; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_26; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_31; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_36; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_41; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_46; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_51; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_56; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_61; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_66; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_71; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_76; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _GEN_81; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire _T_497; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14520.4]
wire [3:0] _GEN_98; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14521.4]
wire [3:0] _T_499; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14522.4]
wire [3:0] _GEN_99; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14523.4]
wire [4:0] _T_500; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14523.4]
wire [4:0] _T_501; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14524.4]
wire [3:0] _T_502; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14525.4]
wire _T_503; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14528.4]
wire _T_504; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14529.4]
wire _T_505; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14530.4]
wire _T_507; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14532.4]
wire _T_508; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14533.4]
wire _T_509; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14538.4]
wire _T_510; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14539.4]
wire _T_511; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14540.4]
wire _T_513; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14542.4]
wire _T_514; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14543.4]
wire _T_515; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14548.4]
reg [3:0] _T_517; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14549.4]
reg [31:0] _RAND_3;
wire _T_519; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14552.4]
wire _T_521; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14554.4]
wire _T_522; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14555.4]
wire _T_523; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14556.4]
wire _T_525; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14558.4]
wire _T_526; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14559.4]
wire [3:0] _GEN_100; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14560.4]
wire [3:0] _T_528; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14561.4]
wire [3:0] _GEN_101; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14562.4]
wire [4:0] _T_529; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14562.4]
wire [4:0] _T_530; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14563.4]
wire [3:0] _T_531; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14564.4]
wire _T_532; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14567.4]
wire _T_533; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14568.4]
wire _T_534; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14569.4]
wire _T_536; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14571.4]
wire _T_537; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14572.4]
wire _T_538; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14577.4]
wire _T_539; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14578.4]
wire _T_540; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14579.4]
wire _T_542; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14581.4]
wire _T_543; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14582.4]
wire _T_544; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14587.4]
reg [3:0] _T_546; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14588.4]
reg [31:0] _RAND_4;
wire _T_548; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14591.4]
wire _T_550; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14593.4]
wire _T_551; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14594.4]
wire _T_552; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14595.4]
wire _T_554; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14597.4]
wire _T_555; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14598.4]
wire [3:0] _GEN_102; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14599.4]
wire [3:0] _T_557; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14600.4]
wire [3:0] _GEN_103; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14601.4]
wire [4:0] _T_558; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14601.4]
wire [4:0] _T_559; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14602.4]
wire [3:0] _T_560; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14603.4]
wire _T_561; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14606.4]
wire _T_562; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14607.4]
wire _T_563; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14608.4]
wire _T_565; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14610.4]
wire _T_566; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14611.4]
wire _T_567; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14616.4]
wire _T_568; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14617.4]
wire _T_569; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14618.4]
wire _T_571; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14620.4]
wire _T_572; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14621.4]
wire _T_573; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14626.4]
reg [3:0] _T_575; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14627.4]
reg [31:0] _RAND_5;
wire _T_577; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14630.4]
wire _T_579; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14632.4]
wire _T_580; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14633.4]
wire _T_581; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14634.4]
wire _T_583; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14636.4]
wire _T_584; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14637.4]
wire [3:0] _GEN_104; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14638.4]
wire [3:0] _T_586; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14639.4]
wire [3:0] _GEN_105; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14640.4]
wire [4:0] _T_587; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14640.4]
wire [4:0] _T_588; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14641.4]
wire [3:0] _T_589; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14642.4]
wire _T_590; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14645.4]
wire _T_591; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14646.4]
wire _T_592; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14647.4]
wire _T_594; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14649.4]
wire _T_595; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14650.4]
wire _T_596; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14655.4]
wire _T_597; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14656.4]
wire _T_598; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14657.4]
wire _T_600; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14659.4]
wire _T_601; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14660.4]
wire _T_602; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14665.4]
reg [3:0] _T_604; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14666.4]
reg [31:0] _RAND_6;
wire _T_606; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14669.4]
wire _T_608; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14671.4]
wire _T_609; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14672.4]
wire _T_610; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14673.4]
wire _T_612; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14675.4]
wire _T_613; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14676.4]
wire [3:0] _GEN_106; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14677.4]
wire [3:0] _T_615; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14678.4]
wire [3:0] _GEN_107; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14679.4]
wire [4:0] _T_616; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14679.4]
wire [4:0] _T_617; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14680.4]
wire [3:0] _T_618; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14681.4]
wire _T_619; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14684.4]
wire _T_620; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14685.4]
wire _T_621; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14686.4]
wire _T_623; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14688.4]
wire _T_624; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14689.4]
wire _T_625; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14694.4]
wire _T_626; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14695.4]
wire _T_627; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14696.4]
wire _T_629; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14698.4]
wire _T_630; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14699.4]
wire _T_631; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14704.4]
reg [3:0] _T_633; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14705.4]
reg [31:0] _RAND_7;
wire _T_635; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14708.4]
wire _T_637; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14710.4]
wire _T_638; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14711.4]
wire _T_639; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14712.4]
wire _T_641; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14714.4]
wire _T_642; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14715.4]
wire [3:0] _GEN_108; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14716.4]
wire [3:0] _T_644; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14717.4]
wire [3:0] _GEN_109; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14718.4]
wire [4:0] _T_645; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14718.4]
wire [4:0] _T_646; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14719.4]
wire [3:0] _T_647; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14720.4]
wire _T_648; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14723.4]
wire _T_649; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14724.4]
wire _T_650; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14725.4]
wire _T_652; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14727.4]
wire _T_653; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14728.4]
wire _T_654; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14733.4]
wire _T_655; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14734.4]
wire _T_656; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14735.4]
wire _T_658; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14737.4]
wire _T_659; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14738.4]
wire _T_660; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14743.4]
reg [3:0] _T_662; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14744.4]
reg [31:0] _RAND_8;
wire _T_664; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14747.4]
wire _T_666; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14749.4]
wire _T_667; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14750.4]
wire _T_668; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14751.4]
wire _T_670; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14753.4]
wire _T_671; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14754.4]
wire [3:0] _GEN_110; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14755.4]
wire [3:0] _T_673; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14756.4]
wire [3:0] _GEN_111; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14757.4]
wire [4:0] _T_674; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14757.4]
wire [4:0] _T_675; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14758.4]
wire [3:0] _T_676; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14759.4]
wire _T_677; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14762.4]
wire _T_678; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14763.4]
wire _T_679; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14764.4]
wire _T_681; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14766.4]
wire _T_682; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14767.4]
wire _T_683; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14772.4]
wire _T_684; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14773.4]
wire _T_685; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14774.4]
wire _T_687; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14776.4]
wire _T_688; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14777.4]
wire _T_689; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14782.4]
reg [3:0] _T_691; // @[Deinterleaver.scala 62:32:freechips.rocketchip.system.LowRiscConfig.fir@14783.4]
reg [31:0] _RAND_9;
wire _T_693; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14786.4]
wire _T_695; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14788.4]
wire _T_696; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14789.4]
wire _T_697; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14790.4]
wire _T_699; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14792.4]
wire _T_700; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14793.4]
wire [3:0] _GEN_112; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14794.4]
wire [3:0] _T_702; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14795.4]
wire [3:0] _GEN_113; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14796.4]
wire [4:0] _T_703; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14796.4]
wire [4:0] _T_704; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14797.4]
wire [3:0] _T_705; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14798.4]
wire _T_706; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14801.4]
wire _T_707; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14802.4]
wire _T_708; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14803.4]
wire _T_710; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14805.4]
wire _T_711; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14806.4]
wire _T_712; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14811.4]
wire _T_713; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14812.4]
wire _T_714; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14813.4]
wire _T_716; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14815.4]
wire _T_717; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14816.4]
wire _T_718; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14821.4]
wire [15:0] _T_733; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@14836.4]
wire [16:0] _GEN_114; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14837.4]
wire [16:0] _T_734; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14837.4]
wire [15:0] _T_735; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14838.4]
wire [15:0] _T_736; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14839.4]
wire [17:0] _GEN_115; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14840.4]
wire [17:0] _T_737; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14840.4]
wire [15:0] _T_738; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14841.4]
wire [15:0] _T_739; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14842.4]
wire [19:0] _GEN_116; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14843.4]
wire [19:0] _T_740; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14843.4]
wire [15:0] _T_741; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14844.4]
wire [15:0] _T_742; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14845.4]
wire [23:0] _GEN_117; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14846.4]
wire [23:0] _T_743; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14846.4]
wire [15:0] _T_744; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14847.4]
wire [15:0] _T_745; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14848.4]
wire [16:0] _GEN_118; // @[Deinterleaver.scala 76:51:freechips.rocketchip.system.LowRiscConfig.fir@14850.4]
wire [16:0] _T_747; // @[Deinterleaver.scala 76:51:freechips.rocketchip.system.LowRiscConfig.fir@14850.4]
wire [16:0] _T_748; // @[Deinterleaver.scala 76:33:freechips.rocketchip.system.LowRiscConfig.fir@14851.4]
wire [16:0] _T_749; // @[Deinterleaver.scala 76:31:freechips.rocketchip.system.LowRiscConfig.fir@14852.4]
wire _T_750; // @[Deinterleaver.scala 77:15:freechips.rocketchip.system.LowRiscConfig.fir@14853.4]
wire _T_752; // @[Deinterleaver.scala 77:39:freechips.rocketchip.system.LowRiscConfig.fir@14855.4]
wire _T_753; // @[Deinterleaver.scala 77:23:freechips.rocketchip.system.LowRiscConfig.fir@14856.4]
wire _T_754; // @[Deinterleaver.scala 78:29:freechips.rocketchip.system.LowRiscConfig.fir@14858.6]
wire _T_755; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14860.6]
wire [15:0] _T_756; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14861.6]
wire [15:0] _GEN_120; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14863.6]
wire [15:0] _T_758; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14863.6]
wire [7:0] _T_759; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14864.6]
wire [7:0] _T_760; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14865.6]
wire _T_761; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@14866.6]
wire [7:0] _T_762; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14867.6]
wire [3:0] _T_763; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14868.6]
wire [3:0] _T_764; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14869.6]
wire _T_765; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@14870.6]
wire [3:0] _T_766; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14871.6]
wire [1:0] _T_767; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14872.6]
wire [1:0] _T_768; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14873.6]
wire _T_769; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@14874.6]
wire [1:0] _T_770; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14875.6]
wire _T_771; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@14876.6]
wire [4:0] _T_775; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@14880.6]
wire [4:0] _GEN_1; // @[Deinterleaver.scala 77:59:freechips.rocketchip.system.LowRiscConfig.fir@14857.4]
wire [3:0] _T_779_0_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
wire [63:0] _T_779_0_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
wire [1:0] _T_779_0_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
wire [8:0] _T_779_0_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
wire [3:0] _T_779_1_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
wire [3:0] _GEN_7; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_1_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
wire [63:0] _GEN_8; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_1_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
wire [1:0] _GEN_9; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_1_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
wire [8:0] _GEN_10; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _T_779_2_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
wire [3:0] _GEN_12; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_2_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
wire [63:0] _GEN_13; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_2_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
wire [1:0] _GEN_14; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_2_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
wire [8:0] _GEN_15; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _T_779_3_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
wire [3:0] _GEN_17; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_3_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
wire [63:0] _GEN_18; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_3_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
wire [1:0] _GEN_19; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_3_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
wire [8:0] _GEN_20; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _T_779_4_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
wire [3:0] _GEN_22; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_4_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
wire [63:0] _GEN_23; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_4_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
wire [1:0] _GEN_24; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_4_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
wire [8:0] _GEN_25; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _T_779_5_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
wire [3:0] _GEN_27; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_5_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
wire [63:0] _GEN_28; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_5_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
wire [1:0] _GEN_29; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_5_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
wire [8:0] _GEN_30; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _T_779_6_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
wire [3:0] _GEN_32; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_6_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
wire [63:0] _GEN_33; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_6_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
wire [1:0] _GEN_34; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_6_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
wire [8:0] _GEN_35; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _T_779_7_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
wire [3:0] _GEN_37; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _T_779_7_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
wire [63:0] _GEN_38; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _T_779_7_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
wire [1:0] _GEN_39; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _T_779_7_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
wire [8:0] _GEN_40; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_42; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_43; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_44; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_45; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_47; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_48; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_49; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_50; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_52; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_53; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_54; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_55; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_57; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_58; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_59; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_60; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_62; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_63; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_64; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_65; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_67; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_68; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_69; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_70; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [3:0] _GEN_72; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [63:0] _GEN_73; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [1:0] _GEN_74; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
wire [8:0] _GEN_75; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
Queue_21 Queue ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14454.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_id(Queue_io_enq_bits_id),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_resp(Queue_io_enq_bits_resp),
.io_enq_bits_user(Queue_io_enq_bits_user),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_id(Queue_io_deq_bits_id),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_resp(Queue_io_deq_bits_resp),
.io_deq_bits_user(Queue_io_deq_bits_user),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
Queue_21 Queue_1 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14458.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_id(Queue_1_io_enq_bits_id),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_resp(Queue_1_io_enq_bits_resp),
.io_enq_bits_user(Queue_1_io_enq_bits_user),
.io_enq_bits_last(Queue_1_io_enq_bits_last),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_id(Queue_1_io_deq_bits_id),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_resp(Queue_1_io_deq_bits_resp),
.io_deq_bits_user(Queue_1_io_deq_bits_user),
.io_deq_bits_last(Queue_1_io_deq_bits_last)
);
Queue_21 Queue_2 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14462.4]
.clock(Queue_2_clock),
.reset(Queue_2_reset),
.io_enq_ready(Queue_2_io_enq_ready),
.io_enq_valid(Queue_2_io_enq_valid),
.io_enq_bits_id(Queue_2_io_enq_bits_id),
.io_enq_bits_data(Queue_2_io_enq_bits_data),
.io_enq_bits_resp(Queue_2_io_enq_bits_resp),
.io_enq_bits_user(Queue_2_io_enq_bits_user),
.io_enq_bits_last(Queue_2_io_enq_bits_last),
.io_deq_ready(Queue_2_io_deq_ready),
.io_deq_valid(Queue_2_io_deq_valid),
.io_deq_bits_id(Queue_2_io_deq_bits_id),
.io_deq_bits_data(Queue_2_io_deq_bits_data),
.io_deq_bits_resp(Queue_2_io_deq_bits_resp),
.io_deq_bits_user(Queue_2_io_deq_bits_user),
.io_deq_bits_last(Queue_2_io_deq_bits_last)
);
Queue_21 Queue_3 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14466.4]
.clock(Queue_3_clock),
.reset(Queue_3_reset),
.io_enq_ready(Queue_3_io_enq_ready),
.io_enq_valid(Queue_3_io_enq_valid),
.io_enq_bits_id(Queue_3_io_enq_bits_id),
.io_enq_bits_data(Queue_3_io_enq_bits_data),
.io_enq_bits_resp(Queue_3_io_enq_bits_resp),
.io_enq_bits_user(Queue_3_io_enq_bits_user),
.io_enq_bits_last(Queue_3_io_enq_bits_last),
.io_deq_ready(Queue_3_io_deq_ready),
.io_deq_valid(Queue_3_io_deq_valid),
.io_deq_bits_id(Queue_3_io_deq_bits_id),
.io_deq_bits_data(Queue_3_io_deq_bits_data),
.io_deq_bits_resp(Queue_3_io_deq_bits_resp),
.io_deq_bits_user(Queue_3_io_deq_bits_user),
.io_deq_bits_last(Queue_3_io_deq_bits_last)
);
Queue_21 Queue_4 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14470.4]
.clock(Queue_4_clock),
.reset(Queue_4_reset),
.io_enq_ready(Queue_4_io_enq_ready),
.io_enq_valid(Queue_4_io_enq_valid),
.io_enq_bits_id(Queue_4_io_enq_bits_id),
.io_enq_bits_data(Queue_4_io_enq_bits_data),
.io_enq_bits_resp(Queue_4_io_enq_bits_resp),
.io_enq_bits_user(Queue_4_io_enq_bits_user),
.io_enq_bits_last(Queue_4_io_enq_bits_last),
.io_deq_ready(Queue_4_io_deq_ready),
.io_deq_valid(Queue_4_io_deq_valid),
.io_deq_bits_id(Queue_4_io_deq_bits_id),
.io_deq_bits_data(Queue_4_io_deq_bits_data),
.io_deq_bits_resp(Queue_4_io_deq_bits_resp),
.io_deq_bits_user(Queue_4_io_deq_bits_user),
.io_deq_bits_last(Queue_4_io_deq_bits_last)
);
Queue_21 Queue_5 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14474.4]
.clock(Queue_5_clock),
.reset(Queue_5_reset),
.io_enq_ready(Queue_5_io_enq_ready),
.io_enq_valid(Queue_5_io_enq_valid),
.io_enq_bits_id(Queue_5_io_enq_bits_id),
.io_enq_bits_data(Queue_5_io_enq_bits_data),
.io_enq_bits_resp(Queue_5_io_enq_bits_resp),
.io_enq_bits_user(Queue_5_io_enq_bits_user),
.io_enq_bits_last(Queue_5_io_enq_bits_last),
.io_deq_ready(Queue_5_io_deq_ready),
.io_deq_valid(Queue_5_io_deq_valid),
.io_deq_bits_id(Queue_5_io_deq_bits_id),
.io_deq_bits_data(Queue_5_io_deq_bits_data),
.io_deq_bits_resp(Queue_5_io_deq_bits_resp),
.io_deq_bits_user(Queue_5_io_deq_bits_user),
.io_deq_bits_last(Queue_5_io_deq_bits_last)
);
Queue_21 Queue_6 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14478.4]
.clock(Queue_6_clock),
.reset(Queue_6_reset),
.io_enq_ready(Queue_6_io_enq_ready),
.io_enq_valid(Queue_6_io_enq_valid),
.io_enq_bits_id(Queue_6_io_enq_bits_id),
.io_enq_bits_data(Queue_6_io_enq_bits_data),
.io_enq_bits_resp(Queue_6_io_enq_bits_resp),
.io_enq_bits_user(Queue_6_io_enq_bits_user),
.io_enq_bits_last(Queue_6_io_enq_bits_last),
.io_deq_ready(Queue_6_io_deq_ready),
.io_deq_valid(Queue_6_io_deq_valid),
.io_deq_bits_id(Queue_6_io_deq_bits_id),
.io_deq_bits_data(Queue_6_io_deq_bits_data),
.io_deq_bits_resp(Queue_6_io_deq_bits_resp),
.io_deq_bits_user(Queue_6_io_deq_bits_user),
.io_deq_bits_last(Queue_6_io_deq_bits_last)
);
Queue_21 Queue_7 ( // @[Deinterleaver.scala 43:19:freechips.rocketchip.system.LowRiscConfig.fir@14482.4]
.clock(Queue_7_clock),
.reset(Queue_7_reset),
.io_enq_ready(Queue_7_io_enq_ready),
.io_enq_valid(Queue_7_io_enq_valid),
.io_enq_bits_id(Queue_7_io_enq_bits_id),
.io_enq_bits_data(Queue_7_io_enq_bits_data),
.io_enq_bits_resp(Queue_7_io_enq_bits_resp),
.io_enq_bits_user(Queue_7_io_enq_bits_user),
.io_enq_bits_last(Queue_7_io_enq_bits_last),
.io_deq_ready(Queue_7_io_deq_ready),
.io_deq_valid(Queue_7_io_deq_valid),
.io_deq_bits_id(Queue_7_io_deq_bits_id),
.io_deq_bits_data(Queue_7_io_deq_bits_data),
.io_deq_bits_resp(Queue_7_io_deq_bits_resp),
.io_deq_bits_user(Queue_7_io_deq_bits_user),
.io_deq_bits_last(Queue_7_io_deq_bits_last)
);
assign _T_482 = 16'h1 << _T_480; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@14505.4]
assign _T_485 = 16'h1 << auto_out_r_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@14508.4]
assign _T_490 = _T_485[0]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14513.4]
assign _T_850_7 = Queue_7_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14976.4]
assign _T_850_6 = Queue_6_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14975.4]
assign _T_850_5 = Queue_5_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14974.4]
assign _T_850_4 = Queue_4_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14973.4]
assign _T_850_3 = Queue_3_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14972.4]
assign _T_850_2 = Queue_2_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14971.4]
assign _T_850_1 = Queue_1_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14970.4]
assign _T_850_0 = Queue_io_enq_ready; // @[Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14967.4 Deinterleaver.scala 90:27:freechips.rocketchip.system.LowRiscConfig.fir@14969.4]
assign _GEN_83 = 4'h1 == auto_out_r_bits_id ? _T_850_1 : _T_850_0; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_84 = 4'h2 == auto_out_r_bits_id ? _T_850_2 : _GEN_83; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_85 = 4'h3 == auto_out_r_bits_id ? _T_850_3 : _GEN_84; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_86 = 4'h4 == auto_out_r_bits_id ? _T_850_4 : _GEN_85; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_87 = 4'h5 == auto_out_r_bits_id ? _T_850_5 : _GEN_86; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_88 = 4'h6 == auto_out_r_bits_id ? _T_850_6 : _GEN_87; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_89 = 4'h7 == auto_out_r_bits_id ? _T_850_7 : _GEN_88; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_90 = 4'h8 == auto_out_r_bits_id ? 1'h0 : _GEN_89; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_91 = 4'h9 == auto_out_r_bits_id ? 1'h0 : _GEN_90; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_92 = 4'ha == auto_out_r_bits_id ? 1'h0 : _GEN_91; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_93 = 4'hb == auto_out_r_bits_id ? 1'h0 : _GEN_92; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_94 = 4'hc == auto_out_r_bits_id ? 1'h0 : _GEN_93; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_95 = 4'hd == auto_out_r_bits_id ? 1'h0 : _GEN_94; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_96 = 4'he == auto_out_r_bits_id ? 1'h0 : _GEN_95; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _GEN_97 = 4'hf == auto_out_r_bits_id ? 1'h0 : _GEN_96; // @[Deinterleaver.scala 90:21:freechips.rocketchip.system.LowRiscConfig.fir@14985.4]
assign _T_491 = _GEN_97 & auto_out_r_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14514.4]
assign _T_492 = _T_490 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14515.4]
assign _T_493 = _T_492 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14516.4]
assign _T_494 = _T_482[0]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14517.4]
assign _T_495 = auto_in_r_ready & _T_478; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@14518.4]
assign _T_496 = _T_494 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14519.4]
assign _T_779_7_last = Queue_7_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
assign _T_779_6_last = Queue_6_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
assign _T_779_5_last = Queue_5_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
assign _T_779_4_last = Queue_4_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
assign _T_779_3_last = Queue_3_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
assign _T_779_2_last = Queue_2_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
assign _T_779_1_last = Queue_1_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
assign _T_779_0_last = Queue_io_deq_bits_last; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
assign _GEN_11 = 4'h1 == _T_480 ? _T_779_1_last : _T_779_0_last; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_16 = 4'h2 == _T_480 ? _T_779_2_last : _GEN_11; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_21 = 4'h3 == _T_480 ? _T_779_3_last : _GEN_16; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_26 = 4'h4 == _T_480 ? _T_779_4_last : _GEN_21; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_31 = 4'h5 == _T_480 ? _T_779_5_last : _GEN_26; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_36 = 4'h6 == _T_480 ? _T_779_6_last : _GEN_31; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_41 = 4'h7 == _T_480 ? _T_779_7_last : _GEN_36; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_46 = 4'h8 == _T_480 ? 1'h0 : _GEN_41; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_51 = 4'h9 == _T_480 ? 1'h0 : _GEN_46; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_56 = 4'ha == _T_480 ? 1'h0 : _GEN_51; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_61 = 4'hb == _T_480 ? 1'h0 : _GEN_56; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_66 = 4'hc == _T_480 ? 1'h0 : _GEN_61; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_71 = 4'hd == _T_480 ? 1'h0 : _GEN_66; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_76 = 4'he == _T_480 ? 1'h0 : _GEN_71; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_81 = 4'hf == _T_480 ? 1'h0 : _GEN_76; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_497 = _T_496 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14520.4]
assign _GEN_98 = {{3'd0}, _T_493}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14521.4]
assign _T_499 = _T_488 + _GEN_98; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14522.4]
assign _GEN_99 = {{3'd0}, _T_497}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14523.4]
assign _T_500 = _T_499 - _GEN_99; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14523.4]
assign _T_501 = $unsigned(_T_500); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14524.4]
assign _T_502 = _T_501[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14525.4]
assign _T_503 = _T_497 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14528.4]
assign _T_504 = _T_488 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14529.4]
assign _T_505 = _T_503 | _T_504; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14530.4]
assign _T_507 = _T_505 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14532.4]
assign _T_508 = _T_507 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14533.4]
assign _T_509 = _T_493 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14538.4]
assign _T_510 = _T_488 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14539.4]
assign _T_511 = _T_509 | _T_510; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14540.4]
assign _T_513 = _T_511 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14542.4]
assign _T_514 = _T_513 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14543.4]
assign _T_515 = _T_502 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14548.4]
assign _T_519 = _T_485[1]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14552.4]
assign _T_521 = _T_519 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14554.4]
assign _T_522 = _T_521 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14555.4]
assign _T_523 = _T_482[1]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14556.4]
assign _T_525 = _T_523 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14558.4]
assign _T_526 = _T_525 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14559.4]
assign _GEN_100 = {{3'd0}, _T_522}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14560.4]
assign _T_528 = _T_517 + _GEN_100; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14561.4]
assign _GEN_101 = {{3'd0}, _T_526}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14562.4]
assign _T_529 = _T_528 - _GEN_101; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14562.4]
assign _T_530 = $unsigned(_T_529); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14563.4]
assign _T_531 = _T_530[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14564.4]
assign _T_532 = _T_526 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14567.4]
assign _T_533 = _T_517 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14568.4]
assign _T_534 = _T_532 | _T_533; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14569.4]
assign _T_536 = _T_534 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14571.4]
assign _T_537 = _T_536 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14572.4]
assign _T_538 = _T_522 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14577.4]
assign _T_539 = _T_517 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14578.4]
assign _T_540 = _T_538 | _T_539; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14579.4]
assign _T_542 = _T_540 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14581.4]
assign _T_543 = _T_542 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14582.4]
assign _T_544 = _T_531 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14587.4]
assign _T_548 = _T_485[2]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14591.4]
assign _T_550 = _T_548 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14593.4]
assign _T_551 = _T_550 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14594.4]
assign _T_552 = _T_482[2]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14595.4]
assign _T_554 = _T_552 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14597.4]
assign _T_555 = _T_554 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14598.4]
assign _GEN_102 = {{3'd0}, _T_551}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14599.4]
assign _T_557 = _T_546 + _GEN_102; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14600.4]
assign _GEN_103 = {{3'd0}, _T_555}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14601.4]
assign _T_558 = _T_557 - _GEN_103; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14601.4]
assign _T_559 = $unsigned(_T_558); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14602.4]
assign _T_560 = _T_559[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14603.4]
assign _T_561 = _T_555 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14606.4]
assign _T_562 = _T_546 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14607.4]
assign _T_563 = _T_561 | _T_562; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14608.4]
assign _T_565 = _T_563 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14610.4]
assign _T_566 = _T_565 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14611.4]
assign _T_567 = _T_551 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14616.4]
assign _T_568 = _T_546 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14617.4]
assign _T_569 = _T_567 | _T_568; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14618.4]
assign _T_571 = _T_569 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14620.4]
assign _T_572 = _T_571 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14621.4]
assign _T_573 = _T_560 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14626.4]
assign _T_577 = _T_485[3]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14630.4]
assign _T_579 = _T_577 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14632.4]
assign _T_580 = _T_579 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14633.4]
assign _T_581 = _T_482[3]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14634.4]
assign _T_583 = _T_581 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14636.4]
assign _T_584 = _T_583 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14637.4]
assign _GEN_104 = {{3'd0}, _T_580}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14638.4]
assign _T_586 = _T_575 + _GEN_104; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14639.4]
assign _GEN_105 = {{3'd0}, _T_584}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14640.4]
assign _T_587 = _T_586 - _GEN_105; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14640.4]
assign _T_588 = $unsigned(_T_587); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14641.4]
assign _T_589 = _T_588[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14642.4]
assign _T_590 = _T_584 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14645.4]
assign _T_591 = _T_575 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14646.4]
assign _T_592 = _T_590 | _T_591; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14647.4]
assign _T_594 = _T_592 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14649.4]
assign _T_595 = _T_594 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14650.4]
assign _T_596 = _T_580 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14655.4]
assign _T_597 = _T_575 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14656.4]
assign _T_598 = _T_596 | _T_597; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14657.4]
assign _T_600 = _T_598 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14659.4]
assign _T_601 = _T_600 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14660.4]
assign _T_602 = _T_589 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14665.4]
assign _T_606 = _T_485[4]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14669.4]
assign _T_608 = _T_606 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14671.4]
assign _T_609 = _T_608 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14672.4]
assign _T_610 = _T_482[4]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14673.4]
assign _T_612 = _T_610 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14675.4]
assign _T_613 = _T_612 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14676.4]
assign _GEN_106 = {{3'd0}, _T_609}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14677.4]
assign _T_615 = _T_604 + _GEN_106; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14678.4]
assign _GEN_107 = {{3'd0}, _T_613}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14679.4]
assign _T_616 = _T_615 - _GEN_107; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14679.4]
assign _T_617 = $unsigned(_T_616); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14680.4]
assign _T_618 = _T_617[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14681.4]
assign _T_619 = _T_613 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14684.4]
assign _T_620 = _T_604 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14685.4]
assign _T_621 = _T_619 | _T_620; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14686.4]
assign _T_623 = _T_621 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14688.4]
assign _T_624 = _T_623 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14689.4]
assign _T_625 = _T_609 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14694.4]
assign _T_626 = _T_604 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14695.4]
assign _T_627 = _T_625 | _T_626; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14696.4]
assign _T_629 = _T_627 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14698.4]
assign _T_630 = _T_629 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14699.4]
assign _T_631 = _T_618 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14704.4]
assign _T_635 = _T_485[5]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14708.4]
assign _T_637 = _T_635 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14710.4]
assign _T_638 = _T_637 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14711.4]
assign _T_639 = _T_482[5]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14712.4]
assign _T_641 = _T_639 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14714.4]
assign _T_642 = _T_641 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14715.4]
assign _GEN_108 = {{3'd0}, _T_638}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14716.4]
assign _T_644 = _T_633 + _GEN_108; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14717.4]
assign _GEN_109 = {{3'd0}, _T_642}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14718.4]
assign _T_645 = _T_644 - _GEN_109; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14718.4]
assign _T_646 = $unsigned(_T_645); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14719.4]
assign _T_647 = _T_646[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14720.4]
assign _T_648 = _T_642 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14723.4]
assign _T_649 = _T_633 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14724.4]
assign _T_650 = _T_648 | _T_649; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14725.4]
assign _T_652 = _T_650 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14727.4]
assign _T_653 = _T_652 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14728.4]
assign _T_654 = _T_638 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14733.4]
assign _T_655 = _T_633 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14734.4]
assign _T_656 = _T_654 | _T_655; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14735.4]
assign _T_658 = _T_656 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14737.4]
assign _T_659 = _T_658 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14738.4]
assign _T_660 = _T_647 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14743.4]
assign _T_664 = _T_485[6]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14747.4]
assign _T_666 = _T_664 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14749.4]
assign _T_667 = _T_666 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14750.4]
assign _T_668 = _T_482[6]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14751.4]
assign _T_670 = _T_668 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14753.4]
assign _T_671 = _T_670 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14754.4]
assign _GEN_110 = {{3'd0}, _T_667}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14755.4]
assign _T_673 = _T_662 + _GEN_110; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14756.4]
assign _GEN_111 = {{3'd0}, _T_671}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14757.4]
assign _T_674 = _T_673 - _GEN_111; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14757.4]
assign _T_675 = $unsigned(_T_674); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14758.4]
assign _T_676 = _T_675[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14759.4]
assign _T_677 = _T_671 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14762.4]
assign _T_678 = _T_662 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14763.4]
assign _T_679 = _T_677 | _T_678; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14764.4]
assign _T_681 = _T_679 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14766.4]
assign _T_682 = _T_681 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14767.4]
assign _T_683 = _T_667 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14772.4]
assign _T_684 = _T_662 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14773.4]
assign _T_685 = _T_683 | _T_684; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14774.4]
assign _T_687 = _T_685 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14776.4]
assign _T_688 = _T_687 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14777.4]
assign _T_689 = _T_676 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14782.4]
assign _T_693 = _T_485[7]; // @[Deinterleaver.scala 64:29:freechips.rocketchip.system.LowRiscConfig.fir@14786.4]
assign _T_695 = _T_693 & _T_491; // @[Deinterleaver.scala 64:33:freechips.rocketchip.system.LowRiscConfig.fir@14788.4]
assign _T_696 = _T_695 & auto_out_r_bits_last; // @[Deinterleaver.scala 64:49:freechips.rocketchip.system.LowRiscConfig.fir@14789.4]
assign _T_697 = _T_482[7]; // @[Deinterleaver.scala 65:29:freechips.rocketchip.system.LowRiscConfig.fir@14790.4]
assign _T_699 = _T_697 & _T_495; // @[Deinterleaver.scala 65:33:freechips.rocketchip.system.LowRiscConfig.fir@14792.4]
assign _T_700 = _T_699 & _GEN_81; // @[Deinterleaver.scala 65:48:freechips.rocketchip.system.LowRiscConfig.fir@14793.4]
assign _GEN_112 = {{3'd0}, _T_696}; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14794.4]
assign _T_702 = _T_691 + _GEN_112; // @[Deinterleaver.scala 66:27:freechips.rocketchip.system.LowRiscConfig.fir@14795.4]
assign _GEN_113 = {{3'd0}, _T_700}; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14796.4]
assign _T_703 = _T_702 - _GEN_113; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14796.4]
assign _T_704 = $unsigned(_T_703); // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14797.4]
assign _T_705 = _T_704[3:0]; // @[Deinterleaver.scala 66:40:freechips.rocketchip.system.LowRiscConfig.fir@14798.4]
assign _T_706 = _T_700 == 1'h0; // @[Deinterleaver.scala 69:21:freechips.rocketchip.system.LowRiscConfig.fir@14801.4]
assign _T_707 = _T_691 != 4'h0; // @[Deinterleaver.scala 69:35:freechips.rocketchip.system.LowRiscConfig.fir@14802.4]
assign _T_708 = _T_706 | _T_707; // @[Deinterleaver.scala 69:26:freechips.rocketchip.system.LowRiscConfig.fir@14803.4]
assign _T_710 = _T_708 | reset; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14805.4]
assign _T_711 = _T_710 == 1'h0; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14806.4]
assign _T_712 = _T_696 == 1'h0; // @[Deinterleaver.scala 70:21:freechips.rocketchip.system.LowRiscConfig.fir@14811.4]
assign _T_713 = _T_691 != 4'h8; // @[Deinterleaver.scala 70:35:freechips.rocketchip.system.LowRiscConfig.fir@14812.4]
assign _T_714 = _T_712 | _T_713; // @[Deinterleaver.scala 70:26:freechips.rocketchip.system.LowRiscConfig.fir@14813.4]
assign _T_716 = _T_714 | reset; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14815.4]
assign _T_717 = _T_716 == 1'h0; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14816.4]
assign _T_718 = _T_705 != 4'h0; // @[Deinterleaver.scala 71:18:freechips.rocketchip.system.LowRiscConfig.fir@14821.4]
assign _T_733 = {8'h0,_T_718,_T_689,_T_660,_T_631,_T_602,_T_573,_T_544,_T_515}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@14836.4]
assign _GEN_114 = {{1'd0}, _T_733}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14837.4]
assign _T_734 = _GEN_114 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14837.4]
assign _T_735 = _T_734[15:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14838.4]
assign _T_736 = _T_733 | _T_735; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14839.4]
assign _GEN_115 = {{2'd0}, _T_736}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14840.4]
assign _T_737 = _GEN_115 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14840.4]
assign _T_738 = _T_737[15:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14841.4]
assign _T_739 = _T_736 | _T_738; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14842.4]
assign _GEN_116 = {{4'd0}, _T_739}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14843.4]
assign _T_740 = _GEN_116 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14843.4]
assign _T_741 = _T_740[15:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14844.4]
assign _T_742 = _T_739 | _T_741; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14845.4]
assign _GEN_117 = {{8'd0}, _T_742}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14846.4]
assign _T_743 = _GEN_117 << 8; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@14846.4]
assign _T_744 = _T_743[15:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@14847.4]
assign _T_745 = _T_742 | _T_744; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@14848.4]
assign _GEN_118 = {{1'd0}, _T_745}; // @[Deinterleaver.scala 76:51:freechips.rocketchip.system.LowRiscConfig.fir@14850.4]
assign _T_747 = _GEN_118 << 1; // @[Deinterleaver.scala 76:51:freechips.rocketchip.system.LowRiscConfig.fir@14850.4]
assign _T_748 = ~ _T_747; // @[Deinterleaver.scala 76:33:freechips.rocketchip.system.LowRiscConfig.fir@14851.4]
assign _T_749 = _GEN_114 & _T_748; // @[Deinterleaver.scala 76:31:freechips.rocketchip.system.LowRiscConfig.fir@14852.4]
assign _T_750 = _T_478 == 1'h0; // @[Deinterleaver.scala 77:15:freechips.rocketchip.system.LowRiscConfig.fir@14853.4]
assign _T_752 = _T_495 & _GEN_81; // @[Deinterleaver.scala 77:39:freechips.rocketchip.system.LowRiscConfig.fir@14855.4]
assign _T_753 = _T_750 | _T_752; // @[Deinterleaver.scala 77:23:freechips.rocketchip.system.LowRiscConfig.fir@14856.4]
assign _T_754 = _T_733 != 16'h0; // @[Deinterleaver.scala 78:29:freechips.rocketchip.system.LowRiscConfig.fir@14858.6]
assign _T_755 = _T_749[16]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14860.6]
assign _T_756 = _T_749[15:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14861.6]
assign _GEN_120 = {{15'd0}, _T_755}; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14863.6]
assign _T_758 = _GEN_120 | _T_756; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14863.6]
assign _T_759 = _T_758[15:8]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14864.6]
assign _T_760 = _T_758[7:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14865.6]
assign _T_761 = _T_759 != 8'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@14866.6]
assign _T_762 = _T_759 | _T_760; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14867.6]
assign _T_763 = _T_762[7:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14868.6]
assign _T_764 = _T_762[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14869.6]
assign _T_765 = _T_763 != 4'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@14870.6]
assign _T_766 = _T_763 | _T_764; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14871.6]
assign _T_767 = _T_766[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@14872.6]
assign _T_768 = _T_766[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@14873.6]
assign _T_769 = _T_767 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@14874.6]
assign _T_770 = _T_767 | _T_768; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@14875.6]
assign _T_771 = _T_770[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@14876.6]
assign _T_775 = {_T_755,_T_761,_T_765,_T_769,_T_771}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@14880.6]
assign _GEN_1 = _T_753 ? _T_775 : {{1'd0}, _T_480}; // @[Deinterleaver.scala 77:59:freechips.rocketchip.system.LowRiscConfig.fir@14857.4]
assign _T_779_0_id = Queue_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
assign _T_779_0_data = Queue_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
assign _T_779_0_resp = Queue_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
assign _T_779_0_user = Queue_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14886.4]
assign _T_779_1_id = Queue_1_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
assign _GEN_7 = 4'h1 == _T_480 ? _T_779_1_id : _T_779_0_id; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_1_data = Queue_1_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
assign _GEN_8 = 4'h1 == _T_480 ? _T_779_1_data : _T_779_0_data; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_1_resp = Queue_1_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
assign _GEN_9 = 4'h1 == _T_480 ? _T_779_1_resp : _T_779_0_resp; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_1_user = Queue_1_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14887.4]
assign _GEN_10 = 4'h1 == _T_480 ? _T_779_1_user : _T_779_0_user; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_2_id = Queue_2_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
assign _GEN_12 = 4'h2 == _T_480 ? _T_779_2_id : _GEN_7; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_2_data = Queue_2_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
assign _GEN_13 = 4'h2 == _T_480 ? _T_779_2_data : _GEN_8; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_2_resp = Queue_2_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
assign _GEN_14 = 4'h2 == _T_480 ? _T_779_2_resp : _GEN_9; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_2_user = Queue_2_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14888.4]
assign _GEN_15 = 4'h2 == _T_480 ? _T_779_2_user : _GEN_10; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_3_id = Queue_3_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
assign _GEN_17 = 4'h3 == _T_480 ? _T_779_3_id : _GEN_12; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_3_data = Queue_3_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
assign _GEN_18 = 4'h3 == _T_480 ? _T_779_3_data : _GEN_13; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_3_resp = Queue_3_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
assign _GEN_19 = 4'h3 == _T_480 ? _T_779_3_resp : _GEN_14; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_3_user = Queue_3_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14889.4]
assign _GEN_20 = 4'h3 == _T_480 ? _T_779_3_user : _GEN_15; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_4_id = Queue_4_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
assign _GEN_22 = 4'h4 == _T_480 ? _T_779_4_id : _GEN_17; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_4_data = Queue_4_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
assign _GEN_23 = 4'h4 == _T_480 ? _T_779_4_data : _GEN_18; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_4_resp = Queue_4_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
assign _GEN_24 = 4'h4 == _T_480 ? _T_779_4_resp : _GEN_19; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_4_user = Queue_4_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14890.4]
assign _GEN_25 = 4'h4 == _T_480 ? _T_779_4_user : _GEN_20; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_5_id = Queue_5_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
assign _GEN_27 = 4'h5 == _T_480 ? _T_779_5_id : _GEN_22; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_5_data = Queue_5_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
assign _GEN_28 = 4'h5 == _T_480 ? _T_779_5_data : _GEN_23; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_5_resp = Queue_5_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
assign _GEN_29 = 4'h5 == _T_480 ? _T_779_5_resp : _GEN_24; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_5_user = Queue_5_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14891.4]
assign _GEN_30 = 4'h5 == _T_480 ? _T_779_5_user : _GEN_25; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_6_id = Queue_6_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
assign _GEN_32 = 4'h6 == _T_480 ? _T_779_6_id : _GEN_27; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_6_data = Queue_6_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
assign _GEN_33 = 4'h6 == _T_480 ? _T_779_6_data : _GEN_28; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_6_resp = Queue_6_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
assign _GEN_34 = 4'h6 == _T_480 ? _T_779_6_resp : _GEN_29; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_6_user = Queue_6_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14892.4]
assign _GEN_35 = 4'h6 == _T_480 ? _T_779_6_user : _GEN_30; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_7_id = Queue_7_io_deq_bits_id; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
assign _GEN_37 = 4'h7 == _T_480 ? _T_779_7_id : _GEN_32; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_7_data = Queue_7_io_deq_bits_data; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
assign _GEN_38 = 4'h7 == _T_480 ? _T_779_7_data : _GEN_33; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_7_resp = Queue_7_io_deq_bits_resp; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
assign _GEN_39 = 4'h7 == _T_480 ? _T_779_7_resp : _GEN_34; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _T_779_7_user = Queue_7_io_deq_bits_user; // @[Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14884.4 Deinterleaver.scala 84:26:freechips.rocketchip.system.LowRiscConfig.fir@14893.4]
assign _GEN_40 = 4'h7 == _T_480 ? _T_779_7_user : _GEN_35; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_42 = 4'h8 == _T_480 ? 4'h0 : _GEN_37; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_43 = 4'h8 == _T_480 ? 64'h0 : _GEN_38; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_44 = 4'h8 == _T_480 ? 2'h0 : _GEN_39; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_45 = 4'h8 == _T_480 ? 9'h0 : _GEN_40; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_47 = 4'h9 == _T_480 ? 4'h0 : _GEN_42; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_48 = 4'h9 == _T_480 ? 64'h0 : _GEN_43; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_49 = 4'h9 == _T_480 ? 2'h0 : _GEN_44; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_50 = 4'h9 == _T_480 ? 9'h0 : _GEN_45; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_52 = 4'ha == _T_480 ? 4'h0 : _GEN_47; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_53 = 4'ha == _T_480 ? 64'h0 : _GEN_48; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_54 = 4'ha == _T_480 ? 2'h0 : _GEN_49; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_55 = 4'ha == _T_480 ? 9'h0 : _GEN_50; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_57 = 4'hb == _T_480 ? 4'h0 : _GEN_52; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_58 = 4'hb == _T_480 ? 64'h0 : _GEN_53; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_59 = 4'hb == _T_480 ? 2'h0 : _GEN_54; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_60 = 4'hb == _T_480 ? 9'h0 : _GEN_55; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_62 = 4'hc == _T_480 ? 4'h0 : _GEN_57; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_63 = 4'hc == _T_480 ? 64'h0 : _GEN_58; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_64 = 4'hc == _T_480 ? 2'h0 : _GEN_59; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_65 = 4'hc == _T_480 ? 9'h0 : _GEN_60; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_67 = 4'hd == _T_480 ? 4'h0 : _GEN_62; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_68 = 4'hd == _T_480 ? 64'h0 : _GEN_63; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_69 = 4'hd == _T_480 ? 2'h0 : _GEN_64; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_70 = 4'hd == _T_480 ? 9'h0 : _GEN_65; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_72 = 4'he == _T_480 ? 4'h0 : _GEN_67; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_73 = 4'he == _T_480 ? 64'h0 : _GEN_68; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_74 = 4'he == _T_480 ? 2'h0 : _GEN_69; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign _GEN_75 = 4'he == _T_480 ? 9'h0 : _GEN_70; // @[Deinterleaver.scala 84:20:freechips.rocketchip.system.LowRiscConfig.fir@14902.4]
assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_b_bits_user = auto_out_b_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_r_valid = _T_478; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_r_bits_id = 4'hf == _T_480 ? 4'h0 : _GEN_72; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_r_bits_data = 4'hf == _T_480 ? 64'h0 : _GEN_73; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_r_bits_resp = 4'hf == _T_480 ? 2'h0 : _GEN_74; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_r_bits_user = 4'hf == _T_480 ? 9'h0 : _GEN_75; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_in_r_bits_last = 4'hf == _T_480 ? 1'h0 : _GEN_76; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@14449.4]
assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_aw_bits_user = auto_in_aw_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_ar_bits_user = auto_in_ar_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign auto_out_r_ready = 4'hf == auto_out_r_bits_id ? 1'h0 : _GEN_96; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@14448.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14456.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14457.4]
assign Queue_io_enq_valid = _T_490 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15003.4]
assign Queue_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15004.4]
assign Queue_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15004.4]
assign Queue_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15004.4]
assign Queue_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15004.4]
assign Queue_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15004.4]
assign Queue_io_deq_ready = _T_494 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14921.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14460.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14461.4]
assign Queue_1_io_enq_valid = _T_519 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15006.4]
assign Queue_1_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15007.4]
assign Queue_1_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15007.4]
assign Queue_1_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15007.4]
assign Queue_1_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15007.4]
assign Queue_1_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15007.4]
assign Queue_1_io_deq_ready = _T_523 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14924.4]
assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14464.4]
assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14465.4]
assign Queue_2_io_enq_valid = _T_548 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15009.4]
assign Queue_2_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15010.4]
assign Queue_2_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15010.4]
assign Queue_2_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15010.4]
assign Queue_2_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15010.4]
assign Queue_2_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15010.4]
assign Queue_2_io_deq_ready = _T_552 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14927.4]
assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14468.4]
assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14469.4]
assign Queue_3_io_enq_valid = _T_577 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15012.4]
assign Queue_3_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15013.4]
assign Queue_3_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15013.4]
assign Queue_3_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15013.4]
assign Queue_3_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15013.4]
assign Queue_3_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15013.4]
assign Queue_3_io_deq_ready = _T_581 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14930.4]
assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14472.4]
assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14473.4]
assign Queue_4_io_enq_valid = _T_606 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15015.4]
assign Queue_4_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15016.4]
assign Queue_4_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15016.4]
assign Queue_4_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15016.4]
assign Queue_4_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15016.4]
assign Queue_4_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15016.4]
assign Queue_4_io_deq_ready = _T_610 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14933.4]
assign Queue_5_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14476.4]
assign Queue_5_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14477.4]
assign Queue_5_io_enq_valid = _T_635 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15018.4]
assign Queue_5_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15019.4]
assign Queue_5_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15019.4]
assign Queue_5_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15019.4]
assign Queue_5_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15019.4]
assign Queue_5_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15019.4]
assign Queue_5_io_deq_ready = _T_639 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14936.4]
assign Queue_6_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14480.4]
assign Queue_6_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14481.4]
assign Queue_6_io_enq_valid = _T_664 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15021.4]
assign Queue_6_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15022.4]
assign Queue_6_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15022.4]
assign Queue_6_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15022.4]
assign Queue_6_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15022.4]
assign Queue_6_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15022.4]
assign Queue_6_io_deq_ready = _T_668 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14939.4]
assign Queue_7_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14484.4]
assign Queue_7_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@14485.4]
assign Queue_7_io_enq_valid = _T_693 & auto_out_r_valid; // @[Deinterleaver.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@15024.4]
assign Queue_7_io_enq_bits_id = auto_out_r_bits_id; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15025.4]
assign Queue_7_io_enq_bits_data = auto_out_r_bits_data; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15025.4]
assign Queue_7_io_enq_bits_resp = auto_out_r_bits_resp; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15025.4]
assign Queue_7_io_enq_bits_user = auto_out_r_bits_user; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15025.4]
assign Queue_7_io_enq_bits_last = auto_out_r_bits_last; // @[Deinterleaver.scala 93:22:freechips.rocketchip.system.LowRiscConfig.fir@15025.4]
assign Queue_7_io_deq_ready = _T_697 & _T_495; // @[Deinterleaver.scala 86:23:freechips.rocketchip.system.LowRiscConfig.fir@14942.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_478 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_480 = _RAND_1[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_488 = _RAND_2[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_517 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_546 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_575 = _RAND_5[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_604 = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_633 = _RAND_7[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_662 = _RAND_8[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_691 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_478 <= 1'h0;
end else begin
if (_T_753) begin
_T_478 <= _T_754;
end
end
_T_480 <= _GEN_1[3:0];
if (reset) begin
_T_488 <= 4'h0;
end else begin
_T_488 <= _T_502;
end
if (reset) begin
_T_517 <= 4'h0;
end else begin
_T_517 <= _T_531;
end
if (reset) begin
_T_546 <= 4'h0;
end else begin
_T_546 <= _T_560;
end
if (reset) begin
_T_575 <= 4'h0;
end else begin
_T_575 <= _T_589;
end
if (reset) begin
_T_604 <= 4'h0;
end else begin
_T_604 <= _T_618;
end
if (reset) begin
_T_633 <= 4'h0;
end else begin
_T_633 <= _T_647;
end
if (reset) begin
_T_662 <= 4'h0;
end else begin
_T_662 <= _T_676;
end
if (reset) begin
_T_691 <= 4'h0;
end else begin
_T_691 <= _T_705;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_508) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14535.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_508) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14536.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_514) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14545.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_514) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14546.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_537) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14574.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_537) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14575.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_543) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14584.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_543) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14585.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_566) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14613.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_566) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14614.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_572) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14623.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_572) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14624.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_595) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14652.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_595) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14653.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_601) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14662.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_601) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14663.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_624) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14691.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_624) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14692.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_630) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14701.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_630) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14702.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_653) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14730.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_653) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14731.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_659) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14740.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_659) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14741.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_682) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14769.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_682) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14770.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_688) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14779.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_688) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14780.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_711) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:69 assert (!dec || count =/= UInt(0))\n"); // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14808.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_711) begin
$fatal; // @[Deinterleaver.scala 69:20:freechips.rocketchip.system.LowRiscConfig.fir@14809.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_717) begin
$fwrite(32'h80000002,"Assertion failed\n at Deinterleaver.scala:70 assert (!inc || count =/= UInt(beats))\n"); // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14818.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_717) begin
$fatal; // @[Deinterleaver.scala 70:20:freechips.rocketchip.system.LowRiscConfig.fir@14819.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module AXI4IdIndexer( // @[:freechips.rocketchip.system.LowRiscConfig.fir@15051.2]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [2:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [30:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [8:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [2:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [8:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [2:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [30:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [8:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [2:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [8:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [8:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [8:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output [8:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input [8:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@15054.4]
);
assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_b_bits_id = auto_out_b_bits_id[2:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_b_bits_user = auto_out_b_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_r_bits_id = auto_out_r_bits_id[2:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_r_bits_user = auto_out_r_bits_user; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@15064.4]
assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_id = {{1'd0}, auto_in_aw_bits_id}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_aw_bits_user = auto_in_aw_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_id = {{1'd0}, auto_in_ar_bits_id}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_ar_bits_user = auto_in_ar_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@15063.4]
endmodule
module TLMonitor_4( // @[:freechips.rocketchip.system.LowRiscConfig.fir@15078.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15079.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15080.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [30:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@15081.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@16442.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15098.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15099.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15104.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15105.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15108.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15109.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15117.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15129.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15130.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15131.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15132.6]
wire [22:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@15134.6]
wire [7:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@15135.6]
wire [7:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@15136.6]
wire [30:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@15137.6]
wire [30:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@15137.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@15138.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@15140.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@15141.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@15142.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@15143.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@15144.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@15145.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@15146.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@15147.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15149.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15150.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15152.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15153.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@15154.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@15155.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@15156.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15157.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15158.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15159.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15160.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15161.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15162.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15163.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15164.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15165.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15166.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15167.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15168.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@15169.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@15170.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@15171.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15172.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15173.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15174.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15175.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15176.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15177.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15178.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15179.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15180.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15181.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15182.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15183.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15184.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15185.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15186.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15187.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15188.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15189.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15190.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15191.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15192.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15193.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15194.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15195.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@15202.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@15275.6]
wire [30:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@15278.8]
wire [31:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@15279.8]
wire [31:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@15280.8]
wire [31:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@15281.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@15282.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@15287.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@15325.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@15326.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@15338.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@15339.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@15345.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@15346.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@15353.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@15354.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@15360.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@15361.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@15366.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@15368.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@15369.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@15374.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@15375.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@15377.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@15378.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@15383.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@15385.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@15386.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@15392.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@15491.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@15493.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@15494.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@15517.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@15520.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@15528.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15531.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15532.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@15551.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@15553.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@15554.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@15559.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@15561.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@15562.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@15576.6]
wire _T_414; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@15579.8]
wire _T_422; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@15587.8]
wire _T_425; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15590.8]
wire _T_426; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15591.8]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@15627.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@15669.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@15670.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@15671.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@15673.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@15674.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@15680.6]
wire _T_490; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@15711.8]
wire _T_492; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@15713.8]
wire _T_493; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@15714.8]
wire _T_498; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@15728.6]
wire _T_516; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@15759.8]
wire _T_518; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@15761.8]
wire _T_519; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@15762.8]
wire _T_524; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@15776.6]
wire _T_550; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@15826.6]
wire _T_552; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@15828.6]
wire _T_553; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@15829.6]
wire [2:0] _T_556; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15836.6]
wire _T_557; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15837.6]
wire _T_562; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15842.6]
wire _T_563; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15843.6]
wire [1:0] _T_566; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15846.6]
wire _T_567; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15847.6]
wire _T_575; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15855.6]
wire _T_591; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15867.6]
wire _T_592; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15868.6]
wire _T_593; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15869.6]
wire _T_594; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15870.6]
wire _T_596; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@15872.6]
wire _T_598; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15875.8]
wire _T_599; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15876.8]
wire _T_600; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@15881.8]
wire _T_602; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@15883.8]
wire _T_603; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@15884.8]
wire _T_608; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@15897.8]
wire _T_610; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@15899.8]
wire _T_611; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@15900.8]
wire _T_612; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@15905.8]
wire _T_614; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@15907.8]
wire _T_615; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@15908.8]
wire _T_616; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@15914.6]
wire _T_644; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@15972.6]
wire _T_664; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@16013.8]
wire _T_666; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@16015.8]
wire _T_667; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@16016.8]
wire _T_673; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@16031.6]
wire _T_690; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@16066.6]
wire _T_708; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@16102.6]
wire _T_737; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@16162.4]
wire [4:0] _T_742; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@16167.4]
wire _T_743; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@16168.4]
wire _T_744; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@16169.4]
reg [4:0] _T_747; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@16171.4]
reg [31:0] _RAND_0;
wire [5:0] _T_748; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16172.4]
wire [5:0] _T_749; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16173.4]
wire [4:0] _T_750; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16174.4]
wire _T_751; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16175.4]
reg [2:0] _T_760; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@16186.4]
reg [31:0] _RAND_1;
reg [2:0] _T_762; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@16187.4]
reg [31:0] _RAND_2;
reg [3:0] _T_764; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@16188.4]
reg [31:0] _RAND_3;
reg [4:0] _T_766; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@16189.4]
reg [31:0] _RAND_4;
reg [30:0] _T_768; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@16190.4]
reg [31:0] _RAND_5;
wire _T_769; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@16191.4]
wire _T_770; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@16192.4]
wire _T_771; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@16194.6]
wire _T_773; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@16196.6]
wire _T_774; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@16197.6]
wire _T_775; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@16202.6]
wire _T_777; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@16204.6]
wire _T_778; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@16205.6]
wire _T_779; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@16210.6]
wire _T_781; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@16212.6]
wire _T_782; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@16213.6]
wire _T_783; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@16218.6]
wire _T_785; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@16220.6]
wire _T_786; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@16221.6]
wire _T_787; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@16226.6]
wire _T_789; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@16228.6]
wire _T_790; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@16229.6]
wire _T_792; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@16236.4]
wire _T_793; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@16244.4]
wire [22:0] _T_795; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@16246.4]
wire [7:0] _T_796; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@16247.4]
wire [7:0] _T_797; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@16248.4]
wire [4:0] _T_798; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@16249.4]
wire _T_799; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@16250.4]
reg [4:0] _T_802; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@16252.4]
reg [31:0] _RAND_6;
wire [5:0] _T_803; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16253.4]
wire [5:0] _T_804; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16254.4]
wire [4:0] _T_805; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16255.4]
wire _T_806; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16256.4]
reg [2:0] _T_815; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@16267.4]
reg [31:0] _RAND_7;
reg [3:0] _T_819; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@16269.4]
reg [31:0] _RAND_8;
reg [4:0] _T_821; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@16270.4]
reg [31:0] _RAND_9;
reg _T_825; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@16272.4]
reg [31:0] _RAND_10;
wire _T_826; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@16273.4]
wire _T_827; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@16274.4]
wire _T_828; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@16276.6]
wire _T_830; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@16278.6]
wire _T_831; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@16279.6]
wire _T_836; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@16292.6]
wire _T_838; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@16294.6]
wire _T_839; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@16295.6]
wire _T_840; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@16300.6]
wire _T_842; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@16302.6]
wire _T_843; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@16303.6]
wire _T_848; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@16316.6]
wire _T_850; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@16318.6]
wire _T_851; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@16319.6]
wire _T_853; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@16326.4]
reg [24:0] _T_855; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@16335.4]
reg [31:0] _RAND_11;
reg [4:0] _T_866; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@16345.4]
reg [31:0] _RAND_12;
wire [5:0] _T_867; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16346.4]
wire [5:0] _T_868; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16347.4]
wire [4:0] _T_869; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16348.4]
wire _T_870; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16349.4]
reg [4:0] _T_887; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@16368.4]
reg [31:0] _RAND_13;
wire [5:0] _T_888; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16369.4]
wire [5:0] _T_889; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16370.4]
wire [4:0] _T_890; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16371.4]
wire _T_891; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16372.4]
wire _T_902; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@16387.4]
wire [31:0] _T_904; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@16390.6]
wire [24:0] _T_905; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@16392.6]
wire _T_906; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@16393.6]
wire _T_907; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@16394.6]
wire _T_909; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@16396.6]
wire _T_910; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@16397.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@16389.4]
wire _T_915; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@16408.4]
wire _T_917; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@16410.4]
wire _T_918; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@16411.4]
wire [31:0] _T_919; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@16413.6]
wire [24:0] _T_900; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16383.4 :freechips.rocketchip.system.LowRiscConfig.fir@16385.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@16391.6]
wire [24:0] _T_920; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@16415.6]
wire [24:0] _T_921; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@16416.6]
wire _T_922; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@16417.6]
wire _T_924; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@16419.6]
wire _T_925; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@16420.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@16412.4]
wire [24:0] _T_912; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16403.4 :freechips.rocketchip.system.LowRiscConfig.fir@16405.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@16414.6]
wire _T_926; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@16426.4]
wire _T_927; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@16427.4]
wire _T_928; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@16428.4]
wire _T_929; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@16429.4]
wire _T_931; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@16431.4]
wire _T_932; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@16432.4]
wire [24:0] _T_933; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@16437.4]
wire [24:0] _T_934; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@16438.4]
wire [24:0] _T_935; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@16439.4]
reg [31:0] _T_937; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@16441.4]
reg [31:0] _RAND_14;
wire _T_938; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@16444.4]
wire _T_939; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@16445.4]
wire _T_940; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@16446.4]
wire _T_941; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@16447.4]
wire _T_942; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@16448.4]
wire _T_943; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@16449.4]
wire _T_945; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@16451.4]
wire _T_946; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@16452.4]
wire [31:0] _T_948; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@16458.4]
wire _T_951; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@16462.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@15289.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@15406.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15534.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15593.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@15644.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@15694.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@15742.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@15790.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15878.10]
wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@15920.10]
wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@15978.10]
wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@16037.10]
wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@16072.10]
wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@16108.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@16442.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15098.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15099.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15104.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15105.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15108.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15109.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15117.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15129.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15130.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15131.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15132.6]
assign _T_62 = 23'hff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@15134.6]
assign _T_63 = _T_62[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@15135.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@15136.6]
assign _GEN_18 = {{23'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@15137.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@15137.6]
assign _T_66 = _T_65 == 31'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@15138.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@15140.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@15141.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@15142.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@15143.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@15144.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@15145.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@15146.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@15147.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15149.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15150.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15152.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15153.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@15154.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@15155.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@15156.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15157.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15158.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15159.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15160.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15161.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15162.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15163.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15164.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15165.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15166.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15167.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15168.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@15169.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@15170.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@15171.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15172.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15173.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15174.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15175.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15176.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15177.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15178.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15179.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15180.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15181.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15182.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15183.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15184.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15185.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15186.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15187.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15188.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15189.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15190.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15191.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15192.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@15193.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@15194.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@15195.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@15202.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@15275.6]
assign _T_201 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@15278.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@15279.8]
assign _T_203 = $signed(_T_202) & $signed(-32'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@15280.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@15281.8]
assign _T_205 = $signed(_T_204) == $signed(32'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@15282.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@15287.8]
assign _T_248 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@15325.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@15326.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@15338.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@15339.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@15345.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@15346.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@15353.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@15354.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@15360.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@15361.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@15366.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@15368.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@15369.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@15374.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@15375.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@15377.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@15378.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@15383.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@15385.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@15386.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@15392.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@15491.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@15493.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@15494.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@15517.6]
assign _T_381 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@15520.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@15528.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15531.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15532.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@15551.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@15553.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@15554.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@15559.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@15561.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@15562.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@15576.6]
assign _T_414 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@15579.8]
assign _T_422 = _T_414 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@15587.8]
assign _T_425 = _T_422 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15590.8]
assign _T_426 = _T_425 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15591.8]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@15627.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@15669.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@15670.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@15671.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@15673.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@15674.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@15680.6]
assign _T_490 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@15711.8]
assign _T_492 = _T_490 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@15713.8]
assign _T_493 = _T_492 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@15714.8]
assign _T_498 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@15728.6]
assign _T_516 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@15759.8]
assign _T_518 = _T_516 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@15761.8]
assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@15762.8]
assign _T_524 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@15776.6]
assign _T_550 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@15826.6]
assign _T_552 = _T_550 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@15828.6]
assign _T_553 = _T_552 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@15829.6]
assign _T_556 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15836.6]
assign _T_557 = _T_556 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15837.6]
assign _T_562 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15842.6]
assign _T_563 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@15843.6]
assign _T_566 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@15846.6]
assign _T_567 = _T_566 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15847.6]
assign _T_575 = _T_566 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@15855.6]
assign _T_591 = _T_557 | _T_562; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15867.6]
assign _T_592 = _T_591 | _T_563; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15868.6]
assign _T_593 = _T_592 | _T_567; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15869.6]
assign _T_594 = _T_593 | _T_575; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@15870.6]
assign _T_596 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@15872.6]
assign _T_598 = _T_594 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15875.8]
assign _T_599 = _T_598 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15876.8]
assign _T_600 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@15881.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@15883.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@15884.8]
assign _T_608 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@15897.8]
assign _T_610 = _T_608 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@15899.8]
assign _T_611 = _T_610 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@15900.8]
assign _T_612 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@15905.8]
assign _T_614 = _T_612 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@15907.8]
assign _T_615 = _T_614 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@15908.8]
assign _T_616 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@15914.6]
assign _T_644 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@15972.6]
assign _T_664 = _T_612 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@16013.8]
assign _T_666 = _T_664 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@16015.8]
assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@16016.8]
assign _T_673 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@16031.6]
assign _T_690 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@16066.6]
assign _T_708 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@16102.6]
assign _T_737 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@16162.4]
assign _T_742 = _T_64[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@16167.4]
assign _T_743 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@16168.4]
assign _T_744 = _T_743 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@16169.4]
assign _T_748 = _T_747 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16172.4]
assign _T_749 = $unsigned(_T_748); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16173.4]
assign _T_750 = _T_749[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16174.4]
assign _T_751 = _T_747 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16175.4]
assign _T_769 = _T_751 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@16191.4]
assign _T_770 = io_in_a_valid & _T_769; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@16192.4]
assign _T_771 = io_in_a_bits_opcode == _T_760; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@16194.6]
assign _T_773 = _T_771 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@16196.6]
assign _T_774 = _T_773 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@16197.6]
assign _T_775 = io_in_a_bits_param == _T_762; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@16202.6]
assign _T_777 = _T_775 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@16204.6]
assign _T_778 = _T_777 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@16205.6]
assign _T_779 = io_in_a_bits_size == _T_764; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@16210.6]
assign _T_781 = _T_779 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@16212.6]
assign _T_782 = _T_781 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@16213.6]
assign _T_783 = io_in_a_bits_source == _T_766; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@16218.6]
assign _T_785 = _T_783 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@16220.6]
assign _T_786 = _T_785 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@16221.6]
assign _T_787 = io_in_a_bits_address == _T_768; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@16226.6]
assign _T_789 = _T_787 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@16228.6]
assign _T_790 = _T_789 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@16229.6]
assign _T_792 = _T_737 & _T_751; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@16236.4]
assign _T_793 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@16244.4]
assign _T_795 = 23'hff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@16246.4]
assign _T_796 = _T_795[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@16247.4]
assign _T_797 = ~ _T_796; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@16248.4]
assign _T_798 = _T_797[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@16249.4]
assign _T_799 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@16250.4]
assign _T_803 = _T_802 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16253.4]
assign _T_804 = $unsigned(_T_803); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16254.4]
assign _T_805 = _T_804[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16255.4]
assign _T_806 = _T_802 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16256.4]
assign _T_826 = _T_806 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@16273.4]
assign _T_827 = io_in_d_valid & _T_826; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@16274.4]
assign _T_828 = io_in_d_bits_opcode == _T_815; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@16276.6]
assign _T_830 = _T_828 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@16278.6]
assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@16279.6]
assign _T_836 = io_in_d_bits_size == _T_819; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@16292.6]
assign _T_838 = _T_836 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@16294.6]
assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@16295.6]
assign _T_840 = io_in_d_bits_source == _T_821; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@16300.6]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@16302.6]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@16303.6]
assign _T_848 = io_in_d_bits_denied == _T_825; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@16316.6]
assign _T_850 = _T_848 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@16318.6]
assign _T_851 = _T_850 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@16319.6]
assign _T_853 = _T_793 & _T_806; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@16326.4]
assign _T_867 = _T_866 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16346.4]
assign _T_868 = $unsigned(_T_867); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16347.4]
assign _T_869 = _T_868[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16348.4]
assign _T_870 = _T_866 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16349.4]
assign _T_888 = _T_887 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16369.4]
assign _T_889 = $unsigned(_T_888); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16370.4]
assign _T_890 = _T_889[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16371.4]
assign _T_891 = _T_887 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16372.4]
assign _T_902 = _T_737 & _T_870; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@16387.4]
assign _T_904 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@16390.6]
assign _T_905 = _T_855 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@16392.6]
assign _T_906 = _T_905[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@16393.6]
assign _T_907 = _T_906 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@16394.6]
assign _T_909 = _T_907 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@16396.6]
assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@16397.6]
assign _GEN_15 = _T_902 ? _T_904 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@16389.4]
assign _T_915 = _T_793 & _T_891; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@16408.4]
assign _T_917 = _T_596 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@16410.4]
assign _T_918 = _T_915 & _T_917; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@16411.4]
assign _T_919 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@16413.6]
assign _T_900 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16383.4 :freechips.rocketchip.system.LowRiscConfig.fir@16385.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@16391.6]
assign _T_920 = _T_900 | _T_855; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@16415.6]
assign _T_921 = _T_920 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@16416.6]
assign _T_922 = _T_921[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@16417.6]
assign _T_924 = _T_922 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@16419.6]
assign _T_925 = _T_924 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@16420.6]
assign _GEN_16 = _T_918 ? _T_919 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@16412.4]
assign _T_912 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16403.4 :freechips.rocketchip.system.LowRiscConfig.fir@16405.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@16414.6]
assign _T_926 = _T_900 != _T_912; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@16426.4]
assign _T_927 = _T_900 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@16427.4]
assign _T_928 = _T_927 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@16428.4]
assign _T_929 = _T_926 | _T_928; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@16429.4]
assign _T_931 = _T_929 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@16431.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@16432.4]
assign _T_933 = _T_855 | _T_900; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@16437.4]
assign _T_934 = ~ _T_912; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@16438.4]
assign _T_935 = _T_933 & _T_934; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@16439.4]
assign _T_938 = _T_855 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@16444.4]
assign _T_939 = _T_938 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@16445.4]
assign _T_940 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@16446.4]
assign _T_941 = _T_939 | _T_940; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@16447.4]
assign _T_942 = _T_937 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@16448.4]
assign _T_943 = _T_941 | _T_942; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@16449.4]
assign _T_945 = _T_943 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@16451.4]
assign _T_946 = _T_945 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@16452.4]
assign _T_948 = _T_937 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@16458.4]
assign _T_951 = _T_737 | _T_793; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@16462.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@15289.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@15406.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15534.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15593.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@15644.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@15694.10]
assign _GEN_95 = io_in_a_valid & _T_498; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@15742.10]
assign _GEN_105 = io_in_a_valid & _T_524; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@15790.10]
assign _GEN_115 = io_in_d_valid & _T_596; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15878.10]
assign _GEN_123 = io_in_d_valid & _T_616; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@15920.10]
assign _GEN_131 = io_in_d_valid & _T_644; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@15978.10]
assign _GEN_139 = io_in_d_valid & _T_673; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@16037.10]
assign _GEN_143 = io_in_d_valid & _T_690; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@16072.10]
assign _GEN_147 = io_in_d_valid & _T_708; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@16108.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_747 = _RAND_0[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_760 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_762 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_764 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_766 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_768 = _RAND_5[30:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_802 = _RAND_6[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_815 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_819 = _RAND_8[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_821 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_825 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_855 = _RAND_11[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_866 = _RAND_12[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_887 = _RAND_13[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_937 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_747 <= 5'h0;
end else begin
if (_T_737) begin
if (_T_751) begin
if (_T_744) begin
_T_747 <= _T_742;
end else begin
_T_747 <= 5'h0;
end
end else begin
_T_747 <= _T_750;
end
end
end
if (_T_792) begin
_T_760 <= io_in_a_bits_opcode;
end
if (_T_792) begin
_T_762 <= io_in_a_bits_param;
end
if (_T_792) begin
_T_764 <= io_in_a_bits_size;
end
if (_T_792) begin
_T_766 <= io_in_a_bits_source;
end
if (_T_792) begin
_T_768 <= io_in_a_bits_address;
end
if (reset) begin
_T_802 <= 5'h0;
end else begin
if (_T_793) begin
if (_T_806) begin
if (_T_799) begin
_T_802 <= _T_798;
end else begin
_T_802 <= 5'h0;
end
end else begin
_T_802 <= _T_805;
end
end
end
if (_T_853) begin
_T_815 <= io_in_d_bits_opcode;
end
if (_T_853) begin
_T_819 <= io_in_d_bits_size;
end
if (_T_853) begin
_T_821 <= io_in_d_bits_source;
end
if (_T_853) begin
_T_825 <= io_in_d_bits_denied;
end
if (reset) begin
_T_855 <= 25'h0;
end else begin
_T_855 <= _T_935;
end
if (reset) begin
_T_866 <= 5'h0;
end else begin
if (_T_737) begin
if (_T_870) begin
if (_T_744) begin
_T_866 <= _T_742;
end else begin
_T_866 <= 5'h0;
end
end else begin
_T_866 <= _T_869;
end
end
end
if (reset) begin
_T_887 <= 5'h0;
end else begin
if (_T_793) begin
if (_T_891) begin
if (_T_799) begin
_T_887 <= _T_798;
end else begin
_T_887 <= 5'h0;
end
end else begin
_T_887 <= _T_890;
end
end
end
if (reset) begin
_T_937 <= 32'h0;
end else begin
if (_T_951) begin
_T_937 <= 32'h0;
end else begin
_T_937 <= _T_948;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:136:11)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@15093.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@15094.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@15272.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@15273.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@15289.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@15290.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:136:11)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@15341.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@15342.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@15348.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@15349.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@15356.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@15357.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@15363.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@15364.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@15371.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@15372.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@15380.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@15381.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@15388.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@15389.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@15406.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@15407.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:136:11)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@15458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@15459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@15465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@15466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@15473.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@15474.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@15480.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@15481.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@15488.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@15489.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:136:11)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@15496.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@15497.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@15505.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@15506.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@15513.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@15514.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15534.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@15535.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@15541.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@15542.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@15548.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@15549.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@15556.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@15557.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@15564.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@15565.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@15572.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@15573.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_426) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_426) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@15594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@15600.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@15601.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@15607.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@15608.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@15615.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@15616.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@15623.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@15624.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_426) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@15644.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_426) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@15645.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@15651.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@15652.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@15658.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@15659.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@15666.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@15667.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@15676.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@15677.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@15694.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@15695.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@15701.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@15702.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@15708.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@15709.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@15716.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@15717.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@15724.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@15725.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@15742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@15743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@15749.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@15750.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@15756.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@15757.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@15764.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@15765.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@15772.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@15773.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:136:11)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@15790.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@15791.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@15797.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@15798.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:136:11)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@15804.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@15805.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:136:11)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@15812.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@15813.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@15820.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@15821.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:136:11)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@15831.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@15832.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15878.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@15879.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@15886.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@15887.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@15894.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@15895.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@15902.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_611) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@15903.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_615) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@15910.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_615) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@15911.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@15920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_599) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@15921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@15927.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@15928.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@15935.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_603) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@15936.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@15943.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@15944.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@15951.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@15952.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@15959.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_611) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@15960.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@15968.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@15969.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@15978.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@15979.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@15985.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@15986.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:136:11)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@15993.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_603) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@15994.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@16001.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@16002.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@16009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@16010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_667) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@16018.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_667) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@16019.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@16027.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@16028.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@16037.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_599) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@16038.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@16045.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@16046.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@16053.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_611) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@16054.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@16062.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@16063.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@16072.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_599) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@16073.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@16080.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@16081.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_667) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@16089.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_667) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@16090.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@16098.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@16099.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@16108.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_599) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@16109.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:136:11)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@16116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@16117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:136:11)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@16124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_611) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@16125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:136:11)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@16133.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@16134.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:136:11)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@16143.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@16144.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:136:11)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@16151.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@16152.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:136:11)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@16159.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@16160.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_774) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@16199.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_774) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@16200.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_778) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@16207.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_778) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@16208.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_782) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@16215.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_782) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@16216.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_786) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@16223.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_786) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@16224.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_790) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@16231.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_790) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@16232.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_831) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@16281.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_831) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@16282.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@16289.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@16290.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_839) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@16297.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_839) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@16298.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@16305.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_843) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@16306.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@16313.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@16314.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_851) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:136:11)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@16321.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_851) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@16322.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_902 & _T_910) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:136:11)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@16399.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_902 & _T_910) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@16400.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918 & _T_925) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:136:11)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@16422.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918 & _T_925) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@16423.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_932) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:136:11)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@16434.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_932) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@16435.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:136:11)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@16454.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@16455.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_29( // @[:freechips.rocketchip.system.LowRiscConfig.fir@16467.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16468.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16469.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
input [7:0] io_enq_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
input io_enq_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
output [7:0] io_deq_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
output io_deq_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@16470.4]
);
reg [63:0] _T_35_data [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
reg [63:0] _RAND_0;
wire [63:0] _T_35_data__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_data__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire [63:0] _T_35_data__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_data__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_data__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_data__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
reg [7:0] _T_35_strb [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
reg [31:0] _RAND_1;
wire [7:0] _T_35_strb__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_strb__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire [7:0] _T_35_strb__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_strb__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_strb__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_strb__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
reg _T_35_last [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
reg [31:0] _RAND_2;
wire _T_35_last__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_last__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_last__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_last__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_last__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
wire _T_35_last__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@16473.4]
reg [31:0] _RAND_3;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@16475.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16478.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16481.4]
wire _GEN_9; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@16512.6]
wire _GEN_14; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16507.4]
wire _GEN_13; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16507.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@16492.4]
wire _T_50; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@16496.4]
assign _T_35_data__T_52_addr = 1'h0;
assign _T_35_data__T_52_data = _T_35_data[_T_35_data__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
assign _T_35_data__T_48_data = io_enq_bits_data;
assign _T_35_data__T_48_addr = 1'h0;
assign _T_35_data__T_48_mask = 1'h1;
assign _T_35_data__T_48_en = _T_39 ? _GEN_9 : _T_42;
assign _T_35_strb__T_52_addr = 1'h0;
assign _T_35_strb__T_52_data = _T_35_strb[_T_35_strb__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
assign _T_35_strb__T_48_data = io_enq_bits_strb;
assign _T_35_strb__T_48_addr = 1'h0;
assign _T_35_strb__T_48_mask = 1'h1;
assign _T_35_strb__T_48_en = _T_39 ? _GEN_9 : _T_42;
assign _T_35_last__T_52_addr = 1'h0;
assign _T_35_last__T_52_data = _T_35_last[_T_35_last__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
assign _T_35_last__T_48_data = io_enq_bits_last;
assign _T_35_last__T_48_addr = 1'h0;
assign _T_35_last__T_48_mask = 1'h1;
assign _T_35_last__T_48_en = _T_39 ? _GEN_9 : _T_42;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@16475.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16478.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16481.4]
assign _GEN_9 = io_deq_ready ? 1'h0 : _T_42; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@16512.6]
assign _GEN_14 = _T_39 ? _GEN_9 : _T_42; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16507.4]
assign _GEN_13 = _T_39 ? 1'h0 : _T_45; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16507.4]
assign _T_49 = _GEN_14 != _GEN_13; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@16492.4]
assign _T_50 = _T_39 == 1'h0; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@16496.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@16499.4]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_50; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@16497.4 Decoupled.scala 241:40:freechips.rocketchip.system.LowRiscConfig.fir@16505.6]
assign io_deq_bits_data = _T_39 ? io_enq_bits_data : _T_35_data__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16503.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16510.6]
assign io_deq_bits_strb = _T_39 ? io_enq_bits_strb : _T_35_strb__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16502.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16509.6]
assign io_deq_bits_last = _T_39 ? io_enq_bits_last : _T_35_last__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16501.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16508.6]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_data[initvar] = _RAND_0[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_strb[initvar] = _RAND_1[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_last[initvar] = _RAND_2[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_37 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_data__T_48_en & _T_35_data__T_48_mask) begin
_T_35_data[_T_35_data__T_48_addr] <= _T_35_data__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
end
if(_T_35_strb__T_48_en & _T_35_strb__T_48_mask) begin
_T_35_strb[_T_35_strb__T_48_addr] <= _T_35_strb__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
end
if(_T_35_last__T_48_en & _T_35_last__T_48_mask) begin
_T_35_last[_T_35_last__T_48_addr] <= _T_35_last__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16472.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
if (_T_39) begin
if (io_deq_ready) begin
_T_37 <= 1'h0;
end else begin
_T_37 <= _T_42;
end
end else begin
_T_37 <= _T_42;
end
end
end
end
endmodule
module Queue_30( // @[:freechips.rocketchip.system.LowRiscConfig.fir@16523.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16524.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16525.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input [2:0] io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input [30:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input [8:0] io_enq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input io_enq_bits_wen, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [2:0] io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [30:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output io_deq_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [3:0] io_deq_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [2:0] io_deq_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [3:0] io_deq_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output [8:0] io_deq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
output io_deq_bits_wen // @[:freechips.rocketchip.system.LowRiscConfig.fir@16526.4]
);
reg [2:0] _T_35_id [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_id__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_id__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [2:0] _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_id__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_id__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_id__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [30:0] _T_35_addr [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_1;
wire [30:0] _T_35_addr__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_addr__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [30:0] _T_35_addr__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_addr__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_addr__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_addr__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [7:0] _T_35_len [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_2;
wire [7:0] _T_35_len__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_len__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [7:0] _T_35_len__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_len__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_len__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_len__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [2:0] _T_35_size [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_3;
wire [2:0] _T_35_size__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_size__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [2:0] _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_size__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_size__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_size__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [1:0] _T_35_burst [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_4;
wire [1:0] _T_35_burst__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_burst__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [1:0] _T_35_burst__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_burst__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_burst__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_burst__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg _T_35_lock [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_5;
wire _T_35_lock__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_lock__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_lock__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_lock__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_lock__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_lock__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [3:0] _T_35_cache [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_6;
wire [3:0] _T_35_cache__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_cache__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [3:0] _T_35_cache__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_cache__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_cache__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_cache__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [2:0] _T_35_prot [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_7;
wire [2:0] _T_35_prot__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_prot__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [2:0] _T_35_prot__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_prot__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_prot__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_prot__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [3:0] _T_35_qos [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_8;
wire [3:0] _T_35_qos__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_qos__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [3:0] _T_35_qos__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_qos__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_qos__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_qos__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [8:0] _T_35_user [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_9;
wire [8:0] _T_35_user__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_user__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire [8:0] _T_35_user__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_user__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_user__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_user__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg _T_35_wen [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg [31:0] _RAND_10;
wire _T_35_wen__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_wen__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_wen__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_wen__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_wen__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
wire _T_35_wen__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@16529.4]
reg [31:0] _RAND_11;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@16531.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16534.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16537.4]
wire _GEN_17; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@16592.6]
wire _GEN_30; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16579.4]
wire _GEN_29; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16579.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@16556.4]
wire _T_50; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@16560.4]
assign _T_35_id__T_52_addr = 1'h0;
assign _T_35_id__T_52_data = _T_35_id[_T_35_id__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_id__T_48_data = io_enq_bits_id;
assign _T_35_id__T_48_addr = 1'h0;
assign _T_35_id__T_48_mask = 1'h1;
assign _T_35_id__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_addr__T_52_addr = 1'h0;
assign _T_35_addr__T_52_data = _T_35_addr[_T_35_addr__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_addr__T_48_data = io_enq_bits_addr;
assign _T_35_addr__T_48_addr = 1'h0;
assign _T_35_addr__T_48_mask = 1'h1;
assign _T_35_addr__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_len__T_52_addr = 1'h0;
assign _T_35_len__T_52_data = _T_35_len[_T_35_len__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_len__T_48_data = io_enq_bits_len;
assign _T_35_len__T_48_addr = 1'h0;
assign _T_35_len__T_48_mask = 1'h1;
assign _T_35_len__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_size__T_52_addr = 1'h0;
assign _T_35_size__T_52_data = _T_35_size[_T_35_size__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_size__T_48_data = io_enq_bits_size;
assign _T_35_size__T_48_addr = 1'h0;
assign _T_35_size__T_48_mask = 1'h1;
assign _T_35_size__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_burst__T_52_addr = 1'h0;
assign _T_35_burst__T_52_data = _T_35_burst[_T_35_burst__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_burst__T_48_data = 2'h1;
assign _T_35_burst__T_48_addr = 1'h0;
assign _T_35_burst__T_48_mask = 1'h1;
assign _T_35_burst__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_lock__T_52_addr = 1'h0;
assign _T_35_lock__T_52_data = _T_35_lock[_T_35_lock__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_lock__T_48_data = 1'h0;
assign _T_35_lock__T_48_addr = 1'h0;
assign _T_35_lock__T_48_mask = 1'h1;
assign _T_35_lock__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_cache__T_52_addr = 1'h0;
assign _T_35_cache__T_52_data = _T_35_cache[_T_35_cache__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_cache__T_48_data = 4'h0;
assign _T_35_cache__T_48_addr = 1'h0;
assign _T_35_cache__T_48_mask = 1'h1;
assign _T_35_cache__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_prot__T_52_addr = 1'h0;
assign _T_35_prot__T_52_data = _T_35_prot[_T_35_prot__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_prot__T_48_data = 3'h1;
assign _T_35_prot__T_48_addr = 1'h0;
assign _T_35_prot__T_48_mask = 1'h1;
assign _T_35_prot__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_qos__T_52_addr = 1'h0;
assign _T_35_qos__T_52_data = _T_35_qos[_T_35_qos__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_qos__T_48_data = 4'h0;
assign _T_35_qos__T_48_addr = 1'h0;
assign _T_35_qos__T_48_mask = 1'h1;
assign _T_35_qos__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_user__T_52_addr = 1'h0;
assign _T_35_user__T_52_data = _T_35_user[_T_35_user__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_user__T_48_data = io_enq_bits_user;
assign _T_35_user__T_48_addr = 1'h0;
assign _T_35_user__T_48_mask = 1'h1;
assign _T_35_user__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_wen__T_52_addr = 1'h0;
assign _T_35_wen__T_52_data = _T_35_wen[_T_35_wen__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
assign _T_35_wen__T_48_data = io_enq_bits_wen;
assign _T_35_wen__T_48_addr = 1'h0;
assign _T_35_wen__T_48_mask = 1'h1;
assign _T_35_wen__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@16531.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16534.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16537.4]
assign _GEN_17 = io_deq_ready ? 1'h0 : _T_42; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@16592.6]
assign _GEN_30 = _T_39 ? _GEN_17 : _T_42; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16579.4]
assign _GEN_29 = _T_39 ? 1'h0 : _T_45; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@16579.4]
assign _T_49 = _GEN_30 != _GEN_29; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@16556.4]
assign _T_50 = _T_39 == 1'h0; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@16560.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@16563.4]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_50; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@16561.4 Decoupled.scala 241:40:freechips.rocketchip.system.LowRiscConfig.fir@16577.6]
assign io_deq_bits_id = _T_39 ? io_enq_bits_id : _T_35_id__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16575.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16590.6]
assign io_deq_bits_addr = _T_39 ? io_enq_bits_addr : _T_35_addr__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16574.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16589.6]
assign io_deq_bits_len = _T_39 ? io_enq_bits_len : _T_35_len__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16573.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16588.6]
assign io_deq_bits_size = _T_39 ? io_enq_bits_size : _T_35_size__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16572.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16587.6]
assign io_deq_bits_burst = _T_39 ? 2'h1 : _T_35_burst__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16571.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16586.6]
assign io_deq_bits_lock = _T_39 ? 1'h0 : _T_35_lock__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16570.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16585.6]
assign io_deq_bits_cache = _T_39 ? 4'h0 : _T_35_cache__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16569.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16584.6]
assign io_deq_bits_prot = _T_39 ? 3'h1 : _T_35_prot__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16568.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16583.6]
assign io_deq_bits_qos = _T_39 ? 4'h0 : _T_35_qos__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16567.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16582.6]
assign io_deq_bits_user = _T_39 ? io_enq_bits_user : _T_35_user__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16566.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16581.6]
assign io_deq_bits_wen = _T_39 ? io_enq_bits_wen : _T_35_wen__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@16565.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@16580.6]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_addr[initvar] = _RAND_1[30:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_len[initvar] = _RAND_2[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_size[initvar] = _RAND_3[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_burst[initvar] = _RAND_4[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_lock[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_cache[initvar] = _RAND_6[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_prot[initvar] = _RAND_7[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_8 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_qos[initvar] = _RAND_8[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_9 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_user[initvar] = _RAND_9[8:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_10 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_wen[initvar] = _RAND_10[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_37 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_48_en & _T_35_id__T_48_mask) begin
_T_35_id[_T_35_id__T_48_addr] <= _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_addr__T_48_en & _T_35_addr__T_48_mask) begin
_T_35_addr[_T_35_addr__T_48_addr] <= _T_35_addr__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_len__T_48_en & _T_35_len__T_48_mask) begin
_T_35_len[_T_35_len__T_48_addr] <= _T_35_len__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_size__T_48_en & _T_35_size__T_48_mask) begin
_T_35_size[_T_35_size__T_48_addr] <= _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_burst__T_48_en & _T_35_burst__T_48_mask) begin
_T_35_burst[_T_35_burst__T_48_addr] <= _T_35_burst__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_lock__T_48_en & _T_35_lock__T_48_mask) begin
_T_35_lock[_T_35_lock__T_48_addr] <= _T_35_lock__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_cache__T_48_en & _T_35_cache__T_48_mask) begin
_T_35_cache[_T_35_cache__T_48_addr] <= _T_35_cache__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_prot__T_48_en & _T_35_prot__T_48_mask) begin
_T_35_prot[_T_35_prot__T_48_addr] <= _T_35_prot__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_qos__T_48_en & _T_35_qos__T_48_mask) begin
_T_35_qos[_T_35_qos__T_48_addr] <= _T_35_qos__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_user__T_48_en & _T_35_user__T_48_mask) begin
_T_35_user[_T_35_user__T_48_addr] <= _T_35_user__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if(_T_35_wen__T_48_en & _T_35_wen__T_48_mask) begin
_T_35_wen[_T_35_wen__T_48_addr] <= _T_35_wen__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@16528.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
if (_T_39) begin
if (io_deq_ready) begin
_T_37 <= 1'h0;
end else begin
_T_37 <= _T_42;
end
end else begin
_T_37 <= _T_42;
end
end
end
end
endmodule
module TLToAXI4( // @[:freechips.rocketchip.system.LowRiscConfig.fir@16603.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16604.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16605.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [30:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [30:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [8:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [2:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [8:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [30:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output [8:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [2:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input [8:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@16606.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [30:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire [7:0] Queue_io_enq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire [7:0] Queue_io_deq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [2:0] Queue_1_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [30:0] Queue_1_io_enq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [7:0] Queue_1_io_enq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [8:0] Queue_1_io_enq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_enq_bits_wen; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [2:0] Queue_1_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [30:0] Queue_1_io_deq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [7:0] Queue_1_io_deq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [1:0] Queue_1_io_deq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_deq_bits_lock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [3:0] Queue_1_io_deq_bits_cache; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [2:0] Queue_1_io_deq_bits_prot; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [3:0] Queue_1_io_deq_bits_qos; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire [8:0] Queue_1_io_deq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire Queue_1_io_deq_bits_wen; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
wire _T_367; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@16715.4]
wire _T_368; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@16716.4]
reg _T_514; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@16943.4]
reg [31:0] _RAND_0;
reg _T_545; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@16985.4]
reg [31:0] _RAND_1;
reg _T_733; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@17239.4]
reg [31:0] _RAND_2;
reg _T_702; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@17197.4]
reg [31:0] _RAND_3;
reg _T_671; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@17155.4]
reg [31:0] _RAND_4;
reg _T_640; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@17113.4]
reg [31:0] _RAND_5;
reg [3:0] _T_608; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@17070.4]
reg [31:0] _RAND_6;
wire _T_611; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.LowRiscConfig.fir@17072.4]
wire _T_635; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.LowRiscConfig.fir@17108.4]
reg _T_610; // @[ToAXI4.scala 226:24:freechips.rocketchip.system.LowRiscConfig.fir@17071.4]
reg [31:0] _RAND_7;
wire _T_634; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.LowRiscConfig.fir@17107.4]
wire _T_636; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.LowRiscConfig.fir@17109.4]
wire _T_637; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.LowRiscConfig.fir@17110.4]
wire _T_638; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.LowRiscConfig.fir@17111.4]
reg [3:0] _T_576; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@17027.4]
reg [31:0] _RAND_8;
wire _T_579; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.LowRiscConfig.fir@17029.4]
wire _T_603; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.LowRiscConfig.fir@17065.4]
reg _T_578; // @[ToAXI4.scala 226:24:freechips.rocketchip.system.LowRiscConfig.fir@17028.4]
reg [31:0] _RAND_9;
wire _T_602; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.LowRiscConfig.fir@17064.4]
wire _T_604; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.LowRiscConfig.fir@17066.4]
wire _T_605; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.LowRiscConfig.fir@17067.4]
wire _T_606; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.LowRiscConfig.fir@17068.4]
wire _GEN_35; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_36; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_37; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_38; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_39; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_40; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_41; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_42; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_43; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_44; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_45; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_46; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_47; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_48; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_49; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_50; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _GEN_51; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
reg [4:0] _T_379; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@16726.4]
reg [31:0] _RAND_10;
wire _T_383; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16730.4]
wire _T_449; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
wire _T_450; // @[ToAXI4.scala 177:21:freechips.rocketchip.system.LowRiscConfig.fir@16847.4]
reg _T_437; // @[ToAXI4.scala 160:30:freechips.rocketchip.system.LowRiscConfig.fir@16822.4]
reg [31:0] _RAND_11;
wire _T_410_ready; // @[ToAXI4.scala 146:25:freechips.rocketchip.system.LowRiscConfig.fir@16764.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@16798.4]
wire _T_451; // @[ToAXI4.scala 177:52:freechips.rocketchip.system.LowRiscConfig.fir@16848.4]
wire _T_413_ready; // @[ToAXI4.scala 147:23:freechips.rocketchip.system.LowRiscConfig.fir@16766.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@16775.4]
wire _T_452; // @[ToAXI4.scala 177:70:freechips.rocketchip.system.LowRiscConfig.fir@16849.4]
wire _T_453; // @[ToAXI4.scala 177:34:freechips.rocketchip.system.LowRiscConfig.fir@16850.4]
wire _T_454; // @[ToAXI4.scala 177:28:freechips.rocketchip.system.LowRiscConfig.fir@16851.4]
wire _T_369; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16717.4]
wire [22:0] _T_371; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@16719.4]
wire [7:0] _T_372; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@16720.4]
wire [7:0] _T_373; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@16721.4]
wire [4:0] _T_374; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@16722.4]
wire [4:0] _T_377; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@16725.4]
wire [5:0] _T_380; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16727.4]
wire [5:0] _T_381; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16728.4]
wire [4:0] _T_382; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16729.4]
wire _T_384; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@16731.4]
wire _T_385; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@16732.4]
wire _T_386; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@16733.4]
wire [8:0] _GEN_63; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@16758.4]
wire [8:0] _T_400; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@16758.4]
wire [8:0] _GEN_64; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.LowRiscConfig.fir@16759.4]
wire [4:0] _T_402; // @[ToAXI4.scala 137:50:freechips.rocketchip.system.LowRiscConfig.fir@16760.4]
wire [3:0] _T_403; // @[ToAXI4.scala 138:50:freechips.rocketchip.system.LowRiscConfig.fir@16761.4]
wire [4:0] _T_404; // @[ToAXI4.scala 141:50:freechips.rocketchip.system.LowRiscConfig.fir@16762.4]
wire [3:0] _T_405; // @[ToAXI4.scala 142:50:freechips.rocketchip.system.LowRiscConfig.fir@16763.4]
wire _T_428_bits_wen; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@16799.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@16800.4]
wire _T_432; // @[ToAXI4.scala 154:42:freechips.rocketchip.system.LowRiscConfig.fir@16815.4]
wire _T_428_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@16799.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@16811.4]
wire _T_439; // @[ToAXI4.scala 161:38:freechips.rocketchip.system.LowRiscConfig.fir@16825.6]
wire [2:0] _GEN_10; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_11; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_12; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_13; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_14; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_15; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_16; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_17; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_18; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_19; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_20; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_21; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_22; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_23; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_24; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_25; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [2:0] _GEN_26; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
wire [25:0] _T_442; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@16832.4]
wire [10:0] _T_443; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@16833.4]
wire [10:0] _T_444; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@16834.4]
wire _T_446; // @[ToAXI4.scala 168:31:freechips.rocketchip.system.LowRiscConfig.fir@16837.4]
wire [3:0] _T_447; // @[ToAXI4.scala 168:23:freechips.rocketchip.system.LowRiscConfig.fir@16838.4]
wire _T_456; // @[ToAXI4.scala 178:31:freechips.rocketchip.system.LowRiscConfig.fir@16854.4]
wire _T_457; // @[ToAXI4.scala 178:61:freechips.rocketchip.system.LowRiscConfig.fir@16855.4]
wire _T_458; // @[ToAXI4.scala 178:69:freechips.rocketchip.system.LowRiscConfig.fir@16856.4]
wire _T_459; // @[ToAXI4.scala 178:51:freechips.rocketchip.system.LowRiscConfig.fir@16857.4]
wire _T_460; // @[ToAXI4.scala 178:45:freechips.rocketchip.system.LowRiscConfig.fir@16858.4]
wire _T_463; // @[ToAXI4.scala 180:43:freechips.rocketchip.system.LowRiscConfig.fir@16862.4]
reg _T_467; // @[ToAXI4.scala 187:30:freechips.rocketchip.system.LowRiscConfig.fir@16869.4]
reg [31:0] _RAND_12;
wire _T_468; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16870.4]
wire _T_469; // @[ToAXI4.scala 188:42:freechips.rocketchip.system.LowRiscConfig.fir@16872.6]
wire _T_470; // @[ToAXI4.scala 190:32:freechips.rocketchip.system.LowRiscConfig.fir@16875.4]
wire _T_471; // @[ToAXI4.scala 193:36:freechips.rocketchip.system.LowRiscConfig.fir@16877.4]
wire _T_473; // @[ToAXI4.scala 194:24:freechips.rocketchip.system.LowRiscConfig.fir@16880.4]
reg _T_475; // @[ToAXI4.scala 199:28:freechips.rocketchip.system.LowRiscConfig.fir@16882.4]
reg [31:0] _RAND_13;
wire _T_477; // @[ToAXI4.scala 201:39:freechips.rocketchip.system.LowRiscConfig.fir@16887.4]
reg _T_479; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@16888.4]
reg [31:0] _RAND_14;
wire _GEN_54; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@16889.4]
wire _T_481; // @[ToAXI4.scala 202:39:freechips.rocketchip.system.LowRiscConfig.fir@16893.4]
wire _T_482; // @[ToAXI4.scala 203:39:freechips.rocketchip.system.LowRiscConfig.fir@16894.4]
wire _T_483; // @[ToAXI4.scala 205:100:freechips.rocketchip.system.LowRiscConfig.fir@16895.4]
wire [7:0] _T_490; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@16920.4]
wire _T_492; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16922.4]
wire _T_493; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16923.4]
wire _T_494; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16924.4]
wire _T_495; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16925.4]
wire _T_496; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16926.4]
wire _T_497; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16927.4]
wire _T_498; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16928.4]
wire _T_499; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16929.4]
wire [2:0] _T_500; // @[ToAXI4.scala 214:31:freechips.rocketchip.system.LowRiscConfig.fir@16930.4]
wire [7:0] _T_502; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@16932.4]
wire _T_504; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16934.4]
wire _T_505; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16935.4]
wire _T_506; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16936.4]
wire _T_507; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16937.4]
wire _T_508; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16938.4]
wire _T_509; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16939.4]
wire _T_510; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16940.4]
wire _T_511; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16941.4]
wire _T_512; // @[ToAXI4.scala 215:23:freechips.rocketchip.system.LowRiscConfig.fir@16942.4]
wire _T_518; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16946.4]
wire _T_519; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@16947.4]
wire _T_520; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@16948.4]
wire _T_521; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16949.4]
wire _T_522; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@16950.4]
wire _T_524; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@16952.4]
wire [1:0] _T_525; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16953.4]
wire [1:0] _T_526; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16954.4]
wire _T_527; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16955.4]
wire _T_528; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@16957.4]
wire _T_530; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@16959.4]
wire _T_532; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@16961.4]
wire _T_533; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@16962.4]
wire _T_534; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@16967.4]
wire _T_535; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@16968.4]
wire _T_536; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@16969.4]
wire _T_538; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@16971.4]
wire _T_539; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@16972.4]
wire _T_550; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@16989.4]
wire _T_551; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@16990.4]
wire _T_553; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@16992.4]
wire _T_555; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@16994.4]
wire [1:0] _T_556; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16995.4]
wire [1:0] _T_557; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16996.4]
wire _T_558; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16997.4]
wire _T_559; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@16999.4]
wire _T_561; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17001.4]
wire _T_563; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17003.4]
wire _T_564; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17004.4]
wire _T_565; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17009.4]
wire _T_566; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17010.4]
wire _T_567; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17011.4]
wire _T_569; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17013.4]
wire _T_570; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17014.4]
wire _T_581; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17031.4]
wire _T_582; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17032.4]
wire _T_584; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17034.4]
wire [3:0] _GEN_65; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17035.4]
wire [3:0] _T_586; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17036.4]
wire [3:0] _GEN_66; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17037.4]
wire [4:0] _T_587; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17037.4]
wire [4:0] _T_588; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17038.4]
wire [3:0] _T_589; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17039.4]
wire _T_590; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17041.4]
wire _T_591; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.LowRiscConfig.fir@17042.4]
wire _T_592; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17043.4]
wire _T_594; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17045.4]
wire _T_595; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17046.4]
wire _T_596; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17051.4]
wire _T_597; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17052.4]
wire _T_598; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17053.4]
wire _T_600; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17055.4]
wire _T_601; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17056.4]
wire _T_613; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17074.4]
wire _T_614; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17075.4]
wire _T_616; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17077.4]
wire [3:0] _GEN_67; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17078.4]
wire [3:0] _T_618; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17079.4]
wire [3:0] _GEN_68; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17080.4]
wire [4:0] _T_619; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17080.4]
wire [4:0] _T_620; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17081.4]
wire [3:0] _T_621; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17082.4]
wire _T_622; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17084.4]
wire _T_623; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.LowRiscConfig.fir@17085.4]
wire _T_624; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17086.4]
wire _T_626; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17088.4]
wire _T_627; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17089.4]
wire _T_628; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17094.4]
wire _T_629; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17095.4]
wire _T_630; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17096.4]
wire _T_632; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17098.4]
wire _T_633; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17099.4]
wire _T_645; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17117.4]
wire _T_646; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17118.4]
wire _T_648; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17120.4]
wire _T_650; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17122.4]
wire [1:0] _T_651; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17123.4]
wire [1:0] _T_652; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17124.4]
wire _T_653; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17125.4]
wire _T_654; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17127.4]
wire _T_656; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17129.4]
wire _T_658; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17131.4]
wire _T_659; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17132.4]
wire _T_660; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17137.4]
wire _T_661; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17138.4]
wire _T_662; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17139.4]
wire _T_664; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17141.4]
wire _T_665; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17142.4]
wire _T_676; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17159.4]
wire _T_677; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17160.4]
wire _T_679; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17162.4]
wire _T_681; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17164.4]
wire [1:0] _T_682; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17165.4]
wire [1:0] _T_683; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17166.4]
wire _T_684; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17167.4]
wire _T_685; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17169.4]
wire _T_687; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17171.4]
wire _T_689; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17173.4]
wire _T_690; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17174.4]
wire _T_691; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17179.4]
wire _T_692; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17180.4]
wire _T_693; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17181.4]
wire _T_695; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17183.4]
wire _T_696; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17184.4]
wire _T_707; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17201.4]
wire _T_708; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17202.4]
wire _T_710; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17204.4]
wire _T_712; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17206.4]
wire [1:0] _T_713; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17207.4]
wire [1:0] _T_714; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17208.4]
wire _T_715; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17209.4]
wire _T_716; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17211.4]
wire _T_718; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17213.4]
wire _T_720; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17215.4]
wire _T_721; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17216.4]
wire _T_722; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17221.4]
wire _T_723; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17222.4]
wire _T_724; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17223.4]
wire _T_726; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17225.4]
wire _T_727; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17226.4]
wire _T_738; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17243.4]
wire _T_739; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17244.4]
wire _T_741; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17246.4]
wire _T_743; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17248.4]
wire [1:0] _T_744; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17249.4]
wire [1:0] _T_745; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17250.4]
wire _T_746; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17251.4]
wire _T_747; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17253.4]
wire _T_749; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17255.4]
wire _T_751; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17257.4]
wire _T_752; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17258.4]
wire _T_753; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17263.4]
wire _T_754; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17264.4]
wire _T_755; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17265.4]
wire _T_757; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17267.4]
wire _T_758; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17268.4]
TLMonitor_4 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@16613.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_29 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16768.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_strb(Queue_io_enq_bits_strb),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_strb(Queue_io_deq_bits_strb),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
Queue_30 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@16783.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_id(Queue_1_io_enq_bits_id),
.io_enq_bits_addr(Queue_1_io_enq_bits_addr),
.io_enq_bits_len(Queue_1_io_enq_bits_len),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_user(Queue_1_io_enq_bits_user),
.io_enq_bits_wen(Queue_1_io_enq_bits_wen),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_id(Queue_1_io_deq_bits_id),
.io_deq_bits_addr(Queue_1_io_deq_bits_addr),
.io_deq_bits_len(Queue_1_io_deq_bits_len),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_burst(Queue_1_io_deq_bits_burst),
.io_deq_bits_lock(Queue_1_io_deq_bits_lock),
.io_deq_bits_cache(Queue_1_io_deq_bits_cache),
.io_deq_bits_prot(Queue_1_io_deq_bits_prot),
.io_deq_bits_qos(Queue_1_io_deq_bits_qos),
.io_deq_bits_user(Queue_1_io_deq_bits_user),
.io_deq_bits_wen(Queue_1_io_deq_bits_wen)
);
assign _T_367 = auto_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@16715.4]
assign _T_368 = _T_367 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@16716.4]
assign _T_611 = _T_608 == 4'h0; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.LowRiscConfig.fir@17072.4]
assign _T_635 = _T_611 == 1'h0; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.LowRiscConfig.fir@17108.4]
assign _T_634 = _T_610 != _T_368; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.LowRiscConfig.fir@17107.4]
assign _T_636 = _T_635 & _T_634; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.LowRiscConfig.fir@17109.4]
assign _T_637 = _T_608 == 4'h8; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.LowRiscConfig.fir@17110.4]
assign _T_638 = _T_636 | _T_637; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.LowRiscConfig.fir@17111.4]
assign _T_579 = _T_576 == 4'h0; // @[ToAXI4.scala 227:26:freechips.rocketchip.system.LowRiscConfig.fir@17029.4]
assign _T_603 = _T_579 == 1'h0; // @[ToAXI4.scala 239:15:freechips.rocketchip.system.LowRiscConfig.fir@17065.4]
assign _T_602 = _T_578 != _T_368; // @[ToAXI4.scala 238:50:freechips.rocketchip.system.LowRiscConfig.fir@17064.4]
assign _T_604 = _T_603 & _T_602; // @[ToAXI4.scala 239:21:freechips.rocketchip.system.LowRiscConfig.fir@17066.4]
assign _T_605 = _T_576 == 4'h8; // @[ToAXI4.scala 239:44:freechips.rocketchip.system.LowRiscConfig.fir@17067.4]
assign _T_606 = _T_604 | _T_605; // @[ToAXI4.scala 239:34:freechips.rocketchip.system.LowRiscConfig.fir@17068.4]
assign _GEN_35 = 5'h8 == auto_in_a_bits_source ? _T_638 : _T_606; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_36 = 5'h9 == auto_in_a_bits_source ? _T_638 : _GEN_35; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_37 = 5'ha == auto_in_a_bits_source ? _T_638 : _GEN_36; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_38 = 5'hb == auto_in_a_bits_source ? _T_638 : _GEN_37; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_39 = 5'hc == auto_in_a_bits_source ? _T_638 : _GEN_38; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_40 = 5'hd == auto_in_a_bits_source ? _T_638 : _GEN_39; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_41 = 5'he == auto_in_a_bits_source ? _T_638 : _GEN_40; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_42 = 5'hf == auto_in_a_bits_source ? _T_638 : _GEN_41; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_43 = 5'h10 == auto_in_a_bits_source ? _T_640 : _GEN_42; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_44 = 5'h11 == auto_in_a_bits_source ? _T_671 : _GEN_43; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_45 = 5'h12 == auto_in_a_bits_source ? _T_702 : _GEN_44; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_46 = 5'h13 == auto_in_a_bits_source ? _T_733 : _GEN_45; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_47 = 5'h14 == auto_in_a_bits_source ? _T_545 : _GEN_46; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_48 = 5'h15 == auto_in_a_bits_source ? 1'h0 : _GEN_47; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_49 = 5'h16 == auto_in_a_bits_source ? 1'h0 : _GEN_48; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_50 = 5'h17 == auto_in_a_bits_source ? 1'h0 : _GEN_49; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _GEN_51 = 5'h18 == auto_in_a_bits_source ? _T_514 : _GEN_50; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _T_383 = _T_379 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@16730.4]
assign _T_449 = _GEN_51 & _T_383; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@16846.4]
assign _T_450 = _T_449 == 1'h0; // @[ToAXI4.scala 177:21:freechips.rocketchip.system.LowRiscConfig.fir@16847.4]
assign _T_410_ready = Queue_1_io_enq_ready; // @[ToAXI4.scala 146:25:freechips.rocketchip.system.LowRiscConfig.fir@16764.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@16798.4]
assign _T_451 = _T_437 | _T_410_ready; // @[ToAXI4.scala 177:52:freechips.rocketchip.system.LowRiscConfig.fir@16848.4]
assign _T_413_ready = Queue_io_enq_ready; // @[ToAXI4.scala 147:23:freechips.rocketchip.system.LowRiscConfig.fir@16766.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@16775.4]
assign _T_452 = _T_451 & _T_413_ready; // @[ToAXI4.scala 177:70:freechips.rocketchip.system.LowRiscConfig.fir@16849.4]
assign _T_453 = _T_368 ? _T_452 : _T_410_ready; // @[ToAXI4.scala 177:34:freechips.rocketchip.system.LowRiscConfig.fir@16850.4]
assign _T_454 = _T_450 & _T_453; // @[ToAXI4.scala 177:28:freechips.rocketchip.system.LowRiscConfig.fir@16851.4]
assign _T_369 = _T_454 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16717.4]
assign _T_371 = 23'hff << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@16719.4]
assign _T_372 = _T_371[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@16720.4]
assign _T_373 = ~ _T_372; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@16721.4]
assign _T_374 = _T_373[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@16722.4]
assign _T_377 = _T_368 ? _T_374 : 5'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@16725.4]
assign _T_380 = _T_379 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16727.4]
assign _T_381 = $unsigned(_T_380); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16728.4]
assign _T_382 = _T_381[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@16729.4]
assign _T_384 = _T_379 == 5'h1; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@16731.4]
assign _T_385 = _T_377 == 5'h0; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@16732.4]
assign _T_386 = _T_384 | _T_385; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@16733.4]
assign _GEN_63 = {{5'd0}, auto_in_a_bits_size}; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@16758.4]
assign _T_400 = _GEN_63 << 5; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@16758.4]
assign _GEN_64 = {{4'd0}, auto_in_a_bits_source}; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.LowRiscConfig.fir@16759.4]
assign _T_402 = auto_out_r_bits_user[4:0]; // @[ToAXI4.scala 137:50:freechips.rocketchip.system.LowRiscConfig.fir@16760.4]
assign _T_403 = auto_out_r_bits_user[8:5]; // @[ToAXI4.scala 138:50:freechips.rocketchip.system.LowRiscConfig.fir@16761.4]
assign _T_404 = auto_out_b_bits_user[4:0]; // @[ToAXI4.scala 141:50:freechips.rocketchip.system.LowRiscConfig.fir@16762.4]
assign _T_405 = auto_out_b_bits_user[8:5]; // @[ToAXI4.scala 142:50:freechips.rocketchip.system.LowRiscConfig.fir@16763.4]
assign _T_428_bits_wen = Queue_1_io_deq_bits_wen; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@16799.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@16800.4]
assign _T_432 = _T_428_bits_wen == 1'h0; // @[ToAXI4.scala 154:42:freechips.rocketchip.system.LowRiscConfig.fir@16815.4]
assign _T_428_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@16799.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@16811.4]
assign _T_439 = _T_386 == 1'h0; // @[ToAXI4.scala 161:38:freechips.rocketchip.system.LowRiscConfig.fir@16825.6]
assign _GEN_10 = 5'h8 == auto_in_a_bits_source ? 3'h3 : 3'h2; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_11 = 5'h9 == auto_in_a_bits_source ? 3'h3 : _GEN_10; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_12 = 5'ha == auto_in_a_bits_source ? 3'h3 : _GEN_11; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_13 = 5'hb == auto_in_a_bits_source ? 3'h3 : _GEN_12; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_14 = 5'hc == auto_in_a_bits_source ? 3'h3 : _GEN_13; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_15 = 5'hd == auto_in_a_bits_source ? 3'h3 : _GEN_14; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_16 = 5'he == auto_in_a_bits_source ? 3'h3 : _GEN_15; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_17 = 5'hf == auto_in_a_bits_source ? 3'h3 : _GEN_16; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_18 = 5'h10 == auto_in_a_bits_source ? 3'h4 : _GEN_17; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_19 = 5'h11 == auto_in_a_bits_source ? 3'h5 : _GEN_18; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_20 = 5'h12 == auto_in_a_bits_source ? 3'h6 : _GEN_19; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_21 = 5'h13 == auto_in_a_bits_source ? 3'h7 : _GEN_20; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_22 = 5'h14 == auto_in_a_bits_source ? 3'h1 : _GEN_21; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_23 = 5'h15 == auto_in_a_bits_source ? 3'h0 : _GEN_22; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_24 = 5'h16 == auto_in_a_bits_source ? 3'h0 : _GEN_23; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_25 = 5'h17 == auto_in_a_bits_source ? 3'h0 : _GEN_24; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _GEN_26 = 5'h18 == auto_in_a_bits_source ? 3'h0 : _GEN_25; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@16829.4]
assign _T_442 = 26'h7ff << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@16832.4]
assign _T_443 = _T_442[10:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@16833.4]
assign _T_444 = ~ _T_443; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@16834.4]
assign _T_446 = auto_in_a_bits_size >= 4'h3; // @[ToAXI4.scala 168:31:freechips.rocketchip.system.LowRiscConfig.fir@16837.4]
assign _T_447 = _T_446 ? 4'h3 : auto_in_a_bits_size; // @[ToAXI4.scala 168:23:freechips.rocketchip.system.LowRiscConfig.fir@16838.4]
assign _T_456 = _T_450 & auto_in_a_valid; // @[ToAXI4.scala 178:31:freechips.rocketchip.system.LowRiscConfig.fir@16854.4]
assign _T_457 = _T_437 == 1'h0; // @[ToAXI4.scala 178:61:freechips.rocketchip.system.LowRiscConfig.fir@16855.4]
assign _T_458 = _T_457 & _T_413_ready; // @[ToAXI4.scala 178:69:freechips.rocketchip.system.LowRiscConfig.fir@16856.4]
assign _T_459 = _T_368 ? _T_458 : 1'h1; // @[ToAXI4.scala 178:51:freechips.rocketchip.system.LowRiscConfig.fir@16857.4]
assign _T_460 = _T_456 & _T_459; // @[ToAXI4.scala 178:45:freechips.rocketchip.system.LowRiscConfig.fir@16858.4]
assign _T_463 = _T_456 & _T_368; // @[ToAXI4.scala 180:43:freechips.rocketchip.system.LowRiscConfig.fir@16862.4]
assign _T_468 = auto_in_d_ready & auto_out_r_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16870.4]
assign _T_469 = auto_out_r_bits_last == 1'h0; // @[ToAXI4.scala 188:42:freechips.rocketchip.system.LowRiscConfig.fir@16872.6]
assign _T_470 = auto_out_r_valid | _T_467; // @[ToAXI4.scala 190:32:freechips.rocketchip.system.LowRiscConfig.fir@16875.4]
assign _T_471 = _T_470 == 1'h0; // @[ToAXI4.scala 193:36:freechips.rocketchip.system.LowRiscConfig.fir@16877.4]
assign _T_473 = _T_470 ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala 194:24:freechips.rocketchip.system.LowRiscConfig.fir@16880.4]
assign _T_477 = auto_out_r_bits_resp == 2'h3; // @[ToAXI4.scala 201:39:freechips.rocketchip.system.LowRiscConfig.fir@16887.4]
assign _GEN_54 = _T_475 ? _T_477 : _T_479; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@16889.4]
assign _T_481 = auto_out_r_bits_resp != 2'h0; // @[ToAXI4.scala 202:39:freechips.rocketchip.system.LowRiscConfig.fir@16893.4]
assign _T_482 = auto_out_b_bits_resp != 2'h0; // @[ToAXI4.scala 203:39:freechips.rocketchip.system.LowRiscConfig.fir@16894.4]
assign _T_483 = _T_481 | _GEN_54; // @[ToAXI4.scala 205:100:freechips.rocketchip.system.LowRiscConfig.fir@16895.4]
assign _T_490 = 8'h1 << _GEN_26; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@16920.4]
assign _T_492 = _T_490[0]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16922.4]
assign _T_493 = _T_490[1]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16923.4]
assign _T_494 = _T_490[2]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16924.4]
assign _T_495 = _T_490[3]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16925.4]
assign _T_496 = _T_490[4]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16926.4]
assign _T_497 = _T_490[5]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16927.4]
assign _T_498 = _T_490[6]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16928.4]
assign _T_499 = _T_490[7]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@16929.4]
assign _T_500 = _T_470 ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala 214:31:freechips.rocketchip.system.LowRiscConfig.fir@16930.4]
assign _T_502 = 8'h1 << _T_500; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@16932.4]
assign _T_504 = _T_502[0]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16934.4]
assign _T_505 = _T_502[1]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16935.4]
assign _T_506 = _T_502[2]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16936.4]
assign _T_507 = _T_502[3]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16937.4]
assign _T_508 = _T_502[4]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16938.4]
assign _T_509 = _T_502[5]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16939.4]
assign _T_510 = _T_502[6]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16940.4]
assign _T_511 = _T_502[7]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@16941.4]
assign _T_512 = _T_470 ? auto_out_r_bits_last : 1'h1; // @[ToAXI4.scala 215:23:freechips.rocketchip.system.LowRiscConfig.fir@16942.4]
assign _T_518 = _T_410_ready & _T_460; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16946.4]
assign _T_519 = _T_492 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@16947.4]
assign _T_520 = _T_504 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@16948.4]
assign _T_521 = auto_in_d_ready & _T_473; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@16949.4]
assign _T_522 = _T_520 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@16950.4]
assign _T_524 = _T_514 + _T_519; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@16952.4]
assign _T_525 = _T_524 - _T_522; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16953.4]
assign _T_526 = $unsigned(_T_525); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16954.4]
assign _T_527 = _T_526[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16955.4]
assign _T_528 = _T_522 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@16957.4]
assign _T_530 = _T_528 | _T_514; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@16959.4]
assign _T_532 = _T_530 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@16961.4]
assign _T_533 = _T_532 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@16962.4]
assign _T_534 = _T_519 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@16967.4]
assign _T_535 = _T_514 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@16968.4]
assign _T_536 = _T_534 | _T_535; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@16969.4]
assign _T_538 = _T_536 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@16971.4]
assign _T_539 = _T_538 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@16972.4]
assign _T_550 = _T_493 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@16989.4]
assign _T_551 = _T_505 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@16990.4]
assign _T_553 = _T_551 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@16992.4]
assign _T_555 = _T_545 + _T_550; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@16994.4]
assign _T_556 = _T_555 - _T_553; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16995.4]
assign _T_557 = $unsigned(_T_556); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16996.4]
assign _T_558 = _T_557[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@16997.4]
assign _T_559 = _T_553 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@16999.4]
assign _T_561 = _T_559 | _T_545; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17001.4]
assign _T_563 = _T_561 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17003.4]
assign _T_564 = _T_563 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17004.4]
assign _T_565 = _T_550 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17009.4]
assign _T_566 = _T_545 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17010.4]
assign _T_567 = _T_565 | _T_566; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17011.4]
assign _T_569 = _T_567 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17013.4]
assign _T_570 = _T_569 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17014.4]
assign _T_581 = _T_494 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17031.4]
assign _T_582 = _T_506 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17032.4]
assign _T_584 = _T_582 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17034.4]
assign _GEN_65 = {{3'd0}, _T_581}; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17035.4]
assign _T_586 = _T_576 + _GEN_65; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17036.4]
assign _GEN_66 = {{3'd0}, _T_584}; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17037.4]
assign _T_587 = _T_586 - _GEN_66; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17037.4]
assign _T_588 = $unsigned(_T_587); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17038.4]
assign _T_589 = _T_588[3:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17039.4]
assign _T_590 = _T_584 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17041.4]
assign _T_591 = _T_576 != 4'h0; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.LowRiscConfig.fir@17042.4]
assign _T_592 = _T_590 | _T_591; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17043.4]
assign _T_594 = _T_592 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17045.4]
assign _T_595 = _T_594 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17046.4]
assign _T_596 = _T_581 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17051.4]
assign _T_597 = _T_576 != 4'h8; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17052.4]
assign _T_598 = _T_596 | _T_597; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17053.4]
assign _T_600 = _T_598 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17055.4]
assign _T_601 = _T_600 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17056.4]
assign _T_613 = _T_495 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17074.4]
assign _T_614 = _T_507 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17075.4]
assign _T_616 = _T_614 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17077.4]
assign _GEN_67 = {{3'd0}, _T_613}; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17078.4]
assign _T_618 = _T_608 + _GEN_67; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17079.4]
assign _GEN_68 = {{3'd0}, _T_616}; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17080.4]
assign _T_619 = _T_618 - _GEN_68; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17080.4]
assign _T_620 = $unsigned(_T_619); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17081.4]
assign _T_621 = _T_620[3:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17082.4]
assign _T_622 = _T_616 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17084.4]
assign _T_623 = _T_608 != 4'h0; // @[ToAXI4.scala 233:31:freechips.rocketchip.system.LowRiscConfig.fir@17085.4]
assign _T_624 = _T_622 | _T_623; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17086.4]
assign _T_626 = _T_624 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17088.4]
assign _T_627 = _T_626 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17089.4]
assign _T_628 = _T_613 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17094.4]
assign _T_629 = _T_608 != 4'h8; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17095.4]
assign _T_630 = _T_628 | _T_629; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17096.4]
assign _T_632 = _T_630 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17098.4]
assign _T_633 = _T_632 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17099.4]
assign _T_645 = _T_496 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17117.4]
assign _T_646 = _T_508 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17118.4]
assign _T_648 = _T_646 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17120.4]
assign _T_650 = _T_640 + _T_645; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17122.4]
assign _T_651 = _T_650 - _T_648; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17123.4]
assign _T_652 = $unsigned(_T_651); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17124.4]
assign _T_653 = _T_652[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17125.4]
assign _T_654 = _T_648 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17127.4]
assign _T_656 = _T_654 | _T_640; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17129.4]
assign _T_658 = _T_656 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17131.4]
assign _T_659 = _T_658 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17132.4]
assign _T_660 = _T_645 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17137.4]
assign _T_661 = _T_640 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17138.4]
assign _T_662 = _T_660 | _T_661; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17139.4]
assign _T_664 = _T_662 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17141.4]
assign _T_665 = _T_664 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17142.4]
assign _T_676 = _T_497 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17159.4]
assign _T_677 = _T_509 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17160.4]
assign _T_679 = _T_677 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17162.4]
assign _T_681 = _T_671 + _T_676; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17164.4]
assign _T_682 = _T_681 - _T_679; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17165.4]
assign _T_683 = $unsigned(_T_682); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17166.4]
assign _T_684 = _T_683[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17167.4]
assign _T_685 = _T_679 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17169.4]
assign _T_687 = _T_685 | _T_671; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17171.4]
assign _T_689 = _T_687 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17173.4]
assign _T_690 = _T_689 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17174.4]
assign _T_691 = _T_676 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17179.4]
assign _T_692 = _T_671 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17180.4]
assign _T_693 = _T_691 | _T_692; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17181.4]
assign _T_695 = _T_693 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17183.4]
assign _T_696 = _T_695 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17184.4]
assign _T_707 = _T_498 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17201.4]
assign _T_708 = _T_510 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17202.4]
assign _T_710 = _T_708 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17204.4]
assign _T_712 = _T_702 + _T_707; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17206.4]
assign _T_713 = _T_712 - _T_710; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17207.4]
assign _T_714 = $unsigned(_T_713); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17208.4]
assign _T_715 = _T_714[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17209.4]
assign _T_716 = _T_710 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17211.4]
assign _T_718 = _T_716 | _T_702; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17213.4]
assign _T_720 = _T_718 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17215.4]
assign _T_721 = _T_720 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17216.4]
assign _T_722 = _T_707 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17221.4]
assign _T_723 = _T_702 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17222.4]
assign _T_724 = _T_722 | _T_723; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17223.4]
assign _T_726 = _T_724 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17225.4]
assign _T_727 = _T_726 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17226.4]
assign _T_738 = _T_499 & _T_518; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@17243.4]
assign _T_739 = _T_511 & _T_512; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@17244.4]
assign _T_741 = _T_739 & _T_521; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@17246.4]
assign _T_743 = _T_733 + _T_738; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@17248.4]
assign _T_744 = _T_743 - _T_741; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17249.4]
assign _T_745 = $unsigned(_T_744); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17250.4]
assign _T_746 = _T_745[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@17251.4]
assign _T_747 = _T_741 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@17253.4]
assign _T_749 = _T_747 | _T_733; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@17255.4]
assign _T_751 = _T_749 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17257.4]
assign _T_752 = _T_751 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17258.4]
assign _T_753 = _T_738 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@17263.4]
assign _T_754 = _T_733 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@17264.4]
assign _T_755 = _T_753 | _T_754; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@17265.4]
assign _T_757 = _T_755 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17267.4]
assign _T_758 = _T_757 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17268.4]
assign auto_in_a_ready = _T_450 & _T_453; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_valid = _T_470 ? auto_out_r_valid : auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_bits_opcode = _T_470 ? 3'h1 : 3'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_bits_size = _T_470 ? _T_403 : _T_405; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_bits_source = _T_470 ? _T_402 : _T_404; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_bits_denied = _T_470 ? _GEN_54 : _T_482; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_in_d_bits_corrupt = _T_470 ? _T_483 : 1'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@16653.4]
assign auto_out_aw_valid = _T_428_valid & _T_428_bits_wen; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_addr = Queue_1_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_len = Queue_1_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_burst = Queue_1_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_lock = Queue_1_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_cache = Queue_1_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_prot = Queue_1_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_qos = Queue_1_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_aw_bits_user = Queue_1_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_w_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_w_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_w_bits_strb = Queue_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_w_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_b_ready = auto_in_d_ready & _T_471; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_valid = _T_428_valid & _T_432; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_addr = Queue_1_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_len = Queue_1_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_burst = Queue_1_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_lock = Queue_1_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_cache = Queue_1_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_prot = Queue_1_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_qos = Queue_1_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_ar_bits_user = Queue_1_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign auto_out_r_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@16652.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16615.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16616.4]
assign TLMonitor_io_in_a_ready = _T_450 & _T_453; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_valid = _T_470 ? auto_out_r_valid : auto_out_b_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_bits_opcode = _T_470 ? 3'h1 : 3'h0; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_bits_size = _T_470 ? _T_403 : _T_405; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_bits_source = _T_470 ? _T_402 : _T_404; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_bits_denied = _T_470 ? _GEN_54 : _T_482; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign TLMonitor_io_in_d_bits_corrupt = _T_470 ? _T_483 : 1'h0; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@16649.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16769.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16770.4]
assign Queue_io_enq_valid = _T_463 & _T_451; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@16771.4]
assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16774.4]
assign Queue_io_enq_bits_strb = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16773.4]
assign Queue_io_enq_bits_last = _T_384 | _T_385; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16772.4]
assign Queue_io_deq_ready = auto_out_w_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@16781.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16784.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@16785.4]
assign Queue_1_io_enq_valid = _T_456 & _T_459; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@16786.4]
assign Queue_1_io_enq_bits_id = 5'h18 == auto_in_a_bits_source ? 3'h0 : _GEN_25; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16797.4]
assign Queue_1_io_enq_bits_addr = auto_in_a_bits_address; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16796.4]
assign Queue_1_io_enq_bits_len = _T_444[10:3]; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16795.4]
assign Queue_1_io_enq_bits_size = _T_447[2:0]; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16794.4]
assign Queue_1_io_enq_bits_user = _GEN_64 | _T_400; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16788.4]
assign Queue_1_io_enq_bits_wen = _T_367 == 1'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@16787.4]
assign Queue_1_io_deq_ready = _T_428_bits_wen ? auto_out_aw_ready : auto_out_ar_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@16812.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_514 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_545 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_733 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_702 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_671 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_640 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_608 = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_610 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_576 = _RAND_8[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_578 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_379 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_437 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_467 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_475 = _RAND_13[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_479 = _RAND_14[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_514 <= 1'h0;
end else begin
_T_514 <= _T_527;
end
if (reset) begin
_T_545 <= 1'h0;
end else begin
_T_545 <= _T_558;
end
if (reset) begin
_T_733 <= 1'h0;
end else begin
_T_733 <= _T_746;
end
if (reset) begin
_T_702 <= 1'h0;
end else begin
_T_702 <= _T_715;
end
if (reset) begin
_T_671 <= 1'h0;
end else begin
_T_671 <= _T_684;
end
if (reset) begin
_T_640 <= 1'h0;
end else begin
_T_640 <= _T_653;
end
if (reset) begin
_T_608 <= 4'h0;
end else begin
_T_608 <= _T_621;
end
if (_T_613) begin
_T_610 <= _T_368;
end
if (reset) begin
_T_576 <= 4'h0;
end else begin
_T_576 <= _T_589;
end
if (_T_581) begin
_T_578 <= _T_368;
end
if (reset) begin
_T_379 <= 5'h0;
end else begin
if (_T_369) begin
if (_T_383) begin
if (_T_368) begin
_T_379 <= _T_374;
end else begin
_T_379 <= 5'h0;
end
end else begin
_T_379 <= _T_382;
end
end
end
if (reset) begin
_T_437 <= 1'h0;
end else begin
if (_T_369) begin
_T_437 <= _T_439;
end
end
if (reset) begin
_T_467 <= 1'h0;
end else begin
if (_T_468) begin
_T_467 <= _T_469;
end
end
if (reset) begin
_T_475 <= 1'h1;
end else begin
if (_T_468) begin
_T_475 <= auto_out_r_bits_last;
end
end
if (_T_475) begin
_T_479 <= _T_477;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:125 assert (a_source < UInt(BigInt(1) << sourceBits))\n"); // @[ToAXI4.scala 125:14:freechips.rocketchip.system.LowRiscConfig.fir@16746.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[ToAXI4.scala 125:14:freechips.rocketchip.system.LowRiscConfig.fir@16747.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:126 assert (a_size < UInt(BigInt(1) << sizeBits))\n"); // @[ToAXI4.scala 126:14:freechips.rocketchip.system.LowRiscConfig.fir@16754.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[ToAXI4.scala 126:14:freechips.rocketchip.system.LowRiscConfig.fir@16755.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_533) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@16964.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_533) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@16965.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_539) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@16974.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_539) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@16975.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_564) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17006.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_564) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17007.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_570) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17016.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_570) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17017.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_595) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17048.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_595) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17049.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_601) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17058.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_601) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17059.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_627) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17091.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_627) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17092.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_633) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17101.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_633) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17102.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_659) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17134.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_659) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17135.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_665) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17144.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_665) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17145.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_690) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17176.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_690) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17177.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_696) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17186.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_696) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17187.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_721) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17218.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_721) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17219.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_727) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17228.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_727) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17229.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_752) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17260.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_752) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@17261.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_758) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17270.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_758) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@17271.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_5( // @[:freechips.rocketchip.system.LowRiscConfig.fir@17292.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17293.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17294.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [30:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@17295.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@18656.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@17312.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@17313.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@17318.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@17319.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@17322.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@17323.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@17331.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17343.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17344.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17345.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17346.6]
wire [22:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@17348.6]
wire [7:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@17349.6]
wire [7:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@17350.6]
wire [30:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@17351.6]
wire [30:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@17351.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@17352.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@17354.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@17355.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@17356.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@17357.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@17358.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@17359.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@17360.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@17361.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17363.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17364.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17366.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17367.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@17368.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@17369.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@17370.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17371.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17372.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17373.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17374.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17375.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17376.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17377.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17378.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17379.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17380.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17381.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17382.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@17383.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@17384.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@17385.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17386.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17387.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17388.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17389.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17390.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17391.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17392.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17393.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17394.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17395.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17396.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17397.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17398.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17399.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17400.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17401.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17402.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17403.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17404.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17405.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17406.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17407.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17408.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17409.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@17416.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@17489.6]
wire [30:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@17492.8]
wire [31:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@17493.8]
wire [31:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@17494.8]
wire [31:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@17495.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@17496.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@17501.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@17539.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@17540.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@17552.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@17553.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@17559.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@17560.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@17567.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@17568.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@17574.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@17575.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@17580.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@17582.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@17583.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@17588.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@17589.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@17591.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@17592.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@17597.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@17599.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@17600.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@17606.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@17705.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@17707.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@17708.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@17731.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@17734.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@17742.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17745.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17746.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@17765.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@17767.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@17768.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@17773.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@17775.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@17776.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@17790.6]
wire _T_414; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@17793.8]
wire _T_422; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@17801.8]
wire _T_425; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17804.8]
wire _T_426; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17805.8]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@17841.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@17883.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@17884.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@17885.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@17887.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@17888.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@17894.6]
wire _T_490; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@17925.8]
wire _T_492; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@17927.8]
wire _T_493; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@17928.8]
wire _T_498; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@17942.6]
wire _T_516; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@17973.8]
wire _T_518; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@17975.8]
wire _T_519; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@17976.8]
wire _T_524; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@17990.6]
wire _T_550; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@18040.6]
wire _T_552; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@18042.6]
wire _T_553; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@18043.6]
wire [2:0] _T_556; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18050.6]
wire _T_557; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18051.6]
wire _T_562; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18056.6]
wire _T_563; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18057.6]
wire [1:0] _T_566; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18060.6]
wire _T_567; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18061.6]
wire _T_575; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18069.6]
wire _T_591; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18081.6]
wire _T_592; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18082.6]
wire _T_593; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18083.6]
wire _T_594; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18084.6]
wire _T_596; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@18086.6]
wire _T_598; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18089.8]
wire _T_599; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18090.8]
wire _T_600; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@18095.8]
wire _T_602; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@18097.8]
wire _T_603; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@18098.8]
wire _T_608; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@18111.8]
wire _T_610; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@18113.8]
wire _T_611; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@18114.8]
wire _T_612; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@18119.8]
wire _T_614; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@18121.8]
wire _T_615; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@18122.8]
wire _T_616; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@18128.6]
wire _T_644; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@18186.6]
wire _T_664; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@18227.8]
wire _T_666; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@18229.8]
wire _T_667; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@18230.8]
wire _T_673; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@18245.6]
wire _T_690; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@18280.6]
wire _T_708; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@18316.6]
wire _T_737; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@18376.4]
wire [4:0] _T_742; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@18381.4]
wire _T_743; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@18382.4]
wire _T_744; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@18383.4]
reg [4:0] _T_747; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@18385.4]
reg [31:0] _RAND_0;
wire [5:0] _T_748; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18386.4]
wire [5:0] _T_749; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18387.4]
wire [4:0] _T_750; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18388.4]
wire _T_751; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18389.4]
reg [2:0] _T_760; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@18400.4]
reg [31:0] _RAND_1;
reg [2:0] _T_762; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@18401.4]
reg [31:0] _RAND_2;
reg [3:0] _T_764; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@18402.4]
reg [31:0] _RAND_3;
reg [4:0] _T_766; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@18403.4]
reg [31:0] _RAND_4;
reg [30:0] _T_768; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@18404.4]
reg [31:0] _RAND_5;
wire _T_769; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@18405.4]
wire _T_770; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@18406.4]
wire _T_771; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@18408.6]
wire _T_773; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@18410.6]
wire _T_774; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@18411.6]
wire _T_775; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@18416.6]
wire _T_777; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@18418.6]
wire _T_778; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@18419.6]
wire _T_779; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@18424.6]
wire _T_781; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@18426.6]
wire _T_782; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@18427.6]
wire _T_783; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@18432.6]
wire _T_785; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@18434.6]
wire _T_786; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@18435.6]
wire _T_787; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@18440.6]
wire _T_789; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@18442.6]
wire _T_790; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@18443.6]
wire _T_792; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@18450.4]
wire _T_793; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@18458.4]
wire [22:0] _T_795; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@18460.4]
wire [7:0] _T_796; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@18461.4]
wire [7:0] _T_797; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@18462.4]
wire [4:0] _T_798; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@18463.4]
wire _T_799; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@18464.4]
reg [4:0] _T_802; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@18466.4]
reg [31:0] _RAND_6;
wire [5:0] _T_803; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18467.4]
wire [5:0] _T_804; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18468.4]
wire [4:0] _T_805; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18469.4]
wire _T_806; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18470.4]
reg [2:0] _T_815; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@18481.4]
reg [31:0] _RAND_7;
reg [3:0] _T_819; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@18483.4]
reg [31:0] _RAND_8;
reg [4:0] _T_821; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@18484.4]
reg [31:0] _RAND_9;
reg _T_825; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@18486.4]
reg [31:0] _RAND_10;
wire _T_826; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@18487.4]
wire _T_827; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@18488.4]
wire _T_828; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@18490.6]
wire _T_830; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@18492.6]
wire _T_831; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@18493.6]
wire _T_836; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@18506.6]
wire _T_838; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@18508.6]
wire _T_839; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@18509.6]
wire _T_840; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@18514.6]
wire _T_842; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@18516.6]
wire _T_843; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@18517.6]
wire _T_848; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@18530.6]
wire _T_850; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@18532.6]
wire _T_851; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@18533.6]
wire _T_853; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@18540.4]
reg [24:0] _T_855; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@18549.4]
reg [31:0] _RAND_11;
reg [4:0] _T_866; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@18559.4]
reg [31:0] _RAND_12;
wire [5:0] _T_867; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18560.4]
wire [5:0] _T_868; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18561.4]
wire [4:0] _T_869; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18562.4]
wire _T_870; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18563.4]
reg [4:0] _T_887; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@18582.4]
reg [31:0] _RAND_13;
wire [5:0] _T_888; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18583.4]
wire [5:0] _T_889; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18584.4]
wire [4:0] _T_890; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18585.4]
wire _T_891; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18586.4]
wire _T_902; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@18601.4]
wire [31:0] _T_904; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@18604.6]
wire [24:0] _T_905; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@18606.6]
wire _T_906; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@18607.6]
wire _T_907; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@18608.6]
wire _T_909; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@18610.6]
wire _T_910; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@18611.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@18603.4]
wire _T_915; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@18622.4]
wire _T_917; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@18624.4]
wire _T_918; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@18625.4]
wire [31:0] _T_919; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@18627.6]
wire [24:0] _T_900; // @[:freechips.rocketchip.system.LowRiscConfig.fir@18597.4 :freechips.rocketchip.system.LowRiscConfig.fir@18599.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@18605.6]
wire [24:0] _T_920; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@18629.6]
wire [24:0] _T_921; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@18630.6]
wire _T_922; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@18631.6]
wire _T_924; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@18633.6]
wire _T_925; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@18634.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@18626.4]
wire [24:0] _T_912; // @[:freechips.rocketchip.system.LowRiscConfig.fir@18617.4 :freechips.rocketchip.system.LowRiscConfig.fir@18619.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@18628.6]
wire _T_926; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@18640.4]
wire _T_927; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@18641.4]
wire _T_928; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@18642.4]
wire _T_929; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@18643.4]
wire _T_931; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@18645.4]
wire _T_932; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@18646.4]
wire [24:0] _T_933; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@18651.4]
wire [24:0] _T_934; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@18652.4]
wire [24:0] _T_935; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@18653.4]
reg [31:0] _T_937; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@18655.4]
reg [31:0] _RAND_14;
wire _T_938; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@18658.4]
wire _T_939; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@18659.4]
wire _T_940; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@18660.4]
wire _T_941; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@18661.4]
wire _T_942; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@18662.4]
wire _T_943; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@18663.4]
wire _T_945; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@18665.4]
wire _T_946; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@18666.4]
wire [31:0] _T_948; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@18672.4]
wire _T_951; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@18676.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@17503.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@17620.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17748.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17807.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@17858.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@17908.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@17956.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@18004.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18092.10]
wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@18134.10]
wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@18192.10]
wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@18251.10]
wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@18286.10]
wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@18322.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@18656.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@17312.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@17313.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@17318.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@17319.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@17322.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@17323.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@17331.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17343.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17344.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17345.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@17346.6]
assign _T_62 = 23'hff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@17348.6]
assign _T_63 = _T_62[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@17349.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@17350.6]
assign _GEN_18 = {{23'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@17351.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@17351.6]
assign _T_66 = _T_65 == 31'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@17352.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@17354.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@17355.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@17356.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@17357.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@17358.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@17359.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@17360.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@17361.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17363.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17364.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17366.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17367.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@17368.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@17369.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@17370.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17371.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17372.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17373.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17374.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17375.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17376.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17377.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17378.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17379.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17380.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17381.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17382.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@17383.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@17384.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@17385.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17386.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17387.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17388.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17389.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17390.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17391.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17392.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17393.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17394.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17395.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17396.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17397.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17398.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17399.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17400.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17401.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17402.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17403.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17404.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17405.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17406.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@17407.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@17408.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@17409.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@17416.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@17489.6]
assign _T_201 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@17492.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@17493.8]
assign _T_203 = $signed(_T_202) & $signed(-32'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@17494.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@17495.8]
assign _T_205 = $signed(_T_204) == $signed(32'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@17496.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@17501.8]
assign _T_248 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@17539.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@17540.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@17552.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@17553.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@17559.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@17560.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@17567.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@17568.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@17574.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@17575.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@17580.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@17582.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@17583.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@17588.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@17589.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@17591.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@17592.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@17597.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@17599.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@17600.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@17606.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@17705.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@17707.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@17708.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@17731.6]
assign _T_381 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@17734.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@17742.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17745.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17746.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@17765.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@17767.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@17768.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@17773.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@17775.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@17776.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@17790.6]
assign _T_414 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@17793.8]
assign _T_422 = _T_414 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@17801.8]
assign _T_425 = _T_422 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17804.8]
assign _T_426 = _T_425 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17805.8]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@17841.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@17883.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@17884.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@17885.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@17887.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@17888.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@17894.6]
assign _T_490 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@17925.8]
assign _T_492 = _T_490 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@17927.8]
assign _T_493 = _T_492 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@17928.8]
assign _T_498 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@17942.6]
assign _T_516 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@17973.8]
assign _T_518 = _T_516 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@17975.8]
assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@17976.8]
assign _T_524 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@17990.6]
assign _T_550 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@18040.6]
assign _T_552 = _T_550 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@18042.6]
assign _T_553 = _T_552 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@18043.6]
assign _T_556 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18050.6]
assign _T_557 = _T_556 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18051.6]
assign _T_562 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18056.6]
assign _T_563 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18057.6]
assign _T_566 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18060.6]
assign _T_567 = _T_566 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18061.6]
assign _T_575 = _T_566 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18069.6]
assign _T_591 = _T_557 | _T_562; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18081.6]
assign _T_592 = _T_591 | _T_563; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18082.6]
assign _T_593 = _T_592 | _T_567; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18083.6]
assign _T_594 = _T_593 | _T_575; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18084.6]
assign _T_596 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@18086.6]
assign _T_598 = _T_594 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18089.8]
assign _T_599 = _T_598 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18090.8]
assign _T_600 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@18095.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@18097.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@18098.8]
assign _T_608 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@18111.8]
assign _T_610 = _T_608 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@18113.8]
assign _T_611 = _T_610 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@18114.8]
assign _T_612 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@18119.8]
assign _T_614 = _T_612 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@18121.8]
assign _T_615 = _T_614 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@18122.8]
assign _T_616 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@18128.6]
assign _T_644 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@18186.6]
assign _T_664 = _T_612 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@18227.8]
assign _T_666 = _T_664 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@18229.8]
assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@18230.8]
assign _T_673 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@18245.6]
assign _T_690 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@18280.6]
assign _T_708 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@18316.6]
assign _T_737 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@18376.4]
assign _T_742 = _T_64[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@18381.4]
assign _T_743 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@18382.4]
assign _T_744 = _T_743 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@18383.4]
assign _T_748 = _T_747 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18386.4]
assign _T_749 = $unsigned(_T_748); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18387.4]
assign _T_750 = _T_749[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18388.4]
assign _T_751 = _T_747 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18389.4]
assign _T_769 = _T_751 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@18405.4]
assign _T_770 = io_in_a_valid & _T_769; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@18406.4]
assign _T_771 = io_in_a_bits_opcode == _T_760; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@18408.6]
assign _T_773 = _T_771 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@18410.6]
assign _T_774 = _T_773 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@18411.6]
assign _T_775 = io_in_a_bits_param == _T_762; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@18416.6]
assign _T_777 = _T_775 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@18418.6]
assign _T_778 = _T_777 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@18419.6]
assign _T_779 = io_in_a_bits_size == _T_764; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@18424.6]
assign _T_781 = _T_779 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@18426.6]
assign _T_782 = _T_781 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@18427.6]
assign _T_783 = io_in_a_bits_source == _T_766; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@18432.6]
assign _T_785 = _T_783 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@18434.6]
assign _T_786 = _T_785 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@18435.6]
assign _T_787 = io_in_a_bits_address == _T_768; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@18440.6]
assign _T_789 = _T_787 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@18442.6]
assign _T_790 = _T_789 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@18443.6]
assign _T_792 = _T_737 & _T_751; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@18450.4]
assign _T_793 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@18458.4]
assign _T_795 = 23'hff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@18460.4]
assign _T_796 = _T_795[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@18461.4]
assign _T_797 = ~ _T_796; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@18462.4]
assign _T_798 = _T_797[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@18463.4]
assign _T_799 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@18464.4]
assign _T_803 = _T_802 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18467.4]
assign _T_804 = $unsigned(_T_803); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18468.4]
assign _T_805 = _T_804[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18469.4]
assign _T_806 = _T_802 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18470.4]
assign _T_826 = _T_806 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@18487.4]
assign _T_827 = io_in_d_valid & _T_826; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@18488.4]
assign _T_828 = io_in_d_bits_opcode == _T_815; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@18490.6]
assign _T_830 = _T_828 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@18492.6]
assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@18493.6]
assign _T_836 = io_in_d_bits_size == _T_819; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@18506.6]
assign _T_838 = _T_836 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@18508.6]
assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@18509.6]
assign _T_840 = io_in_d_bits_source == _T_821; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@18514.6]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@18516.6]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@18517.6]
assign _T_848 = io_in_d_bits_denied == _T_825; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@18530.6]
assign _T_850 = _T_848 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@18532.6]
assign _T_851 = _T_850 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@18533.6]
assign _T_853 = _T_793 & _T_806; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@18540.4]
assign _T_867 = _T_866 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18560.4]
assign _T_868 = $unsigned(_T_867); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18561.4]
assign _T_869 = _T_868[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18562.4]
assign _T_870 = _T_866 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18563.4]
assign _T_888 = _T_887 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18583.4]
assign _T_889 = $unsigned(_T_888); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18584.4]
assign _T_890 = _T_889[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@18585.4]
assign _T_891 = _T_887 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@18586.4]
assign _T_902 = _T_737 & _T_870; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@18601.4]
assign _T_904 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@18604.6]
assign _T_905 = _T_855 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@18606.6]
assign _T_906 = _T_905[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@18607.6]
assign _T_907 = _T_906 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@18608.6]
assign _T_909 = _T_907 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@18610.6]
assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@18611.6]
assign _GEN_15 = _T_902 ? _T_904 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@18603.4]
assign _T_915 = _T_793 & _T_891; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@18622.4]
assign _T_917 = _T_596 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@18624.4]
assign _T_918 = _T_915 & _T_917; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@18625.4]
assign _T_919 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@18627.6]
assign _T_900 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@18597.4 :freechips.rocketchip.system.LowRiscConfig.fir@18599.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@18605.6]
assign _T_920 = _T_900 | _T_855; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@18629.6]
assign _T_921 = _T_920 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@18630.6]
assign _T_922 = _T_921[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@18631.6]
assign _T_924 = _T_922 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@18633.6]
assign _T_925 = _T_924 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@18634.6]
assign _GEN_16 = _T_918 ? _T_919 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@18626.4]
assign _T_912 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@18617.4 :freechips.rocketchip.system.LowRiscConfig.fir@18619.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@18628.6]
assign _T_926 = _T_900 != _T_912; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@18640.4]
assign _T_927 = _T_900 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@18641.4]
assign _T_928 = _T_927 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@18642.4]
assign _T_929 = _T_926 | _T_928; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@18643.4]
assign _T_931 = _T_929 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@18645.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@18646.4]
assign _T_933 = _T_855 | _T_900; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@18651.4]
assign _T_934 = ~ _T_912; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@18652.4]
assign _T_935 = _T_933 & _T_934; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@18653.4]
assign _T_938 = _T_855 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@18658.4]
assign _T_939 = _T_938 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@18659.4]
assign _T_940 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@18660.4]
assign _T_941 = _T_939 | _T_940; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@18661.4]
assign _T_942 = _T_937 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@18662.4]
assign _T_943 = _T_941 | _T_942; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@18663.4]
assign _T_945 = _T_943 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@18665.4]
assign _T_946 = _T_945 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@18666.4]
assign _T_948 = _T_937 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@18672.4]
assign _T_951 = _T_737 | _T_793; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@18676.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@17503.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@17620.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17748.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17807.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@17858.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@17908.10]
assign _GEN_95 = io_in_a_valid & _T_498; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@17956.10]
assign _GEN_105 = io_in_a_valid & _T_524; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@18004.10]
assign _GEN_115 = io_in_d_valid & _T_596; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18092.10]
assign _GEN_123 = io_in_d_valid & _T_616; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@18134.10]
assign _GEN_131 = io_in_d_valid & _T_644; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@18192.10]
assign _GEN_139 = io_in_d_valid & _T_673; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@18251.10]
assign _GEN_143 = io_in_d_valid & _T_690; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@18286.10]
assign _GEN_147 = io_in_d_valid & _T_708; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@18322.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_747 = _RAND_0[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_760 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_762 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_764 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_766 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_768 = _RAND_5[30:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_802 = _RAND_6[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_815 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_819 = _RAND_8[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_821 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_825 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_855 = _RAND_11[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_866 = _RAND_12[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_887 = _RAND_13[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_937 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_747 <= 5'h0;
end else begin
if (_T_737) begin
if (_T_751) begin
if (_T_744) begin
_T_747 <= _T_742;
end else begin
_T_747 <= 5'h0;
end
end else begin
_T_747 <= _T_750;
end
end
end
if (_T_792) begin
_T_760 <= io_in_a_bits_opcode;
end
if (_T_792) begin
_T_762 <= io_in_a_bits_param;
end
if (_T_792) begin
_T_764 <= io_in_a_bits_size;
end
if (_T_792) begin
_T_766 <= io_in_a_bits_source;
end
if (_T_792) begin
_T_768 <= io_in_a_bits_address;
end
if (reset) begin
_T_802 <= 5'h0;
end else begin
if (_T_793) begin
if (_T_806) begin
if (_T_799) begin
_T_802 <= _T_798;
end else begin
_T_802 <= 5'h0;
end
end else begin
_T_802 <= _T_805;
end
end
end
if (_T_853) begin
_T_815 <= io_in_d_bits_opcode;
end
if (_T_853) begin
_T_819 <= io_in_d_bits_size;
end
if (_T_853) begin
_T_821 <= io_in_d_bits_source;
end
if (_T_853) begin
_T_825 <= io_in_d_bits_denied;
end
if (reset) begin
_T_855 <= 25'h0;
end else begin
_T_855 <= _T_935;
end
if (reset) begin
_T_866 <= 5'h0;
end else begin
if (_T_737) begin
if (_T_870) begin
if (_T_744) begin
_T_866 <= _T_742;
end else begin
_T_866 <= 5'h0;
end
end else begin
_T_866 <= _T_869;
end
end
end
if (reset) begin
_T_887 <= 5'h0;
end else begin
if (_T_793) begin
if (_T_891) begin
if (_T_799) begin
_T_887 <= _T_798;
end else begin
_T_887 <= 5'h0;
end
end else begin
_T_887 <= _T_890;
end
end
end
if (reset) begin
_T_937 <= 32'h0;
end else begin
if (_T_951) begin
_T_937 <= 32'h0;
end else begin
_T_937 <= _T_948;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:136:39)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@17307.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@17308.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@17486.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@17487.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@17503.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@17504.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:136:39)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@17555.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@17556.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@17562.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@17563.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@17570.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@17571.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@17577.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@17578.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@17585.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@17586.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@17594.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@17595.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@17602.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@17603.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@17620.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@17621.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:136:39)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@17672.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@17673.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@17679.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@17680.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@17687.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@17688.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@17694.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@17695.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@17702.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@17703.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:136:39)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@17710.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@17711.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@17719.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@17720.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@17727.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@17728.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17748.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@17749.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@17755.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@17756.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@17762.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@17763.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@17770.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@17771.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@17778.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@17779.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@17786.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@17787.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_426) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17807.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_426) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@17808.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@17814.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@17815.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@17821.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@17822.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@17829.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@17830.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@17837.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@17838.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_426) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@17858.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_426) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@17859.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@17865.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@17866.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@17872.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@17873.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@17880.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@17881.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@17890.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@17891.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@17908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@17909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@17915.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@17916.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@17922.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@17923.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@17930.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@17931.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@17938.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@17939.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@17956.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@17957.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@17963.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@17964.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@17970.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@17971.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@17978.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@17979.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@17986.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@17987.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:136:39)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@18004.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@18005.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@18011.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@18012.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:136:39)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@18018.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@18019.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:136:39)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@18026.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@18027.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@18034.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@18035.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:136:39)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@18045.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@18046.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18092.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@18093.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@18100.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@18101.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@18108.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@18109.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@18116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_611) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@18117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_615) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@18124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_615) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@18125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@18134.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_599) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@18135.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@18141.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@18142.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@18149.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_603) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@18150.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@18157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@18158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@18165.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@18166.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@18173.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_611) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@18174.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@18182.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@18183.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@18192.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@18193.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@18199.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@18200.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:136:39)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@18207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_603) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@18208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@18215.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@18216.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@18223.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@18224.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_667) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@18232.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_667) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@18233.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@18241.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@18242.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@18251.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_599) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@18252.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@18259.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@18260.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@18267.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_611) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@18268.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@18276.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@18277.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@18286.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_599) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@18287.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@18294.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@18295.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_667) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@18303.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_667) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@18304.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@18312.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@18313.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@18322.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_599) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@18323.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:136:39)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@18330.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@18331.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:136:39)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@18338.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_611) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@18339.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:136:39)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@18347.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@18348.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:136:39)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@18357.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@18358.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:136:39)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@18365.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@18366.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:136:39)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@18373.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@18374.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_774) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@18413.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_774) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@18414.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_778) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@18421.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_778) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@18422.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_782) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@18429.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_782) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@18430.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_786) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@18437.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_786) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@18438.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_790) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@18445.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_790) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@18446.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_831) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@18495.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_831) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@18496.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@18503.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@18504.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_839) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@18511.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_839) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@18512.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@18519.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_843) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@18520.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@18527.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@18528.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_851) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:136:39)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@18535.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_851) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@18536.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_902 & _T_910) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:136:39)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@18613.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_902 & _T_910) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@18614.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918 & _T_925) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:136:39)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@18636.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918 & _T_925) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@18637.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_932) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:136:39)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@18648.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_932) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@18649.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:136:39)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@18668.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@18669.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLWidthWidget( // @[:freechips.rocketchip.system.LowRiscConfig.fir@18681.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18682.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18683.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [30:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [30:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@18684.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [30:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
TLMonitor_5 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@18691.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@18731.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@18730.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@18693.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@18694.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@18727.4]
endmodule
module TLMonitor_6( // @[:freechips.rocketchip.system.LowRiscConfig.fir@18748.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18749.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18750.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [30:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@18751.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@20112.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18768.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18769.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18774.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18775.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18778.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18779.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18787.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18799.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18800.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18801.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18802.6]
wire [22:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@18804.6]
wire [7:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@18805.6]
wire [7:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@18806.6]
wire [30:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@18807.6]
wire [30:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@18807.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@18808.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@18810.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@18811.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@18812.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@18813.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@18814.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@18815.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@18816.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@18817.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18819.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18820.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18822.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18823.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@18824.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@18825.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@18826.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18827.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18828.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18829.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18830.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18831.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18832.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18833.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18834.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18835.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18836.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18837.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18838.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@18839.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@18840.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@18841.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18842.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18843.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18844.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18845.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18846.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18847.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18848.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18849.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18850.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18851.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18852.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18853.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18854.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18855.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18856.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18857.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18858.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18859.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18860.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18861.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18862.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18863.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18864.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18865.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@18872.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@18945.6]
wire [30:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@18948.8]
wire [31:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@18949.8]
wire [31:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@18950.8]
wire [31:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@18951.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@18952.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@18957.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@18995.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@18996.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@19008.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@19009.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@19015.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@19016.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@19023.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@19024.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@19030.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@19031.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@19036.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@19038.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@19039.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@19044.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@19045.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@19047.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@19048.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@19053.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@19055.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@19056.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@19062.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@19161.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@19163.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@19164.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@19187.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@19190.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@19198.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19201.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19202.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@19221.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@19223.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@19224.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@19229.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@19231.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@19232.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@19246.6]
wire _T_414; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@19249.8]
wire _T_422; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@19257.8]
wire _T_425; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19260.8]
wire _T_426; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19261.8]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@19297.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@19339.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@19340.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@19341.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@19343.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@19344.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@19350.6]
wire _T_490; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@19381.8]
wire _T_492; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@19383.8]
wire _T_493; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@19384.8]
wire _T_498; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@19398.6]
wire _T_516; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@19429.8]
wire _T_518; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@19431.8]
wire _T_519; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@19432.8]
wire _T_524; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@19446.6]
wire _T_550; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@19496.6]
wire _T_552; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@19498.6]
wire _T_553; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@19499.6]
wire [2:0] _T_556; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@19506.6]
wire _T_557; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@19507.6]
wire _T_562; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@19512.6]
wire _T_563; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@19513.6]
wire [1:0] _T_566; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@19516.6]
wire _T_567; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@19517.6]
wire _T_575; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@19525.6]
wire _T_591; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19537.6]
wire _T_592; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19538.6]
wire _T_593; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19539.6]
wire _T_594; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19540.6]
wire _T_596; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@19542.6]
wire _T_598; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19545.8]
wire _T_599; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19546.8]
wire _T_600; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@19551.8]
wire _T_602; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@19553.8]
wire _T_603; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@19554.8]
wire _T_608; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@19567.8]
wire _T_610; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@19569.8]
wire _T_611; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@19570.8]
wire _T_612; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@19575.8]
wire _T_614; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@19577.8]
wire _T_615; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@19578.8]
wire _T_616; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@19584.6]
wire _T_644; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@19642.6]
wire _T_664; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@19683.8]
wire _T_666; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@19685.8]
wire _T_667; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@19686.8]
wire _T_673; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@19701.6]
wire _T_690; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@19736.6]
wire _T_708; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@19772.6]
wire _T_737; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@19832.4]
wire [4:0] _T_742; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@19837.4]
wire _T_743; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@19838.4]
wire _T_744; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@19839.4]
reg [4:0] _T_747; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@19841.4]
reg [31:0] _RAND_0;
wire [5:0] _T_748; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19842.4]
wire [5:0] _T_749; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19843.4]
wire [4:0] _T_750; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19844.4]
wire _T_751; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@19845.4]
reg [2:0] _T_760; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@19856.4]
reg [31:0] _RAND_1;
reg [2:0] _T_762; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@19857.4]
reg [31:0] _RAND_2;
reg [3:0] _T_764; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@19858.4]
reg [31:0] _RAND_3;
reg [4:0] _T_766; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@19859.4]
reg [31:0] _RAND_4;
reg [30:0] _T_768; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@19860.4]
reg [31:0] _RAND_5;
wire _T_769; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@19861.4]
wire _T_770; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@19862.4]
wire _T_771; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@19864.6]
wire _T_773; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@19866.6]
wire _T_774; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@19867.6]
wire _T_775; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@19872.6]
wire _T_777; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@19874.6]
wire _T_778; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@19875.6]
wire _T_779; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@19880.6]
wire _T_781; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@19882.6]
wire _T_782; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@19883.6]
wire _T_783; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@19888.6]
wire _T_785; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@19890.6]
wire _T_786; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@19891.6]
wire _T_787; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@19896.6]
wire _T_789; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@19898.6]
wire _T_790; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@19899.6]
wire _T_792; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@19906.4]
wire _T_793; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@19914.4]
wire [22:0] _T_795; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@19916.4]
wire [7:0] _T_796; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@19917.4]
wire [7:0] _T_797; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@19918.4]
wire [4:0] _T_798; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@19919.4]
wire _T_799; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@19920.4]
reg [4:0] _T_802; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@19922.4]
reg [31:0] _RAND_6;
wire [5:0] _T_803; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19923.4]
wire [5:0] _T_804; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19924.4]
wire [4:0] _T_805; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19925.4]
wire _T_806; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@19926.4]
reg [2:0] _T_815; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@19937.4]
reg [31:0] _RAND_7;
reg [3:0] _T_819; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@19939.4]
reg [31:0] _RAND_8;
reg [4:0] _T_821; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@19940.4]
reg [31:0] _RAND_9;
reg _T_825; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@19942.4]
reg [31:0] _RAND_10;
wire _T_826; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@19943.4]
wire _T_827; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@19944.4]
wire _T_828; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@19946.6]
wire _T_830; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@19948.6]
wire _T_831; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@19949.6]
wire _T_836; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@19962.6]
wire _T_838; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@19964.6]
wire _T_839; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@19965.6]
wire _T_840; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@19970.6]
wire _T_842; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@19972.6]
wire _T_843; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@19973.6]
wire _T_848; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@19986.6]
wire _T_850; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@19988.6]
wire _T_851; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@19989.6]
wire _T_853; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@19996.4]
reg [24:0] _T_855; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@20005.4]
reg [31:0] _RAND_11;
reg [4:0] _T_866; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@20015.4]
reg [31:0] _RAND_12;
wire [5:0] _T_867; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20016.4]
wire [5:0] _T_868; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20017.4]
wire [4:0] _T_869; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20018.4]
wire _T_870; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@20019.4]
reg [4:0] _T_887; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@20038.4]
reg [31:0] _RAND_13;
wire [5:0] _T_888; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20039.4]
wire [5:0] _T_889; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20040.4]
wire [4:0] _T_890; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20041.4]
wire _T_891; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@20042.4]
wire _T_902; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@20057.4]
wire [31:0] _T_904; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@20060.6]
wire [24:0] _T_905; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@20062.6]
wire _T_906; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@20063.6]
wire _T_907; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@20064.6]
wire _T_909; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@20066.6]
wire _T_910; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@20067.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@20059.4]
wire _T_915; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@20078.4]
wire _T_917; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@20080.4]
wire _T_918; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@20081.4]
wire [31:0] _T_919; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@20083.6]
wire [24:0] _T_900; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20053.4 :freechips.rocketchip.system.LowRiscConfig.fir@20055.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@20061.6]
wire [24:0] _T_920; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@20085.6]
wire [24:0] _T_921; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@20086.6]
wire _T_922; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@20087.6]
wire _T_924; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@20089.6]
wire _T_925; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@20090.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@20082.4]
wire [24:0] _T_912; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20073.4 :freechips.rocketchip.system.LowRiscConfig.fir@20075.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@20084.6]
wire _T_926; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@20096.4]
wire _T_927; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@20097.4]
wire _T_928; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@20098.4]
wire _T_929; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@20099.4]
wire _T_931; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@20101.4]
wire _T_932; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@20102.4]
wire [24:0] _T_933; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@20107.4]
wire [24:0] _T_934; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@20108.4]
wire [24:0] _T_935; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@20109.4]
reg [31:0] _T_937; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@20111.4]
reg [31:0] _RAND_14;
wire _T_938; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@20114.4]
wire _T_939; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@20115.4]
wire _T_940; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@20116.4]
wire _T_941; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@20117.4]
wire _T_942; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@20118.4]
wire _T_943; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@20119.4]
wire _T_945; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@20121.4]
wire _T_946; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@20122.4]
wire [31:0] _T_948; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@20128.4]
wire _T_951; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@20132.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@18959.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@19076.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19204.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19263.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@19314.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@19364.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@19412.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@19460.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19548.10]
wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@19590.10]
wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@19648.10]
wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@19707.10]
wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@19742.10]
wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@19778.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@20112.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18768.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18769.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18774.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@18775.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@18778.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18779.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@18787.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18799.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18800.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18801.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@18802.6]
assign _T_62 = 23'hff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@18804.6]
assign _T_63 = _T_62[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@18805.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@18806.6]
assign _GEN_18 = {{23'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@18807.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@18807.6]
assign _T_66 = _T_65 == 31'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@18808.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@18810.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@18811.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@18812.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@18813.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@18814.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@18815.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@18816.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@18817.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18819.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18820.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18822.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18823.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@18824.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@18825.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@18826.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18827.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18828.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18829.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18830.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18831.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18832.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18833.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18834.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18835.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18836.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18837.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18838.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@18839.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@18840.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@18841.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18842.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18843.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18844.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18845.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18846.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18847.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18848.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18849.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18850.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18851.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18852.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18853.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18854.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18855.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18856.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18857.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18858.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18859.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18860.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18861.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18862.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@18863.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@18864.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@18865.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@18872.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@18945.6]
assign _T_201 = io_in_a_bits_address ^ 31'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@18948.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@18949.8]
assign _T_203 = $signed(_T_202) & $signed(-32'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@18950.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@18951.8]
assign _T_205 = $signed(_T_204) == $signed(32'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@18952.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@18957.8]
assign _T_248 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@18995.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@18996.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@19008.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@19009.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@19015.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@19016.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@19023.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@19024.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@19030.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@19031.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@19036.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@19038.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@19039.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@19044.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@19045.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@19047.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@19048.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@19053.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@19055.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@19056.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@19062.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@19161.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@19163.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@19164.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@19187.6]
assign _T_381 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@19190.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@19198.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19201.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19202.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@19221.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@19223.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@19224.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@19229.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@19231.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@19232.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@19246.6]
assign _T_414 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@19249.8]
assign _T_422 = _T_414 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@19257.8]
assign _T_425 = _T_422 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19260.8]
assign _T_426 = _T_425 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19261.8]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@19297.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@19339.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@19340.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@19341.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@19343.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@19344.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@19350.6]
assign _T_490 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@19381.8]
assign _T_492 = _T_490 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@19383.8]
assign _T_493 = _T_492 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@19384.8]
assign _T_498 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@19398.6]
assign _T_516 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@19429.8]
assign _T_518 = _T_516 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@19431.8]
assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@19432.8]
assign _T_524 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@19446.6]
assign _T_550 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@19496.6]
assign _T_552 = _T_550 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@19498.6]
assign _T_553 = _T_552 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@19499.6]
assign _T_556 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@19506.6]
assign _T_557 = _T_556 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@19507.6]
assign _T_562 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@19512.6]
assign _T_563 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@19513.6]
assign _T_566 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@19516.6]
assign _T_567 = _T_566 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@19517.6]
assign _T_575 = _T_566 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@19525.6]
assign _T_591 = _T_557 | _T_562; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19537.6]
assign _T_592 = _T_591 | _T_563; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19538.6]
assign _T_593 = _T_592 | _T_567; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19539.6]
assign _T_594 = _T_593 | _T_575; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@19540.6]
assign _T_596 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@19542.6]
assign _T_598 = _T_594 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19545.8]
assign _T_599 = _T_598 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19546.8]
assign _T_600 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@19551.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@19553.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@19554.8]
assign _T_608 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@19567.8]
assign _T_610 = _T_608 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@19569.8]
assign _T_611 = _T_610 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@19570.8]
assign _T_612 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@19575.8]
assign _T_614 = _T_612 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@19577.8]
assign _T_615 = _T_614 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@19578.8]
assign _T_616 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@19584.6]
assign _T_644 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@19642.6]
assign _T_664 = _T_612 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@19683.8]
assign _T_666 = _T_664 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@19685.8]
assign _T_667 = _T_666 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@19686.8]
assign _T_673 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@19701.6]
assign _T_690 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@19736.6]
assign _T_708 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@19772.6]
assign _T_737 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@19832.4]
assign _T_742 = _T_64[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@19837.4]
assign _T_743 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@19838.4]
assign _T_744 = _T_743 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@19839.4]
assign _T_748 = _T_747 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19842.4]
assign _T_749 = $unsigned(_T_748); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19843.4]
assign _T_750 = _T_749[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19844.4]
assign _T_751 = _T_747 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@19845.4]
assign _T_769 = _T_751 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@19861.4]
assign _T_770 = io_in_a_valid & _T_769; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@19862.4]
assign _T_771 = io_in_a_bits_opcode == _T_760; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@19864.6]
assign _T_773 = _T_771 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@19866.6]
assign _T_774 = _T_773 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@19867.6]
assign _T_775 = io_in_a_bits_param == _T_762; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@19872.6]
assign _T_777 = _T_775 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@19874.6]
assign _T_778 = _T_777 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@19875.6]
assign _T_779 = io_in_a_bits_size == _T_764; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@19880.6]
assign _T_781 = _T_779 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@19882.6]
assign _T_782 = _T_781 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@19883.6]
assign _T_783 = io_in_a_bits_source == _T_766; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@19888.6]
assign _T_785 = _T_783 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@19890.6]
assign _T_786 = _T_785 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@19891.6]
assign _T_787 = io_in_a_bits_address == _T_768; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@19896.6]
assign _T_789 = _T_787 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@19898.6]
assign _T_790 = _T_789 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@19899.6]
assign _T_792 = _T_737 & _T_751; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@19906.4]
assign _T_793 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@19914.4]
assign _T_795 = 23'hff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@19916.4]
assign _T_796 = _T_795[7:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@19917.4]
assign _T_797 = ~ _T_796; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@19918.4]
assign _T_798 = _T_797[7:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@19919.4]
assign _T_799 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@19920.4]
assign _T_803 = _T_802 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19923.4]
assign _T_804 = $unsigned(_T_803); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19924.4]
assign _T_805 = _T_804[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@19925.4]
assign _T_806 = _T_802 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@19926.4]
assign _T_826 = _T_806 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@19943.4]
assign _T_827 = io_in_d_valid & _T_826; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@19944.4]
assign _T_828 = io_in_d_bits_opcode == _T_815; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@19946.6]
assign _T_830 = _T_828 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@19948.6]
assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@19949.6]
assign _T_836 = io_in_d_bits_size == _T_819; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@19962.6]
assign _T_838 = _T_836 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@19964.6]
assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@19965.6]
assign _T_840 = io_in_d_bits_source == _T_821; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@19970.6]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@19972.6]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@19973.6]
assign _T_848 = io_in_d_bits_denied == _T_825; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@19986.6]
assign _T_850 = _T_848 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@19988.6]
assign _T_851 = _T_850 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@19989.6]
assign _T_853 = _T_793 & _T_806; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@19996.4]
assign _T_867 = _T_866 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20016.4]
assign _T_868 = $unsigned(_T_867); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20017.4]
assign _T_869 = _T_868[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20018.4]
assign _T_870 = _T_866 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@20019.4]
assign _T_888 = _T_887 - 5'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20039.4]
assign _T_889 = $unsigned(_T_888); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20040.4]
assign _T_890 = _T_889[4:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@20041.4]
assign _T_891 = _T_887 == 5'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@20042.4]
assign _T_902 = _T_737 & _T_870; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@20057.4]
assign _T_904 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@20060.6]
assign _T_905 = _T_855 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@20062.6]
assign _T_906 = _T_905[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@20063.6]
assign _T_907 = _T_906 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@20064.6]
assign _T_909 = _T_907 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@20066.6]
assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@20067.6]
assign _GEN_15 = _T_902 ? _T_904 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@20059.4]
assign _T_915 = _T_793 & _T_891; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@20078.4]
assign _T_917 = _T_596 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@20080.4]
assign _T_918 = _T_915 & _T_917; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@20081.4]
assign _T_919 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@20083.6]
assign _T_900 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20053.4 :freechips.rocketchip.system.LowRiscConfig.fir@20055.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@20061.6]
assign _T_920 = _T_900 | _T_855; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@20085.6]
assign _T_921 = _T_920 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@20086.6]
assign _T_922 = _T_921[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@20087.6]
assign _T_924 = _T_922 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@20089.6]
assign _T_925 = _T_924 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@20090.6]
assign _GEN_16 = _T_918 ? _T_919 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@20082.4]
assign _T_912 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20073.4 :freechips.rocketchip.system.LowRiscConfig.fir@20075.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@20084.6]
assign _T_926 = _T_900 != _T_912; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@20096.4]
assign _T_927 = _T_900 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@20097.4]
assign _T_928 = _T_927 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@20098.4]
assign _T_929 = _T_926 | _T_928; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@20099.4]
assign _T_931 = _T_929 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@20101.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@20102.4]
assign _T_933 = _T_855 | _T_900; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@20107.4]
assign _T_934 = ~ _T_912; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@20108.4]
assign _T_935 = _T_933 & _T_934; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@20109.4]
assign _T_938 = _T_855 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@20114.4]
assign _T_939 = _T_938 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@20115.4]
assign _T_940 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@20116.4]
assign _T_941 = _T_939 | _T_940; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@20117.4]
assign _T_942 = _T_937 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@20118.4]
assign _T_943 = _T_941 | _T_942; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@20119.4]
assign _T_945 = _T_943 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@20121.4]
assign _T_946 = _T_945 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@20122.4]
assign _T_948 = _T_937 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@20128.4]
assign _T_951 = _T_737 | _T_793; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@20132.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@18959.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@19076.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19204.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19263.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@19314.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@19364.10]
assign _GEN_95 = io_in_a_valid & _T_498; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@19412.10]
assign _GEN_105 = io_in_a_valid & _T_524; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@19460.10]
assign _GEN_115 = io_in_d_valid & _T_596; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19548.10]
assign _GEN_123 = io_in_d_valid & _T_616; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@19590.10]
assign _GEN_131 = io_in_d_valid & _T_644; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@19648.10]
assign _GEN_139 = io_in_d_valid & _T_673; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@19707.10]
assign _GEN_143 = io_in_d_valid & _T_690; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@19742.10]
assign _GEN_147 = io_in_d_valid & _T_708; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@19778.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_747 = _RAND_0[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_760 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_762 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_764 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_766 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_768 = _RAND_5[30:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_802 = _RAND_6[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_815 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_819 = _RAND_8[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_821 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_825 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_855 = _RAND_11[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_866 = _RAND_12[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_887 = _RAND_13[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_937 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_747 <= 5'h0;
end else begin
if (_T_737) begin
if (_T_751) begin
if (_T_744) begin
_T_747 <= _T_742;
end else begin
_T_747 <= 5'h0;
end
end else begin
_T_747 <= _T_750;
end
end
end
if (_T_792) begin
_T_760 <= io_in_a_bits_opcode;
end
if (_T_792) begin
_T_762 <= io_in_a_bits_param;
end
if (_T_792) begin
_T_764 <= io_in_a_bits_size;
end
if (_T_792) begin
_T_766 <= io_in_a_bits_source;
end
if (_T_792) begin
_T_768 <= io_in_a_bits_address;
end
if (reset) begin
_T_802 <= 5'h0;
end else begin
if (_T_793) begin
if (_T_806) begin
if (_T_799) begin
_T_802 <= _T_798;
end else begin
_T_802 <= 5'h0;
end
end else begin
_T_802 <= _T_805;
end
end
end
if (_T_853) begin
_T_815 <= io_in_d_bits_opcode;
end
if (_T_853) begin
_T_819 <= io_in_d_bits_size;
end
if (_T_853) begin
_T_821 <= io_in_d_bits_source;
end
if (_T_853) begin
_T_825 <= io_in_d_bits_denied;
end
if (reset) begin
_T_855 <= 25'h0;
end else begin
_T_855 <= _T_935;
end
if (reset) begin
_T_866 <= 5'h0;
end else begin
if (_T_737) begin
if (_T_870) begin
if (_T_744) begin
_T_866 <= _T_742;
end else begin
_T_866 <= 5'h0;
end
end else begin
_T_866 <= _T_869;
end
end
end
if (reset) begin
_T_887 <= 5'h0;
end else begin
if (_T_793) begin
if (_T_891) begin
if (_T_799) begin
_T_887 <= _T_798;
end else begin
_T_887 <= 5'h0;
end
end else begin
_T_887 <= _T_890;
end
end
end
if (reset) begin
_T_937 <= 32'h0;
end else begin
if (_T_951) begin
_T_937 <= 32'h0;
end else begin
_T_937 <= _T_948;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:136:60)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@18763.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@18764.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@18942.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@18943.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@18959.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@18960.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:136:60)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@19011.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@19012.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@19018.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@19019.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@19026.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@19027.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@19033.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@19034.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@19041.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@19042.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@19050.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@19051.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@19058.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@19059.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@19076.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@19077.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:136:60)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@19128.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@19129.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@19135.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@19136.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@19143.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@19144.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@19150.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@19151.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@19158.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@19159.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:136:60)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@19166.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@19167.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@19175.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@19176.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@19183.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@19184.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19204.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@19205.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@19211.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@19212.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@19218.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@19219.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@19226.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@19227.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@19234.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@19235.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@19242.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@19243.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_426) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19263.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_426) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@19264.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@19270.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@19271.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@19277.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@19278.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@19285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@19286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@19293.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@19294.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_426) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@19314.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_426) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@19315.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@19321.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@19322.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@19328.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@19329.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@19336.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@19337.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@19346.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@19347.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@19364.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@19365.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@19371.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@19372.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@19378.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@19379.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@19386.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@19387.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@19394.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@19395.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@19412.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@19413.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@19419.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@19420.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@19426.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@19427.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@19434.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@19435.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@19442.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@19443.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:136:60)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@19460.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@19461.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@19467.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@19468.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:136:60)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@19474.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@19475.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:136:60)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@19482.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@19483.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@19490.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@19491.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:136:60)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@19501.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@19502.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19548.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@19549.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@19556.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@19557.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@19564.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@19565.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@19572.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_611) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@19573.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_615) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@19580.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_615) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@19581.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@19590.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_599) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@19591.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@19597.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@19598.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@19605.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_603) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@19606.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@19613.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@19614.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@19621.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@19622.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@19629.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_611) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@19630.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@19638.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@19639.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@19648.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@19649.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@19655.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@19656.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:136:60)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@19663.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_603) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@19664.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@19671.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@19672.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@19679.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@19680.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_667) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@19688.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_667) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@19689.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@19697.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@19698.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@19707.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_599) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@19708.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@19715.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@19716.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@19723.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_611) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@19724.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@19732.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@19733.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@19742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_599) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@19743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@19750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@19751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_667) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@19759.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_667) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@19760.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@19768.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@19769.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@19778.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_599) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@19779.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:136:60)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@19786.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@19787.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_611) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:136:60)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@19794.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_611) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@19795.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:136:60)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@19803.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@19804.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:136:60)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@19813.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@19814.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:136:60)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@19821.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@19822.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:136:60)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@19829.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@19830.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_774) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@19869.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_774) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@19870.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_778) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@19877.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_778) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@19878.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_782) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@19885.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_782) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@19886.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_786) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@19893.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_786) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@19894.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_790) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@19901.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_790) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@19902.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_831) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@19951.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_831) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@19952.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@19959.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@19960.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_839) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@19967.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_839) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@19968.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@19975.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_843) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@19976.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@19983.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@19984.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_851) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:136:60)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@19991.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_851) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@19992.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_902 & _T_910) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:136:60)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@20069.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_902 & _T_910) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@20070.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918 & _T_925) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:136:60)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@20092.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918 & _T_925) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@20093.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_932) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:136:60)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@20104.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_932) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@20105.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:136:60)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@20124.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@20125.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLBuffer_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@20137.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20138.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20139.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [30:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [30:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@20140.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [30:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
TLMonitor_6 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@20147.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20187.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20186.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20149.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20150.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@20183.4]
endmodule
module SimpleLazyModule_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@20197.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20198.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20199.4]
output auto_buffer_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_buffer_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [2:0] auto_buffer_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [2:0] auto_buffer_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [3:0] auto_buffer_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [4:0] auto_buffer_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [30:0] auto_buffer_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [7:0] auto_buffer_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [63:0] auto_buffer_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_buffer_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_buffer_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_buffer_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [2:0] auto_buffer_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_buffer_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [4:0] auto_buffer_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_buffer_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [63:0] auto_buffer_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_buffer_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_axi4buf_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_axi4buf_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [30:0] auto_axi4buf_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [7:0] auto_axi4buf_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [2:0] auto_axi4buf_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [1:0] auto_axi4buf_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_axi4buf_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [2:0] auto_axi4buf_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_axi4buf_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_axi4buf_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [63:0] auto_axi4buf_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [7:0] auto_axi4buf_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_axi4buf_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [3:0] auto_axi4buf_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [1:0] auto_axi4buf_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_axi4buf_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_axi4buf_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [30:0] auto_axi4buf_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [7:0] auto_axi4buf_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [2:0] auto_axi4buf_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [1:0] auto_axi4buf_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_axi4buf_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [2:0] auto_axi4buf_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output [3:0] auto_axi4buf_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
output auto_axi4buf_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_axi4buf_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [3:0] auto_axi4buf_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [63:0] auto_axi4buf_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input [1:0] auto_axi4buf_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
input auto_axi4buf_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@20200.4]
);
wire axi4buf_clock; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_reset; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_aw_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_aw_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_aw_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [30:0] axi4buf_auto_in_aw_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [7:0] axi4buf_auto_in_aw_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_in_aw_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_in_aw_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_aw_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_aw_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_in_aw_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_aw_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_w_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_w_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [63:0] axi4buf_auto_in_w_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [7:0] axi4buf_auto_in_w_bits_strb; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_w_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_b_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_b_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_b_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_in_b_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_ar_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_ar_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_ar_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [30:0] axi4buf_auto_in_ar_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [7:0] axi4buf_auto_in_ar_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_in_ar_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_in_ar_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_ar_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_ar_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_in_ar_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_ar_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_r_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_r_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_in_r_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [63:0] axi4buf_auto_in_r_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_in_r_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_in_r_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_aw_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_aw_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_aw_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [30:0] axi4buf_auto_out_aw_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [7:0] axi4buf_auto_out_aw_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_out_aw_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_out_aw_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_aw_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_aw_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_out_aw_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_aw_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_w_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_w_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [63:0] axi4buf_auto_out_w_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [7:0] axi4buf_auto_out_w_bits_strb; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_w_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_b_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_b_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_b_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_out_b_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_ar_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_ar_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_ar_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [30:0] axi4buf_auto_out_ar_bits_addr; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [7:0] axi4buf_auto_out_ar_bits_len; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_out_ar_bits_size; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_out_ar_bits_burst; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_ar_bits_lock; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_ar_bits_cache; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [2:0] axi4buf_auto_out_ar_bits_prot; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_ar_bits_qos; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_r_ready; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_r_valid; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [3:0] axi4buf_auto_out_r_bits_id; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [63:0] axi4buf_auto_out_r_bits_data; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire [1:0] axi4buf_auto_out_r_bits_resp; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4buf_auto_out_r_bits_last; // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
wire axi4yank_clock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_reset; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [30:0] axi4yank_auto_in_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [7:0] axi4yank_auto_in_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_in_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_in_aw_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_aw_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_aw_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_in_aw_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_aw_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [8:0] axi4yank_auto_in_aw_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [63:0] axi4yank_auto_in_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [7:0] axi4yank_auto_in_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [8:0] axi4yank_auto_in_b_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [30:0] axi4yank_auto_in_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [7:0] axi4yank_auto_in_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_in_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_in_ar_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_ar_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_ar_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_in_ar_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_ar_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [8:0] axi4yank_auto_in_ar_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_in_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [63:0] axi4yank_auto_in_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [8:0] axi4yank_auto_in_r_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_in_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [30:0] axi4yank_auto_out_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [7:0] axi4yank_auto_out_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_out_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_out_aw_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_aw_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_aw_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_out_aw_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_aw_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [63:0] axi4yank_auto_out_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [7:0] axi4yank_auto_out_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_out_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [30:0] axi4yank_auto_out_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [7:0] axi4yank_auto_out_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_out_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_out_ar_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_ar_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_ar_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [2:0] axi4yank_auto_out_ar_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_ar_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [3:0] axi4yank_auto_out_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [63:0] axi4yank_auto_out_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire [1:0] axi4yank_auto_out_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4yank_auto_out_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
wire axi4deint_clock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_reset; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_aw_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_aw_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_aw_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [30:0] axi4deint_auto_in_aw_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [7:0] axi4deint_auto_in_aw_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_in_aw_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_in_aw_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_aw_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_aw_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_in_aw_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_aw_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_in_aw_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_w_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_w_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [63:0] axi4deint_auto_in_w_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [7:0] axi4deint_auto_in_w_bits_strb; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_w_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_b_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_b_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_b_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_in_b_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_in_b_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_ar_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_ar_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_ar_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [30:0] axi4deint_auto_in_ar_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [7:0] axi4deint_auto_in_ar_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_in_ar_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_in_ar_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_ar_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_ar_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_in_ar_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_ar_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_in_ar_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_r_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_r_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_in_r_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [63:0] axi4deint_auto_in_r_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_in_r_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_in_r_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_in_r_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_aw_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_aw_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_aw_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [30:0] axi4deint_auto_out_aw_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [7:0] axi4deint_auto_out_aw_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_out_aw_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_out_aw_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_aw_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_aw_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_out_aw_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_aw_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_out_aw_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_w_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_w_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [63:0] axi4deint_auto_out_w_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [7:0] axi4deint_auto_out_w_bits_strb; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_w_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_b_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_b_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_b_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_out_b_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_out_b_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_ar_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_ar_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_ar_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [30:0] axi4deint_auto_out_ar_bits_addr; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [7:0] axi4deint_auto_out_ar_bits_len; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_out_ar_bits_size; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_out_ar_bits_burst; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_ar_bits_lock; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_ar_bits_cache; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [2:0] axi4deint_auto_out_ar_bits_prot; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_ar_bits_qos; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_out_ar_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_r_ready; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_r_valid; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [3:0] axi4deint_auto_out_r_bits_id; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [63:0] axi4deint_auto_out_r_bits_data; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [1:0] axi4deint_auto_out_r_bits_resp; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire [8:0] axi4deint_auto_out_r_bits_user; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4deint_auto_out_r_bits_last; // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
wire axi4index_auto_in_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [30:0] axi4index_auto_in_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [7:0] axi4index_auto_in_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_in_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_aw_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_in_aw_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_aw_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_in_aw_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_in_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [63:0] axi4index_auto_in_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [7:0] axi4index_auto_in_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_in_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [30:0] axi4index_auto_in_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [7:0] axi4index_auto_in_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_in_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_ar_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_in_ar_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_ar_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_in_ar_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_in_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_in_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [63:0] axi4index_auto_in_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_in_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_in_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [30:0] axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [7:0] axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_out_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [63:0] axi4index_auto_out_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [7:0] axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_out_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_out_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [30:0] axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [7:0] axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [2:0] axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_out_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [3:0] axi4index_auto_out_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [63:0] axi4index_auto_out_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [1:0] axi4index_auto_out_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire [8:0] axi4index_auto_out_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire axi4index_auto_out_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
wire tl2axi4_clock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_reset; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_a_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_a_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_in_a_bits_opcode; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_in_a_bits_param; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [3:0] tl2axi4_auto_in_a_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [4:0] tl2axi4_auto_in_a_bits_source; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [30:0] tl2axi4_auto_in_a_bits_address; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [7:0] tl2axi4_auto_in_a_bits_mask; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [63:0] tl2axi4_auto_in_a_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_a_bits_corrupt; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_d_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_d_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_in_d_bits_opcode; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [3:0] tl2axi4_auto_in_d_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [4:0] tl2axi4_auto_in_d_bits_source; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_d_bits_denied; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [63:0] tl2axi4_auto_in_d_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_in_d_bits_corrupt; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_aw_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [30:0] tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [7:0] tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [1:0] tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [3:0] tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [3:0] tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [8:0] tl2axi4_auto_out_aw_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_w_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_w_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [63:0] tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [7:0] tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_b_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_b_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_b_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [1:0] tl2axi4_auto_out_b_bits_resp; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [8:0] tl2axi4_auto_out_b_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_ar_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [30:0] tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [7:0] tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [1:0] tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [3:0] tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [3:0] tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [8:0] tl2axi4_auto_out_ar_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_r_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_r_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [2:0] tl2axi4_auto_out_r_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [63:0] tl2axi4_auto_out_r_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [1:0] tl2axi4_auto_out_r_bits_resp; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire [8:0] tl2axi4_auto_out_r_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire tl2axi4_auto_out_r_bits_last; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [4:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [30:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [4:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [4:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [30:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [4:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [30:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [30:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
AXI4Buffer axi4buf ( // @[Buffer.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@20205.4]
.clock(axi4buf_clock),
.reset(axi4buf_reset),
.auto_in_aw_ready(axi4buf_auto_in_aw_ready),
.auto_in_aw_valid(axi4buf_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4buf_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4buf_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4buf_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4buf_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4buf_auto_in_aw_bits_burst),
.auto_in_aw_bits_lock(axi4buf_auto_in_aw_bits_lock),
.auto_in_aw_bits_cache(axi4buf_auto_in_aw_bits_cache),
.auto_in_aw_bits_prot(axi4buf_auto_in_aw_bits_prot),
.auto_in_aw_bits_qos(axi4buf_auto_in_aw_bits_qos),
.auto_in_w_ready(axi4buf_auto_in_w_ready),
.auto_in_w_valid(axi4buf_auto_in_w_valid),
.auto_in_w_bits_data(axi4buf_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4buf_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4buf_auto_in_w_bits_last),
.auto_in_b_ready(axi4buf_auto_in_b_ready),
.auto_in_b_valid(axi4buf_auto_in_b_valid),
.auto_in_b_bits_id(axi4buf_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4buf_auto_in_b_bits_resp),
.auto_in_ar_ready(axi4buf_auto_in_ar_ready),
.auto_in_ar_valid(axi4buf_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4buf_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4buf_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4buf_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4buf_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4buf_auto_in_ar_bits_burst),
.auto_in_ar_bits_lock(axi4buf_auto_in_ar_bits_lock),
.auto_in_ar_bits_cache(axi4buf_auto_in_ar_bits_cache),
.auto_in_ar_bits_prot(axi4buf_auto_in_ar_bits_prot),
.auto_in_ar_bits_qos(axi4buf_auto_in_ar_bits_qos),
.auto_in_r_ready(axi4buf_auto_in_r_ready),
.auto_in_r_valid(axi4buf_auto_in_r_valid),
.auto_in_r_bits_id(axi4buf_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4buf_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4buf_auto_in_r_bits_resp),
.auto_in_r_bits_last(axi4buf_auto_in_r_bits_last),
.auto_out_aw_ready(axi4buf_auto_out_aw_ready),
.auto_out_aw_valid(axi4buf_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4buf_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4buf_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4buf_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4buf_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4buf_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(axi4buf_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(axi4buf_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(axi4buf_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(axi4buf_auto_out_aw_bits_qos),
.auto_out_w_ready(axi4buf_auto_out_w_ready),
.auto_out_w_valid(axi4buf_auto_out_w_valid),
.auto_out_w_bits_data(axi4buf_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4buf_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4buf_auto_out_w_bits_last),
.auto_out_b_ready(axi4buf_auto_out_b_ready),
.auto_out_b_valid(axi4buf_auto_out_b_valid),
.auto_out_b_bits_id(axi4buf_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4buf_auto_out_b_bits_resp),
.auto_out_ar_ready(axi4buf_auto_out_ar_ready),
.auto_out_ar_valid(axi4buf_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4buf_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4buf_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4buf_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4buf_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4buf_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(axi4buf_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(axi4buf_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(axi4buf_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(axi4buf_auto_out_ar_bits_qos),
.auto_out_r_ready(axi4buf_auto_out_r_ready),
.auto_out_r_valid(axi4buf_auto_out_r_valid),
.auto_out_r_bits_id(axi4buf_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4buf_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4buf_auto_out_r_bits_resp),
.auto_out_r_bits_last(axi4buf_auto_out_r_bits_last)
);
AXI4UserYanker axi4yank ( // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@20211.4]
.clock(axi4yank_clock),
.reset(axi4yank_reset),
.auto_in_aw_ready(axi4yank_auto_in_aw_ready),
.auto_in_aw_valid(axi4yank_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4yank_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4yank_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4yank_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4yank_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4yank_auto_in_aw_bits_burst),
.auto_in_aw_bits_lock(axi4yank_auto_in_aw_bits_lock),
.auto_in_aw_bits_cache(axi4yank_auto_in_aw_bits_cache),
.auto_in_aw_bits_prot(axi4yank_auto_in_aw_bits_prot),
.auto_in_aw_bits_qos(axi4yank_auto_in_aw_bits_qos),
.auto_in_aw_bits_user(axi4yank_auto_in_aw_bits_user),
.auto_in_w_ready(axi4yank_auto_in_w_ready),
.auto_in_w_valid(axi4yank_auto_in_w_valid),
.auto_in_w_bits_data(axi4yank_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4yank_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4yank_auto_in_w_bits_last),
.auto_in_b_ready(axi4yank_auto_in_b_ready),
.auto_in_b_valid(axi4yank_auto_in_b_valid),
.auto_in_b_bits_id(axi4yank_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4yank_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4yank_auto_in_b_bits_user),
.auto_in_ar_ready(axi4yank_auto_in_ar_ready),
.auto_in_ar_valid(axi4yank_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4yank_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4yank_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4yank_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4yank_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4yank_auto_in_ar_bits_burst),
.auto_in_ar_bits_lock(axi4yank_auto_in_ar_bits_lock),
.auto_in_ar_bits_cache(axi4yank_auto_in_ar_bits_cache),
.auto_in_ar_bits_prot(axi4yank_auto_in_ar_bits_prot),
.auto_in_ar_bits_qos(axi4yank_auto_in_ar_bits_qos),
.auto_in_ar_bits_user(axi4yank_auto_in_ar_bits_user),
.auto_in_r_ready(axi4yank_auto_in_r_ready),
.auto_in_r_valid(axi4yank_auto_in_r_valid),
.auto_in_r_bits_id(axi4yank_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4yank_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4yank_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4yank_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4yank_auto_in_r_bits_last),
.auto_out_aw_ready(axi4yank_auto_out_aw_ready),
.auto_out_aw_valid(axi4yank_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4yank_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4yank_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4yank_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4yank_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4yank_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(axi4yank_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(axi4yank_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(axi4yank_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(axi4yank_auto_out_aw_bits_qos),
.auto_out_w_ready(axi4yank_auto_out_w_ready),
.auto_out_w_valid(axi4yank_auto_out_w_valid),
.auto_out_w_bits_data(axi4yank_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4yank_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4yank_auto_out_w_bits_last),
.auto_out_b_ready(axi4yank_auto_out_b_ready),
.auto_out_b_valid(axi4yank_auto_out_b_valid),
.auto_out_b_bits_id(axi4yank_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4yank_auto_out_b_bits_resp),
.auto_out_ar_ready(axi4yank_auto_out_ar_ready),
.auto_out_ar_valid(axi4yank_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4yank_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4yank_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4yank_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4yank_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4yank_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(axi4yank_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(axi4yank_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(axi4yank_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(axi4yank_auto_out_ar_bits_qos),
.auto_out_r_ready(axi4yank_auto_out_r_ready),
.auto_out_r_valid(axi4yank_auto_out_r_valid),
.auto_out_r_bits_id(axi4yank_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4yank_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4yank_auto_out_r_bits_resp),
.auto_out_r_bits_last(axi4yank_auto_out_r_bits_last)
);
AXI4Deinterleaver axi4deint ( // @[Deinterleaver.scala 104:31:freechips.rocketchip.system.LowRiscConfig.fir@20217.4]
.clock(axi4deint_clock),
.reset(axi4deint_reset),
.auto_in_aw_ready(axi4deint_auto_in_aw_ready),
.auto_in_aw_valid(axi4deint_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4deint_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4deint_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4deint_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4deint_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4deint_auto_in_aw_bits_burst),
.auto_in_aw_bits_lock(axi4deint_auto_in_aw_bits_lock),
.auto_in_aw_bits_cache(axi4deint_auto_in_aw_bits_cache),
.auto_in_aw_bits_prot(axi4deint_auto_in_aw_bits_prot),
.auto_in_aw_bits_qos(axi4deint_auto_in_aw_bits_qos),
.auto_in_aw_bits_user(axi4deint_auto_in_aw_bits_user),
.auto_in_w_ready(axi4deint_auto_in_w_ready),
.auto_in_w_valid(axi4deint_auto_in_w_valid),
.auto_in_w_bits_data(axi4deint_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4deint_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4deint_auto_in_w_bits_last),
.auto_in_b_ready(axi4deint_auto_in_b_ready),
.auto_in_b_valid(axi4deint_auto_in_b_valid),
.auto_in_b_bits_id(axi4deint_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4deint_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4deint_auto_in_b_bits_user),
.auto_in_ar_ready(axi4deint_auto_in_ar_ready),
.auto_in_ar_valid(axi4deint_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4deint_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4deint_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4deint_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4deint_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4deint_auto_in_ar_bits_burst),
.auto_in_ar_bits_lock(axi4deint_auto_in_ar_bits_lock),
.auto_in_ar_bits_cache(axi4deint_auto_in_ar_bits_cache),
.auto_in_ar_bits_prot(axi4deint_auto_in_ar_bits_prot),
.auto_in_ar_bits_qos(axi4deint_auto_in_ar_bits_qos),
.auto_in_ar_bits_user(axi4deint_auto_in_ar_bits_user),
.auto_in_r_ready(axi4deint_auto_in_r_ready),
.auto_in_r_valid(axi4deint_auto_in_r_valid),
.auto_in_r_bits_id(axi4deint_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4deint_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4deint_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4deint_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4deint_auto_in_r_bits_last),
.auto_out_aw_ready(axi4deint_auto_out_aw_ready),
.auto_out_aw_valid(axi4deint_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4deint_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4deint_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4deint_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4deint_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4deint_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(axi4deint_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(axi4deint_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(axi4deint_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(axi4deint_auto_out_aw_bits_qos),
.auto_out_aw_bits_user(axi4deint_auto_out_aw_bits_user),
.auto_out_w_ready(axi4deint_auto_out_w_ready),
.auto_out_w_valid(axi4deint_auto_out_w_valid),
.auto_out_w_bits_data(axi4deint_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4deint_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4deint_auto_out_w_bits_last),
.auto_out_b_ready(axi4deint_auto_out_b_ready),
.auto_out_b_valid(axi4deint_auto_out_b_valid),
.auto_out_b_bits_id(axi4deint_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4deint_auto_out_b_bits_resp),
.auto_out_b_bits_user(axi4deint_auto_out_b_bits_user),
.auto_out_ar_ready(axi4deint_auto_out_ar_ready),
.auto_out_ar_valid(axi4deint_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4deint_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4deint_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4deint_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4deint_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4deint_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(axi4deint_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(axi4deint_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(axi4deint_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(axi4deint_auto_out_ar_bits_qos),
.auto_out_ar_bits_user(axi4deint_auto_out_ar_bits_user),
.auto_out_r_ready(axi4deint_auto_out_r_ready),
.auto_out_r_valid(axi4deint_auto_out_r_valid),
.auto_out_r_bits_id(axi4deint_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4deint_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4deint_auto_out_r_bits_resp),
.auto_out_r_bits_user(axi4deint_auto_out_r_bits_user),
.auto_out_r_bits_last(axi4deint_auto_out_r_bits_last)
);
AXI4IdIndexer axi4index ( // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@20223.4]
.auto_in_aw_ready(axi4index_auto_in_aw_ready),
.auto_in_aw_valid(axi4index_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4index_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4index_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4index_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4index_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4index_auto_in_aw_bits_burst),
.auto_in_aw_bits_lock(axi4index_auto_in_aw_bits_lock),
.auto_in_aw_bits_cache(axi4index_auto_in_aw_bits_cache),
.auto_in_aw_bits_prot(axi4index_auto_in_aw_bits_prot),
.auto_in_aw_bits_qos(axi4index_auto_in_aw_bits_qos),
.auto_in_aw_bits_user(axi4index_auto_in_aw_bits_user),
.auto_in_w_ready(axi4index_auto_in_w_ready),
.auto_in_w_valid(axi4index_auto_in_w_valid),
.auto_in_w_bits_data(axi4index_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4index_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4index_auto_in_w_bits_last),
.auto_in_b_ready(axi4index_auto_in_b_ready),
.auto_in_b_valid(axi4index_auto_in_b_valid),
.auto_in_b_bits_id(axi4index_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4index_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4index_auto_in_b_bits_user),
.auto_in_ar_ready(axi4index_auto_in_ar_ready),
.auto_in_ar_valid(axi4index_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4index_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4index_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4index_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4index_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4index_auto_in_ar_bits_burst),
.auto_in_ar_bits_lock(axi4index_auto_in_ar_bits_lock),
.auto_in_ar_bits_cache(axi4index_auto_in_ar_bits_cache),
.auto_in_ar_bits_prot(axi4index_auto_in_ar_bits_prot),
.auto_in_ar_bits_qos(axi4index_auto_in_ar_bits_qos),
.auto_in_ar_bits_user(axi4index_auto_in_ar_bits_user),
.auto_in_r_ready(axi4index_auto_in_r_ready),
.auto_in_r_valid(axi4index_auto_in_r_valid),
.auto_in_r_bits_id(axi4index_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4index_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4index_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4index_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4index_auto_in_r_bits_last),
.auto_out_aw_ready(axi4index_auto_out_aw_ready),
.auto_out_aw_valid(axi4index_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4index_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4index_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4index_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4index_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4index_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(axi4index_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(axi4index_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(axi4index_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(axi4index_auto_out_aw_bits_qos),
.auto_out_aw_bits_user(axi4index_auto_out_aw_bits_user),
.auto_out_w_ready(axi4index_auto_out_w_ready),
.auto_out_w_valid(axi4index_auto_out_w_valid),
.auto_out_w_bits_data(axi4index_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4index_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4index_auto_out_w_bits_last),
.auto_out_b_ready(axi4index_auto_out_b_ready),
.auto_out_b_valid(axi4index_auto_out_b_valid),
.auto_out_b_bits_id(axi4index_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4index_auto_out_b_bits_resp),
.auto_out_b_bits_user(axi4index_auto_out_b_bits_user),
.auto_out_ar_ready(axi4index_auto_out_ar_ready),
.auto_out_ar_valid(axi4index_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4index_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4index_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4index_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4index_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4index_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(axi4index_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(axi4index_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(axi4index_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(axi4index_auto_out_ar_bits_qos),
.auto_out_ar_bits_user(axi4index_auto_out_ar_bits_user),
.auto_out_r_ready(axi4index_auto_out_r_ready),
.auto_out_r_valid(axi4index_auto_out_r_valid),
.auto_out_r_bits_id(axi4index_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4index_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4index_auto_out_r_bits_resp),
.auto_out_r_bits_user(axi4index_auto_out_r_bits_user),
.auto_out_r_bits_last(axi4index_auto_out_r_bits_last)
);
TLToAXI4 tl2axi4 ( // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@20229.4]
.clock(tl2axi4_clock),
.reset(tl2axi4_reset),
.auto_in_a_ready(tl2axi4_auto_in_a_ready),
.auto_in_a_valid(tl2axi4_auto_in_a_valid),
.auto_in_a_bits_opcode(tl2axi4_auto_in_a_bits_opcode),
.auto_in_a_bits_param(tl2axi4_auto_in_a_bits_param),
.auto_in_a_bits_size(tl2axi4_auto_in_a_bits_size),
.auto_in_a_bits_source(tl2axi4_auto_in_a_bits_source),
.auto_in_a_bits_address(tl2axi4_auto_in_a_bits_address),
.auto_in_a_bits_mask(tl2axi4_auto_in_a_bits_mask),
.auto_in_a_bits_data(tl2axi4_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(tl2axi4_auto_in_a_bits_corrupt),
.auto_in_d_ready(tl2axi4_auto_in_d_ready),
.auto_in_d_valid(tl2axi4_auto_in_d_valid),
.auto_in_d_bits_opcode(tl2axi4_auto_in_d_bits_opcode),
.auto_in_d_bits_size(tl2axi4_auto_in_d_bits_size),
.auto_in_d_bits_source(tl2axi4_auto_in_d_bits_source),
.auto_in_d_bits_denied(tl2axi4_auto_in_d_bits_denied),
.auto_in_d_bits_data(tl2axi4_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(tl2axi4_auto_in_d_bits_corrupt),
.auto_out_aw_ready(tl2axi4_auto_out_aw_ready),
.auto_out_aw_valid(tl2axi4_auto_out_aw_valid),
.auto_out_aw_bits_id(tl2axi4_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(tl2axi4_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(tl2axi4_auto_out_aw_bits_len),
.auto_out_aw_bits_size(tl2axi4_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(tl2axi4_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(tl2axi4_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(tl2axi4_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(tl2axi4_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(tl2axi4_auto_out_aw_bits_qos),
.auto_out_aw_bits_user(tl2axi4_auto_out_aw_bits_user),
.auto_out_w_ready(tl2axi4_auto_out_w_ready),
.auto_out_w_valid(tl2axi4_auto_out_w_valid),
.auto_out_w_bits_data(tl2axi4_auto_out_w_bits_data),
.auto_out_w_bits_strb(tl2axi4_auto_out_w_bits_strb),
.auto_out_w_bits_last(tl2axi4_auto_out_w_bits_last),
.auto_out_b_ready(tl2axi4_auto_out_b_ready),
.auto_out_b_valid(tl2axi4_auto_out_b_valid),
.auto_out_b_bits_id(tl2axi4_auto_out_b_bits_id),
.auto_out_b_bits_resp(tl2axi4_auto_out_b_bits_resp),
.auto_out_b_bits_user(tl2axi4_auto_out_b_bits_user),
.auto_out_ar_ready(tl2axi4_auto_out_ar_ready),
.auto_out_ar_valid(tl2axi4_auto_out_ar_valid),
.auto_out_ar_bits_id(tl2axi4_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(tl2axi4_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(tl2axi4_auto_out_ar_bits_len),
.auto_out_ar_bits_size(tl2axi4_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(tl2axi4_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(tl2axi4_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(tl2axi4_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(tl2axi4_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(tl2axi4_auto_out_ar_bits_qos),
.auto_out_ar_bits_user(tl2axi4_auto_out_ar_bits_user),
.auto_out_r_ready(tl2axi4_auto_out_r_ready),
.auto_out_r_valid(tl2axi4_auto_out_r_valid),
.auto_out_r_bits_id(tl2axi4_auto_out_r_bits_id),
.auto_out_r_bits_data(tl2axi4_auto_out_r_bits_data),
.auto_out_r_bits_resp(tl2axi4_auto_out_r_bits_resp),
.auto_out_r_bits_user(tl2axi4_auto_out_r_bits_user),
.auto_out_r_bits_last(tl2axi4_auto_out_r_bits_last)
);
TLWidthWidget widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@20235.4]
.clock(widget_clock),
.reset(widget_reset),
.auto_in_a_ready(widget_auto_in_a_ready),
.auto_in_a_valid(widget_auto_in_a_valid),
.auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
.auto_in_a_bits_param(widget_auto_in_a_bits_param),
.auto_in_a_bits_size(widget_auto_in_a_bits_size),
.auto_in_a_bits_source(widget_auto_in_a_bits_source),
.auto_in_a_bits_address(widget_auto_in_a_bits_address),
.auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
.auto_in_a_bits_data(widget_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
.auto_in_d_ready(widget_auto_in_d_ready),
.auto_in_d_valid(widget_auto_in_d_valid),
.auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
.auto_in_d_bits_size(widget_auto_in_d_bits_size),
.auto_in_d_bits_source(widget_auto_in_d_bits_source),
.auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
.auto_in_d_bits_data(widget_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
.auto_out_a_ready(widget_auto_out_a_ready),
.auto_out_a_valid(widget_auto_out_a_valid),
.auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
.auto_out_a_bits_param(widget_auto_out_a_bits_param),
.auto_out_a_bits_size(widget_auto_out_a_bits_size),
.auto_out_a_bits_source(widget_auto_out_a_bits_source),
.auto_out_a_bits_address(widget_auto_out_a_bits_address),
.auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
.auto_out_a_bits_data(widget_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
.auto_out_d_ready(widget_auto_out_d_ready),
.auto_out_d_valid(widget_auto_out_d_valid),
.auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
.auto_out_d_bits_size(widget_auto_out_d_bits_size),
.auto_out_d_bits_source(widget_auto_out_d_bits_source),
.auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
.auto_out_d_bits_data(widget_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
);
TLBuffer_1 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@20241.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
);
assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign auto_axi4buf_out_aw_valid = axi4buf_auto_out_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_id = axi4buf_auto_out_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_addr = axi4buf_auto_out_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_len = axi4buf_auto_out_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_size = axi4buf_auto_out_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_burst = axi4buf_auto_out_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_lock = axi4buf_auto_out_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_cache = axi4buf_auto_out_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_prot = axi4buf_auto_out_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_aw_bits_qos = axi4buf_auto_out_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_w_valid = axi4buf_auto_out_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_w_bits_data = axi4buf_auto_out_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_w_bits_strb = axi4buf_auto_out_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_w_bits_last = axi4buf_auto_out_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_b_ready = axi4buf_auto_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_valid = axi4buf_auto_out_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_id = axi4buf_auto_out_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_addr = axi4buf_auto_out_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_len = axi4buf_auto_out_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_size = axi4buf_auto_out_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_burst = axi4buf_auto_out_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_lock = axi4buf_auto_out_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_cache = axi4buf_auto_out_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_prot = axi4buf_auto_out_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_ar_bits_qos = axi4buf_auto_out_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign auto_axi4buf_out_r_ready = axi4buf_auto_out_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20209.4]
assign axi4buf_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20210.4]
assign axi4buf_auto_in_aw_valid = axi4yank_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_id = axi4yank_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_addr = axi4yank_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_len = axi4yank_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_size = axi4yank_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_burst = axi4yank_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_lock = axi4yank_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_cache = axi4yank_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_prot = axi4yank_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_aw_bits_qos = axi4yank_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_w_valid = axi4yank_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_w_bits_data = axi4yank_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_w_bits_strb = axi4yank_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_w_bits_last = axi4yank_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_b_ready = axi4yank_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_valid = axi4yank_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_id = axi4yank_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_addr = axi4yank_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_len = axi4yank_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_size = axi4yank_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_burst = axi4yank_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_lock = axi4yank_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_cache = axi4yank_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_prot = axi4yank_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_ar_bits_qos = axi4yank_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_in_r_ready = axi4yank_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4buf_auto_out_aw_ready = auto_axi4buf_out_aw_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_w_ready = auto_axi4buf_out_w_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_b_valid = auto_axi4buf_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_b_bits_id = auto_axi4buf_out_b_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_b_bits_resp = auto_axi4buf_out_b_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_ar_ready = auto_axi4buf_out_ar_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_r_valid = auto_axi4buf_out_r_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_r_bits_id = auto_axi4buf_out_r_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_r_bits_data = auto_axi4buf_out_r_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_r_bits_resp = auto_axi4buf_out_r_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4buf_auto_out_r_bits_last = auto_axi4buf_out_r_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@20253.4]
assign axi4yank_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20215.4]
assign axi4yank_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20216.4]
assign axi4yank_auto_in_aw_valid = axi4deint_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_id = axi4deint_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_addr = axi4deint_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_len = axi4deint_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_size = axi4deint_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_burst = axi4deint_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_lock = axi4deint_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_cache = axi4deint_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_prot = axi4deint_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_qos = axi4deint_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_aw_bits_user = axi4deint_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_w_valid = axi4deint_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_w_bits_data = axi4deint_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_w_bits_strb = axi4deint_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_w_bits_last = axi4deint_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_b_ready = axi4deint_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_valid = axi4deint_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_id = axi4deint_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_addr = axi4deint_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_len = axi4deint_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_size = axi4deint_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_burst = axi4deint_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_lock = axi4deint_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_cache = axi4deint_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_prot = axi4deint_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_qos = axi4deint_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_ar_bits_user = axi4deint_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_in_r_ready = axi4deint_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4yank_auto_out_aw_ready = axi4buf_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_w_ready = axi4buf_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_b_valid = axi4buf_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_b_bits_id = axi4buf_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_b_bits_resp = axi4buf_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_ar_ready = axi4buf_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_r_valid = axi4buf_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_r_bits_id = axi4buf_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_r_bits_data = axi4buf_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_r_bits_resp = axi4buf_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4yank_auto_out_r_bits_last = axi4buf_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20247.4]
assign axi4deint_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20221.4]
assign axi4deint_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20222.4]
assign axi4deint_auto_in_aw_valid = axi4index_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_id = axi4index_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_addr = axi4index_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_len = axi4index_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_size = axi4index_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_burst = axi4index_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_lock = axi4index_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_cache = axi4index_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_prot = axi4index_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_qos = axi4index_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_aw_bits_user = axi4index_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_w_valid = axi4index_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_w_bits_data = axi4index_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_w_bits_strb = axi4index_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_w_bits_last = axi4index_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_b_ready = axi4index_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_valid = axi4index_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_id = axi4index_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_addr = axi4index_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_len = axi4index_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_size = axi4index_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_burst = axi4index_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_lock = axi4index_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_cache = axi4index_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_prot = axi4index_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_qos = axi4index_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_ar_bits_user = axi4index_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_in_r_ready = axi4index_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4deint_auto_out_aw_ready = axi4yank_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_w_ready = axi4yank_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_b_valid = axi4yank_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_b_bits_id = axi4yank_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_b_bits_resp = axi4yank_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_b_bits_user = axi4yank_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_ar_ready = axi4yank_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_r_valid = axi4yank_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_r_bits_id = axi4yank_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_r_bits_data = axi4yank_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_r_bits_resp = axi4yank_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_r_bits_user = axi4yank_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4deint_auto_out_r_bits_last = axi4yank_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20248.4]
assign axi4index_auto_in_aw_valid = tl2axi4_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_id = tl2axi4_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_addr = tl2axi4_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_len = tl2axi4_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_size = tl2axi4_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_burst = tl2axi4_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_lock = tl2axi4_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_cache = tl2axi4_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_prot = tl2axi4_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_qos = tl2axi4_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_aw_bits_user = tl2axi4_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_w_valid = tl2axi4_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_w_bits_data = tl2axi4_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_w_bits_strb = tl2axi4_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_w_bits_last = tl2axi4_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_b_ready = tl2axi4_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_valid = tl2axi4_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_id = tl2axi4_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_addr = tl2axi4_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_len = tl2axi4_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_size = tl2axi4_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_burst = tl2axi4_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_lock = tl2axi4_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_cache = tl2axi4_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_prot = tl2axi4_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_qos = tl2axi4_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_ar_bits_user = tl2axi4_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_in_r_ready = tl2axi4_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign axi4index_auto_out_aw_ready = axi4deint_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_w_ready = axi4deint_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_b_valid = axi4deint_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_b_bits_id = axi4deint_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_b_bits_resp = axi4deint_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_b_bits_user = axi4deint_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_ar_ready = axi4deint_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_r_valid = axi4deint_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_r_bits_id = axi4deint_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_r_bits_data = axi4deint_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_r_bits_resp = axi4deint_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_r_bits_user = axi4deint_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign axi4index_auto_out_r_bits_last = axi4deint_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20249.4]
assign tl2axi4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20233.4]
assign tl2axi4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20234.4]
assign tl2axi4_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign tl2axi4_auto_out_aw_ready = axi4index_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_w_ready = axi4index_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_b_valid = axi4index_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_b_bits_id = axi4index_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_b_bits_resp = axi4index_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_b_bits_user = axi4index_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_ar_ready = axi4index_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_r_valid = axi4index_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_r_bits_id = axi4index_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_r_bits_data = axi4index_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_r_bits_resp = axi4index_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_r_bits_user = axi4index_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign tl2axi4_auto_out_r_bits_last = axi4index_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20250.4]
assign widget_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20239.4]
assign widget_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20240.4]
assign widget_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign widget_auto_out_a_ready = tl2axi4_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_valid = tl2axi4_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_bits_opcode = tl2axi4_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_bits_size = tl2axi4_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_bits_source = tl2axi4_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_bits_denied = tl2axi4_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_bits_data = tl2axi4_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign widget_auto_out_d_bits_corrupt = tl2axi4_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20251.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20245.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@20246.4]
assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_data = auto_buffer_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@20254.4]
assign buffer_auto_out_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
assign buffer_auto_out_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@20252.4]
endmodule
module TLMonitor_7( // @[:freechips.rocketchip.system.LowRiscConfig.fir@20263.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20264.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20265.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@20266.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@21853.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@20283.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@20284.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@20289.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@20290.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@20293.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@20294.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@20302.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20314.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20315.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20316.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20317.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@20319.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@20320.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@20321.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@20322.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@20322.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@20323.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@20325.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@20326.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@20327.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@20328.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@20329.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@20330.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@20331.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@20332.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20334.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20335.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20337.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20338.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@20339.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@20340.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@20341.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20342.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20343.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20344.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20345.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20346.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20347.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20348.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20349.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20350.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20351.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20352.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20353.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@20354.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@20355.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@20356.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20357.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20358.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20359.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20360.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20361.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20362.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20363.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20364.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20365.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20366.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20367.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20368.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20369.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20370.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20371.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20372.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20373.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20374.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20375.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20376.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20377.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20378.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20379.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20380.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@20387.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20398.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@20460.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20463.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20464.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20465.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20466.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20467.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20468.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20469.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20470.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20471.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20472.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20473.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20474.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20475.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20476.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20477.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20480.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20481.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20482.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20483.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20484.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20485.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20486.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20487.8]
wire _T_226; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20488.8]
wire _T_227; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20489.8]
wire _T_228; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20490.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@20496.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@20534.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@20535.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@20547.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@20548.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@20554.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@20555.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@20562.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@20563.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@20569.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@20570.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@20575.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@20577.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@20578.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@20583.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@20584.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@20586.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@20587.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@20592.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@20594.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@20595.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@20601.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@20724.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@20726.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@20727.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@20750.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@20753.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20776.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20777.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20778.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@20779.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@20781.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@20789.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@20791.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20793.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20794.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@20813.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@20815.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@20816.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@20821.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@20823.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@20824.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@20838.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@20868.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@20881.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20883.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20884.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@20920.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@20993.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@20994.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@20995.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@20997.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@20998.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@21004.6]
wire _T_620; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@21014.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@21040.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21044.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21045.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@21064.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@21066.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@21067.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@21081.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@21141.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@21143.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@21144.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@21158.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21198.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21199.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@21237.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@21239.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@21240.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@21247.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21248.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@21253.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@21254.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@21257.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21258.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21266.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21278.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21279.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21280.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21281.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@21283.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21286.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21287.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@21292.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@21294.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@21295.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@21300.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@21302.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@21303.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@21308.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@21310.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@21311.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@21316.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@21318.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@21319.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@21325.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@21349.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@21351.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@21352.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@21357.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@21359.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@21360.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@21383.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@21424.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@21426.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@21427.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@21442.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@21477.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@21513.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@21573.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@21578.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@21579.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@21580.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@21582.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21583.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21584.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21585.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21586.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@21597.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@21598.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@21599.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@21600.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@21601.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@21602.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@21603.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@21605.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@21607.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@21608.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@21613.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@21615.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@21616.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@21621.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@21623.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@21624.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@21629.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@21631.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@21632.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@21637.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@21639.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@21640.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@21647.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@21655.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@21657.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@21658.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@21659.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@21660.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@21661.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@21663.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21664.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21665.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21666.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21667.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@21678.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@21679.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@21680.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@21681.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@21682.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@21683.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@21684.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@21685.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@21687.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@21689.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@21690.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@21695.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@21697.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@21698.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@21703.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@21705.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@21706.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@21711.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@21713.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@21714.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@21719.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@21721.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@21722.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@21727.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@21729.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@21730.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@21737.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@21746.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@21756.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21757.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21758.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21759.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21760.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@21779.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21780.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21781.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21782.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21783.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@21798.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@21801.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@21803.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@21804.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@21805.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@21807.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@21808.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@21800.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@21819.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@21821.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@21822.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@21824.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21794.4 :freechips.rocketchip.system.LowRiscConfig.fir@21796.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@21802.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@21826.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@21827.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@21828.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@21830.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@21831.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@21823.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21814.4 :freechips.rocketchip.system.LowRiscConfig.fir@21816.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@21825.6]
wire _T_1152; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@21837.4]
wire _T_1153; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@21838.4]
wire _T_1154; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@21839.4]
wire _T_1155; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@21840.4]
wire _T_1157; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@21842.4]
wire _T_1158; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@21843.4]
wire [24:0] _T_1159; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@21848.4]
wire [24:0] _T_1160; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@21849.4]
wire [24:0] _T_1161; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@21850.4]
reg [31:0] _T_1163; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@21852.4]
reg [31:0] _RAND_16;
wire _T_1164; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@21855.4]
wire _T_1165; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@21856.4]
wire _T_1166; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@21857.4]
wire _T_1167; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@21858.4]
wire _T_1168; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@21859.4]
wire _T_1169; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@21860.4]
wire _T_1171; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@21862.4]
wire _T_1172; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@21863.4]
wire [31:0] _T_1174; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@21869.4]
wire _T_1177; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@21873.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@20498.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@20639.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20796.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20886.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@20968.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21047.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@21124.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21201.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21289.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@21331.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@21389.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@21448.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@21483.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@21519.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@21853.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@20283.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@20284.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@20289.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@20290.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@20293.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@20294.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@20302.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20314.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20315.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20316.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@20317.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@20319.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@20320.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@20321.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@20322.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@20322.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@20323.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@20325.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@20326.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@20327.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@20328.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@20329.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@20330.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@20331.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@20332.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20334.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20335.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20337.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20338.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@20339.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@20340.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@20341.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20342.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20343.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20344.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20345.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20346.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20347.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20348.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20349.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20350.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20351.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20352.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20353.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@20354.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@20355.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@20356.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20357.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20358.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20359.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20360.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20361.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20362.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20363.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20364.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20365.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20366.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20367.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20368.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20369.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20370.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20371.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20372.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20373.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20374.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20375.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20376.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20377.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@20378.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@20379.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@20380.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@20387.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20398.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@20460.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20463.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20464.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20465.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20466.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20467.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20468.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20469.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20470.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20471.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20472.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20473.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20474.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20475.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20476.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20477.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20480.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20481.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20482.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@20483.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@20484.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20485.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@20486.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@20487.8]
assign _T_226 = _T_205 | _T_210; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20488.8]
assign _T_227 = _T_226 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20489.8]
assign _T_228 = _T_227 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20490.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@20496.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@20534.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@20535.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@20547.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@20548.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@20554.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@20555.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@20562.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@20563.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@20569.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@20570.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@20575.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@20577.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@20578.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@20583.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@20584.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@20586.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@20587.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@20592.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@20594.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@20595.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@20601.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@20724.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@20726.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@20727.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@20750.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@20753.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20776.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20777.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@20778.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@20779.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@20781.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@20789.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@20791.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20793.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20794.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@20813.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@20815.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@20816.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@20821.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@20823.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@20824.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@20838.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@20868.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@20881.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20883.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20884.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@20920.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@20993.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@20994.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@20995.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@20997.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@20998.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@21004.6]
assign _T_620 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@21014.8]
assign _T_646 = _T_620 & _T_228; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@21040.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21044.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21045.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@21064.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@21066.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@21067.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@21081.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@21141.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@21143.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@21144.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@21158.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21198.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21199.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@21237.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@21239.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@21240.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@21247.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21248.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@21253.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@21254.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@21257.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21258.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21266.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21278.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21279.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21280.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@21281.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@21283.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21286.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21287.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@21292.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@21294.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@21295.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@21300.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@21302.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@21303.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@21308.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@21310.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@21311.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@21316.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@21318.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@21319.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@21325.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@21349.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@21351.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@21352.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@21357.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@21359.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@21360.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@21383.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@21424.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@21426.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@21427.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@21442.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@21477.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@21513.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@21573.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@21578.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@21579.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@21580.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21583.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21584.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21585.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21586.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@21602.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@21603.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@21605.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@21607.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@21608.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@21613.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@21615.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@21616.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@21621.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@21623.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@21624.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@21629.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@21631.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@21632.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@21637.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@21639.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@21640.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@21647.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@21655.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@21657.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@21658.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@21659.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@21660.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@21661.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21664.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21665.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21666.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21667.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@21684.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@21685.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@21687.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@21689.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@21690.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@21695.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@21697.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@21698.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@21703.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@21705.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@21706.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@21711.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@21713.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@21714.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@21719.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@21721.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@21722.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@21727.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@21729.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@21730.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@21737.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21757.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21758.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21759.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21760.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21780.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21781.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@21782.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@21783.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@21798.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@21801.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@21803.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@21804.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@21805.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@21807.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@21808.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@21800.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@21819.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@21821.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@21822.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@21824.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21794.4 :freechips.rocketchip.system.LowRiscConfig.fir@21796.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@21802.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@21826.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@21827.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@21828.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@21830.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@21831.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@21823.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21814.4 :freechips.rocketchip.system.LowRiscConfig.fir@21816.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@21825.6]
assign _T_1152 = _T_1126 != _T_1138; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@21837.4]
assign _T_1153 = _T_1126 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@21838.4]
assign _T_1154 = _T_1153 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@21839.4]
assign _T_1155 = _T_1152 | _T_1154; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@21840.4]
assign _T_1157 = _T_1155 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@21842.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@21843.4]
assign _T_1159 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@21848.4]
assign _T_1160 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@21849.4]
assign _T_1161 = _T_1159 & _T_1160; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@21850.4]
assign _T_1164 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@21855.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@21856.4]
assign _T_1166 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@21857.4]
assign _T_1167 = _T_1165 | _T_1166; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@21858.4]
assign _T_1168 = _T_1163 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@21859.4]
assign _T_1169 = _T_1167 | _T_1168; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@21860.4]
assign _T_1171 = _T_1169 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@21862.4]
assign _T_1172 = _T_1171 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@21863.4]
assign _T_1174 = _T_1163 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@21869.4]
assign _T_1177 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@21873.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@20498.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@20639.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20796.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20886.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@20968.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21047.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@21124.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21201.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21289.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@21331.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@21389.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@21448.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@21483.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@21519.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1163 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1161;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1163 <= 32'h0;
end else begin
if (_T_1177) begin
_T_1163 <= 32'h0;
end else begin
_T_1163 <= _T_1174;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:56:61)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@20278.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@20279.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@20457.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@20458.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@20498.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@20499.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:56:61)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@20550.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@20551.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@20557.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@20558.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@20565.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@20566.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@20572.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@20573.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@20580.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@20581.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@20589.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@20590.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@20597.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@20598.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@20639.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@20640.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:56:61)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@20691.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@20692.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@20698.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@20699.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@20706.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@20707.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@20713.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@20714.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@20721.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@20722.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:56:61)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@20729.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@20730.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@20738.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@20739.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@20746.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@20747.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20796.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@20797.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@20803.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@20804.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@20810.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@20811.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@20818.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@20819.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@20826.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@20827.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@20834.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@20835.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20886.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@20887.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@20893.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@20894.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@20900.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@20901.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@20908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@20909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@20916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@20917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@20968.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@20969.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@20975.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@20976.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@20982.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@20983.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@20990.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@20991.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@21000.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@21001.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21047.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@21048.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@21054.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@21055.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@21061.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@21062.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@21069.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@21070.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@21077.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@21078.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@21124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@21125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@21131.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@21132.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@21138.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@21139.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@21146.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@21147.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@21154.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@21155.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:56:61)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21201.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@21202.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@21208.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@21209.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:56:61)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@21215.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@21216.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:56:61)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@21223.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@21224.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@21231.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@21232.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:56:61)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@21242.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@21243.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21289.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@21290.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@21297.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@21298.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@21305.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@21306.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@21313.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@21314.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@21321.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@21322.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@21331.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@21332.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@21338.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@21339.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@21346.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@21347.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@21354.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@21355.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@21362.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@21363.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@21370.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@21371.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@21379.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@21380.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@21389.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@21390.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@21396.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@21397.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:56:61)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@21404.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@21405.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@21412.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@21413.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@21420.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@21421.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@21429.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@21430.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@21438.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@21439.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@21448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@21449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@21456.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@21457.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@21464.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@21465.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@21473.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@21474.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@21483.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@21484.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@21491.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@21492.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@21500.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@21501.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@21509.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@21510.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@21519.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@21520.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:56:61)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@21527.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@21528.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:56:61)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@21535.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@21536.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:56:61)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@21544.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@21545.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:56:61)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@21554.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@21555.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:56:61)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@21562.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@21563.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:56:61)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@21570.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@21571.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@21610.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@21611.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@21618.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@21619.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@21626.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@21627.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@21634.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@21635.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@21642.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@21643.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@21692.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@21693.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@21700.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@21701.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@21708.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@21709.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@21716.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@21717.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@21724.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@21725.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:56:61)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@21732.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@21733.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:56:61)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@21810.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@21811.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:56:61)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@21833.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@21834.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1158) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at BusWrapper.scala:56:61)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@21845.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1158) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@21846.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1172) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:56:61)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@21865.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1172) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@21866.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLWidthWidget_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@21878.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21879.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21880.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@21881.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
TLMonitor_7 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@21888.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21928.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21927.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21890.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21891.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@21924.4]
endmodule
module SimpleLazyModule_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@21938.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21939.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21940.4]
output auto_widget_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_widget_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [2:0] auto_widget_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [2:0] auto_widget_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [3:0] auto_widget_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [4:0] auto_widget_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [27:0] auto_widget_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [7:0] auto_widget_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [63:0] auto_widget_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_widget_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_widget_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_widget_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [2:0] auto_widget_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [1:0] auto_widget_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [3:0] auto_widget_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [4:0] auto_widget_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_widget_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_widget_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [63:0] auto_widget_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_widget_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_bus_xing_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_bus_xing_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [2:0] auto_bus_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [2:0] auto_bus_xing_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [3:0] auto_bus_xing_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [4:0] auto_bus_xing_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [27:0] auto_bus_xing_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [7:0] auto_bus_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output [63:0] auto_bus_xing_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_bus_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
output auto_bus_xing_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_bus_xing_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [2:0] auto_bus_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [1:0] auto_bus_xing_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [3:0] auto_bus_xing_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [4:0] auto_bus_xing_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_bus_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_bus_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input [63:0] auto_bus_xing_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
input auto_bus_xing_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@21941.4]
);
wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [4:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [27:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [4:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [4:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [27:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [4:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
TLWidthWidget_1 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@21946.4]
.clock(widget_clock),
.reset(widget_reset),
.auto_in_a_ready(widget_auto_in_a_ready),
.auto_in_a_valid(widget_auto_in_a_valid),
.auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
.auto_in_a_bits_param(widget_auto_in_a_bits_param),
.auto_in_a_bits_size(widget_auto_in_a_bits_size),
.auto_in_a_bits_source(widget_auto_in_a_bits_source),
.auto_in_a_bits_address(widget_auto_in_a_bits_address),
.auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
.auto_in_a_bits_data(widget_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
.auto_in_d_ready(widget_auto_in_d_ready),
.auto_in_d_valid(widget_auto_in_d_valid),
.auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
.auto_in_d_bits_param(widget_auto_in_d_bits_param),
.auto_in_d_bits_size(widget_auto_in_d_bits_size),
.auto_in_d_bits_source(widget_auto_in_d_bits_source),
.auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
.auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
.auto_in_d_bits_data(widget_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
.auto_out_a_ready(widget_auto_out_a_ready),
.auto_out_a_valid(widget_auto_out_a_valid),
.auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
.auto_out_a_bits_param(widget_auto_out_a_bits_param),
.auto_out_a_bits_size(widget_auto_out_a_bits_size),
.auto_out_a_bits_source(widget_auto_out_a_bits_source),
.auto_out_a_bits_address(widget_auto_out_a_bits_address),
.auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
.auto_out_a_bits_data(widget_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
.auto_out_d_ready(widget_auto_out_d_ready),
.auto_out_d_valid(widget_auto_out_d_valid),
.auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
.auto_out_d_bits_param(widget_auto_out_d_bits_param),
.auto_out_d_bits_size(widget_auto_out_d_bits_size),
.auto_out_d_bits_source(widget_auto_out_d_bits_source),
.auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
.auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
.auto_out_d_bits_data(widget_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
);
assign auto_widget_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_widget_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign auto_bus_xing_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign auto_bus_xing_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@21958.4]
assign widget_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21950.4]
assign widget_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@21951.4]
assign widget_auto_in_a_valid = auto_widget_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_opcode = auto_widget_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_param = auto_widget_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_size = auto_widget_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_source = auto_widget_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_address = auto_widget_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_mask = auto_widget_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_data = auto_widget_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_a_bits_corrupt = auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_in_d_ready = auto_widget_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@21959.4]
assign widget_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
assign widget_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@21957.4]
endmodule
module TLMonitor_8( // @[:freechips.rocketchip.system.LowRiscConfig.fir@21968.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21969.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21970.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@21971.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@23518.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@21988.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21989.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@22006.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@22008.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@22009.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@22010.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@22011.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@22011.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@22012.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@22014.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@22015.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@22016.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@22017.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@22018.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@22019.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@22020.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@22021.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22023.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22024.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22026.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22027.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@22028.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@22029.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@22030.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22031.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22032.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22033.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22034.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22035.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22036.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22037.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22038.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22039.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22040.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22041.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22042.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@22043.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@22044.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@22045.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22046.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22047.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22048.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22049.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22050.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22051.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22052.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22053.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22054.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22055.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22056.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22057.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22058.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22059.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22060.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22061.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22062.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22063.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22064.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22065.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22066.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22067.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22068.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22069.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@22076.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22087.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@22115.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22118.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22119.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22120.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22121.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22122.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22123.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22124.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22125.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22126.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22127.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22128.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22129.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22130.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22131.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22132.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22133.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22134.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22135.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22136.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22137.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22140.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22141.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22142.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22143.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22144.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22145.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22146.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22147.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22155.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22158.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22159.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22160.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22161.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22162.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22163.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22167.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22168.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@22175.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@22181.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@22182.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@22189.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@22190.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@22196.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@22197.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@22202.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@22204.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@22205.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@22210.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@22211.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@22213.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@22214.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@22219.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@22221.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@22222.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@22228.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@22323.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@22325.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@22326.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@22349.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22385.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22386.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22387.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22388.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22389.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22390.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22392.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22400.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@22402.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22404.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22405.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@22424.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@22426.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@22427.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@22432.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@22434.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@22435.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@22449.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22482.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22483.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22484.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22485.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22487.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22495.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@22508.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@22509.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22511.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22512.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@22548.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@22638.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@22639.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@22640.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@22642.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@22643.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@22649.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22671.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22694.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22695.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22696.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22697.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22701.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22702.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@22721.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@22723.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@22724.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@22738.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@22810.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@22812.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@22813.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@22827.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22879.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22880.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@22918.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@22920.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@22921.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@22928.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@22929.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@22946.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@22948.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22951.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22952.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@22957.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@22959.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@22960.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@22965.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@22967.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@22968.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@22973.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@22975.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@22976.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@22981.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@22983.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@22984.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@22990.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@23014.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@23016.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@23017.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@23022.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@23024.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@23025.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@23048.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@23089.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@23091.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@23092.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@23107.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@23142.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@23178.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@23238.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@23243.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@23244.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@23245.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@23247.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23248.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23249.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23250.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23251.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@23262.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@23263.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@23264.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@23265.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@23266.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@23267.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@23268.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@23270.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@23272.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@23273.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@23278.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@23280.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@23281.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@23286.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@23288.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@23289.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@23294.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@23296.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@23297.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@23302.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@23304.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@23305.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@23312.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@23320.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@23322.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@23323.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@23324.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@23325.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@23326.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@23328.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23329.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23330.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23331.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23332.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@23343.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@23344.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@23345.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@23346.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@23347.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@23348.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@23349.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@23350.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@23352.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@23354.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@23355.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@23360.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@23362.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@23363.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@23368.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@23370.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@23371.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@23376.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@23378.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@23379.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@23384.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@23386.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@23387.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@23392.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@23394.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@23395.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@23402.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@23411.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@23421.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23422.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23423.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23424.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23425.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@23444.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23445.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23446.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23447.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23448.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@23463.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@23466.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@23468.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@23469.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@23470.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@23472.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@23473.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@23465.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@23484.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@23486.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@23487.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@23489.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@23491.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@23492.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@23493.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@23495.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@23496.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@23488.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@23502.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@23503.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@23504.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@23505.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@23507.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@23508.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@23513.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@23514.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@23515.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@23517.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@23520.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@23521.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@23522.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@23523.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@23524.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@23525.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@23527.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@23528.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@23534.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@23538.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22170.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@22283.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22407.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22514.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@22613.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22704.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@22793.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22882.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22954.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@22996.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@23054.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@23113.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@23148.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@23184.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@23518.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@21988.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@21989.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@22006.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@22008.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@22009.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@22010.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@22011.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@22011.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@22012.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@22014.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@22015.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@22016.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@22017.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@22018.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@22019.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@22020.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@22021.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22023.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22024.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22026.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22027.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@22028.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@22029.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@22030.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22031.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22032.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22033.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22034.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22035.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22036.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22037.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22038.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22039.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22040.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22041.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22042.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@22043.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@22044.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@22045.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22046.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22047.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22048.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22049.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22050.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22051.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22052.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22053.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22054.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22055.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22056.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22057.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22058.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22059.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22060.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22061.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22062.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22063.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22064.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22065.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22066.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@22067.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@22068.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@22069.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@22076.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22087.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@22115.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22118.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22119.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22120.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22121.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22122.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22123.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22124.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22125.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22126.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22127.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22128.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22129.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22130.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22131.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22132.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22133.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22134.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22135.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22136.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22137.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22140.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22141.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22142.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22143.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22144.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22145.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22146.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22147.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22155.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@22158.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@22159.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22160.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@22161.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@22162.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22163.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22167.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22168.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@22175.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@22181.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@22182.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@22189.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@22190.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@22196.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@22197.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@22202.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@22204.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@22205.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@22210.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@22211.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@22213.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@22214.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@22219.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@22221.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@22222.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@22228.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@22323.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@22325.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@22326.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@22349.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22385.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22386.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22387.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22388.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22389.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22390.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22392.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22400.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@22402.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22404.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22405.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@22424.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@22426.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@22427.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@22432.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@22434.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@22435.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@22449.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22482.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22483.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22484.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22485.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22487.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22495.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@22508.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@22509.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22511.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22512.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@22548.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@22638.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@22639.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@22640.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@22642.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@22643.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@22649.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@22671.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22694.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22695.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@22696.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@22697.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22701.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22702.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@22721.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@22723.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@22724.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@22738.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@22810.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@22812.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@22813.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@22827.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22879.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22880.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@22918.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@22920.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@22921.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@22928.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@22929.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@22946.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@22948.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22951.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22952.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@22957.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@22959.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@22960.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@22965.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@22967.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@22968.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@22973.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@22975.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@22976.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@22981.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@22983.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@22984.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@22990.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@23014.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@23016.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@23017.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@23022.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@23024.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@23025.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@23048.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@23089.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@23091.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@23092.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@23107.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@23142.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@23178.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@23238.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@23243.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@23244.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@23245.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23248.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23249.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23250.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23251.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@23267.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@23268.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@23270.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@23272.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@23273.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@23278.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@23280.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@23281.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@23286.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@23288.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@23289.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@23294.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@23296.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@23297.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@23302.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@23304.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@23305.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@23312.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@23320.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@23322.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@23323.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@23324.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@23325.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@23326.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23329.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23330.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23331.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23332.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@23349.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@23350.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@23352.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@23354.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@23355.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@23360.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@23362.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@23363.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@23368.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@23370.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@23371.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@23376.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@23378.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@23379.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@23384.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@23386.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@23387.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@23392.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@23394.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@23395.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@23402.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23422.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23423.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23424.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23425.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23445.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23446.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@23447.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@23448.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@23463.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@23466.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@23468.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@23469.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@23470.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@23472.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@23473.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@23465.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@23484.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@23486.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@23487.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@23489.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@23491.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@23492.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@23493.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@23495.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@23496.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@23488.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@23502.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@23503.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@23504.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@23505.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@23507.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@23508.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@23513.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@23514.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@23515.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@23520.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@23521.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@23522.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@23523.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@23524.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@23525.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@23527.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@23528.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@23534.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@23538.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22170.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@22283.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22407.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22514.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@22613.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22704.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@22793.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22882.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22954.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@22996.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@23054.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@23113.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@23148.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@23184.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:62:42)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@21983.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@21984.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@22112.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@22113.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22170.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@22171.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:62:42)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@22177.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@22178.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@22184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@22185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@22192.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@22193.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@22199.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@22200.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@22207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@22208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@22216.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@22217.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@22224.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@22225.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@22283.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@22284.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:62:42)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@22290.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@22291.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@22297.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@22298.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@22305.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@22306.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@22312.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@22313.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@22320.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@22321.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:62:42)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@22328.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@22329.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@22337.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@22338.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@22345.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@22346.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22407.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@22408.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@22414.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@22415.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@22421.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@22422.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@22429.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@22430.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@22437.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@22438.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@22445.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@22446.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22514.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@22515.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@22521.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@22522.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@22528.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@22529.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@22536.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@22537.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@22544.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@22545.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@22613.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@22614.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@22620.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@22621.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@22627.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@22628.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@22635.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@22636.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@22645.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@22646.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22704.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@22705.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@22711.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@22712.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@22718.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@22719.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@22726.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@22727.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@22734.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@22735.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@22793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@22794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@22800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@22801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@22807.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@22808.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@22815.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@22816.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@22823.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@22824.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:62:42)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22882.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@22883.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@22889.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@22890.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:62:42)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@22896.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@22897.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:62:42)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@22904.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@22905.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@22912.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@22913.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:62:42)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@22923.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@22924.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22954.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@22955.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@22962.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@22963.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@22970.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@22971.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@22978.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@22979.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@22986.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@22987.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@22996.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@22997.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@23003.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@23004.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@23011.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@23012.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@23019.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@23020.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@23027.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@23028.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@23035.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@23036.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@23044.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@23045.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@23054.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@23055.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@23061.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@23062.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:62:42)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@23069.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@23070.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@23077.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@23078.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@23085.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@23086.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@23094.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@23095.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@23103.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@23104.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@23113.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@23114.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@23121.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@23122.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@23129.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@23130.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@23138.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@23139.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@23148.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@23149.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@23156.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@23157.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@23165.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@23166.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@23174.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@23175.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@23184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@23185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:62:42)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@23192.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@23193.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:62:42)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@23200.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@23201.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:62:42)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@23209.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@23210.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:62:42)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@23219.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@23220.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:62:42)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@23227.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@23228.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:62:42)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@23235.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@23236.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@23275.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@23276.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@23283.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@23284.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@23291.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@23292.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@23299.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@23300.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@23307.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@23308.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@23357.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@23358.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@23365.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@23366.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@23373.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@23374.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@23381.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@23382.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@23389.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@23390.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:62:42)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@23397.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@23398.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:62:42)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@23475.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@23476.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:62:42)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@23498.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@23499.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at BusWrapper.scala:62:42)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@23510.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@23511.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:62:42)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@23530.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@23531.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLWidthWidget_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@23543.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23544.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23545.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@23546.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
TLMonitor_8 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@23553.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23593.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23592.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23555.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23556.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@23589.4]
endmodule
module SimpleLazyModule_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@23603.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23604.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23605.4]
input auto_widget_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_widget_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [2:0] auto_widget_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [2:0] auto_widget_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [3:0] auto_widget_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [3:0] auto_widget_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [31:0] auto_widget_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [7:0] auto_widget_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [63:0] auto_widget_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_widget_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_widget_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input auto_widget_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [2:0] auto_widget_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [1:0] auto_widget_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [3:0] auto_widget_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [3:0] auto_widget_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [1:0] auto_widget_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input auto_widget_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [63:0] auto_widget_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input auto_widget_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_bus_xing_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input auto_bus_xing_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [2:0] auto_bus_xing_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [3:0] auto_bus_xing_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [3:0] auto_bus_xing_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [31:0] auto_bus_xing_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input [63:0] auto_bus_xing_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input auto_bus_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
input auto_bus_xing_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_bus_xing_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [1:0] auto_bus_xing_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [3:0] auto_bus_xing_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [3:0] auto_bus_xing_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [1:0] auto_bus_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_bus_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output [63:0] auto_bus_xing_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
output auto_bus_xing_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@23606.4]
);
wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [1:0] widget_auto_in_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [1:0] widget_auto_in_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [3:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [1:0] widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
TLWidthWidget_2 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@23611.4]
.clock(widget_clock),
.reset(widget_reset),
.auto_in_a_ready(widget_auto_in_a_ready),
.auto_in_a_valid(widget_auto_in_a_valid),
.auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
.auto_in_a_bits_param(widget_auto_in_a_bits_param),
.auto_in_a_bits_size(widget_auto_in_a_bits_size),
.auto_in_a_bits_source(widget_auto_in_a_bits_source),
.auto_in_a_bits_address(widget_auto_in_a_bits_address),
.auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
.auto_in_a_bits_data(widget_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
.auto_in_d_ready(widget_auto_in_d_ready),
.auto_in_d_valid(widget_auto_in_d_valid),
.auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
.auto_in_d_bits_param(widget_auto_in_d_bits_param),
.auto_in_d_bits_size(widget_auto_in_d_bits_size),
.auto_in_d_bits_source(widget_auto_in_d_bits_source),
.auto_in_d_bits_sink(widget_auto_in_d_bits_sink),
.auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
.auto_in_d_bits_data(widget_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
.auto_out_a_ready(widget_auto_out_a_ready),
.auto_out_a_valid(widget_auto_out_a_valid),
.auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
.auto_out_a_bits_param(widget_auto_out_a_bits_param),
.auto_out_a_bits_size(widget_auto_out_a_bits_size),
.auto_out_a_bits_source(widget_auto_out_a_bits_source),
.auto_out_a_bits_address(widget_auto_out_a_bits_address),
.auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
.auto_out_a_bits_data(widget_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
.auto_out_d_ready(widget_auto_out_d_ready),
.auto_out_d_valid(widget_auto_out_d_valid),
.auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
.auto_out_d_bits_param(widget_auto_out_d_bits_param),
.auto_out_d_bits_size(widget_auto_out_d_bits_size),
.auto_out_d_bits_source(widget_auto_out_d_bits_source),
.auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
.auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
.auto_out_d_bits_data(widget_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
);
assign auto_widget_out_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_widget_out_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign auto_bus_xing_in_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_param = widget_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_sink = widget_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign auto_bus_xing_in_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23623.4]
assign widget_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23615.4]
assign widget_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23616.4]
assign widget_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23622.4]
assign widget_auto_out_a_ready = auto_widget_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_valid = auto_widget_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_opcode = auto_widget_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_param = auto_widget_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_size = auto_widget_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_source = auto_widget_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_sink = auto_widget_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_denied = auto_widget_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_data = auto_widget_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
assign widget_auto_out_d_bits_corrupt = auto_widget_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23624.4]
endmodule
module SystemBus( // @[:freechips.rocketchip.system.LowRiscConfig.fir@23635.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23636.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23637.4]
output auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [31:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [7:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [63:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [63:0] auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [4:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [27:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [7:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [63:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [4:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [63:0] auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [30:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [7:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [63:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [7:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [30:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [7:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [63:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [31:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [7:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [63:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_tile_named_tile_tl_master_xing_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [31:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_tile_named_tile_tl_master_xing_in_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [31:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [63:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [3:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [63:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_coupler_from_tile_named_tile_tl_master_xing_in_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_coupler_from_tile_named_tile_tl_master_xing_in_e_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_system_bus_xbar_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_system_bus_xbar_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_system_bus_xbar_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_system_bus_xbar_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [4:0] auto_system_bus_xbar_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [31:0] auto_system_bus_xbar_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [7:0] auto_system_bus_xbar_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [63:0] auto_system_bus_xbar_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_system_bus_xbar_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_system_bus_xbar_out_b_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [31:0] auto_system_bus_xbar_out_b_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_system_bus_xbar_out_c_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_c_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_system_bus_xbar_out_c_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_system_bus_xbar_out_c_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [2:0] auto_system_bus_xbar_out_c_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [4:0] auto_system_bus_xbar_out_c_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [31:0] auto_system_bus_xbar_out_c_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [63:0] auto_system_bus_xbar_out_c_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_c_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_system_bus_xbar_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_system_bus_xbar_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_system_bus_xbar_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [2:0] auto_system_bus_xbar_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [4:0] auto_system_bus_xbar_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [1:0] auto_system_bus_xbar_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_system_bus_xbar_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input [63:0] auto_system_bus_xbar_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
input auto_system_bus_xbar_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output auto_system_bus_xbar_out_e_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
output [1:0] auto_system_bus_xbar_out_e_bits_sink // @[:freechips.rocketchip.system.LowRiscConfig.fir@23638.4]
);
wire system_bus_xbar_clock; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_reset; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_1_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_1_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_1_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_1_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_in_1_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [7:0] system_bus_xbar_auto_in_1_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_in_1_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_1_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_in_1_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_1_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_1_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_in_1_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_in_1_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_1_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_0_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_0_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_0_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_0_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_in_0_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [7:0] system_bus_xbar_auto_in_0_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_in_0_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_b_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_b_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_in_0_b_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_in_0_b_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_c_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_c_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_0_c_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_0_c_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_0_c_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_0_c_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_in_0_c_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_in_0_c_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_c_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_in_0_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_in_0_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_0_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_in_0_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_in_0_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_in_0_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_in_0_e_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_in_0_e_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_2_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_out_2_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [7:0] system_bus_xbar_auto_out_2_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_2_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_b_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_b_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_out_2_b_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_out_2_b_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_c_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_c_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_c_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_c_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_c_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_2_c_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [31:0] system_bus_xbar_auto_out_2_c_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_2_c_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_c_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_out_2_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_2_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_2_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_out_2_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_2_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_2_e_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_out_2_e_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_1_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_1_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_out_1_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_1_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [27:0] system_bus_xbar_auto_out_1_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [7:0] system_bus_xbar_auto_out_1_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_1_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_1_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [1:0] system_bus_xbar_auto_out_1_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_out_1_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_1_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_1_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_1_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_0_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_0_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_out_0_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_0_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [30:0] system_bus_xbar_auto_out_0_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [7:0] system_bus_xbar_auto_out_0_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_0_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [2:0] system_bus_xbar_auto_out_0_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [3:0] system_bus_xbar_auto_out_0_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [4:0] system_bus_xbar_auto_out_0_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire [63:0] system_bus_xbar_auto_out_0_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire system_bus_xbar_auto_out_0_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
wire coupler_from_tile_named_tile_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [31:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [7:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [63:0] coupler_from_tile_named_tile_auto_buffer_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_buffer_out_b_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [31:0] coupler_from_tile_named_tile_auto_buffer_out_b_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_c_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_c_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_c_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_c_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_c_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_c_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [31:0] coupler_from_tile_named_tile_auto_buffer_out_c_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [63:0] coupler_from_tile_named_tile_auto_buffer_out_c_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_c_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [63:0] coupler_from_tile_named_tile_auto_buffer_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_buffer_out_e_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_buffer_out_e_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [31:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [7:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [63:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_b_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [31:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_b_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_c_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_c_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [31:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [63:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [2:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [3:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [63:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_from_tile_named_tile_auto_tl_master_xing_in_e_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire [1:0] coupler_from_tile_named_tile_auto_tl_master_xing_in_e_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
wire coupler_to_port_named_mmio_port_axi4_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [4:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [30:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [7:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [63:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [4:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [63:0] coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [30:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [7:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_lock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_cache; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_prot; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_qos; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [63:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [7:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_strb; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [30:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [7:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_lock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_cache; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [2:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_prot; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_qos; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [3:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [63:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire [1:0] coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
wire coupler_to_bus_named_periphery_bus_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [2:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [2:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [3:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [4:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [27:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [7:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [63:0] coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [2:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [1:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [3:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [4:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [63:0] coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [2:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [2:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [3:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [4:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [27:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [7:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [63:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [2:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [1:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [3:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [4:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire [63:0] coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
wire coupler_from_bus_named_front_bus_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [2:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [2:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [31:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [7:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [63:0] coupler_from_bus_named_front_bus_auto_widget_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [2:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [1:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [1:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [63:0] coupler_from_bus_named_front_bus_auto_widget_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_widget_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [2:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [2:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [31:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [7:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [63:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [2:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [1:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [3:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [1:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire [63:0] coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
wire coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
TLXbar system_bus_xbar ( // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@23643.4]
.clock(system_bus_xbar_clock),
.reset(system_bus_xbar_reset),
.auto_in_1_a_ready(system_bus_xbar_auto_in_1_a_ready),
.auto_in_1_a_valid(system_bus_xbar_auto_in_1_a_valid),
.auto_in_1_a_bits_opcode(system_bus_xbar_auto_in_1_a_bits_opcode),
.auto_in_1_a_bits_param(system_bus_xbar_auto_in_1_a_bits_param),
.auto_in_1_a_bits_size(system_bus_xbar_auto_in_1_a_bits_size),
.auto_in_1_a_bits_source(system_bus_xbar_auto_in_1_a_bits_source),
.auto_in_1_a_bits_address(system_bus_xbar_auto_in_1_a_bits_address),
.auto_in_1_a_bits_mask(system_bus_xbar_auto_in_1_a_bits_mask),
.auto_in_1_a_bits_data(system_bus_xbar_auto_in_1_a_bits_data),
.auto_in_1_a_bits_corrupt(system_bus_xbar_auto_in_1_a_bits_corrupt),
.auto_in_1_d_ready(system_bus_xbar_auto_in_1_d_ready),
.auto_in_1_d_valid(system_bus_xbar_auto_in_1_d_valid),
.auto_in_1_d_bits_opcode(system_bus_xbar_auto_in_1_d_bits_opcode),
.auto_in_1_d_bits_param(system_bus_xbar_auto_in_1_d_bits_param),
.auto_in_1_d_bits_size(system_bus_xbar_auto_in_1_d_bits_size),
.auto_in_1_d_bits_source(system_bus_xbar_auto_in_1_d_bits_source),
.auto_in_1_d_bits_sink(system_bus_xbar_auto_in_1_d_bits_sink),
.auto_in_1_d_bits_denied(system_bus_xbar_auto_in_1_d_bits_denied),
.auto_in_1_d_bits_data(system_bus_xbar_auto_in_1_d_bits_data),
.auto_in_1_d_bits_corrupt(system_bus_xbar_auto_in_1_d_bits_corrupt),
.auto_in_0_a_ready(system_bus_xbar_auto_in_0_a_ready),
.auto_in_0_a_valid(system_bus_xbar_auto_in_0_a_valid),
.auto_in_0_a_bits_opcode(system_bus_xbar_auto_in_0_a_bits_opcode),
.auto_in_0_a_bits_param(system_bus_xbar_auto_in_0_a_bits_param),
.auto_in_0_a_bits_size(system_bus_xbar_auto_in_0_a_bits_size),
.auto_in_0_a_bits_source(system_bus_xbar_auto_in_0_a_bits_source),
.auto_in_0_a_bits_address(system_bus_xbar_auto_in_0_a_bits_address),
.auto_in_0_a_bits_mask(system_bus_xbar_auto_in_0_a_bits_mask),
.auto_in_0_a_bits_data(system_bus_xbar_auto_in_0_a_bits_data),
.auto_in_0_a_bits_corrupt(system_bus_xbar_auto_in_0_a_bits_corrupt),
.auto_in_0_b_ready(system_bus_xbar_auto_in_0_b_ready),
.auto_in_0_b_valid(system_bus_xbar_auto_in_0_b_valid),
.auto_in_0_b_bits_param(system_bus_xbar_auto_in_0_b_bits_param),
.auto_in_0_b_bits_address(system_bus_xbar_auto_in_0_b_bits_address),
.auto_in_0_c_ready(system_bus_xbar_auto_in_0_c_ready),
.auto_in_0_c_valid(system_bus_xbar_auto_in_0_c_valid),
.auto_in_0_c_bits_opcode(system_bus_xbar_auto_in_0_c_bits_opcode),
.auto_in_0_c_bits_param(system_bus_xbar_auto_in_0_c_bits_param),
.auto_in_0_c_bits_size(system_bus_xbar_auto_in_0_c_bits_size),
.auto_in_0_c_bits_source(system_bus_xbar_auto_in_0_c_bits_source),
.auto_in_0_c_bits_address(system_bus_xbar_auto_in_0_c_bits_address),
.auto_in_0_c_bits_data(system_bus_xbar_auto_in_0_c_bits_data),
.auto_in_0_c_bits_corrupt(system_bus_xbar_auto_in_0_c_bits_corrupt),
.auto_in_0_d_ready(system_bus_xbar_auto_in_0_d_ready),
.auto_in_0_d_valid(system_bus_xbar_auto_in_0_d_valid),
.auto_in_0_d_bits_opcode(system_bus_xbar_auto_in_0_d_bits_opcode),
.auto_in_0_d_bits_param(system_bus_xbar_auto_in_0_d_bits_param),
.auto_in_0_d_bits_size(system_bus_xbar_auto_in_0_d_bits_size),
.auto_in_0_d_bits_source(system_bus_xbar_auto_in_0_d_bits_source),
.auto_in_0_d_bits_sink(system_bus_xbar_auto_in_0_d_bits_sink),
.auto_in_0_d_bits_denied(system_bus_xbar_auto_in_0_d_bits_denied),
.auto_in_0_d_bits_data(system_bus_xbar_auto_in_0_d_bits_data),
.auto_in_0_d_bits_corrupt(system_bus_xbar_auto_in_0_d_bits_corrupt),
.auto_in_0_e_valid(system_bus_xbar_auto_in_0_e_valid),
.auto_in_0_e_bits_sink(system_bus_xbar_auto_in_0_e_bits_sink),
.auto_out_2_a_ready(system_bus_xbar_auto_out_2_a_ready),
.auto_out_2_a_valid(system_bus_xbar_auto_out_2_a_valid),
.auto_out_2_a_bits_opcode(system_bus_xbar_auto_out_2_a_bits_opcode),
.auto_out_2_a_bits_param(system_bus_xbar_auto_out_2_a_bits_param),
.auto_out_2_a_bits_size(system_bus_xbar_auto_out_2_a_bits_size),
.auto_out_2_a_bits_source(system_bus_xbar_auto_out_2_a_bits_source),
.auto_out_2_a_bits_address(system_bus_xbar_auto_out_2_a_bits_address),
.auto_out_2_a_bits_mask(system_bus_xbar_auto_out_2_a_bits_mask),
.auto_out_2_a_bits_data(system_bus_xbar_auto_out_2_a_bits_data),
.auto_out_2_a_bits_corrupt(system_bus_xbar_auto_out_2_a_bits_corrupt),
.auto_out_2_b_ready(system_bus_xbar_auto_out_2_b_ready),
.auto_out_2_b_valid(system_bus_xbar_auto_out_2_b_valid),
.auto_out_2_b_bits_param(system_bus_xbar_auto_out_2_b_bits_param),
.auto_out_2_b_bits_address(system_bus_xbar_auto_out_2_b_bits_address),
.auto_out_2_c_ready(system_bus_xbar_auto_out_2_c_ready),
.auto_out_2_c_valid(system_bus_xbar_auto_out_2_c_valid),
.auto_out_2_c_bits_opcode(system_bus_xbar_auto_out_2_c_bits_opcode),
.auto_out_2_c_bits_param(system_bus_xbar_auto_out_2_c_bits_param),
.auto_out_2_c_bits_size(system_bus_xbar_auto_out_2_c_bits_size),
.auto_out_2_c_bits_source(system_bus_xbar_auto_out_2_c_bits_source),
.auto_out_2_c_bits_address(system_bus_xbar_auto_out_2_c_bits_address),
.auto_out_2_c_bits_data(system_bus_xbar_auto_out_2_c_bits_data),
.auto_out_2_c_bits_corrupt(system_bus_xbar_auto_out_2_c_bits_corrupt),
.auto_out_2_d_ready(system_bus_xbar_auto_out_2_d_ready),
.auto_out_2_d_valid(system_bus_xbar_auto_out_2_d_valid),
.auto_out_2_d_bits_opcode(system_bus_xbar_auto_out_2_d_bits_opcode),
.auto_out_2_d_bits_param(system_bus_xbar_auto_out_2_d_bits_param),
.auto_out_2_d_bits_size(system_bus_xbar_auto_out_2_d_bits_size),
.auto_out_2_d_bits_source(system_bus_xbar_auto_out_2_d_bits_source),
.auto_out_2_d_bits_sink(system_bus_xbar_auto_out_2_d_bits_sink),
.auto_out_2_d_bits_denied(system_bus_xbar_auto_out_2_d_bits_denied),
.auto_out_2_d_bits_data(system_bus_xbar_auto_out_2_d_bits_data),
.auto_out_2_d_bits_corrupt(system_bus_xbar_auto_out_2_d_bits_corrupt),
.auto_out_2_e_valid(system_bus_xbar_auto_out_2_e_valid),
.auto_out_2_e_bits_sink(system_bus_xbar_auto_out_2_e_bits_sink),
.auto_out_1_a_ready(system_bus_xbar_auto_out_1_a_ready),
.auto_out_1_a_valid(system_bus_xbar_auto_out_1_a_valid),
.auto_out_1_a_bits_opcode(system_bus_xbar_auto_out_1_a_bits_opcode),
.auto_out_1_a_bits_param(system_bus_xbar_auto_out_1_a_bits_param),
.auto_out_1_a_bits_size(system_bus_xbar_auto_out_1_a_bits_size),
.auto_out_1_a_bits_source(system_bus_xbar_auto_out_1_a_bits_source),
.auto_out_1_a_bits_address(system_bus_xbar_auto_out_1_a_bits_address),
.auto_out_1_a_bits_mask(system_bus_xbar_auto_out_1_a_bits_mask),
.auto_out_1_a_bits_data(system_bus_xbar_auto_out_1_a_bits_data),
.auto_out_1_a_bits_corrupt(system_bus_xbar_auto_out_1_a_bits_corrupt),
.auto_out_1_d_ready(system_bus_xbar_auto_out_1_d_ready),
.auto_out_1_d_valid(system_bus_xbar_auto_out_1_d_valid),
.auto_out_1_d_bits_opcode(system_bus_xbar_auto_out_1_d_bits_opcode),
.auto_out_1_d_bits_param(system_bus_xbar_auto_out_1_d_bits_param),
.auto_out_1_d_bits_size(system_bus_xbar_auto_out_1_d_bits_size),
.auto_out_1_d_bits_source(system_bus_xbar_auto_out_1_d_bits_source),
.auto_out_1_d_bits_sink(system_bus_xbar_auto_out_1_d_bits_sink),
.auto_out_1_d_bits_denied(system_bus_xbar_auto_out_1_d_bits_denied),
.auto_out_1_d_bits_data(system_bus_xbar_auto_out_1_d_bits_data),
.auto_out_1_d_bits_corrupt(system_bus_xbar_auto_out_1_d_bits_corrupt),
.auto_out_0_a_ready(system_bus_xbar_auto_out_0_a_ready),
.auto_out_0_a_valid(system_bus_xbar_auto_out_0_a_valid),
.auto_out_0_a_bits_opcode(system_bus_xbar_auto_out_0_a_bits_opcode),
.auto_out_0_a_bits_param(system_bus_xbar_auto_out_0_a_bits_param),
.auto_out_0_a_bits_size(system_bus_xbar_auto_out_0_a_bits_size),
.auto_out_0_a_bits_source(system_bus_xbar_auto_out_0_a_bits_source),
.auto_out_0_a_bits_address(system_bus_xbar_auto_out_0_a_bits_address),
.auto_out_0_a_bits_mask(system_bus_xbar_auto_out_0_a_bits_mask),
.auto_out_0_a_bits_data(system_bus_xbar_auto_out_0_a_bits_data),
.auto_out_0_a_bits_corrupt(system_bus_xbar_auto_out_0_a_bits_corrupt),
.auto_out_0_d_ready(system_bus_xbar_auto_out_0_d_ready),
.auto_out_0_d_valid(system_bus_xbar_auto_out_0_d_valid),
.auto_out_0_d_bits_opcode(system_bus_xbar_auto_out_0_d_bits_opcode),
.auto_out_0_d_bits_size(system_bus_xbar_auto_out_0_d_bits_size),
.auto_out_0_d_bits_source(system_bus_xbar_auto_out_0_d_bits_source),
.auto_out_0_d_bits_denied(system_bus_xbar_auto_out_0_d_bits_denied),
.auto_out_0_d_bits_data(system_bus_xbar_auto_out_0_d_bits_data),
.auto_out_0_d_bits_corrupt(system_bus_xbar_auto_out_0_d_bits_corrupt)
);
SimpleLazyModule coupler_from_tile_named_tile ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23649.4]
.clock(coupler_from_tile_named_tile_clock),
.reset(coupler_from_tile_named_tile_reset),
.auto_buffer_out_a_ready(coupler_from_tile_named_tile_auto_buffer_out_a_ready),
.auto_buffer_out_a_valid(coupler_from_tile_named_tile_auto_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode(coupler_from_tile_named_tile_auto_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param(coupler_from_tile_named_tile_auto_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size(coupler_from_tile_named_tile_auto_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source(coupler_from_tile_named_tile_auto_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address(coupler_from_tile_named_tile_auto_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask(coupler_from_tile_named_tile_auto_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data(coupler_from_tile_named_tile_auto_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt(coupler_from_tile_named_tile_auto_buffer_out_a_bits_corrupt),
.auto_buffer_out_b_ready(coupler_from_tile_named_tile_auto_buffer_out_b_ready),
.auto_buffer_out_b_valid(coupler_from_tile_named_tile_auto_buffer_out_b_valid),
.auto_buffer_out_b_bits_param(coupler_from_tile_named_tile_auto_buffer_out_b_bits_param),
.auto_buffer_out_b_bits_address(coupler_from_tile_named_tile_auto_buffer_out_b_bits_address),
.auto_buffer_out_c_ready(coupler_from_tile_named_tile_auto_buffer_out_c_ready),
.auto_buffer_out_c_valid(coupler_from_tile_named_tile_auto_buffer_out_c_valid),
.auto_buffer_out_c_bits_opcode(coupler_from_tile_named_tile_auto_buffer_out_c_bits_opcode),
.auto_buffer_out_c_bits_param(coupler_from_tile_named_tile_auto_buffer_out_c_bits_param),
.auto_buffer_out_c_bits_size(coupler_from_tile_named_tile_auto_buffer_out_c_bits_size),
.auto_buffer_out_c_bits_source(coupler_from_tile_named_tile_auto_buffer_out_c_bits_source),
.auto_buffer_out_c_bits_address(coupler_from_tile_named_tile_auto_buffer_out_c_bits_address),
.auto_buffer_out_c_bits_data(coupler_from_tile_named_tile_auto_buffer_out_c_bits_data),
.auto_buffer_out_c_bits_corrupt(coupler_from_tile_named_tile_auto_buffer_out_c_bits_corrupt),
.auto_buffer_out_d_ready(coupler_from_tile_named_tile_auto_buffer_out_d_ready),
.auto_buffer_out_d_valid(coupler_from_tile_named_tile_auto_buffer_out_d_valid),
.auto_buffer_out_d_bits_opcode(coupler_from_tile_named_tile_auto_buffer_out_d_bits_opcode),
.auto_buffer_out_d_bits_param(coupler_from_tile_named_tile_auto_buffer_out_d_bits_param),
.auto_buffer_out_d_bits_size(coupler_from_tile_named_tile_auto_buffer_out_d_bits_size),
.auto_buffer_out_d_bits_source(coupler_from_tile_named_tile_auto_buffer_out_d_bits_source),
.auto_buffer_out_d_bits_sink(coupler_from_tile_named_tile_auto_buffer_out_d_bits_sink),
.auto_buffer_out_d_bits_denied(coupler_from_tile_named_tile_auto_buffer_out_d_bits_denied),
.auto_buffer_out_d_bits_data(coupler_from_tile_named_tile_auto_buffer_out_d_bits_data),
.auto_buffer_out_d_bits_corrupt(coupler_from_tile_named_tile_auto_buffer_out_d_bits_corrupt),
.auto_buffer_out_e_valid(coupler_from_tile_named_tile_auto_buffer_out_e_valid),
.auto_buffer_out_e_bits_sink(coupler_from_tile_named_tile_auto_buffer_out_e_bits_sink),
.auto_tl_master_xing_in_a_ready(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_ready),
.auto_tl_master_xing_in_a_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_valid),
.auto_tl_master_xing_in_a_bits_opcode(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_opcode),
.auto_tl_master_xing_in_a_bits_param(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_param),
.auto_tl_master_xing_in_a_bits_size(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_size),
.auto_tl_master_xing_in_a_bits_source(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_source),
.auto_tl_master_xing_in_a_bits_address(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_address),
.auto_tl_master_xing_in_a_bits_mask(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_mask),
.auto_tl_master_xing_in_a_bits_data(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_data),
.auto_tl_master_xing_in_a_bits_corrupt(coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_corrupt),
.auto_tl_master_xing_in_b_ready(coupler_from_tile_named_tile_auto_tl_master_xing_in_b_ready),
.auto_tl_master_xing_in_b_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_b_valid),
.auto_tl_master_xing_in_b_bits_param(coupler_from_tile_named_tile_auto_tl_master_xing_in_b_bits_param),
.auto_tl_master_xing_in_b_bits_address(coupler_from_tile_named_tile_auto_tl_master_xing_in_b_bits_address),
.auto_tl_master_xing_in_c_ready(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_ready),
.auto_tl_master_xing_in_c_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_valid),
.auto_tl_master_xing_in_c_bits_opcode(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_opcode),
.auto_tl_master_xing_in_c_bits_param(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_param),
.auto_tl_master_xing_in_c_bits_size(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_size),
.auto_tl_master_xing_in_c_bits_source(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_source),
.auto_tl_master_xing_in_c_bits_address(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_address),
.auto_tl_master_xing_in_c_bits_data(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_data),
.auto_tl_master_xing_in_c_bits_corrupt(coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_corrupt),
.auto_tl_master_xing_in_d_ready(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_ready),
.auto_tl_master_xing_in_d_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_valid),
.auto_tl_master_xing_in_d_bits_opcode(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_opcode),
.auto_tl_master_xing_in_d_bits_param(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_param),
.auto_tl_master_xing_in_d_bits_size(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_size),
.auto_tl_master_xing_in_d_bits_source(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_source),
.auto_tl_master_xing_in_d_bits_sink(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_sink),
.auto_tl_master_xing_in_d_bits_denied(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_denied),
.auto_tl_master_xing_in_d_bits_data(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_data),
.auto_tl_master_xing_in_d_bits_corrupt(coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_corrupt),
.auto_tl_master_xing_in_e_valid(coupler_from_tile_named_tile_auto_tl_master_xing_in_e_valid),
.auto_tl_master_xing_in_e_bits_sink(coupler_from_tile_named_tile_auto_tl_master_xing_in_e_bits_sink)
);
SimpleLazyModule_1 coupler_to_port_named_mmio_port_axi4 ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23655.4]
.clock(coupler_to_port_named_mmio_port_axi4_clock),
.reset(coupler_to_port_named_mmio_port_axi4_reset),
.auto_buffer_in_a_ready(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_ready),
.auto_buffer_in_a_valid(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_valid),
.auto_buffer_in_a_bits_opcode(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_opcode),
.auto_buffer_in_a_bits_param(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_param),
.auto_buffer_in_a_bits_size(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_size),
.auto_buffer_in_a_bits_source(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_source),
.auto_buffer_in_a_bits_address(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_address),
.auto_buffer_in_a_bits_mask(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_mask),
.auto_buffer_in_a_bits_data(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_data),
.auto_buffer_in_a_bits_corrupt(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_corrupt),
.auto_buffer_in_d_ready(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_ready),
.auto_buffer_in_d_valid(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_valid),
.auto_buffer_in_d_bits_opcode(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_opcode),
.auto_buffer_in_d_bits_size(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_size),
.auto_buffer_in_d_bits_source(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_source),
.auto_buffer_in_d_bits_denied(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_denied),
.auto_buffer_in_d_bits_data(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_data),
.auto_buffer_in_d_bits_corrupt(coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_corrupt),
.auto_axi4buf_out_aw_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_ready),
.auto_axi4buf_out_aw_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_valid),
.auto_axi4buf_out_aw_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_id),
.auto_axi4buf_out_aw_bits_addr(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_addr),
.auto_axi4buf_out_aw_bits_len(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_len),
.auto_axi4buf_out_aw_bits_size(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_size),
.auto_axi4buf_out_aw_bits_burst(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_burst),
.auto_axi4buf_out_aw_bits_lock(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_lock),
.auto_axi4buf_out_aw_bits_cache(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_cache),
.auto_axi4buf_out_aw_bits_prot(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_prot),
.auto_axi4buf_out_aw_bits_qos(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_qos),
.auto_axi4buf_out_w_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_ready),
.auto_axi4buf_out_w_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_valid),
.auto_axi4buf_out_w_bits_data(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_data),
.auto_axi4buf_out_w_bits_strb(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_strb),
.auto_axi4buf_out_w_bits_last(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_last),
.auto_axi4buf_out_b_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_ready),
.auto_axi4buf_out_b_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_valid),
.auto_axi4buf_out_b_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_id),
.auto_axi4buf_out_b_bits_resp(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_resp),
.auto_axi4buf_out_ar_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_ready),
.auto_axi4buf_out_ar_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_valid),
.auto_axi4buf_out_ar_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_id),
.auto_axi4buf_out_ar_bits_addr(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_addr),
.auto_axi4buf_out_ar_bits_len(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_len),
.auto_axi4buf_out_ar_bits_size(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_size),
.auto_axi4buf_out_ar_bits_burst(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_burst),
.auto_axi4buf_out_ar_bits_lock(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_lock),
.auto_axi4buf_out_ar_bits_cache(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_cache),
.auto_axi4buf_out_ar_bits_prot(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_prot),
.auto_axi4buf_out_ar_bits_qos(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_qos),
.auto_axi4buf_out_r_ready(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_ready),
.auto_axi4buf_out_r_valid(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_valid),
.auto_axi4buf_out_r_bits_id(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_id),
.auto_axi4buf_out_r_bits_data(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_data),
.auto_axi4buf_out_r_bits_resp(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_resp),
.auto_axi4buf_out_r_bits_last(coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_last)
);
SimpleLazyModule_2 coupler_to_bus_named_periphery_bus ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23661.4]
.clock(coupler_to_bus_named_periphery_bus_clock),
.reset(coupler_to_bus_named_periphery_bus_reset),
.auto_widget_in_a_ready(coupler_to_bus_named_periphery_bus_auto_widget_in_a_ready),
.auto_widget_in_a_valid(coupler_to_bus_named_periphery_bus_auto_widget_in_a_valid),
.auto_widget_in_a_bits_opcode(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_opcode),
.auto_widget_in_a_bits_param(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_param),
.auto_widget_in_a_bits_size(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_size),
.auto_widget_in_a_bits_source(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_source),
.auto_widget_in_a_bits_address(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_address),
.auto_widget_in_a_bits_mask(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_mask),
.auto_widget_in_a_bits_data(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_data),
.auto_widget_in_a_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_corrupt),
.auto_widget_in_d_ready(coupler_to_bus_named_periphery_bus_auto_widget_in_d_ready),
.auto_widget_in_d_valid(coupler_to_bus_named_periphery_bus_auto_widget_in_d_valid),
.auto_widget_in_d_bits_opcode(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_opcode),
.auto_widget_in_d_bits_param(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_param),
.auto_widget_in_d_bits_size(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_size),
.auto_widget_in_d_bits_source(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_source),
.auto_widget_in_d_bits_sink(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_sink),
.auto_widget_in_d_bits_denied(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_denied),
.auto_widget_in_d_bits_data(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_data),
.auto_widget_in_d_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_corrupt),
.auto_bus_xing_out_a_ready(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_ready),
.auto_bus_xing_out_a_valid(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_valid),
.auto_bus_xing_out_a_bits_opcode(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_opcode),
.auto_bus_xing_out_a_bits_param(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_param),
.auto_bus_xing_out_a_bits_size(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_size),
.auto_bus_xing_out_a_bits_source(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_source),
.auto_bus_xing_out_a_bits_address(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_address),
.auto_bus_xing_out_a_bits_mask(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_mask),
.auto_bus_xing_out_a_bits_data(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_data),
.auto_bus_xing_out_a_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_corrupt),
.auto_bus_xing_out_d_ready(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_ready),
.auto_bus_xing_out_d_valid(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_valid),
.auto_bus_xing_out_d_bits_opcode(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_opcode),
.auto_bus_xing_out_d_bits_param(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_param),
.auto_bus_xing_out_d_bits_size(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_size),
.auto_bus_xing_out_d_bits_source(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_source),
.auto_bus_xing_out_d_bits_sink(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_sink),
.auto_bus_xing_out_d_bits_denied(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_denied),
.auto_bus_xing_out_d_bits_data(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_data),
.auto_bus_xing_out_d_bits_corrupt(coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_corrupt)
);
SimpleLazyModule_3 coupler_from_bus_named_front_bus ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@23667.4]
.clock(coupler_from_bus_named_front_bus_clock),
.reset(coupler_from_bus_named_front_bus_reset),
.auto_widget_out_a_ready(coupler_from_bus_named_front_bus_auto_widget_out_a_ready),
.auto_widget_out_a_valid(coupler_from_bus_named_front_bus_auto_widget_out_a_valid),
.auto_widget_out_a_bits_opcode(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_opcode),
.auto_widget_out_a_bits_param(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_param),
.auto_widget_out_a_bits_size(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_size),
.auto_widget_out_a_bits_source(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_source),
.auto_widget_out_a_bits_address(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_address),
.auto_widget_out_a_bits_mask(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_mask),
.auto_widget_out_a_bits_data(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_data),
.auto_widget_out_a_bits_corrupt(coupler_from_bus_named_front_bus_auto_widget_out_a_bits_corrupt),
.auto_widget_out_d_ready(coupler_from_bus_named_front_bus_auto_widget_out_d_ready),
.auto_widget_out_d_valid(coupler_from_bus_named_front_bus_auto_widget_out_d_valid),
.auto_widget_out_d_bits_opcode(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_opcode),
.auto_widget_out_d_bits_param(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_param),
.auto_widget_out_d_bits_size(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_size),
.auto_widget_out_d_bits_source(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_source),
.auto_widget_out_d_bits_sink(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_sink),
.auto_widget_out_d_bits_denied(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_denied),
.auto_widget_out_d_bits_data(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_data),
.auto_widget_out_d_bits_corrupt(coupler_from_bus_named_front_bus_auto_widget_out_d_bits_corrupt),
.auto_bus_xing_in_a_ready(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_ready),
.auto_bus_xing_in_a_valid(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_valid),
.auto_bus_xing_in_a_bits_opcode(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_opcode),
.auto_bus_xing_in_a_bits_param(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_param),
.auto_bus_xing_in_a_bits_size(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_size),
.auto_bus_xing_in_a_bits_source(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_source),
.auto_bus_xing_in_a_bits_address(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_address),
.auto_bus_xing_in_a_bits_mask(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_mask),
.auto_bus_xing_in_a_bits_data(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_data),
.auto_bus_xing_in_a_bits_corrupt(coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_corrupt),
.auto_bus_xing_in_d_ready(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_ready),
.auto_bus_xing_in_d_valid(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_valid),
.auto_bus_xing_in_d_bits_opcode(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_opcode),
.auto_bus_xing_in_d_bits_param(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_param),
.auto_bus_xing_in_d_bits_size(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_size),
.auto_bus_xing_in_d_bits_source(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_source),
.auto_bus_xing_in_d_bits_sink(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_sink),
.auto_bus_xing_in_d_bits_denied(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_denied),
.auto_bus_xing_in_d_bits_data(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_data),
.auto_bus_xing_in_d_bits_corrupt(coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_corrupt)
);
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_a_ready = coupler_from_bus_named_front_bus_auto_bus_xing_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_valid = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_opcode = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_param = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_size = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_source = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_sink = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_denied = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_data = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_from_bus_named_front_bus_bus_xing_in_d_bits_corrupt = coupler_from_bus_named_front_bus_auto_bus_xing_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_valid = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_opcode = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_param = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_size = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_source = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_address = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_mask = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_data = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_bits_corrupt = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_ready = coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_valid = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_id = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_addr = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_len = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_size = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_burst = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_lock = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_cache = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_prot = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_bits_qos = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_valid = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_data = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_strb = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_bits_last = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_ready = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_valid = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_id = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_addr = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_len = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_size = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_burst = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_lock = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_cache = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_prot = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_bits_qos = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_ready = coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_a_ready = coupler_from_tile_named_tile_auto_tl_master_xing_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_b_valid = coupler_from_tile_named_tile_auto_tl_master_xing_in_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_b_bits_param = coupler_from_tile_named_tile_auto_tl_master_xing_in_b_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_b_bits_address = coupler_from_tile_named_tile_auto_tl_master_xing_in_b_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_c_ready = coupler_from_tile_named_tile_auto_tl_master_xing_in_c_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_valid = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_opcode = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_param = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_size = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_source = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_sink = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_denied = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_data = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_coupler_from_tile_named_tile_tl_master_xing_in_d_bits_corrupt = coupler_from_tile_named_tile_auto_tl_master_xing_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign auto_system_bus_xbar_out_a_valid = system_bus_xbar_auto_out_2_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_opcode = system_bus_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_param = system_bus_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_size = system_bus_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_source = system_bus_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_address = system_bus_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_mask = system_bus_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_data = system_bus_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_a_bits_corrupt = system_bus_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_b_ready = system_bus_xbar_auto_out_2_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_valid = system_bus_xbar_auto_out_2_c_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_opcode = system_bus_xbar_auto_out_2_c_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_param = system_bus_xbar_auto_out_2_c_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_size = system_bus_xbar_auto_out_2_c_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_source = system_bus_xbar_auto_out_2_c_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_address = system_bus_xbar_auto_out_2_c_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_data = system_bus_xbar_auto_out_2_c_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_c_bits_corrupt = system_bus_xbar_auto_out_2_c_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_d_ready = system_bus_xbar_auto_out_2_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_e_valid = system_bus_xbar_auto_out_2_e_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign auto_system_bus_xbar_out_e_bits_sink = system_bus_xbar_auto_out_2_e_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23647.4]
assign system_bus_xbar_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23648.4]
assign system_bus_xbar_auto_in_1_a_valid = coupler_from_bus_named_front_bus_auto_widget_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_opcode = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_param = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_size = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_source = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_address = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_mask = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_data = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_a_bits_corrupt = coupler_from_bus_named_front_bus_auto_widget_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_1_d_ready = coupler_from_bus_named_front_bus_auto_widget_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign system_bus_xbar_auto_in_0_a_valid = coupler_from_tile_named_tile_auto_buffer_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_opcode = coupler_from_tile_named_tile_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_param = coupler_from_tile_named_tile_auto_buffer_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_size = coupler_from_tile_named_tile_auto_buffer_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_source = coupler_from_tile_named_tile_auto_buffer_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_address = coupler_from_tile_named_tile_auto_buffer_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_mask = coupler_from_tile_named_tile_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_data = coupler_from_tile_named_tile_auto_buffer_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_a_bits_corrupt = coupler_from_tile_named_tile_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_b_ready = coupler_from_tile_named_tile_auto_buffer_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_valid = coupler_from_tile_named_tile_auto_buffer_out_c_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_opcode = coupler_from_tile_named_tile_auto_buffer_out_c_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_param = coupler_from_tile_named_tile_auto_buffer_out_c_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_size = coupler_from_tile_named_tile_auto_buffer_out_c_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_source = coupler_from_tile_named_tile_auto_buffer_out_c_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_address = coupler_from_tile_named_tile_auto_buffer_out_c_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_data = coupler_from_tile_named_tile_auto_buffer_out_c_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_c_bits_corrupt = coupler_from_tile_named_tile_auto_buffer_out_c_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_d_ready = coupler_from_tile_named_tile_auto_buffer_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_e_valid = coupler_from_tile_named_tile_auto_buffer_out_e_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_in_0_e_bits_sink = coupler_from_tile_named_tile_auto_buffer_out_e_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign system_bus_xbar_auto_out_2_a_ready = auto_system_bus_xbar_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_b_valid = auto_system_bus_xbar_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_b_bits_param = auto_system_bus_xbar_out_b_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_b_bits_address = auto_system_bus_xbar_out_b_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_c_ready = auto_system_bus_xbar_out_c_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_valid = auto_system_bus_xbar_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_opcode = auto_system_bus_xbar_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_param = auto_system_bus_xbar_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_size = auto_system_bus_xbar_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_source = auto_system_bus_xbar_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_sink = auto_system_bus_xbar_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_denied = auto_system_bus_xbar_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_data = auto_system_bus_xbar_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_2_d_bits_corrupt = auto_system_bus_xbar_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23683.4]
assign system_bus_xbar_auto_out_1_a_ready = coupler_to_bus_named_periphery_bus_auto_widget_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_valid = coupler_to_bus_named_periphery_bus_auto_widget_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_opcode = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_param = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_size = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_source = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_sink = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_denied = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_data = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_1_d_bits_corrupt = coupler_to_bus_named_periphery_bus_auto_widget_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign system_bus_xbar_auto_out_0_a_ready = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_valid = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_bits_opcode = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_bits_size = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_bits_source = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_bits_denied = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_bits_data = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign system_bus_xbar_auto_out_0_d_bits_corrupt = coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_from_tile_named_tile_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23653.4]
assign coupler_from_tile_named_tile_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23654.4]
assign coupler_from_tile_named_tile_auto_buffer_out_a_ready = system_bus_xbar_auto_in_0_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_b_valid = system_bus_xbar_auto_in_0_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_b_bits_param = system_bus_xbar_auto_in_0_b_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_b_bits_address = system_bus_xbar_auto_in_0_b_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_c_ready = system_bus_xbar_auto_in_0_c_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_valid = system_bus_xbar_auto_in_0_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_opcode = system_bus_xbar_auto_in_0_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_param = system_bus_xbar_auto_in_0_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_size = system_bus_xbar_auto_in_0_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_source = system_bus_xbar_auto_in_0_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_sink = system_bus_xbar_auto_in_0_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_denied = system_bus_xbar_auto_in_0_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_data = system_bus_xbar_auto_in_0_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_buffer_out_d_bits_corrupt = system_bus_xbar_auto_in_0_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23681.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_valid = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_opcode = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_param = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_size = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_source = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_address = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_mask = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_data = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_a_bits_corrupt = auto_coupler_from_tile_named_tile_tl_master_xing_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_b_ready = auto_coupler_from_tile_named_tile_tl_master_xing_in_b_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_valid = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_opcode = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_param = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_size = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_source = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_address = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_data = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_c_bits_corrupt = auto_coupler_from_tile_named_tile_tl_master_xing_in_c_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_d_ready = auto_coupler_from_tile_named_tile_tl_master_xing_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_e_valid = auto_coupler_from_tile_named_tile_tl_master_xing_in_e_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_from_tile_named_tile_auto_tl_master_xing_in_e_bits_sink = auto_coupler_from_tile_named_tile_tl_master_xing_in_e_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23684.4]
assign coupler_to_port_named_mmio_port_axi4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23659.4]
assign coupler_to_port_named_mmio_port_axi4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23660.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_valid = system_bus_xbar_auto_out_0_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_opcode = system_bus_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_param = system_bus_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_size = system_bus_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_source = system_bus_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_address = system_bus_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_mask = system_bus_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_data = system_bus_xbar_auto_out_0_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_a_bits_corrupt = system_bus_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_buffer_in_d_ready = system_bus_xbar_auto_out_0_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23679.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_aw_ready = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_aw_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_w_ready = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_w_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_valid = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_id = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_b_bits_resp = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_b_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_ar_ready = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_ar_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_valid = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_id = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_data = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_resp = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_port_named_mmio_port_axi4_auto_axi4buf_out_r_bits_last = auto_coupler_to_port_named_mmio_port_axi4_axi4buf_out_r_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23685.4]
assign coupler_to_bus_named_periphery_bus_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23665.4]
assign coupler_to_bus_named_periphery_bus_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23666.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_valid = system_bus_xbar_auto_out_1_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_opcode = system_bus_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_param = system_bus_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_size = system_bus_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_source = system_bus_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_address = system_bus_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_mask = system_bus_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_data = system_bus_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_a_bits_corrupt = system_bus_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_widget_in_d_ready = system_bus_xbar_auto_out_1_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@23680.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_a_ready = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_valid = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_opcode = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_param = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_size = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_source = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_sink = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_denied = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_data = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_to_bus_named_periphery_bus_auto_bus_xing_out_d_bits_corrupt = auto_coupler_to_bus_named_periphery_bus_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@23686.4]
assign coupler_from_bus_named_front_bus_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23671.4]
assign coupler_from_bus_named_front_bus_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@23672.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_a_ready = system_bus_xbar_auto_in_1_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_valid = system_bus_xbar_auto_in_1_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_opcode = system_bus_xbar_auto_in_1_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_param = system_bus_xbar_auto_in_1_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_size = system_bus_xbar_auto_in_1_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_source = system_bus_xbar_auto_in_1_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_sink = system_bus_xbar_auto_in_1_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_denied = system_bus_xbar_auto_in_1_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_data = system_bus_xbar_auto_in_1_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_widget_out_d_bits_corrupt = system_bus_xbar_auto_in_1_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@23682.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_valid = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_opcode = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_param = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_size = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_source = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_address = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_mask = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_data = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_a_bits_corrupt = auto_coupler_from_bus_named_front_bus_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
assign coupler_from_bus_named_front_bus_auto_bus_xing_in_d_ready = auto_coupler_from_bus_named_front_bus_bus_xing_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@23687.4]
endmodule
module TLMonitor_9( // @[:freechips.rocketchip.system.LowRiscConfig.fir@23803.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23804.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23805.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@23806.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@25353.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@23823.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@23824.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@23841.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@23843.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@23844.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@23845.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@23846.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@23846.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@23847.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@23849.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@23850.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@23851.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@23852.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@23853.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@23854.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@23855.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@23856.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23858.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23859.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23861.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23862.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@23863.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@23864.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@23865.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23866.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23867.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23868.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23869.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23870.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23871.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23872.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23873.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23874.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23875.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23876.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23877.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@23878.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@23879.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@23880.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23881.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23882.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23883.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23884.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23885.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23886.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23887.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23888.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23889.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23890.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23891.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23892.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23893.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23894.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23895.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23896.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23897.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23898.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23899.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23900.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23901.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23902.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23903.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23904.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@23911.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23922.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@23950.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23953.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23954.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23955.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23956.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23957.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23958.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23959.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23960.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23961.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23962.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23963.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23964.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23965.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23966.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23967.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23968.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23969.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23970.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23971.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23972.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23975.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23976.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23977.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23978.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23979.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23980.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23981.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23982.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@23990.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23993.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23994.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23995.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23996.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23997.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@23998.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24002.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24003.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@24010.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@24016.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@24017.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@24024.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@24025.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@24031.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@24032.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@24037.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@24039.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@24040.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@24045.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@24046.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@24048.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@24049.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@24054.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@24056.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@24057.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@24063.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@24158.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@24160.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@24161.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@24184.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24220.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24221.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24222.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24223.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24224.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24225.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@24227.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24235.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@24237.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24239.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24240.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@24259.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@24261.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@24262.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@24267.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@24269.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@24270.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@24284.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24317.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24318.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24319.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24320.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@24322.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24330.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@24343.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@24344.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24346.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24347.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@24383.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@24473.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@24474.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@24475.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@24477.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@24478.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@24484.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@24506.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24529.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24530.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24531.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24532.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24536.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24537.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@24556.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@24558.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@24559.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@24573.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@24645.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@24647.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@24648.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@24662.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24714.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24715.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@24753.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@24755.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@24756.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@24763.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@24764.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@24781.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@24783.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24786.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24787.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@24792.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@24794.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@24795.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@24800.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@24802.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@24803.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@24808.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@24810.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@24811.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@24816.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@24818.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@24819.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@24825.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@24849.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@24851.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@24852.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@24857.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@24859.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@24860.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@24883.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@24924.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@24926.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@24927.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@24942.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@24977.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@25013.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@25073.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@25078.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@25079.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@25080.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@25082.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25083.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25084.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25085.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25086.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@25097.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@25098.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@25099.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@25100.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@25101.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@25102.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@25103.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@25105.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@25107.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@25108.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@25113.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@25115.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@25116.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@25121.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@25123.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@25124.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@25129.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@25131.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@25132.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@25137.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@25139.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@25140.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@25147.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@25155.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@25157.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@25158.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@25159.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@25160.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@25161.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@25163.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25164.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25165.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25166.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25167.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@25178.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@25179.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@25180.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@25181.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@25182.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@25183.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@25184.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@25185.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@25187.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@25189.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@25190.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@25195.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@25197.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@25198.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@25203.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@25205.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@25206.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@25211.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@25213.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@25214.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@25219.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@25221.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@25222.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@25227.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@25229.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@25230.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@25237.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@25246.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@25256.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25257.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25258.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25259.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25260.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@25279.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25280.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25281.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25282.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25283.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@25298.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@25301.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@25303.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@25304.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@25305.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@25307.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@25308.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@25300.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@25319.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@25321.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@25322.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@25324.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@25326.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@25327.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@25328.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@25330.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@25331.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@25323.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@25337.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@25338.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@25339.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@25340.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@25342.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@25343.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@25348.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@25349.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@25350.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@25352.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@25355.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@25356.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@25357.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@25358.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@25359.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@25360.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@25362.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@25363.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@25369.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@25373.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24005.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@24118.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24242.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24349.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@24448.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24539.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@24628.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24717.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24789.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@24831.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@24889.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@24948.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@24983.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@25019.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@25353.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@23823.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@23824.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@23841.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@23843.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@23844.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@23845.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@23846.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@23846.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@23847.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@23849.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@23850.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@23851.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@23852.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@23853.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@23854.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@23855.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@23856.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23858.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23859.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23861.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23862.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@23863.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@23864.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@23865.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23866.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23867.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23868.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23869.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23870.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23871.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23872.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23873.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23874.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23875.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23876.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23877.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@23878.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@23879.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@23880.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23881.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23882.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23883.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23884.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23885.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23886.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23887.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23888.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23889.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23890.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23891.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23892.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23893.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23894.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23895.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23896.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23897.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23898.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23899.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23900.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23901.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@23902.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@23903.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@23904.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@23911.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23922.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@23950.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23953.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23954.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23955.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23956.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23957.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23958.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23959.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23960.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23961.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23962.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23963.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23964.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23965.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23966.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23967.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23968.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23969.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23970.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23971.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23972.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23975.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23976.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23977.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23978.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23979.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23980.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23981.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23982.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@23990.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@23993.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@23994.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23995.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@23996.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@23997.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@23998.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24002.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24003.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@24010.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@24016.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@24017.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@24024.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@24025.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@24031.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@24032.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@24037.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@24039.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@24040.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@24045.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@24046.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@24048.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@24049.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@24054.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@24056.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@24057.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@24063.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@24158.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@24160.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@24161.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@24184.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24220.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24221.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24222.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24223.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24224.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24225.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@24227.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24235.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@24237.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24239.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24240.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@24259.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@24261.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@24262.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@24267.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@24269.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@24270.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@24284.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24317.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24318.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24319.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24320.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@24322.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24330.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@24343.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@24344.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24346.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24347.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@24383.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@24473.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@24474.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@24475.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@24477.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@24478.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@24484.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@24506.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24529.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24530.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@24531.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@24532.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24536.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24537.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@24556.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@24558.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@24559.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@24573.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@24645.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@24647.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@24648.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@24662.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24714.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24715.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@24753.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@24755.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@24756.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@24763.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@24764.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@24781.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@24783.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24786.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24787.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@24792.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@24794.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@24795.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@24800.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@24802.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@24803.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@24808.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@24810.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@24811.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@24816.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@24818.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@24819.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@24825.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@24849.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@24851.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@24852.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@24857.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@24859.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@24860.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@24883.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@24924.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@24926.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@24927.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@24942.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@24977.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@25013.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@25073.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@25078.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@25079.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@25080.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25083.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25084.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25085.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25086.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@25102.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@25103.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@25105.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@25107.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@25108.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@25113.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@25115.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@25116.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@25121.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@25123.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@25124.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@25129.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@25131.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@25132.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@25137.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@25139.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@25140.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@25147.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@25155.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@25157.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@25158.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@25159.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@25160.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@25161.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25164.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25165.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25166.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25167.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@25184.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@25185.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@25187.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@25189.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@25190.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@25195.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@25197.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@25198.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@25203.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@25205.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@25206.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@25211.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@25213.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@25214.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@25219.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@25221.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@25222.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@25227.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@25229.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@25230.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@25237.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25257.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25258.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25259.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25260.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25280.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25281.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@25282.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@25283.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@25298.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@25301.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@25303.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@25304.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@25305.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@25307.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@25308.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@25300.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@25319.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@25321.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@25322.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@25324.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@25326.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@25327.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@25328.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@25330.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@25331.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@25323.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@25337.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@25338.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@25339.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@25340.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@25342.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@25343.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@25348.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@25349.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@25350.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@25355.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@25356.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@25357.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@25358.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@25359.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@25360.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@25362.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@25363.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@25369.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@25373.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24005.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@24118.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24242.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24349.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@24448.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24539.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@24628.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24717.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24789.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@24831.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@24889.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@24948.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@24983.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@25019.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:164:18)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@23818.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@23819.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@23947.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@23948.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24005.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@24006.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:164:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@24012.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@24013.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@24019.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@24020.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@24027.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@24028.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@24034.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@24035.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@24042.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@24043.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@24051.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@24052.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@24059.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@24060.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@24118.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@24119.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:164:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@24125.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@24126.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@24132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@24133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@24140.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@24141.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@24147.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@24148.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@24155.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@24156.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:164:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@24163.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@24164.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@24172.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@24173.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@24180.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@24181.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24242.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@24243.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@24249.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@24250.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@24256.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@24257.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@24264.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@24265.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@24272.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@24273.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@24280.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@24281.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24349.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@24350.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@24356.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@24357.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@24363.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@24364.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@24371.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@24372.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@24379.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@24380.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@24448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@24449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@24455.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@24456.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@24462.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@24463.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@24470.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@24471.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@24480.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@24481.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24539.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@24540.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@24546.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@24547.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@24553.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@24554.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@24561.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@24562.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@24569.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@24570.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@24628.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@24629.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@24635.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@24636.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@24642.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@24643.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@24650.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@24651.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@24658.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@24659.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:164:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24717.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@24718.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@24724.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@24725.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:164:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@24731.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@24732.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:164:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@24739.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@24740.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@24747.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@24748.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:164:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@24758.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@24759.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24789.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@24790.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@24797.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@24798.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@24805.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@24806.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@24813.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@24814.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@24821.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@24822.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@24831.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@24832.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@24838.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@24839.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@24846.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@24847.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@24854.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@24855.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@24862.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@24863.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@24870.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@24871.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@24879.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@24880.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@24889.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@24890.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@24896.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@24897.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:164:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@24904.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@24905.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@24912.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@24913.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@24920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@24921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@24929.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@24930.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@24938.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@24939.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@24948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@24949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@24956.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@24957.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@24964.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@24965.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@24973.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@24974.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@24983.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@24984.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@24991.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@24992.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@25000.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@25001.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@25009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@25010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@25019.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@25020.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:164:18)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@25027.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@25028.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:164:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@25035.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@25036.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:164:18)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@25044.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@25045.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:164:18)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@25054.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@25055.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:164:18)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@25062.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@25063.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:164:18)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@25070.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@25071.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@25110.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@25111.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@25118.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@25119.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@25126.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@25127.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@25134.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@25135.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@25142.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@25143.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@25192.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@25193.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@25200.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@25201.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@25208.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@25209.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@25216.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@25217.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@25224.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@25225.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:164:18)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@25232.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@25233.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:164:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@25310.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@25311.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:164:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@25333.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@25334.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at BusWrapper.scala:164:18)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@25345.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@25346.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:164:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@25365.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@25366.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLXbar_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@25378.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25379.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25380.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@25381.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
TLMonitor_9 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@25388.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@25428.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@25427.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@25390.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@25391.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@25424.4]
endmodule
module TLMonitor_10( // @[:freechips.rocketchip.system.LowRiscConfig.fir@25569.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25570.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25571.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@25572.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@27119.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@25589.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@25590.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@25607.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@25609.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@25610.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@25611.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@25612.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@25612.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@25613.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@25615.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@25616.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@25617.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@25618.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@25619.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@25620.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@25621.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@25622.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25624.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25625.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25627.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25628.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@25629.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@25630.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@25631.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25632.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25633.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25634.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25635.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25636.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25637.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25638.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25639.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25640.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25641.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25642.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25643.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@25644.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@25645.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@25646.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25647.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25648.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25649.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25650.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25651.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25652.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25653.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25654.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25655.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25656.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25657.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25658.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25659.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25660.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25661.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25662.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25663.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25664.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25665.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25666.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25667.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25668.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25669.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25670.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@25677.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25688.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@25716.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25719.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25720.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25721.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25722.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25723.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25724.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25725.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25726.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25727.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25728.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25729.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25730.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25731.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25732.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25733.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25734.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25735.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25736.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25737.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25738.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25741.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25742.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25743.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25744.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25745.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25746.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25747.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25748.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@25756.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25759.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25760.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25761.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25762.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25763.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@25764.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25768.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25769.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@25776.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@25782.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@25783.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@25790.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@25791.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@25797.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@25798.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@25803.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@25805.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@25806.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@25811.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@25812.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@25814.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@25815.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@25820.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@25822.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@25823.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@25829.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@25924.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@25926.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@25927.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@25950.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25986.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25987.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25988.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25989.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25990.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@25991.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@25993.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26001.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@26003.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26005.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26006.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@26025.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@26027.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@26028.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@26033.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@26035.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@26036.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@26050.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26083.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26084.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26085.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26086.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@26088.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26096.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@26109.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@26110.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26112.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26113.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@26149.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@26239.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@26240.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@26241.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@26243.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@26244.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@26250.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@26272.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26295.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26296.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26297.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26298.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26302.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26303.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@26322.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@26324.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@26325.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@26339.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@26411.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@26413.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@26414.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@26428.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26480.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26481.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@26519.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@26521.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@26522.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@26529.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@26530.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@26547.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@26549.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26552.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26553.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@26558.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@26560.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@26561.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@26566.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@26568.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@26569.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@26574.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@26576.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@26577.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@26582.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@26584.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@26585.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@26591.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@26615.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@26617.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@26618.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@26623.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@26625.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@26626.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@26649.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@26690.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@26692.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@26693.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@26708.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@26743.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@26779.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@26839.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@26844.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@26845.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@26846.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@26848.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26849.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26850.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26851.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@26852.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@26863.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@26864.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@26865.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@26866.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@26867.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@26868.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@26869.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@26871.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@26873.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@26874.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@26879.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@26881.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@26882.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@26887.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@26889.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@26890.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@26895.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@26897.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@26898.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@26903.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@26905.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@26906.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@26913.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@26921.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@26923.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@26924.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@26925.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@26926.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@26927.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@26929.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26930.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26931.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26932.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@26933.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@26944.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@26945.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@26946.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@26947.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@26948.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@26949.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@26950.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@26951.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@26953.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@26955.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@26956.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@26961.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@26963.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@26964.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@26969.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@26971.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@26972.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@26977.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@26979.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@26980.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@26985.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@26987.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@26988.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@26993.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@26995.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@26996.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@27003.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@27012.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@27022.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27023.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27024.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27025.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@27026.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@27045.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27046.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27047.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27048.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@27049.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@27064.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@27067.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@27069.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@27070.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@27071.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@27073.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@27074.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@27066.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@27085.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@27087.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@27088.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@27090.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@27092.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@27093.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@27094.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@27096.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@27097.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@27089.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@27103.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@27104.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@27105.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@27106.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@27108.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@27109.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@27114.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@27115.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@27116.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@27118.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@27121.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@27122.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@27123.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@27124.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@27125.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@27126.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@27128.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@27129.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@27135.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@27139.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25771.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@25884.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26008.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26115.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@26214.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26305.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@26394.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26483.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26555.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@26597.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@26655.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@26714.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@26749.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@26785.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@27119.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@25589.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@25590.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@25607.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@25609.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@25610.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@25611.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@25612.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@25612.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@25613.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@25615.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@25616.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@25617.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@25618.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@25619.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@25620.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@25621.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@25622.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25624.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25625.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25627.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25628.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@25629.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@25630.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@25631.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25632.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25633.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25634.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25635.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25636.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25637.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25638.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25639.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25640.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25641.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25642.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25643.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@25644.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@25645.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@25646.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25647.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25648.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25649.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25650.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25651.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25652.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25653.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25654.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25655.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25656.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25657.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25658.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25659.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25660.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25661.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25662.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25663.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25664.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25665.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25666.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25667.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@25668.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@25669.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@25670.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@25677.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25688.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@25716.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25719.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25720.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25721.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25722.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25723.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25724.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25725.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25726.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25727.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25728.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25729.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25730.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25731.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25732.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25733.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25734.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25735.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25736.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25737.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25738.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25741.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25742.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25743.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25744.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25745.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25746.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25747.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25748.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@25756.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@25759.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@25760.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25761.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@25762.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@25763.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@25764.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25768.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25769.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@25776.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@25782.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@25783.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@25790.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@25791.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@25797.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@25798.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@25803.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@25805.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@25806.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@25811.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@25812.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@25814.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@25815.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@25820.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@25822.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@25823.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@25829.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@25924.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@25926.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@25927.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@25950.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25986.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25987.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25988.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25989.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@25990.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@25991.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@25993.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26001.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@26003.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26005.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26006.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@26025.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@26027.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@26028.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@26033.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@26035.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@26036.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@26050.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26083.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26084.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26085.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26086.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@26088.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26096.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@26109.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@26110.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26112.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26113.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@26149.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@26239.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@26240.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@26241.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@26243.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@26244.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@26250.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@26272.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26295.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26296.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@26297.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@26298.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26302.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26303.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@26322.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@26324.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@26325.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@26339.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@26411.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@26413.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@26414.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@26428.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26480.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26481.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@26519.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@26521.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@26522.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@26529.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@26530.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@26547.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@26549.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26552.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26553.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@26558.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@26560.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@26561.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@26566.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@26568.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@26569.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@26574.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@26576.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@26577.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@26582.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@26584.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@26585.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@26591.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@26615.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@26617.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@26618.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@26623.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@26625.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@26626.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@26649.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@26690.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@26692.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@26693.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@26708.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@26743.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@26779.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@26839.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@26844.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@26845.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@26846.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26849.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26850.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26851.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@26852.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@26868.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@26869.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@26871.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@26873.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@26874.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@26879.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@26881.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@26882.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@26887.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@26889.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@26890.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@26895.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@26897.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@26898.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@26903.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@26905.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@26906.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@26913.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@26921.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@26923.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@26924.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@26925.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@26926.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@26927.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26930.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26931.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@26932.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@26933.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@26950.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@26951.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@26953.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@26955.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@26956.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@26961.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@26963.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@26964.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@26969.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@26971.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@26972.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@26977.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@26979.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@26980.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@26985.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@26987.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@26988.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@26993.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@26995.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@26996.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@27003.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27023.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27024.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27025.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@27026.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27046.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27047.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@27048.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@27049.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@27064.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@27067.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@27069.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@27070.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@27071.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@27073.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@27074.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@27066.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@27085.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@27087.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@27088.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@27090.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@27092.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@27093.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@27094.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@27096.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@27097.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@27089.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@27103.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@27104.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@27105.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@27106.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@27108.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@27109.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@27114.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@27115.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@27116.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@27121.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@27122.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@27123.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@27124.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@27125.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@27126.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@27128.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@27129.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@27135.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@27139.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25771.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@25884.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26008.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26115.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@26214.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26305.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@26394.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26483.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26555.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@26597.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@26655.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@26714.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@26749.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@26785.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:164:39)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@25584.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@25585.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@25713.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@25714.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25771.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@25772.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:164:39)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@25778.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@25779.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@25785.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@25786.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@25793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@25794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@25800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@25801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@25808.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@25809.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@25817.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@25818.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@25825.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@25826.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@25884.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@25885.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:164:39)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@25891.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@25892.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@25898.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@25899.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@25906.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@25907.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@25913.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@25914.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@25921.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@25922.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:164:39)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@25929.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@25930.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@25938.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@25939.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@25946.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@25947.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26008.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@26009.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@26015.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@26016.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@26022.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@26023.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@26030.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@26031.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@26038.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@26039.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@26046.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@26047.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26115.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@26116.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@26122.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@26123.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@26129.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@26130.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@26137.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@26138.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@26145.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@26146.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@26214.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@26215.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@26221.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@26222.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@26228.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@26229.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@26236.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@26237.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@26246.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@26247.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26305.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@26306.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@26312.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@26313.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@26319.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@26320.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@26327.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@26328.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@26335.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@26336.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@26394.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@26395.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@26401.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@26402.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@26408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@26409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@26416.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@26417.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@26424.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@26425.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:164:39)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26483.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@26484.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@26490.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@26491.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:164:39)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@26497.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@26498.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:164:39)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@26505.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@26506.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@26513.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@26514.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:164:39)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@26524.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@26525.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26555.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@26556.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@26563.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@26564.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@26571.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@26572.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@26579.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@26580.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@26587.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@26588.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@26597.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@26598.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@26604.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@26605.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@26612.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@26613.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@26620.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@26621.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@26628.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@26629.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@26636.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@26637.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@26645.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@26646.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@26655.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@26656.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@26662.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@26663.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:164:39)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@26670.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@26671.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@26678.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@26679.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@26686.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@26687.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@26695.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@26696.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@26704.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@26705.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@26714.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@26715.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@26722.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@26723.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@26730.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@26731.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@26739.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@26740.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@26749.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@26750.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@26757.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@26758.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@26766.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@26767.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@26775.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@26776.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@26785.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@26786.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:164:39)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@26793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@26794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:164:39)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@26801.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@26802.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:164:39)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@26810.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@26811.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:164:39)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@26820.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@26821.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:164:39)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@26828.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@26829.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:164:39)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@26836.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@26837.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@26876.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@26877.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@26884.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@26885.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@26892.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@26893.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@26900.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@26901.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@26908.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@26909.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@26958.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@26959.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@26966.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@26967.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@26974.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@26975.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@26982.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@26983.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@26990.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@26991.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:164:39)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@26998.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@26999.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:164:39)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@27076.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@27077.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:164:39)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@27099.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@27100.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 5 (connected at BusWrapper.scala:164:39)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@27111.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@27112.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:164:39)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@27131.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@27132.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_31( // @[:freechips.rocketchip.system.LowRiscConfig.fir@27144.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27145.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27146.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [3:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [31:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [3:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [31:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@27147.4]
);
reg [2:0] _T_35_opcode [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_opcode__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_opcode__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [2:0] _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_opcode__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_opcode__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_opcode__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [2:0] _T_35_param [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_1;
wire [2:0] _T_35_param__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_param__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [2:0] _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_param__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_param__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_param__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [3:0] _T_35_size [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_2;
wire [3:0] _T_35_size__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_size__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [3:0] _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_size__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_size__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_size__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [3:0] _T_35_source [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_3;
wire [3:0] _T_35_source__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_source__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [3:0] _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_source__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_source__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_source__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _T_35_address [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_4;
wire [31:0] _T_35_address__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_address__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [31:0] _T_35_address__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_address__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_address__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_address__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [7:0] _T_35_mask [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_5;
wire [7:0] _T_35_mask__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_mask__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [7:0] _T_35_mask__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_mask__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_mask__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_mask__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [63:0] _T_35_data [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [63:0] _RAND_6;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg _T_35_corrupt [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg [31:0] _RAND_7;
wire _T_35_corrupt__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_corrupt__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_corrupt__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_corrupt__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
wire _T_35_corrupt__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@27150.4]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@27151.4]
reg [31:0] _RAND_9;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@27152.4]
reg [31:0] _RAND_10;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@27153.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@27154.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@27155.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@27156.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27157.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27160.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27175.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27181.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@27184.4]
assign _T_35_opcode__T_58_addr = value_1;
assign _T_35_opcode__T_58_data = _T_35_opcode[_T_35_opcode__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_opcode__T_50_data = io_enq_bits_opcode;
assign _T_35_opcode__T_50_addr = value;
assign _T_35_opcode__T_50_mask = 1'h1;
assign _T_35_opcode__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_param__T_58_addr = value_1;
assign _T_35_param__T_58_data = _T_35_param[_T_35_param__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_param__T_50_data = io_enq_bits_param;
assign _T_35_param__T_50_addr = value;
assign _T_35_param__T_50_mask = 1'h1;
assign _T_35_param__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_58_addr = value_1;
assign _T_35_size__T_58_data = _T_35_size[_T_35_size__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_size__T_50_data = io_enq_bits_size;
assign _T_35_size__T_50_addr = value;
assign _T_35_size__T_50_mask = 1'h1;
assign _T_35_size__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_source__T_58_addr = value_1;
assign _T_35_source__T_58_data = _T_35_source[_T_35_source__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_source__T_50_data = io_enq_bits_source;
assign _T_35_source__T_50_addr = value;
assign _T_35_source__T_50_mask = 1'h1;
assign _T_35_source__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_address__T_58_addr = value_1;
assign _T_35_address__T_58_data = _T_35_address[_T_35_address__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_address__T_50_data = io_enq_bits_address;
assign _T_35_address__T_50_addr = value;
assign _T_35_address__T_50_mask = 1'h1;
assign _T_35_address__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_mask__T_58_addr = value_1;
assign _T_35_mask__T_58_data = _T_35_mask[_T_35_mask__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_mask__T_50_data = io_enq_bits_mask;
assign _T_35_mask__T_50_addr = value;
assign _T_35_mask__T_50_mask = 1'h1;
assign _T_35_mask__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_corrupt__T_58_addr = value_1;
assign _T_35_corrupt__T_58_data = _T_35_corrupt[_T_35_corrupt__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
assign _T_35_corrupt__T_50_data = io_enq_bits_corrupt;
assign _T_35_corrupt__T_50_addr = value;
assign _T_35_corrupt__T_50_mask = 1'h1;
assign _T_35_corrupt__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@27153.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@27154.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@27155.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@27156.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27157.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27160.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27175.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27181.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@27184.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@27191.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@27189.4]
assign io_deq_bits_opcode = _T_35_opcode__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27200.4]
assign io_deq_bits_param = _T_35_param__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27199.4]
assign io_deq_bits_size = _T_35_size__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27198.4]
assign io_deq_bits_source = _T_35_source__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27197.4]
assign io_deq_bits_address = _T_35_address__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27196.4]
assign io_deq_bits_mask = _T_35_mask__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27195.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27194.4]
assign io_deq_bits_corrupt = _T_35_corrupt__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27193.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_source[initvar] = _RAND_3[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_address[initvar] = _RAND_4[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_mask[initvar] = _RAND_5[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_data[initvar] = _RAND_6[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_39 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_opcode__T_50_en & _T_35_opcode__T_50_mask) begin
_T_35_opcode[_T_35_opcode__T_50_addr] <= _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_param__T_50_en & _T_35_param__T_50_mask) begin
_T_35_param[_T_35_param__T_50_addr] <= _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_size__T_50_en & _T_35_size__T_50_mask) begin
_T_35_size[_T_35_size__T_50_addr] <= _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_source__T_50_en & _T_35_source__T_50_mask) begin
_T_35_source[_T_35_source__T_50_addr] <= _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_address__T_50_en & _T_35_address__T_50_mask) begin
_T_35_address[_T_35_address__T_50_addr] <= _T_35_address__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_mask__T_50_en & _T_35_mask__T_50_mask) begin
_T_35_mask[_T_35_mask__T_50_addr] <= _T_35_mask__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if(_T_35_corrupt__T_50_en & _T_35_corrupt__T_50_mask) begin
_T_35_corrupt[_T_35_corrupt__T_50_addr] <= _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27149.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module Queue_32( // @[:freechips.rocketchip.system.LowRiscConfig.fir@27208.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27209.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27210.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input [1:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input [3:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input [1:0] io_enq_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input io_enq_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output [3:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output [1:0] io_deq_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output io_deq_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@27211.4]
);
reg [2:0] _T_35_opcode [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_opcode__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_opcode__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire [2:0] _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_opcode__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_opcode__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_opcode__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [1:0] _T_35_param [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_1;
wire [1:0] _T_35_param__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_param__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire [1:0] _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_param__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_param__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_param__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [3:0] _T_35_size [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_2;
wire [3:0] _T_35_size__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_size__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire [3:0] _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_size__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_size__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_size__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [3:0] _T_35_source [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_3;
wire [3:0] _T_35_source__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_source__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire [3:0] _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_source__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_source__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_source__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [1:0] _T_35_sink [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_4;
wire [1:0] _T_35_sink__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_sink__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire [1:0] _T_35_sink__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_sink__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_sink__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_sink__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg _T_35_denied [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_5;
wire _T_35_denied__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_denied__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_denied__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_denied__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_denied__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_denied__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [63:0] _T_35_data [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [63:0] _RAND_6;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg _T_35_corrupt [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg [31:0] _RAND_7;
wire _T_35_corrupt__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_corrupt__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_corrupt__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_corrupt__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
wire _T_35_corrupt__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@27214.4]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@27215.4]
reg [31:0] _RAND_9;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@27216.4]
reg [31:0] _RAND_10;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@27217.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@27218.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@27219.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@27220.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27221.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27224.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27239.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27245.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@27248.4]
assign _T_35_opcode__T_58_addr = value_1;
assign _T_35_opcode__T_58_data = _T_35_opcode[_T_35_opcode__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_opcode__T_50_data = io_enq_bits_opcode;
assign _T_35_opcode__T_50_addr = value;
assign _T_35_opcode__T_50_mask = 1'h1;
assign _T_35_opcode__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_param__T_58_addr = value_1;
assign _T_35_param__T_58_data = _T_35_param[_T_35_param__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_param__T_50_data = io_enq_bits_param;
assign _T_35_param__T_50_addr = value;
assign _T_35_param__T_50_mask = 1'h1;
assign _T_35_param__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_58_addr = value_1;
assign _T_35_size__T_58_data = _T_35_size[_T_35_size__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_size__T_50_data = io_enq_bits_size;
assign _T_35_size__T_50_addr = value;
assign _T_35_size__T_50_mask = 1'h1;
assign _T_35_size__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_source__T_58_addr = value_1;
assign _T_35_source__T_58_data = _T_35_source[_T_35_source__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_source__T_50_data = io_enq_bits_source;
assign _T_35_source__T_50_addr = value;
assign _T_35_source__T_50_mask = 1'h1;
assign _T_35_source__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_sink__T_58_addr = value_1;
assign _T_35_sink__T_58_data = _T_35_sink[_T_35_sink__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_sink__T_50_data = io_enq_bits_sink;
assign _T_35_sink__T_50_addr = value;
assign _T_35_sink__T_50_mask = 1'h1;
assign _T_35_sink__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_denied__T_58_addr = value_1;
assign _T_35_denied__T_58_data = _T_35_denied[_T_35_denied__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_denied__T_50_data = io_enq_bits_denied;
assign _T_35_denied__T_50_addr = value;
assign _T_35_denied__T_50_mask = 1'h1;
assign _T_35_denied__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_corrupt__T_58_addr = value_1;
assign _T_35_corrupt__T_58_data = _T_35_corrupt[_T_35_corrupt__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
assign _T_35_corrupt__T_50_data = io_enq_bits_corrupt;
assign _T_35_corrupt__T_50_addr = value;
assign _T_35_corrupt__T_50_mask = 1'h1;
assign _T_35_corrupt__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@27217.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@27218.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@27219.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@27220.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27221.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@27224.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27239.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@27245.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@27248.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@27255.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@27253.4]
assign io_deq_bits_opcode = _T_35_opcode__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27264.4]
assign io_deq_bits_param = _T_35_param__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27263.4]
assign io_deq_bits_size = _T_35_size__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27262.4]
assign io_deq_bits_source = _T_35_source__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27261.4]
assign io_deq_bits_sink = _T_35_sink__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27260.4]
assign io_deq_bits_denied = _T_35_denied__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27259.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27258.4]
assign io_deq_bits_corrupt = _T_35_corrupt__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@27257.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_param[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_source[initvar] = _RAND_3[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_sink[initvar] = _RAND_4[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_denied[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_data[initvar] = _RAND_6[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_39 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_opcode__T_50_en & _T_35_opcode__T_50_mask) begin
_T_35_opcode[_T_35_opcode__T_50_addr] <= _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_param__T_50_en & _T_35_param__T_50_mask) begin
_T_35_param[_T_35_param__T_50_addr] <= _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_size__T_50_en & _T_35_size__T_50_mask) begin
_T_35_size[_T_35_size__T_50_addr] <= _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_source__T_50_en & _T_35_source__T_50_mask) begin
_T_35_source[_T_35_source__T_50_addr] <= _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_sink__T_50_en & _T_35_sink__T_50_mask) begin
_T_35_sink[_T_35_sink__T_50_addr] <= _T_35_sink__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_denied__T_50_en & _T_35_denied__T_50_mask) begin
_T_35_denied[_T_35_denied__T_50_addr] <= _T_35_denied__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if(_T_35_corrupt__T_50_en & _T_35_corrupt__T_50_mask) begin
_T_35_corrupt[_T_35_corrupt__T_50_addr] <= _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@27213.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module TLBuffer_4( // @[:freechips.rocketchip.system.LowRiscConfig.fir@27272.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27273.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27274.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@27275.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [3:0] Queue_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [7:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [3:0] Queue_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [7:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [3:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [1:0] Queue_1_io_enq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [63:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [3:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [1:0] Queue_1_io_deq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire [63:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
TLMonitor_10 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@27282.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_31 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27323.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_opcode(Queue_io_enq_bits_opcode),
.io_enq_bits_param(Queue_io_enq_bits_param),
.io_enq_bits_size(Queue_io_enq_bits_size),
.io_enq_bits_source(Queue_io_enq_bits_source),
.io_enq_bits_address(Queue_io_enq_bits_address),
.io_enq_bits_mask(Queue_io_enq_bits_mask),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_io_enq_bits_corrupt),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_opcode(Queue_io_deq_bits_opcode),
.io_deq_bits_param(Queue_io_deq_bits_param),
.io_deq_bits_size(Queue_io_deq_bits_size),
.io_deq_bits_source(Queue_io_deq_bits_source),
.io_deq_bits_address(Queue_io_deq_bits_address),
.io_deq_bits_mask(Queue_io_deq_bits_mask),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_io_deq_bits_corrupt)
);
Queue_32 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@27337.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_opcode(Queue_1_io_enq_bits_opcode),
.io_enq_bits_param(Queue_1_io_enq_bits_param),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_source(Queue_1_io_enq_bits_source),
.io_enq_bits_sink(Queue_1_io_enq_bits_sink),
.io_enq_bits_denied(Queue_1_io_enq_bits_denied),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_opcode(Queue_1_io_deq_bits_opcode),
.io_deq_bits_param(Queue_1_io_deq_bits_param),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_source(Queue_1_io_deq_bits_source),
.io_deq_bits_sink(Queue_1_io_deq_bits_sink),
.io_deq_bits_denied(Queue_1_io_deq_bits_denied),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt)
);
assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@27322.4]
assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@27321.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@27284.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@27285.4]
assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@27318.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@27324.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@27325.4]
assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@27326.4]
assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27334.4]
assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27333.4]
assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27332.4]
assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27331.4]
assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27330.4]
assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27329.4]
assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27328.4]
assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27327.4]
assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.LowRiscConfig.fir@27336.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@27338.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@27339.4]
assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@27340.4]
assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27348.4]
assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27347.4]
assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27346.4]
assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27345.4]
assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27344.4]
assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27343.4]
assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27342.4]
assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@27341.4]
assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.LowRiscConfig.fir@27350.4]
endmodule
module TLMonitor_11( // @[:freechips.rocketchip.system.LowRiscConfig.fir@27365.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27366.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27367.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@27368.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@28915.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@27385.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@27386.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@27403.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@27405.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@27406.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@27407.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@27408.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@27408.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@27409.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@27411.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@27412.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@27413.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@27414.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@27415.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@27416.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@27417.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@27418.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27420.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27421.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27423.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27424.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@27425.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@27426.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@27427.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27428.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27429.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27430.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27431.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27432.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27433.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27434.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27435.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27436.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27437.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27438.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27439.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@27440.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@27441.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@27442.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27443.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27444.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27445.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27446.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27447.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27448.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27449.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27450.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27451.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27452.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27453.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27454.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27455.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27456.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27457.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27458.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27459.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27460.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27461.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27462.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27463.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27464.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27465.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27466.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@27473.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27484.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@27512.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27515.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27516.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27517.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27518.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27519.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27520.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27521.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27522.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27523.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27524.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27525.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27526.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27527.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27528.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27529.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27530.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27531.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27532.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27533.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27534.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27537.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27538.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27539.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27540.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27541.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27542.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27543.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27544.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@27552.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27555.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27556.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27557.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27558.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27559.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27560.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27564.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27565.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@27572.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@27578.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@27579.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@27586.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@27587.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@27593.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@27594.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@27599.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@27601.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@27602.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@27607.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@27608.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@27610.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@27611.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@27616.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@27618.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@27619.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@27625.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@27720.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@27722.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@27723.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@27746.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27782.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27783.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27784.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27785.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27786.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27787.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@27789.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27797.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@27799.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27801.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27802.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@27821.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@27823.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@27824.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@27829.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@27831.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@27832.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@27846.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27879.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27880.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27881.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27882.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@27884.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27892.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@27905.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@27906.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27908.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27909.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@27945.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@28035.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@28036.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@28037.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@28039.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@28040.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@28046.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@28068.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@28091.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@28092.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@28093.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@28094.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28098.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28099.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@28118.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@28120.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@28121.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@28135.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@28207.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@28209.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@28210.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@28224.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28276.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28277.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@28315.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@28317.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@28318.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@28325.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@28326.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@28343.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@28345.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28348.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28349.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@28354.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@28356.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@28357.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@28362.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@28364.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@28365.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@28370.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@28372.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@28373.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@28378.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@28380.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@28381.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@28387.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@28411.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@28413.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@28414.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@28419.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@28421.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@28422.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@28445.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@28486.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@28488.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@28489.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@28504.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@28539.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@28575.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@28635.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@28640.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@28641.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@28642.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@28644.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28645.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28646.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28647.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28648.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@28659.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@28660.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@28661.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@28662.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@28663.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@28664.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@28665.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@28667.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@28669.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@28670.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@28675.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@28677.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@28678.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@28683.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@28685.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@28686.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@28691.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@28693.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@28694.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@28699.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@28701.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@28702.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@28709.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@28717.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@28719.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@28720.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@28721.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@28722.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@28723.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@28725.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28726.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28727.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28728.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28729.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@28740.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@28741.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@28742.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@28743.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@28744.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@28745.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@28746.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@28747.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@28749.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@28751.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@28752.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@28757.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@28759.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@28760.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@28765.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@28767.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@28768.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@28773.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@28775.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@28776.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@28781.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@28783.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@28784.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@28789.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@28791.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@28792.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@28799.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@28808.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@28818.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28819.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28820.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28821.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28822.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@28841.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28842.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28843.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28844.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28845.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@28860.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@28863.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@28865.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@28866.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@28867.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@28869.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@28870.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@28862.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@28881.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@28883.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@28884.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@28886.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@28888.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@28889.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@28890.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@28892.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@28893.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@28885.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@28899.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@28900.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@28901.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@28902.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@28904.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@28905.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@28910.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@28911.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@28912.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@28914.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@28917.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@28918.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@28919.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@28920.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@28921.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@28922.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@28924.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@28925.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@28931.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@28935.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27567.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@27680.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27804.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27911.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@28010.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28101.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@28190.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28279.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28351.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@28393.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@28451.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@28510.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@28545.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@28581.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@28915.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@27385.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@27386.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@27403.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@27405.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@27406.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@27407.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@27408.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@27408.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@27409.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@27411.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@27412.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@27413.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@27414.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@27415.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@27416.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@27417.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@27418.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27420.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27421.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27423.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27424.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@27425.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@27426.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@27427.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27428.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27429.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27430.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27431.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27432.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27433.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27434.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27435.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27436.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27437.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27438.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27439.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@27440.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@27441.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@27442.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27443.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27444.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27445.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27446.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27447.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27448.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27449.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27450.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27451.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27452.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27453.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27454.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27455.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27456.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27457.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27458.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27459.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27460.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27461.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27462.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27463.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@27464.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@27465.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@27466.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@27473.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27484.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@27512.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27515.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27516.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27517.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27518.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27519.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27520.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27521.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27522.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27523.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27524.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27525.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27526.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27527.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27528.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27529.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27530.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27531.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27532.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27533.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27534.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27537.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27538.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27539.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27540.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27541.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27542.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27543.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27544.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@27552.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@27555.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@27556.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27557.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@27558.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@27559.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27560.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27564.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27565.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@27572.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@27578.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@27579.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@27586.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@27587.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@27593.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@27594.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@27599.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@27601.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@27602.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@27607.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@27608.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@27610.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@27611.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@27616.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@27618.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@27619.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@27625.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@27720.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@27722.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@27723.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@27746.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27782.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27783.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27784.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27785.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27786.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27787.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@27789.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27797.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@27799.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27801.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27802.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@27821.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@27823.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@27824.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@27829.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@27831.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@27832.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@27846.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27879.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27880.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@27881.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27882.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@27884.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@27892.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@27905.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@27906.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27908.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27909.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@27945.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@28035.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@28036.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@28037.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@28039.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@28040.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@28046.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@28068.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@28091.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@28092.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@28093.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@28094.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28098.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28099.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@28118.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@28120.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@28121.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@28135.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@28207.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@28209.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@28210.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@28224.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28276.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28277.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@28315.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@28317.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@28318.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@28325.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@28326.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@28343.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@28345.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28348.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28349.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@28354.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@28356.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@28357.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@28362.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@28364.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@28365.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@28370.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@28372.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@28373.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@28378.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@28380.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@28381.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@28387.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@28411.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@28413.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@28414.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@28419.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@28421.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@28422.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@28445.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@28486.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@28488.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@28489.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@28504.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@28539.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@28575.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@28635.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@28640.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@28641.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@28642.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28645.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28646.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28647.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28648.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@28664.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@28665.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@28667.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@28669.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@28670.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@28675.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@28677.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@28678.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@28683.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@28685.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@28686.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@28691.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@28693.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@28694.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@28699.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@28701.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@28702.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@28709.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@28717.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@28719.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@28720.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@28721.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@28722.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@28723.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28726.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28727.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28728.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28729.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@28746.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@28747.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@28749.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@28751.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@28752.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@28757.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@28759.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@28760.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@28765.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@28767.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@28768.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@28773.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@28775.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@28776.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@28781.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@28783.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@28784.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@28789.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@28791.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@28792.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@28799.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28819.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28820.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28821.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28822.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28842.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28843.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@28844.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@28845.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@28860.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@28863.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@28865.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@28866.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@28867.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@28869.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@28870.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@28862.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@28881.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@28883.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@28884.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@28886.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@28888.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@28889.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@28890.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@28892.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@28893.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@28885.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@28899.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@28900.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@28901.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@28902.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@28904.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@28905.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@28910.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@28911.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@28912.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@28917.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@28918.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@28919.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@28920.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@28921.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@28922.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@28924.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@28925.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@28931.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@28935.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27567.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@27680.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27804.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27911.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@28010.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28101.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@28190.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28279.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28351.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@28393.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@28451.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@28510.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@28545.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@28581.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BusWrapper.scala:164:72)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@27380.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@27381.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@27509.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@27510.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27567.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@27568.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BusWrapper.scala:164:72)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@27574.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@27575.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@27581.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@27582.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@27589.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@27590.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@27596.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@27597.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@27604.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@27605.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@27613.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@27614.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@27621.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@27622.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@27680.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@27681.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BusWrapper.scala:164:72)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@27687.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@27688.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@27694.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@27695.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@27702.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@27703.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@27709.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@27710.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@27717.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@27718.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BusWrapper.scala:164:72)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@27725.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@27726.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@27734.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@27735.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@27742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@27743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27804.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@27805.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@27811.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@27812.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@27818.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@27819.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@27826.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@27827.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@27834.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@27835.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@27842.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@27843.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27911.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@27912.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@27918.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@27919.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@27925.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@27926.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@27933.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@27934.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@27941.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@27942.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@28010.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@28011.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@28017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@28018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@28024.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@28025.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@28032.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@28033.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@28042.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@28043.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28101.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@28102.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@28108.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@28109.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@28115.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@28116.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@28123.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@28124.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@28131.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@28132.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@28190.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@28191.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@28197.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@28198.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@28204.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@28205.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@28212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@28213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@28220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@28221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BusWrapper.scala:164:72)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28279.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@28280.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@28286.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@28287.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BusWrapper.scala:164:72)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@28293.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@28294.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BusWrapper.scala:164:72)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@28301.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@28302.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@28309.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@28310.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BusWrapper.scala:164:72)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@28320.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@28321.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28351.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@28352.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@28359.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@28360.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@28367.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@28368.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@28375.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@28376.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@28383.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@28384.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@28393.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@28394.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@28400.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@28401.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@28408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@28409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@28416.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@28417.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@28424.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@28425.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@28432.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@28433.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@28441.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@28442.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@28451.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@28452.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@28458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@28459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BusWrapper.scala:164:72)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@28466.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@28467.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@28474.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@28475.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@28482.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@28483.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@28491.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@28492.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@28500.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@28501.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@28510.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@28511.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@28518.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@28519.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@28526.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@28527.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@28535.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@28536.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@28545.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@28546.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@28553.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@28554.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@28562.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@28563.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@28571.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@28572.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@28581.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@28582.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BusWrapper.scala:164:72)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@28589.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@28590.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BusWrapper.scala:164:72)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@28597.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@28598.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BusWrapper.scala:164:72)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@28606.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@28607.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BusWrapper.scala:164:72)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@28616.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@28617.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BusWrapper.scala:164:72)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@28624.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@28625.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BusWrapper.scala:164:72)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@28632.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@28633.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@28672.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@28673.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@28680.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@28681.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@28688.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@28689.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@28696.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@28697.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@28704.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@28705.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@28754.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@28755.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@28762.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@28763.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@28770.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@28771.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@28778.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@28779.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@28786.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@28787.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BusWrapper.scala:164:72)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@28794.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@28795.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BusWrapper.scala:164:72)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@28872.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@28873.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BusWrapper.scala:164:72)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@28895.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@28896.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 5 (connected at BusWrapper.scala:164:72)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@28907.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@28908.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BusWrapper.scala:164:72)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@28927.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@28928.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLFIFOFixer_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@28940.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28941.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28942.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@28943.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
wire [32:0] _T_244; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@28992.4]
wire [32:0] _T_250; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@28998.4]
wire [32:0] _T_251; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@28999.4]
wire _T_252; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29000.4]
wire [31:0] _T_253; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29001.4]
wire [32:0] _T_254; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29002.4]
wire [32:0] _T_255; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29003.4]
wire [32:0] _T_256; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29004.4]
wire _T_257; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29005.4]
wire [1:0] _T_264; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@29011.4]
wire [1:0] _GEN_70; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@29014.4]
wire [1:0] _T_267; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@29014.4]
wire _T_271; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.LowRiscConfig.fir@29018.4]
wire _T_441; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@29100.4]
wire _T_442; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@29101.4]
reg [8:0] _T_282; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@29028.4]
reg [31:0] _RAND_0;
wire _T_286; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@29032.4]
wire _T_453; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@29114.4]
reg _T_375_0; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_1;
reg _T_375_1; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_2;
wire _T_454; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29115.4]
reg _T_375_2; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_3;
wire _T_455; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29116.4]
reg _T_375_3; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_4;
wire _T_456; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29117.4]
reg _T_375_4; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_5;
wire _T_457; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29118.4]
reg _T_375_5; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_6;
wire _T_458; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29119.4]
reg _T_375_6; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_7;
wire _T_459; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29120.4]
reg _T_375_7; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_8;
wire _T_460; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29121.4]
wire _T_461; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@29122.4]
reg [1:0] _T_452; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@29110.4]
reg [31:0] _RAND_9;
wire _T_462; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@29123.4]
wire _T_463; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@29124.4]
wire _T_464; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@29125.4]
wire _T_479; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@29142.4]
reg _T_375_8; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_10;
reg _T_375_9; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_11;
wire _T_480; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29143.4]
reg _T_375_10; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_12;
wire _T_481; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29144.4]
reg _T_375_11; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_13;
wire _T_482; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29145.4]
reg _T_375_12; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_14;
wire _T_483; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29146.4]
reg _T_375_13; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_15;
wire _T_484; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29147.4]
reg _T_375_14; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_16;
wire _T_485; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29148.4]
reg _T_375_15; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@29086.4]
reg [31:0] _RAND_17;
wire _T_486; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29149.4]
wire _T_487; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@29150.4]
reg [1:0] _T_478; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@29138.4]
reg [31:0] _RAND_18;
wire _T_488; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@29151.4]
wire _T_489; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@29152.4]
wire _T_490; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@29153.4]
wire _T_492; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.LowRiscConfig.fir@29155.4]
wire _T_496; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.LowRiscConfig.fir@29162.4]
wire _T_498; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.LowRiscConfig.fir@29164.4]
wire _T_272; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@29019.4]
wire [26:0] _T_274; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@29021.4]
wire [11:0] _T_275; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@29022.4]
wire [11:0] _T_276; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@29023.4]
wire [8:0] _T_277; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@29024.4]
wire _T_278; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@29025.4]
wire _T_279; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@29026.4]
wire [9:0] _T_283; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29029.4]
wire [9:0] _T_284; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29030.4]
wire [8:0] _T_285; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29031.4]
wire _T_294; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@29043.4]
wire [26:0] _T_296; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@29045.4]
wire [11:0] _T_297; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@29046.4]
wire [11:0] _T_298; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@29047.4]
wire [8:0] _T_299; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@29048.4]
wire _T_300; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@29049.4]
reg [8:0] _T_303; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@29051.4]
reg [31:0] _RAND_19;
wire [9:0] _T_304; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29052.4]
wire [9:0] _T_305; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29053.4]
wire [8:0] _T_306; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29054.4]
wire _T_307; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@29055.4]
wire _T_315; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.LowRiscConfig.fir@29066.4]
wire _T_316; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.LowRiscConfig.fir@29067.4]
wire _T_429; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.LowRiscConfig.fir@29088.4]
wire _T_435; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.LowRiscConfig.fir@29094.4]
wire _T_448; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@29107.4]
wire _T_474; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@29135.4]
TLMonitor_11 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@28950.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign _T_244 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@28992.4]
assign _T_250 = $signed(_T_244) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@28998.4]
assign _T_251 = $signed(_T_250); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@28999.4]
assign _T_252 = $signed(_T_251) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29000.4]
assign _T_253 = auto_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29001.4]
assign _T_254 = {1'b0,$signed(_T_253)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29002.4]
assign _T_255 = $signed(_T_254) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29003.4]
assign _T_256 = $signed(_T_255); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29004.4]
assign _T_257 = $signed(_T_256) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29005.4]
assign _T_264 = _T_252 ? 2'h2 : 2'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@29011.4]
assign _GEN_70 = {{1'd0}, _T_257}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@29014.4]
assign _T_267 = _T_264 | _GEN_70; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@29014.4]
assign _T_271 = _T_267 == 2'h0; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.LowRiscConfig.fir@29018.4]
assign _T_441 = auto_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@29100.4]
assign _T_442 = _T_441 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@29101.4]
assign _T_286 = _T_282 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@29032.4]
assign _T_453 = _T_442 & _T_286; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@29114.4]
assign _T_454 = _T_375_0 | _T_375_1; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29115.4]
assign _T_455 = _T_454 | _T_375_2; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29116.4]
assign _T_456 = _T_455 | _T_375_3; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29117.4]
assign _T_457 = _T_456 | _T_375_4; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29118.4]
assign _T_458 = _T_457 | _T_375_5; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29119.4]
assign _T_459 = _T_458 | _T_375_6; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29120.4]
assign _T_460 = _T_459 | _T_375_7; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29121.4]
assign _T_461 = _T_453 & _T_460; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@29122.4]
assign _T_462 = _T_452 != _T_267; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@29123.4]
assign _T_463 = _T_271 | _T_462; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@29124.4]
assign _T_464 = _T_461 & _T_463; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@29125.4]
assign _T_479 = _T_441 & _T_286; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@29142.4]
assign _T_480 = _T_375_8 | _T_375_9; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29143.4]
assign _T_481 = _T_480 | _T_375_10; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29144.4]
assign _T_482 = _T_481 | _T_375_11; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29145.4]
assign _T_483 = _T_482 | _T_375_12; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29146.4]
assign _T_484 = _T_483 | _T_375_13; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29147.4]
assign _T_485 = _T_484 | _T_375_14; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29148.4]
assign _T_486 = _T_485 | _T_375_15; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@29149.4]
assign _T_487 = _T_479 & _T_486; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@29150.4]
assign _T_488 = _T_478 != _T_267; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@29151.4]
assign _T_489 = _T_271 | _T_488; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@29152.4]
assign _T_490 = _T_487 & _T_489; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@29153.4]
assign _T_492 = _T_464 | _T_490; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.LowRiscConfig.fir@29155.4]
assign _T_496 = _T_492 == 1'h0; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.LowRiscConfig.fir@29162.4]
assign _T_498 = auto_out_a_ready & _T_496; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.LowRiscConfig.fir@29164.4]
assign _T_272 = _T_498 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@29019.4]
assign _T_274 = 27'hfff << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@29021.4]
assign _T_275 = _T_274[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@29022.4]
assign _T_276 = ~ _T_275; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@29023.4]
assign _T_277 = _T_276[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@29024.4]
assign _T_278 = auto_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@29025.4]
assign _T_279 = _T_278 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@29026.4]
assign _T_283 = _T_282 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29029.4]
assign _T_284 = $unsigned(_T_283); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29030.4]
assign _T_285 = _T_284[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29031.4]
assign _T_294 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@29043.4]
assign _T_296 = 27'hfff << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@29045.4]
assign _T_297 = _T_296[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@29046.4]
assign _T_298 = ~ _T_297; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@29047.4]
assign _T_299 = _T_298[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@29048.4]
assign _T_300 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@29049.4]
assign _T_304 = _T_303 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29052.4]
assign _T_305 = $unsigned(_T_304); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29053.4]
assign _T_306 = _T_305[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@29054.4]
assign _T_307 = _T_303 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@29055.4]
assign _T_315 = auto_out_d_bits_opcode != 3'h6; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.LowRiscConfig.fir@29066.4]
assign _T_316 = _T_307 & _T_315; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.LowRiscConfig.fir@29067.4]
assign _T_429 = _T_286 & _T_272; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.LowRiscConfig.fir@29088.4]
assign _T_435 = _T_316 & _T_294; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.LowRiscConfig.fir@29094.4]
assign _T_448 = _T_272 & _T_442; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@29107.4]
assign _T_474 = _T_272 & _T_441; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@29135.4]
assign auto_in_a_ready = auto_out_a_ready & _T_496; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@28990.4]
assign auto_out_a_valid = auto_in_a_valid & _T_496; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@28989.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@28952.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@28953.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready & _T_496; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@28986.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_282 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_375_0 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_375_1 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_375_2 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_375_3 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_375_4 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_375_5 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_375_6 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_375_7 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_452 = _RAND_9[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_375_8 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_375_9 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_375_10 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_375_11 = _RAND_13[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_375_12 = _RAND_14[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_375_13 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_375_14 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_375_15 = _RAND_17[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_478 = _RAND_18[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_303 = _RAND_19[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_282 <= 9'h0;
end else begin
if (_T_272) begin
if (_T_286) begin
if (_T_279) begin
_T_282 <= _T_277;
end else begin
_T_282 <= 9'h0;
end
end else begin
_T_282 <= _T_285;
end
end
end
if (reset) begin
_T_375_0 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h0 == auto_out_d_bits_source) begin
_T_375_0 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h0 == auto_in_a_bits_source) begin
_T_375_0 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h0 == auto_in_a_bits_source) begin
_T_375_0 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_1 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h1 == auto_out_d_bits_source) begin
_T_375_1 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h1 == auto_in_a_bits_source) begin
_T_375_1 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h1 == auto_in_a_bits_source) begin
_T_375_1 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_2 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h2 == auto_out_d_bits_source) begin
_T_375_2 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h2 == auto_in_a_bits_source) begin
_T_375_2 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h2 == auto_in_a_bits_source) begin
_T_375_2 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_3 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h3 == auto_out_d_bits_source) begin
_T_375_3 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h3 == auto_in_a_bits_source) begin
_T_375_3 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h3 == auto_in_a_bits_source) begin
_T_375_3 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_4 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h4 == auto_out_d_bits_source) begin
_T_375_4 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h4 == auto_in_a_bits_source) begin
_T_375_4 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h4 == auto_in_a_bits_source) begin
_T_375_4 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_5 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h5 == auto_out_d_bits_source) begin
_T_375_5 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h5 == auto_in_a_bits_source) begin
_T_375_5 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h5 == auto_in_a_bits_source) begin
_T_375_5 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_6 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h6 == auto_out_d_bits_source) begin
_T_375_6 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h6 == auto_in_a_bits_source) begin
_T_375_6 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h6 == auto_in_a_bits_source) begin
_T_375_6 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_7 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h7 == auto_out_d_bits_source) begin
_T_375_7 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h7 == auto_in_a_bits_source) begin
_T_375_7 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h7 == auto_in_a_bits_source) begin
_T_375_7 <= 1'h1;
end
end
end
end
if (_T_448) begin
_T_452 <= _T_267;
end
if (reset) begin
_T_375_8 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h8 == auto_out_d_bits_source) begin
_T_375_8 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h8 == auto_in_a_bits_source) begin
_T_375_8 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h8 == auto_in_a_bits_source) begin
_T_375_8 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_9 <= 1'h0;
end else begin
if (_T_435) begin
if (4'h9 == auto_out_d_bits_source) begin
_T_375_9 <= 1'h0;
end else begin
if (_T_429) begin
if (4'h9 == auto_in_a_bits_source) begin
_T_375_9 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'h9 == auto_in_a_bits_source) begin
_T_375_9 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_10 <= 1'h0;
end else begin
if (_T_435) begin
if (4'ha == auto_out_d_bits_source) begin
_T_375_10 <= 1'h0;
end else begin
if (_T_429) begin
if (4'ha == auto_in_a_bits_source) begin
_T_375_10 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'ha == auto_in_a_bits_source) begin
_T_375_10 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_11 <= 1'h0;
end else begin
if (_T_435) begin
if (4'hb == auto_out_d_bits_source) begin
_T_375_11 <= 1'h0;
end else begin
if (_T_429) begin
if (4'hb == auto_in_a_bits_source) begin
_T_375_11 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'hb == auto_in_a_bits_source) begin
_T_375_11 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_12 <= 1'h0;
end else begin
if (_T_435) begin
if (4'hc == auto_out_d_bits_source) begin
_T_375_12 <= 1'h0;
end else begin
if (_T_429) begin
if (4'hc == auto_in_a_bits_source) begin
_T_375_12 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'hc == auto_in_a_bits_source) begin
_T_375_12 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_13 <= 1'h0;
end else begin
if (_T_435) begin
if (4'hd == auto_out_d_bits_source) begin
_T_375_13 <= 1'h0;
end else begin
if (_T_429) begin
if (4'hd == auto_in_a_bits_source) begin
_T_375_13 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'hd == auto_in_a_bits_source) begin
_T_375_13 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_14 <= 1'h0;
end else begin
if (_T_435) begin
if (4'he == auto_out_d_bits_source) begin
_T_375_14 <= 1'h0;
end else begin
if (_T_429) begin
if (4'he == auto_in_a_bits_source) begin
_T_375_14 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'he == auto_in_a_bits_source) begin
_T_375_14 <= 1'h1;
end
end
end
end
if (reset) begin
_T_375_15 <= 1'h0;
end else begin
if (_T_435) begin
if (4'hf == auto_out_d_bits_source) begin
_T_375_15 <= 1'h0;
end else begin
if (_T_429) begin
if (4'hf == auto_in_a_bits_source) begin
_T_375_15 <= 1'h1;
end
end
end
end else begin
if (_T_429) begin
if (4'hf == auto_in_a_bits_source) begin
_T_375_15 <= 1'h1;
end
end
end
end
if (_T_474) begin
_T_478 <= _T_267;
end
if (reset) begin
_T_303 <= 9'h0;
end else begin
if (_T_294) begin
if (_T_307) begin
if (_T_300) begin
_T_303 <= _T_299;
end else begin
_T_303 <= 9'h0;
end
end else begin
_T_303 <= _T_306;
end
end
end
end
endmodule
module TLMonitor_12( // @[:freechips.rocketchip.system.LowRiscConfig.fir@29224.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29225.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29226.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@29227.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@30774.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@29244.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@29245.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@29262.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@29264.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@29265.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@29266.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@29267.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@29267.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@29268.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@29270.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@29271.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@29272.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@29273.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@29274.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@29275.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@29276.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@29277.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29279.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29280.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29282.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29283.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@29284.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@29285.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@29286.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29287.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29288.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29289.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29290.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29291.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29292.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29293.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29294.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29295.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29296.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29297.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29298.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@29299.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@29300.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@29301.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29302.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29303.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29304.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29305.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29306.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29307.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29308.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29309.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29310.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29311.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29312.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29313.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29314.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29315.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29316.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29317.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29318.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29319.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29320.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29321.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29322.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29323.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29324.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29325.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@29332.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29343.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@29371.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29374.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29375.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29376.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29377.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29378.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29379.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29380.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29381.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29382.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29383.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29384.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29385.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29386.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29387.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29388.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29389.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29390.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29391.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29392.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29393.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29396.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29397.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29398.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29399.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29400.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29401.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29402.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29403.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29411.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29414.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29415.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29416.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29417.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29418.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29419.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29423.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29424.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@29431.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@29437.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@29438.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@29445.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@29446.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@29452.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@29453.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@29458.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@29460.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@29461.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@29466.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@29467.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@29469.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@29470.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@29475.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@29477.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@29478.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@29484.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@29579.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@29581.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@29582.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@29605.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29641.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29642.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29643.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29644.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29645.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29646.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29648.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29656.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@29658.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29660.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29661.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@29680.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@29682.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@29683.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@29688.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@29690.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@29691.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@29705.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29738.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29739.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29740.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29741.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29743.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29751.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@29764.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@29765.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29767.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29768.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@29804.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@29894.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@29895.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@29896.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@29898.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@29899.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@29905.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29927.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29950.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29951.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29952.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29953.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29957.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29958.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@29977.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@29979.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@29980.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@29994.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@30066.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@30068.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@30069.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@30083.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30135.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30136.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@30174.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@30176.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@30177.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@30184.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@30185.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@30202.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@30204.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30207.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30208.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@30213.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@30215.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@30216.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@30221.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@30223.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@30224.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@30229.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@30231.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@30232.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@30237.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@30239.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@30240.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@30246.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@30270.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@30272.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@30273.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@30278.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@30280.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@30281.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@30304.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@30345.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@30347.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@30348.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@30363.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@30398.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@30434.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@30494.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@30499.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@30500.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@30501.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@30503.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30504.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30505.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30506.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30507.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@30518.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@30519.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@30520.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@30521.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@30522.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@30523.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@30524.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@30526.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@30528.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@30529.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@30534.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@30536.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@30537.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@30542.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@30544.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@30545.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@30550.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@30552.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@30553.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@30558.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@30560.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@30561.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@30568.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@30576.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@30578.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@30579.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@30580.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@30581.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@30582.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@30584.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30585.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30586.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30587.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30588.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@30599.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@30600.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@30601.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@30602.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@30603.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@30604.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@30605.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@30606.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@30608.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@30610.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@30611.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@30616.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@30618.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@30619.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@30624.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@30626.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@30627.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@30632.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@30634.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@30635.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@30640.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@30642.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@30643.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@30648.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@30650.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@30651.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@30658.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@30667.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@30677.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30678.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30679.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30680.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30681.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@30700.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30701.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30702.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30703.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30704.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@30719.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@30722.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@30724.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@30725.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@30726.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@30728.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@30729.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@30721.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@30740.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@30742.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@30743.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@30745.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@30747.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@30748.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@30749.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@30751.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@30752.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@30744.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@30758.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@30759.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@30760.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@30761.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@30763.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@30764.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@30769.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@30770.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@30771.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@30773.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@30776.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@30777.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@30778.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@30779.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@30780.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@30781.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@30783.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@30784.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@30790.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@30794.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29426.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@29539.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29663.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29770.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@29869.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29960.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@30049.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30138.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30210.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@30252.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@30310.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@30369.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@30404.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@30440.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@30774.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@29244.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@29245.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@29262.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@29264.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@29265.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@29266.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@29267.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@29267.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@29268.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@29270.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@29271.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@29272.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@29273.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@29274.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@29275.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@29276.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@29277.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29279.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29280.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29282.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29283.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@29284.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@29285.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@29286.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29287.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29288.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29289.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29290.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29291.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29292.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29293.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29294.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29295.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29296.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29297.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29298.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@29299.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@29300.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@29301.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29302.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29303.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29304.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29305.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29306.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29307.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29308.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29309.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29310.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29311.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29312.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29313.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29314.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29315.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29316.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29317.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29318.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29319.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29320.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29321.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29322.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@29323.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@29324.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@29325.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@29332.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29343.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@29371.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29374.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29375.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29376.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29377.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29378.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29379.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29380.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29381.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29382.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29383.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29384.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29385.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29386.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29387.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29388.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29389.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29390.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29391.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29392.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29393.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29396.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29397.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29398.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29399.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29400.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29401.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29402.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29403.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29411.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@29414.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@29415.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29416.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@29417.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@29418.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29419.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29423.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29424.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@29431.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@29437.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@29438.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@29445.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@29446.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@29452.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@29453.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@29458.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@29460.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@29461.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@29466.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@29467.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@29469.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@29470.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@29475.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@29477.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@29478.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@29484.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@29579.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@29581.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@29582.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@29605.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29641.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29642.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29643.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29644.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29645.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29646.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29648.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29656.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@29658.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29660.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29661.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@29680.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@29682.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@29683.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@29688.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@29690.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@29691.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@29705.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29738.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29739.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29740.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29741.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29743.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29751.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@29764.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@29765.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29767.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29768.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@29804.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@29894.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@29895.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@29896.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@29898.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@29899.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@29905.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@29927.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29950.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29951.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@29952.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@29953.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29957.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29958.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@29977.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@29979.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@29980.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@29994.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@30066.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@30068.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@30069.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@30083.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30135.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30136.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@30174.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@30176.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@30177.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@30184.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@30185.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@30202.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@30204.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30207.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30208.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@30213.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@30215.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@30216.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@30221.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@30223.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@30224.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@30229.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@30231.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@30232.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@30237.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@30239.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@30240.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@30246.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@30270.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@30272.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@30273.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@30278.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@30280.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@30281.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@30304.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@30345.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@30347.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@30348.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@30363.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@30398.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@30434.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@30494.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@30499.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@30500.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@30501.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30504.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30505.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30506.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30507.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@30523.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@30524.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@30526.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@30528.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@30529.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@30534.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@30536.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@30537.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@30542.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@30544.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@30545.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@30550.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@30552.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@30553.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@30558.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@30560.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@30561.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@30568.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@30576.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@30578.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@30579.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@30580.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@30581.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@30582.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30585.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30586.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30587.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30588.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@30605.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@30606.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@30608.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@30610.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@30611.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@30616.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@30618.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@30619.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@30624.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@30626.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@30627.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@30632.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@30634.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@30635.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@30640.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@30642.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@30643.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@30648.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@30650.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@30651.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@30658.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30678.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30679.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30680.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30681.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30701.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30702.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@30703.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@30704.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@30719.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@30722.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@30724.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@30725.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@30726.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@30728.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@30729.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@30721.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@30740.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@30742.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@30743.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@30745.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@30747.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@30748.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@30749.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@30751.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@30752.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@30744.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@30758.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@30759.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@30760.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@30761.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@30763.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@30764.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@30769.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@30770.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@30771.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@30776.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@30777.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@30778.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@30779.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@30780.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@30781.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@30783.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@30784.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@30790.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@30794.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29426.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@29539.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29663.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29770.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@29869.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29960.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@30049.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30138.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30210.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@30252.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@30310.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@30369.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@30404.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@30440.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Ports.scala:141:9)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@29239.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@29240.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@29368.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@29369.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29426.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@29427.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Ports.scala:141:9)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@29433.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@29434.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@29440.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@29441.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Ports.scala:141:9)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@29448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@29449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@29455.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@29456.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Ports.scala:141:9)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@29463.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@29464.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@29472.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@29473.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@29480.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@29481.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@29539.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@29540.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Ports.scala:141:9)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@29546.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@29547.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@29553.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@29554.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Ports.scala:141:9)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@29561.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@29562.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@29568.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@29569.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Ports.scala:141:9)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@29576.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@29577.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Ports.scala:141:9)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@29584.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@29585.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@29593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@29594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@29601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@29602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29663.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@29664.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@29670.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@29671.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@29677.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@29678.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@29685.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@29686.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@29693.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@29694.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@29701.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@29702.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29770.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@29771.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@29777.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@29778.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@29784.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@29785.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@29792.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@29793.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@29800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@29801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@29869.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@29870.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@29876.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@29877.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@29883.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@29884.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@29891.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@29892.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@29901.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@29902.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29960.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@29961.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@29967.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@29968.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@29974.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@29975.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Ports.scala:141:9)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@29982.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@29983.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@29990.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@29991.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@30049.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@30050.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@30056.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@30057.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@30063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@30064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Ports.scala:141:9)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@30071.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@30072.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@30079.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@30080.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Ports.scala:141:9)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30138.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@30139.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@30145.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@30146.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Ports.scala:141:9)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@30152.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@30153.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Ports.scala:141:9)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@30160.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@30161.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@30168.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@30169.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Ports.scala:141:9)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@30179.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@30180.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30210.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@30211.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Ports.scala:141:9)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@30218.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@30219.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@30226.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@30227.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@30234.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@30235.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Ports.scala:141:9)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@30242.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@30243.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@30252.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@30253.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Ports.scala:141:9)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@30259.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@30260.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Ports.scala:141:9)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@30267.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@30268.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Ports.scala:141:9)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@30275.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@30276.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Ports.scala:141:9)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@30283.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@30284.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@30291.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@30292.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Ports.scala:141:9)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@30300.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@30301.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@30310.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@30311.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Ports.scala:141:9)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@30317.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@30318.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Ports.scala:141:9)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@30325.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@30326.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Ports.scala:141:9)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@30333.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@30334.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Ports.scala:141:9)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@30341.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@30342.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@30350.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@30351.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Ports.scala:141:9)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@30359.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@30360.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@30369.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@30370.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@30377.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@30378.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@30385.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@30386.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Ports.scala:141:9)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@30394.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@30395.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@30404.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@30405.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@30412.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@30413.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@30421.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@30422.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Ports.scala:141:9)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@30430.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@30431.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Ports.scala:141:9)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@30440.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@30441.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Ports.scala:141:9)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@30448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@30449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Ports.scala:141:9)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@30456.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@30457.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Ports.scala:141:9)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@30465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@30466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Ports.scala:141:9)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@30475.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@30476.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Ports.scala:141:9)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@30483.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@30484.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Ports.scala:141:9)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@30491.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@30492.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@30531.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@30532.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@30539.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@30540.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@30547.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@30548.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@30555.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@30556.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@30563.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@30564.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@30613.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@30614.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@30621.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@30622.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@30629.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@30630.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@30637.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@30638.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@30645.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@30646.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Ports.scala:141:9)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@30653.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@30654.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Ports.scala:141:9)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@30731.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@30732.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Ports.scala:141:9)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@30754.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@30755.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 5 (connected at Ports.scala:141:9)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@30766.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@30767.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Ports.scala:141:9)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@30786.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@30787.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLWidthWidget_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@30799.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30800.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30801.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@30802.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
TLMonitor_12 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@30809.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30849.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30848.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@30811.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@30812.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@30845.4]
endmodule
module Queue_33( // @[:freechips.rocketchip.system.LowRiscConfig.fir@30859.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30860.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30861.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
input io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
input io_enq_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
output io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
output [1:0] io_deq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
output io_deq_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@30862.4]
);
reg _T_35_id [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg [31:0] _RAND_0;
wire _T_35_id__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_id__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_id__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_id__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_id__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg [63:0] _T_35_data [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg [63:0] _RAND_1;
wire [63:0] _T_35_data__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_data__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire [63:0] _T_35_data__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_data__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_data__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_data__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg [1:0] _T_35_resp [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg [31:0] _RAND_2;
wire [1:0] _T_35_resp__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_resp__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire [1:0] _T_35_resp__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_resp__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_resp__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_resp__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg _T_35_last [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg [31:0] _RAND_3;
wire _T_35_last__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_last__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_last__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_last__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_last__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
wire _T_35_last__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@30865.4]
reg [31:0] _RAND_4;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@30867.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30870.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30873.4]
wire _GEN_10; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@30907.6]
wire _GEN_16; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30901.4]
wire _GEN_15; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30901.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@30885.4]
wire _T_50; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@30889.4]
assign _T_35_id__T_52_addr = 1'h0;
assign _T_35_id__T_52_data = _T_35_id[_T_35_id__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
assign _T_35_id__T_48_data = io_enq_bits_id;
assign _T_35_id__T_48_addr = 1'h0;
assign _T_35_id__T_48_mask = 1'h1;
assign _T_35_id__T_48_en = _T_39 ? _GEN_10 : _T_42;
assign _T_35_data__T_52_addr = 1'h0;
assign _T_35_data__T_52_data = _T_35_data[_T_35_data__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
assign _T_35_data__T_48_data = io_enq_bits_data;
assign _T_35_data__T_48_addr = 1'h0;
assign _T_35_data__T_48_mask = 1'h1;
assign _T_35_data__T_48_en = _T_39 ? _GEN_10 : _T_42;
assign _T_35_resp__T_52_addr = 1'h0;
assign _T_35_resp__T_52_data = _T_35_resp[_T_35_resp__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
assign _T_35_resp__T_48_data = io_enq_bits_resp;
assign _T_35_resp__T_48_addr = 1'h0;
assign _T_35_resp__T_48_mask = 1'h1;
assign _T_35_resp__T_48_en = _T_39 ? _GEN_10 : _T_42;
assign _T_35_last__T_52_addr = 1'h0;
assign _T_35_last__T_52_data = _T_35_last[_T_35_last__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
assign _T_35_last__T_48_data = io_enq_bits_last;
assign _T_35_last__T_48_addr = 1'h0;
assign _T_35_last__T_48_mask = 1'h1;
assign _T_35_last__T_48_en = _T_39 ? _GEN_10 : _T_42;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@30867.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30870.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30873.4]
assign _GEN_10 = io_deq_ready ? 1'h0 : _T_42; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@30907.6]
assign _GEN_16 = _T_39 ? _GEN_10 : _T_42; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30901.4]
assign _GEN_15 = _T_39 ? 1'h0 : _T_45; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30901.4]
assign _T_49 = _GEN_16 != _GEN_15; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@30885.4]
assign _T_50 = _T_39 == 1'h0; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@30889.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@30892.4]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_50; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@30890.4 Decoupled.scala 241:40:freechips.rocketchip.system.LowRiscConfig.fir@30899.6]
assign io_deq_bits_id = _T_39 ? io_enq_bits_id : _T_35_id__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@30897.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@30905.6]
assign io_deq_bits_data = _T_39 ? io_enq_bits_data : _T_35_data__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@30896.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@30904.6]
assign io_deq_bits_resp = _T_39 ? io_enq_bits_resp : _T_35_resp__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@30895.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@30903.6]
assign io_deq_bits_last = _T_39 ? io_enq_bits_last : _T_35_last__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@30894.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@30902.6]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_data[initvar] = _RAND_1[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_resp[initvar] = _RAND_2[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_last[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_37 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_48_en & _T_35_id__T_48_mask) begin
_T_35_id[_T_35_id__T_48_addr] <= _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
end
if(_T_35_data__T_48_en & _T_35_data__T_48_mask) begin
_T_35_data[_T_35_data__T_48_addr] <= _T_35_data__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
end
if(_T_35_resp__T_48_en & _T_35_resp__T_48_mask) begin
_T_35_resp[_T_35_resp__T_48_addr] <= _T_35_resp__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
end
if(_T_35_last__T_48_en & _T_35_last__T_48_mask) begin
_T_35_last[_T_35_last__T_48_addr] <= _T_35_last__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30864.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
if (_T_39) begin
if (io_deq_ready) begin
_T_37 <= 1'h0;
end else begin
_T_37 <= _T_42;
end
end else begin
_T_37 <= _T_42;
end
end
end
end
endmodule
module Queue_34( // @[:freechips.rocketchip.system.LowRiscConfig.fir@30918.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30919.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30920.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
input io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
input [1:0] io_enq_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
output io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
output [1:0] io_deq_bits_resp // @[:freechips.rocketchip.system.LowRiscConfig.fir@30921.4]
);
reg _T_35_id [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
reg [31:0] _RAND_0;
wire _T_35_id__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_id__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_id__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_id__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_id__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
reg [1:0] _T_35_resp [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
reg [31:0] _RAND_1;
wire [1:0] _T_35_resp__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_resp__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire [1:0] _T_35_resp__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_resp__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_resp__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
wire _T_35_resp__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@30924.4]
reg [31:0] _RAND_2;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@30926.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30929.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30932.4]
wire _GEN_8; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@30960.6]
wire _GEN_12; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30956.4]
wire _GEN_11; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30956.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@30942.4]
wire _T_50; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@30946.4]
assign _T_35_id__T_52_addr = 1'h0;
assign _T_35_id__T_52_data = _T_35_id[_T_35_id__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
assign _T_35_id__T_48_data = io_enq_bits_id;
assign _T_35_id__T_48_addr = 1'h0;
assign _T_35_id__T_48_mask = 1'h1;
assign _T_35_id__T_48_en = _T_39 ? _GEN_8 : _T_42;
assign _T_35_resp__T_52_addr = 1'h0;
assign _T_35_resp__T_52_data = _T_35_resp[_T_35_resp__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
assign _T_35_resp__T_48_data = io_enq_bits_resp;
assign _T_35_resp__T_48_addr = 1'h0;
assign _T_35_resp__T_48_mask = 1'h1;
assign _T_35_resp__T_48_en = _T_39 ? _GEN_8 : _T_42;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@30926.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30929.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@30932.4]
assign _GEN_8 = io_deq_ready ? 1'h0 : _T_42; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@30960.6]
assign _GEN_12 = _T_39 ? _GEN_8 : _T_42; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30956.4]
assign _GEN_11 = _T_39 ? 1'h0 : _T_45; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@30956.4]
assign _T_49 = _GEN_12 != _GEN_11; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@30942.4]
assign _T_50 = _T_39 == 1'h0; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@30946.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@30949.4]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_50; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@30947.4 Decoupled.scala 241:40:freechips.rocketchip.system.LowRiscConfig.fir@30954.6]
assign io_deq_bits_id = _T_39 ? io_enq_bits_id : _T_35_id__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@30952.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@30958.6]
assign io_deq_bits_resp = _T_39 ? io_enq_bits_resp : _T_35_resp__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@30951.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@30957.6]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_resp[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_37 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_48_en & _T_35_id__T_48_mask) begin
_T_35_id[_T_35_id__T_48_addr] <= _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
end
if(_T_35_resp__T_48_en & _T_35_resp__T_48_mask) begin
_T_35_resp[_T_35_resp__T_48_addr] <= _T_35_resp__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@30923.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
if (_T_39) begin
if (io_deq_ready) begin
_T_37 <= 1'h0;
end else begin
_T_37 <= _T_42;
end
end else begin
_T_37 <= _T_42;
end
end
end
end
endmodule
module AXI4ToTL( // @[:freechips.rocketchip.system.LowRiscConfig.fir@30971.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30972.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30973.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@30974.4]
);
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire [1:0] Queue_io_enq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire [1:0] Queue_io_deq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire [1:0] Queue_1_io_enq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire Queue_1_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire [1:0] Queue_1_io_deq_bits_resp; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
wire [15:0] _T_224; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@30987.4]
wire [22:0] _GEN_16; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@30988.4]
wire [22:0] _T_225; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@30988.4]
wire [14:0] _T_226; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@30989.4]
wire [15:0] _GEN_17; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@30990.4]
wire [15:0] _T_227; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@30990.4]
wire [15:0] _T_228; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@30991.4]
wire [15:0] _T_229; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@30992.4]
wire [15:0] _T_230; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@30993.4]
wire [15:0] _T_231; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@30994.4]
wire [7:0] _T_232; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@30995.4]
wire [7:0] _T_233; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@30996.4]
wire _T_234; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@30997.4]
wire [7:0] _T_235; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@30998.4]
wire [3:0] _T_236; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@30999.4]
wire [3:0] _T_237; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31000.4]
wire _T_238; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31001.4]
wire [3:0] _T_239; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31002.4]
wire [1:0] _T_240; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31003.4]
wire [1:0] _T_241; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31004.4]
wire _T_242; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31005.4]
wire [1:0] _T_243; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31006.4]
wire _T_244; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@31007.4]
wire [3:0] _T_247; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31010.4]
wire _T_249; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31012.4]
wire [31:0] _T_252; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31015.4]
wire [32:0] _T_253; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31016.4]
wire [32:0] _T_254; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31017.4]
wire [32:0] _T_255; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31018.4]
wire _T_256; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31019.4]
wire [31:0] _T_257; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31020.4]
wire [32:0] _T_258; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31021.4]
wire [32:0] _T_259; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31022.4]
wire [32:0] _T_260; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31023.4]
wire _T_261; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31024.4]
wire [31:0] _T_262; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31025.4]
wire [32:0] _T_263; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31026.4]
wire [32:0] _T_264; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31027.4]
wire [32:0] _T_265; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31028.4]
wire _T_266; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31029.4]
wire [32:0] _T_268; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31031.4]
wire [32:0] _T_269; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31032.4]
wire [32:0] _T_270; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31033.4]
wire _T_271; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31034.4]
wire [31:0] _T_272; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31035.4]
wire [32:0] _T_273; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31036.4]
wire [32:0] _T_274; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31037.4]
wire [32:0] _T_275; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31038.4]
wire _T_276; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31039.4]
wire [31:0] _T_277; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31040.4]
wire [32:0] _T_278; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31041.4]
wire [32:0] _T_279; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31042.4]
wire [32:0] _T_280; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31043.4]
wire _T_281; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31044.4]
wire _T_282; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31045.4]
wire _T_283; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31046.4]
wire _T_284; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31047.4]
wire _T_285; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31048.4]
wire _T_286; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31049.4]
wire _T_287; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31050.4]
wire _T_289; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31052.4]
wire [31:0] _T_292; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31055.4]
wire [32:0] _T_293; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31056.4]
wire [32:0] _T_294; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31057.4]
wire [32:0] _T_295; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31058.4]
wire _T_296; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31059.4]
wire _T_297; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31060.4]
wire _T_299; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@31062.4]
wire [2:0] _T_300; // @[ToTL.scala 74:76:freechips.rocketchip.system.LowRiscConfig.fir@31063.4]
wire [13:0] _GEN_18; // @[ToTL.scala 74:59:freechips.rocketchip.system.LowRiscConfig.fir@31064.4]
wire [13:0] _T_301; // @[ToTL.scala 74:59:freechips.rocketchip.system.LowRiscConfig.fir@31064.4]
wire [31:0] _T_302; // @[ToTL.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@31065.4]
reg [2:0] _T_319_0; // @[ToTL.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@31070.4]
reg [31:0] _RAND_0;
reg [2:0] _T_319_1; // @[ToTL.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@31070.4]
reg [31:0] _RAND_1;
wire [2:0] _GEN_1; // @[ToTL.scala 76:59:freechips.rocketchip.system.LowRiscConfig.fir@31071.4]
wire [1:0] _T_333; // @[ToTL.scala 76:59:freechips.rocketchip.system.LowRiscConfig.fir@31071.4]
wire _T_336; // @[ToTL.scala 78:15:freechips.rocketchip.system.LowRiscConfig.fir@31074.4]
wire [29:0] _T_338; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@31076.4]
wire [14:0] _T_339; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@31077.4]
wire [14:0] _T_340; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@31078.4]
wire _T_341; // @[ToTL.scala 78:39:freechips.rocketchip.system.LowRiscConfig.fir@31079.4]
wire _T_342; // @[ToTL.scala 78:28:freechips.rocketchip.system.LowRiscConfig.fir@31080.4]
wire _T_344; // @[ToTL.scala 78:14:freechips.rocketchip.system.LowRiscConfig.fir@31082.4]
wire _T_345; // @[ToTL.scala 78:14:freechips.rocketchip.system.LowRiscConfig.fir@31083.4]
wire [1:0] _T_401; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@31150.4]
wire [3:0] _T_402; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31151.4]
wire [2:0] _T_403; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@31152.4]
wire [2:0] _T_404; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@31153.4]
wire _T_405; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@31154.4]
wire _T_406; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@31155.4]
wire _T_407; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@31156.4]
wire _T_408; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@31157.4]
wire _T_410; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31159.4]
wire _T_411; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31160.4]
wire _T_413; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31162.4]
wire _T_414; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31163.4]
wire _T_415; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@31164.4]
wire _T_416; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@31165.4]
wire _T_417; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@31166.4]
wire _T_418; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31167.4]
wire _T_419; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31168.4]
wire _T_420; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31169.4]
wire _T_421; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31170.4]
wire _T_422; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31171.4]
wire _T_423; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31172.4]
wire _T_424; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31173.4]
wire _T_425; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31174.4]
wire _T_426; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31175.4]
wire _T_427; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31176.4]
wire _T_428; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31177.4]
wire _T_429; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31178.4]
wire _T_430; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@31179.4]
wire _T_431; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@31180.4]
wire _T_432; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@31181.4]
wire _T_433; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31182.4]
wire _T_434; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31183.4]
wire _T_435; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31184.4]
wire _T_436; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31185.4]
wire _T_437; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31186.4]
wire _T_438; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31187.4]
wire _T_439; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31188.4]
wire _T_440; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31189.4]
wire _T_441; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31190.4]
wire _T_442; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31191.4]
wire _T_443; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31192.4]
wire _T_444; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31193.4]
wire _T_445; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31194.4]
wire _T_446; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31195.4]
wire _T_447; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31196.4]
wire _T_448; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31197.4]
wire _T_449; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31198.4]
wire _T_450; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31199.4]
wire _T_451; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31200.4]
wire _T_452; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31201.4]
wire _T_453; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31202.4]
wire _T_454; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31203.4]
wire _T_455; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31204.4]
wire _T_456; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31205.4]
wire [1:0] _T_465; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31218.4]
wire _T_467; // @[ToTL.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@31220.4]
wire _T_468; // @[ToTL.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@31221.4]
reg [7:0] _T_696; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@31454.4]
reg [31:0] _RAND_2;
wire _T_697; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@31455.4]
wire _T_620; // @[ToTL.scala 100:34:freechips.rocketchip.system.LowRiscConfig.fir@31363.4]
wire [1:0] _T_699; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31457.4]
reg [1:0] _T_707; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@31468.4]
reg [31:0] _RAND_3;
wire [1:0] _T_708; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@31469.4]
wire [1:0] _T_709; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@31470.4]
wire [3:0] _T_710; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31471.4]
wire [2:0] _T_711; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@31472.4]
wire [3:0] _GEN_19; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@31473.4]
wire [3:0] _T_712; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@31473.4]
wire [2:0] _T_714; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@31475.4]
wire [3:0] _GEN_20; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@31476.4]
wire [3:0] _T_715; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@31476.4]
wire [3:0] _GEN_21; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@31477.4]
wire [3:0] _T_716; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@31477.4]
wire [1:0] _T_717; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@31478.4]
wire [1:0] _T_718; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@31479.4]
wire [1:0] _T_719; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@31480.4]
wire [1:0] _T_720; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@31481.4]
wire _T_729; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@31493.4]
reg _T_792_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@31545.4]
reg [31:0] _RAND_4;
wire _T_811_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@31548.4]
wire _T_819; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@31549.4]
wire _T_469; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31222.4]
wire _T_470; // @[ToTL.scala 85:28:freechips.rocketchip.system.LowRiscConfig.fir@31223.4]
wire [2:0] _T_472; // @[ToTL.scala 85:43:freechips.rocketchip.system.LowRiscConfig.fir@31226.6]
wire _T_474; // @[ToTL.scala 85:28:freechips.rocketchip.system.LowRiscConfig.fir@31230.4]
wire [2:0] _T_476; // @[ToTL.scala 85:43:freechips.rocketchip.system.LowRiscConfig.fir@31233.6]
wire [15:0] _T_480; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31238.4]
wire [22:0] _GEN_22; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@31239.4]
wire [22:0] _T_481; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@31239.4]
wire [14:0] _T_482; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@31240.4]
wire [15:0] _GEN_23; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@31241.4]
wire [15:0] _T_483; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@31241.4]
wire [15:0] _T_484; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@31242.4]
wire [15:0] _T_485; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31243.4]
wire [15:0] _T_486; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@31244.4]
wire [15:0] _T_487; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@31245.4]
wire [7:0] _T_488; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31246.4]
wire [7:0] _T_489; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31247.4]
wire _T_490; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31248.4]
wire [7:0] _T_491; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31249.4]
wire [3:0] _T_492; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31250.4]
wire [3:0] _T_493; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31251.4]
wire _T_494; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31252.4]
wire [3:0] _T_495; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31253.4]
wire [1:0] _T_496; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31254.4]
wire [1:0] _T_497; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31255.4]
wire _T_498; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31256.4]
wire [1:0] _T_499; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31257.4]
wire _T_500; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@31258.4]
wire [3:0] _T_503; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31261.4]
wire _T_512; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31270.4]
wire [31:0] _T_515; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31273.4]
wire [32:0] _T_516; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31274.4]
wire [32:0] _T_517; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31275.4]
wire [32:0] _T_518; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31276.4]
wire _T_519; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31277.4]
wire [31:0] _T_520; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31278.4]
wire [32:0] _T_521; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31279.4]
wire [32:0] _T_522; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31280.4]
wire [32:0] _T_523; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31281.4]
wire _T_524; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31282.4]
wire [32:0] _T_526; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31284.4]
wire [32:0] _T_527; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31285.4]
wire [32:0] _T_528; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31286.4]
wire _T_529; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31287.4]
wire [31:0] _T_530; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31288.4]
wire [32:0] _T_531; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31289.4]
wire [32:0] _T_532; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31290.4]
wire [32:0] _T_533; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31291.4]
wire _T_534; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31292.4]
wire _T_535; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31293.4]
wire _T_536; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31294.4]
wire _T_537; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31295.4]
wire _T_538; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31296.4]
wire _T_540; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31298.4]
wire [31:0] _T_543; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31301.4]
wire [32:0] _T_544; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31302.4]
wire [32:0] _T_545; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31303.4]
wire [32:0] _T_546; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31304.4]
wire _T_547; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31305.4]
wire _T_548; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31306.4]
wire _T_550; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31308.4]
wire [31:0] _T_553; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31311.4]
wire [32:0] _T_554; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31312.4]
wire [32:0] _T_555; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31313.4]
wire [32:0] _T_556; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31314.4]
wire _T_557; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31315.4]
wire _T_558; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31316.4]
wire _T_561; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@31319.4]
wire _T_562; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@31320.4]
wire [2:0] _T_563; // @[ToTL.scala 92:76:freechips.rocketchip.system.LowRiscConfig.fir@31321.4]
wire [13:0] _GEN_24; // @[ToTL.scala 92:59:freechips.rocketchip.system.LowRiscConfig.fir@31322.4]
wire [13:0] _T_564; // @[ToTL.scala 92:59:freechips.rocketchip.system.LowRiscConfig.fir@31322.4]
wire [31:0] _T_565; // @[ToTL.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@31323.4]
reg [2:0] _T_582_0; // @[ToTL.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@31328.4]
reg [31:0] _RAND_5;
reg [2:0] _T_582_1; // @[ToTL.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@31328.4]
reg [31:0] _RAND_6;
wire [2:0] _GEN_5; // @[ToTL.scala 94:59:freechips.rocketchip.system.LowRiscConfig.fir@31329.4]
wire [1:0] _T_596; // @[ToTL.scala 94:59:freechips.rocketchip.system.LowRiscConfig.fir@31329.4]
wire _T_599; // @[ToTL.scala 96:15:freechips.rocketchip.system.LowRiscConfig.fir@31332.4]
wire [29:0] _T_601; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@31334.4]
wire [14:0] _T_602; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@31335.4]
wire [14:0] _T_603; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@31336.4]
wire _T_604; // @[ToTL.scala 96:39:freechips.rocketchip.system.LowRiscConfig.fir@31337.4]
wire _T_605; // @[ToTL.scala 96:28:freechips.rocketchip.system.LowRiscConfig.fir@31338.4]
wire _T_607; // @[ToTL.scala 96:14:freechips.rocketchip.system.LowRiscConfig.fir@31340.4]
wire _T_608; // @[ToTL.scala 96:14:freechips.rocketchip.system.LowRiscConfig.fir@31341.4]
wire _T_610; // @[ToTL.scala 97:46:freechips.rocketchip.system.LowRiscConfig.fir@31347.4]
wire _T_611; // @[ToTL.scala 97:28:freechips.rocketchip.system.LowRiscConfig.fir@31348.4]
wire _T_612; // @[ToTL.scala 97:77:freechips.rocketchip.system.LowRiscConfig.fir@31349.4]
wire _T_613; // @[ToTL.scala 97:58:freechips.rocketchip.system.LowRiscConfig.fir@31350.4]
wire _T_615; // @[ToTL.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@31352.4]
wire _T_616; // @[ToTL.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@31353.4]
wire _T_730; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@31494.4]
reg _T_792_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@31545.4]
reg [31:0] _RAND_7;
wire _T_811_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@31548.4]
wire _T_820; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@31551.4]
wire _T_617; // @[ToTL.scala 98:34:freechips.rocketchip.system.LowRiscConfig.fir@31358.4]
wire _T_618; // @[ToTL.scala 98:48:freechips.rocketchip.system.LowRiscConfig.fir@31359.4]
wire [1:0] _T_683; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31436.4]
wire _T_685; // @[ToTL.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@31438.4]
wire _T_686; // @[ToTL.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@31439.4]
wire _T_687; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31440.4]
wire _T_688; // @[ToTL.scala 106:28:freechips.rocketchip.system.LowRiscConfig.fir@31441.4]
wire [2:0] _T_690; // @[ToTL.scala 106:43:freechips.rocketchip.system.LowRiscConfig.fir@31444.6]
wire _T_692; // @[ToTL.scala 106:28:freechips.rocketchip.system.LowRiscConfig.fir@31448.4]
wire [2:0] _T_694; // @[ToTL.scala 106:43:freechips.rocketchip.system.LowRiscConfig.fir@31451.6]
wire _T_698; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@31456.4]
wire _T_701; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@31459.4]
wire _T_703; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@31461.4]
wire _T_704; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@31462.4]
wire _T_721; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@31482.4]
wire _T_722; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@31483.4]
wire [1:0] _T_723; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@31485.6]
wire [2:0] _GEN_25; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@31486.6]
wire [2:0] _T_724; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@31486.6]
wire [1:0] _T_725; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@31487.6]
wire [1:0] _T_726; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@31488.6]
wire _T_739; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@31499.4]
wire _T_740; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@31500.4]
wire _T_750; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@31506.4]
wire _T_752; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@31508.4]
wire _T_755; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@31511.4]
wire _T_756; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@31512.4]
wire _T_759; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@31515.4]
wire _T_760; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@31516.4]
wire _T_761; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@31521.4]
wire _T_762; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@31522.4]
wire _T_764; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@31524.4]
wire _T_766; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@31526.4]
wire _T_767; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@31527.4]
wire _T_823; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31554.4]
wire _T_824; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31555.4]
wire _T_825; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31556.4]
wire _T_828; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@31559.4]
wire _T_771; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31535.4]
wire [7:0] _GEN_26; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31536.4]
wire [8:0] _T_772; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31536.4]
wire [8:0] _T_773; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31537.4]
wire [7:0] _T_774; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31538.4]
wire _T_803_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@31546.4]
wire _T_803_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@31546.4]
wire [104:0] _T_832; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31563.4]
wire [118:0] _T_836; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31567.4]
wire [118:0] _T_837; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31568.4]
wire [104:0] _T_840; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31571.4]
wire [118:0] _T_844; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31575.4]
wire [118:0] _T_845; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31576.4]
wire [118:0] _T_846; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31577.4]
wire _T_865; // @[ToTL.scala 114:42:freechips.rocketchip.system.LowRiscConfig.fir@31602.4]
wire _T_867; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@31604.4]
wire _T_862_ready; // @[ToTL.scala 112:23:freechips.rocketchip.system.LowRiscConfig.fir@31600.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@31648.4]
wire _T_859_ready; // @[ToTL.scala 111:23:freechips.rocketchip.system.LowRiscConfig.fir@31598.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@31666.4]
wire _T_889; // @[ToTL.scala 118:25:freechips.rocketchip.system.LowRiscConfig.fir@31628.4]
wire _T_868; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31605.4]
wire [26:0] _T_870; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@31607.4]
wire [11:0] _T_871; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@31608.4]
wire [11:0] _T_872; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@31609.4]
wire [8:0] _T_873; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@31610.4]
wire [8:0] _T_875; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@31612.4]
reg [8:0] _T_877; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@31613.4]
reg [31:0] _RAND_8;
wire [9:0] _T_878; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@31614.4]
wire [9:0] _T_879; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@31615.4]
wire [8:0] _T_880; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@31616.4]
wire _T_881; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@31617.4]
wire _T_882; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@31618.4]
wire _T_883; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@31619.4]
wire _T_891; // @[ToTL.scala 120:36:freechips.rocketchip.system.LowRiscConfig.fir@31632.4]
reg [2:0] _T_927_0; // @[ToTL.scala 138:28:freechips.rocketchip.system.LowRiscConfig.fir@31676.4]
reg [31:0] _RAND_9;
reg [2:0] _T_927_1; // @[ToTL.scala 138:28:freechips.rocketchip.system.LowRiscConfig.fir@31676.4]
reg [31:0] _RAND_10;
wire _T_907_bits_id; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@31667.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@31669.4]
wire [2:0] _GEN_11; // @[ToTL.scala 139:43:freechips.rocketchip.system.LowRiscConfig.fir@31677.4]
wire [2:0] _GEN_13; // @[ToTL.scala 139:43:freechips.rocketchip.system.LowRiscConfig.fir@31677.4]
wire _T_944; // @[ToTL.scala 139:43:freechips.rocketchip.system.LowRiscConfig.fir@31677.4]
wire [1:0] _T_946; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31679.4]
wire _T_948; // @[ToTL.scala 142:14:freechips.rocketchip.system.LowRiscConfig.fir@31681.4]
wire _T_949; // @[ToTL.scala 142:14:freechips.rocketchip.system.LowRiscConfig.fir@31682.4]
wire _T_907_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@31667.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@31670.4]
wire _T_958; // @[ToTL.scala 147:31:freechips.rocketchip.system.LowRiscConfig.fir@31698.4]
wire _T_950; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31683.4]
wire _T_951; // @[ToTL.scala 143:27:freechips.rocketchip.system.LowRiscConfig.fir@31684.4]
wire [2:0] _T_953; // @[ToTL.scala 143:42:freechips.rocketchip.system.LowRiscConfig.fir@31687.6]
wire _T_955; // @[ToTL.scala 143:27:freechips.rocketchip.system.LowRiscConfig.fir@31691.4]
wire [2:0] _T_957; // @[ToTL.scala 143:42:freechips.rocketchip.system.LowRiscConfig.fir@31694.6]
Queue_33 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31640.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_id(Queue_io_enq_bits_id),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_resp(Queue_io_enq_bits_resp),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_id(Queue_io_deq_bits_id),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_resp(Queue_io_deq_bits_resp),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
Queue_34 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@31660.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_id(Queue_1_io_enq_bits_id),
.io_enq_bits_resp(Queue_1_io_enq_bits_resp),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_id(Queue_1_io_deq_bits_id),
.io_deq_bits_resp(Queue_1_io_deq_bits_resp)
);
assign _T_224 = {auto_in_ar_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@30987.4]
assign _GEN_16 = {{7'd0}, _T_224}; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@30988.4]
assign _T_225 = _GEN_16 << auto_in_ar_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@30988.4]
assign _T_226 = _T_225[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@30989.4]
assign _GEN_17 = {{1'd0}, _T_226}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@30990.4]
assign _T_227 = _GEN_17 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@30990.4]
assign _T_228 = _T_227 | 16'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@30991.4]
assign _T_229 = {1'h0,_T_226}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@30992.4]
assign _T_230 = ~ _T_229; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@30993.4]
assign _T_231 = _T_228 & _T_230; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@30994.4]
assign _T_232 = _T_231[15:8]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@30995.4]
assign _T_233 = _T_231[7:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@30996.4]
assign _T_234 = _T_232 != 8'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@30997.4]
assign _T_235 = _T_232 | _T_233; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@30998.4]
assign _T_236 = _T_235[7:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@30999.4]
assign _T_237 = _T_235[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31000.4]
assign _T_238 = _T_236 != 4'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31001.4]
assign _T_239 = _T_236 | _T_237; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31002.4]
assign _T_240 = _T_239[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31003.4]
assign _T_241 = _T_239[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31004.4]
assign _T_242 = _T_240 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31005.4]
assign _T_243 = _T_240 | _T_241; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31006.4]
assign _T_244 = _T_243[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@31007.4]
assign _T_247 = {_T_234,_T_238,_T_242,_T_244}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31010.4]
assign _T_249 = _T_247 <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31012.4]
assign _T_252 = auto_in_ar_bits_addr ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31015.4]
assign _T_253 = {1'b0,$signed(_T_252)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31016.4]
assign _T_254 = $signed(_T_253) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31017.4]
assign _T_255 = $signed(_T_254); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31018.4]
assign _T_256 = $signed(_T_255) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31019.4]
assign _T_257 = auto_in_ar_bits_addr ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31020.4]
assign _T_258 = {1'b0,$signed(_T_257)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31021.4]
assign _T_259 = $signed(_T_258) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31022.4]
assign _T_260 = $signed(_T_259); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31023.4]
assign _T_261 = $signed(_T_260) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31024.4]
assign _T_262 = auto_in_ar_bits_addr ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31025.4]
assign _T_263 = {1'b0,$signed(_T_262)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31026.4]
assign _T_264 = $signed(_T_263) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31027.4]
assign _T_265 = $signed(_T_264); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31028.4]
assign _T_266 = $signed(_T_265) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31029.4]
assign _T_268 = {1'b0,$signed(auto_in_ar_bits_addr)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31031.4]
assign _T_269 = $signed(_T_268) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31032.4]
assign _T_270 = $signed(_T_269); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31033.4]
assign _T_271 = $signed(_T_270) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31034.4]
assign _T_272 = auto_in_ar_bits_addr ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31035.4]
assign _T_273 = {1'b0,$signed(_T_272)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31036.4]
assign _T_274 = $signed(_T_273) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31037.4]
assign _T_275 = $signed(_T_274); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31038.4]
assign _T_276 = $signed(_T_275) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31039.4]
assign _T_277 = auto_in_ar_bits_addr ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31040.4]
assign _T_278 = {1'b0,$signed(_T_277)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31041.4]
assign _T_279 = $signed(_T_278) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31042.4]
assign _T_280 = $signed(_T_279); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31043.4]
assign _T_281 = $signed(_T_280) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31044.4]
assign _T_282 = _T_256 | _T_261; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31045.4]
assign _T_283 = _T_282 | _T_266; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31046.4]
assign _T_284 = _T_283 | _T_271; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31047.4]
assign _T_285 = _T_284 | _T_276; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31048.4]
assign _T_286 = _T_285 | _T_281; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31049.4]
assign _T_287 = _T_249 & _T_286; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31050.4]
assign _T_289 = _T_247 <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31052.4]
assign _T_292 = auto_in_ar_bits_addr ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31055.4]
assign _T_293 = {1'b0,$signed(_T_292)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31056.4]
assign _T_294 = $signed(_T_293) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31057.4]
assign _T_295 = $signed(_T_294); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31058.4]
assign _T_296 = $signed(_T_295) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31059.4]
assign _T_297 = _T_289 & _T_296; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31060.4]
assign _T_299 = _T_287 | _T_297; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@31062.4]
assign _T_300 = auto_in_ar_bits_addr[2:0]; // @[ToTL.scala 74:76:freechips.rocketchip.system.LowRiscConfig.fir@31063.4]
assign _GEN_18 = {{11'd0}, _T_300}; // @[ToTL.scala 74:59:freechips.rocketchip.system.LowRiscConfig.fir@31064.4]
assign _T_301 = 14'h3000 | _GEN_18; // @[ToTL.scala 74:59:freechips.rocketchip.system.LowRiscConfig.fir@31064.4]
assign _T_302 = _T_299 ? auto_in_ar_bits_addr : {{18'd0}, _T_301}; // @[ToTL.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@31065.4]
assign _GEN_1 = auto_in_ar_bits_id ? _T_319_1 : _T_319_0; // @[ToTL.scala 76:59:freechips.rocketchip.system.LowRiscConfig.fir@31071.4]
assign _T_333 = _GEN_1[1:0]; // @[ToTL.scala 76:59:freechips.rocketchip.system.LowRiscConfig.fir@31071.4]
assign _T_336 = auto_in_ar_valid == 1'h0; // @[ToTL.scala 78:15:freechips.rocketchip.system.LowRiscConfig.fir@31074.4]
assign _T_338 = 30'h7fff << _T_247; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@31076.4]
assign _T_339 = _T_338[14:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@31077.4]
assign _T_340 = ~ _T_339; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@31078.4]
assign _T_341 = _T_226 == _T_340; // @[ToTL.scala 78:39:freechips.rocketchip.system.LowRiscConfig.fir@31079.4]
assign _T_342 = _T_336 | _T_341; // @[ToTL.scala 78:28:freechips.rocketchip.system.LowRiscConfig.fir@31080.4]
assign _T_344 = _T_342 | reset; // @[ToTL.scala 78:14:freechips.rocketchip.system.LowRiscConfig.fir@31082.4]
assign _T_345 = _T_344 == 1'h0; // @[ToTL.scala 78:14:freechips.rocketchip.system.LowRiscConfig.fir@31083.4]
assign _T_401 = _T_247[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@31150.4]
assign _T_402 = 4'h1 << _T_401; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31151.4]
assign _T_403 = _T_402[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@31152.4]
assign _T_404 = _T_403 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@31153.4]
assign _T_405 = _T_247 >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@31154.4]
assign _T_406 = _T_404[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@31155.4]
assign _T_407 = _T_302[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@31156.4]
assign _T_408 = _T_407 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@31157.4]
assign _T_410 = _T_406 & _T_408; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31159.4]
assign _T_411 = _T_405 | _T_410; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31160.4]
assign _T_413 = _T_406 & _T_407; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31162.4]
assign _T_414 = _T_405 | _T_413; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31163.4]
assign _T_415 = _T_404[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@31164.4]
assign _T_416 = _T_302[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@31165.4]
assign _T_417 = _T_416 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@31166.4]
assign _T_418 = _T_408 & _T_417; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31167.4]
assign _T_419 = _T_415 & _T_418; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31168.4]
assign _T_420 = _T_411 | _T_419; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31169.4]
assign _T_421 = _T_408 & _T_416; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31170.4]
assign _T_422 = _T_415 & _T_421; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31171.4]
assign _T_423 = _T_411 | _T_422; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31172.4]
assign _T_424 = _T_407 & _T_417; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31173.4]
assign _T_425 = _T_415 & _T_424; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31174.4]
assign _T_426 = _T_414 | _T_425; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31175.4]
assign _T_427 = _T_407 & _T_416; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31176.4]
assign _T_428 = _T_415 & _T_427; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31177.4]
assign _T_429 = _T_414 | _T_428; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31178.4]
assign _T_430 = _T_404[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@31179.4]
assign _T_431 = _T_302[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@31180.4]
assign _T_432 = _T_431 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@31181.4]
assign _T_433 = _T_418 & _T_432; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31182.4]
assign _T_434 = _T_430 & _T_433; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31183.4]
assign _T_435 = _T_420 | _T_434; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31184.4]
assign _T_436 = _T_418 & _T_431; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31185.4]
assign _T_437 = _T_430 & _T_436; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31186.4]
assign _T_438 = _T_420 | _T_437; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31187.4]
assign _T_439 = _T_421 & _T_432; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31188.4]
assign _T_440 = _T_430 & _T_439; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31189.4]
assign _T_441 = _T_423 | _T_440; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31190.4]
assign _T_442 = _T_421 & _T_431; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31191.4]
assign _T_443 = _T_430 & _T_442; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31192.4]
assign _T_444 = _T_423 | _T_443; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31193.4]
assign _T_445 = _T_424 & _T_432; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31194.4]
assign _T_446 = _T_430 & _T_445; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31195.4]
assign _T_447 = _T_426 | _T_446; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31196.4]
assign _T_448 = _T_424 & _T_431; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31197.4]
assign _T_449 = _T_430 & _T_448; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31198.4]
assign _T_450 = _T_426 | _T_449; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31199.4]
assign _T_451 = _T_427 & _T_432; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31200.4]
assign _T_452 = _T_430 & _T_451; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31201.4]
assign _T_453 = _T_429 | _T_452; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31202.4]
assign _T_454 = _T_427 & _T_431; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@31203.4]
assign _T_455 = _T_430 & _T_454; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@31204.4]
assign _T_456 = _T_429 | _T_455; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@31205.4]
assign _T_465 = 2'h1 << auto_in_ar_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31218.4]
assign _T_467 = _T_465[0]; // @[ToTL.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@31220.4]
assign _T_468 = _T_465[1]; // @[ToTL.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@31221.4]
assign _T_697 = _T_696 == 8'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@31455.4]
assign _T_620 = auto_in_aw_valid & auto_in_w_valid; // @[ToTL.scala 100:34:freechips.rocketchip.system.LowRiscConfig.fir@31363.4]
assign _T_699 = {_T_620,auto_in_ar_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31457.4]
assign _T_708 = ~ _T_707; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@31469.4]
assign _T_709 = _T_699 & _T_708; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@31470.4]
assign _T_710 = {_T_709,_T_620,auto_in_ar_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31471.4]
assign _T_711 = _T_710[3:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@31472.4]
assign _GEN_19 = {{1'd0}, _T_711}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@31473.4]
assign _T_712 = _T_710 | _GEN_19; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@31473.4]
assign _T_714 = _T_712[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@31475.4]
assign _GEN_20 = {{2'd0}, _T_707}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@31476.4]
assign _T_715 = _GEN_20 << 2; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@31476.4]
assign _GEN_21 = {{1'd0}, _T_714}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@31477.4]
assign _T_716 = _GEN_21 | _T_715; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@31477.4]
assign _T_717 = _T_716[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@31478.4]
assign _T_718 = _T_716[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@31479.4]
assign _T_719 = _T_717 & _T_718; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@31480.4]
assign _T_720 = ~ _T_719; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@31481.4]
assign _T_729 = _T_720[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@31493.4]
assign _T_811_0 = _T_697 ? _T_729 : _T_792_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@31548.4]
assign _T_819 = auto_out_a_ready & _T_811_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@31549.4]
assign _T_469 = _T_819 & auto_in_ar_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31222.4]
assign _T_470 = _T_469 & _T_467; // @[ToTL.scala 85:28:freechips.rocketchip.system.LowRiscConfig.fir@31223.4]
assign _T_472 = _T_319_0 + 3'h1; // @[ToTL.scala 85:43:freechips.rocketchip.system.LowRiscConfig.fir@31226.6]
assign _T_474 = _T_469 & _T_468; // @[ToTL.scala 85:28:freechips.rocketchip.system.LowRiscConfig.fir@31230.4]
assign _T_476 = _T_319_1 + 3'h1; // @[ToTL.scala 85:43:freechips.rocketchip.system.LowRiscConfig.fir@31233.6]
assign _T_480 = {auto_in_aw_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31238.4]
assign _GEN_22 = {{7'd0}, _T_480}; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@31239.4]
assign _T_481 = _GEN_22 << auto_in_aw_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@31239.4]
assign _T_482 = _T_481[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@31240.4]
assign _GEN_23 = {{1'd0}, _T_482}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@31241.4]
assign _T_483 = _GEN_23 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@31241.4]
assign _T_484 = _T_483 | 16'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@31242.4]
assign _T_485 = {1'h0,_T_482}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31243.4]
assign _T_486 = ~ _T_485; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@31244.4]
assign _T_487 = _T_484 & _T_486; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@31245.4]
assign _T_488 = _T_487[15:8]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31246.4]
assign _T_489 = _T_487[7:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31247.4]
assign _T_490 = _T_488 != 8'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31248.4]
assign _T_491 = _T_488 | _T_489; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31249.4]
assign _T_492 = _T_491[7:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31250.4]
assign _T_493 = _T_491[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31251.4]
assign _T_494 = _T_492 != 4'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31252.4]
assign _T_495 = _T_492 | _T_493; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31253.4]
assign _T_496 = _T_495[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@31254.4]
assign _T_497 = _T_495[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@31255.4]
assign _T_498 = _T_496 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@31256.4]
assign _T_499 = _T_496 | _T_497; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@31257.4]
assign _T_500 = _T_499[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@31258.4]
assign _T_503 = {_T_490,_T_494,_T_498,_T_500}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@31261.4]
assign _T_512 = _T_503 <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31270.4]
assign _T_515 = auto_in_aw_bits_addr ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31273.4]
assign _T_516 = {1'b0,$signed(_T_515)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31274.4]
assign _T_517 = $signed(_T_516) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31275.4]
assign _T_518 = $signed(_T_517); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31276.4]
assign _T_519 = $signed(_T_518) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31277.4]
assign _T_520 = auto_in_aw_bits_addr ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31278.4]
assign _T_521 = {1'b0,$signed(_T_520)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31279.4]
assign _T_522 = $signed(_T_521) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31280.4]
assign _T_523 = $signed(_T_522); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31281.4]
assign _T_524 = $signed(_T_523) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31282.4]
assign _T_526 = {1'b0,$signed(auto_in_aw_bits_addr)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31284.4]
assign _T_527 = $signed(_T_526) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31285.4]
assign _T_528 = $signed(_T_527); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31286.4]
assign _T_529 = $signed(_T_528) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31287.4]
assign _T_530 = auto_in_aw_bits_addr ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31288.4]
assign _T_531 = {1'b0,$signed(_T_530)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31289.4]
assign _T_532 = $signed(_T_531) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31290.4]
assign _T_533 = $signed(_T_532); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31291.4]
assign _T_534 = $signed(_T_533) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31292.4]
assign _T_535 = _T_519 | _T_524; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31293.4]
assign _T_536 = _T_535 | _T_529; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31294.4]
assign _T_537 = _T_536 | _T_534; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@31295.4]
assign _T_538 = _T_512 & _T_537; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31296.4]
assign _T_540 = _T_503 <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31298.4]
assign _T_543 = auto_in_aw_bits_addr ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31301.4]
assign _T_544 = {1'b0,$signed(_T_543)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31302.4]
assign _T_545 = $signed(_T_544) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31303.4]
assign _T_546 = $signed(_T_545); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31304.4]
assign _T_547 = $signed(_T_546) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31305.4]
assign _T_548 = _T_540 & _T_547; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31306.4]
assign _T_550 = _T_503 <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@31308.4]
assign _T_553 = auto_in_aw_bits_addr ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@31311.4]
assign _T_554 = {1'b0,$signed(_T_553)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@31312.4]
assign _T_555 = $signed(_T_554) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31313.4]
assign _T_556 = $signed(_T_555); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@31314.4]
assign _T_557 = $signed(_T_556) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@31315.4]
assign _T_558 = _T_550 & _T_557; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@31316.4]
assign _T_561 = _T_538 | _T_548; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@31319.4]
assign _T_562 = _T_561 | _T_558; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@31320.4]
assign _T_563 = auto_in_aw_bits_addr[2:0]; // @[ToTL.scala 92:76:freechips.rocketchip.system.LowRiscConfig.fir@31321.4]
assign _GEN_24 = {{11'd0}, _T_563}; // @[ToTL.scala 92:59:freechips.rocketchip.system.LowRiscConfig.fir@31322.4]
assign _T_564 = 14'h3000 | _GEN_24; // @[ToTL.scala 92:59:freechips.rocketchip.system.LowRiscConfig.fir@31322.4]
assign _T_565 = _T_562 ? auto_in_aw_bits_addr : {{18'd0}, _T_564}; // @[ToTL.scala 92:23:freechips.rocketchip.system.LowRiscConfig.fir@31323.4]
assign _GEN_5 = auto_in_aw_bits_id ? _T_582_1 : _T_582_0; // @[ToTL.scala 94:59:freechips.rocketchip.system.LowRiscConfig.fir@31329.4]
assign _T_596 = _GEN_5[1:0]; // @[ToTL.scala 94:59:freechips.rocketchip.system.LowRiscConfig.fir@31329.4]
assign _T_599 = auto_in_aw_valid == 1'h0; // @[ToTL.scala 96:15:freechips.rocketchip.system.LowRiscConfig.fir@31332.4]
assign _T_601 = 30'h7fff << _T_503; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@31334.4]
assign _T_602 = _T_601[14:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@31335.4]
assign _T_603 = ~ _T_602; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@31336.4]
assign _T_604 = _T_482 == _T_603; // @[ToTL.scala 96:39:freechips.rocketchip.system.LowRiscConfig.fir@31337.4]
assign _T_605 = _T_599 | _T_604; // @[ToTL.scala 96:28:freechips.rocketchip.system.LowRiscConfig.fir@31338.4]
assign _T_607 = _T_605 | reset; // @[ToTL.scala 96:14:freechips.rocketchip.system.LowRiscConfig.fir@31340.4]
assign _T_608 = _T_607 == 1'h0; // @[ToTL.scala 96:14:freechips.rocketchip.system.LowRiscConfig.fir@31341.4]
assign _T_610 = auto_in_aw_bits_len == 8'h0; // @[ToTL.scala 97:46:freechips.rocketchip.system.LowRiscConfig.fir@31347.4]
assign _T_611 = _T_599 | _T_610; // @[ToTL.scala 97:28:freechips.rocketchip.system.LowRiscConfig.fir@31348.4]
assign _T_612 = auto_in_aw_bits_size == 3'h3; // @[ToTL.scala 97:77:freechips.rocketchip.system.LowRiscConfig.fir@31349.4]
assign _T_613 = _T_611 | _T_612; // @[ToTL.scala 97:58:freechips.rocketchip.system.LowRiscConfig.fir@31350.4]
assign _T_615 = _T_613 | reset; // @[ToTL.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@31352.4]
assign _T_616 = _T_615 == 1'h0; // @[ToTL.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@31353.4]
assign _T_730 = _T_720[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@31494.4]
assign _T_811_1 = _T_697 ? _T_730 : _T_792_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@31548.4]
assign _T_820 = auto_out_a_ready & _T_811_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@31551.4]
assign _T_617 = _T_820 & auto_in_w_valid; // @[ToTL.scala 98:34:freechips.rocketchip.system.LowRiscConfig.fir@31358.4]
assign _T_618 = _T_617 & auto_in_w_bits_last; // @[ToTL.scala 98:48:freechips.rocketchip.system.LowRiscConfig.fir@31359.4]
assign _T_683 = 2'h1 << auto_in_aw_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31436.4]
assign _T_685 = _T_683[0]; // @[ToTL.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@31438.4]
assign _T_686 = _T_683[1]; // @[ToTL.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@31439.4]
assign _T_687 = _T_618 & auto_in_aw_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31440.4]
assign _T_688 = _T_687 & _T_685; // @[ToTL.scala 106:28:freechips.rocketchip.system.LowRiscConfig.fir@31441.4]
assign _T_690 = _T_582_0 + 3'h1; // @[ToTL.scala 106:43:freechips.rocketchip.system.LowRiscConfig.fir@31444.6]
assign _T_692 = _T_687 & _T_686; // @[ToTL.scala 106:28:freechips.rocketchip.system.LowRiscConfig.fir@31448.4]
assign _T_694 = _T_582_1 + 3'h1; // @[ToTL.scala 106:43:freechips.rocketchip.system.LowRiscConfig.fir@31451.6]
assign _T_698 = _T_697 & auto_out_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@31456.4]
assign _T_701 = _T_699 == _T_699; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@31459.4]
assign _T_703 = _T_701 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@31461.4]
assign _T_704 = _T_703 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@31462.4]
assign _T_721 = _T_699 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@31482.4]
assign _T_722 = _T_698 & _T_721; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@31483.4]
assign _T_723 = _T_720 & _T_699; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@31485.6]
assign _GEN_25 = {{1'd0}, _T_723}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@31486.6]
assign _T_724 = _GEN_25 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@31486.6]
assign _T_725 = _T_724[1:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@31487.6]
assign _T_726 = _T_723 | _T_725; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@31488.6]
assign _T_739 = _T_729 & auto_in_ar_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@31499.4]
assign _T_740 = _T_730 & _T_620; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@31500.4]
assign _T_750 = _T_739 | _T_740; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@31506.4]
assign _T_752 = _T_739 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@31508.4]
assign _T_755 = _T_740 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@31511.4]
assign _T_756 = _T_752 | _T_755; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@31512.4]
assign _T_759 = _T_756 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@31515.4]
assign _T_760 = _T_759 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@31516.4]
assign _T_761 = auto_in_ar_valid | _T_620; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@31521.4]
assign _T_762 = _T_761 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@31522.4]
assign _T_764 = _T_762 | _T_750; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@31524.4]
assign _T_766 = _T_764 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@31526.4]
assign _T_767 = _T_766 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@31527.4]
assign _T_823 = _T_792_0 ? auto_in_ar_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31554.4]
assign _T_824 = _T_792_1 ? _T_620 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31555.4]
assign _T_825 = _T_823 | _T_824; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31556.4]
assign _T_828 = _T_697 ? _T_761 : _T_825; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@31559.4]
assign _T_771 = auto_out_a_ready & _T_828; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31535.4]
assign _GEN_26 = {{7'd0}, _T_771}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31536.4]
assign _T_772 = _T_696 - _GEN_26; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31536.4]
assign _T_773 = $unsigned(_T_772); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31537.4]
assign _T_774 = _T_773[7:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@31538.4]
assign _T_803_0 = _T_697 ? _T_739 : _T_792_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@31546.4]
assign _T_803_1 = _T_697 ? _T_740 : _T_792_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@31546.4]
assign _T_832 = {_T_302,_T_456,_T_453,_T_450,_T_447,_T_444,_T_441,_T_438,_T_435,65'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31563.4]
assign _T_836 = {6'h20,_T_234,_T_238,_T_242,_T_244,auto_in_ar_bits_id,_T_333,1'h0,_T_832}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31567.4]
assign _T_837 = _T_803_0 ? _T_836 : 119'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31568.4]
assign _T_840 = {_T_565,auto_in_w_bits_strb,auto_in_w_bits_data,1'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31571.4]
assign _T_844 = {6'h8,_T_490,_T_494,_T_498,_T_500,auto_in_aw_bits_id,_T_596,1'h1,_T_840}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31575.4]
assign _T_845 = _T_803_1 ? _T_844 : 119'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31576.4]
assign _T_846 = _T_837 | _T_845; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@31577.4]
assign _T_865 = auto_out_d_bits_denied | auto_out_d_bits_corrupt; // @[ToTL.scala 114:42:freechips.rocketchip.system.LowRiscConfig.fir@31602.4]
assign _T_867 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@31604.4]
assign _T_862_ready = Queue_io_enq_ready; // @[ToTL.scala 112:23:freechips.rocketchip.system.LowRiscConfig.fir@31600.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@31648.4]
assign _T_859_ready = Queue_1_io_enq_ready; // @[ToTL.scala 111:23:freechips.rocketchip.system.LowRiscConfig.fir@31598.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@31666.4]
assign _T_889 = _T_867 ? _T_862_ready : _T_859_ready; // @[ToTL.scala 118:25:freechips.rocketchip.system.LowRiscConfig.fir@31628.4]
assign _T_868 = _T_889 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31605.4]
assign _T_870 = 27'hfff << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@31607.4]
assign _T_871 = _T_870[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@31608.4]
assign _T_872 = ~ _T_871; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@31609.4]
assign _T_873 = _T_872[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@31610.4]
assign _T_875 = _T_867 ? _T_873 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@31612.4]
assign _T_878 = _T_877 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@31614.4]
assign _T_879 = $unsigned(_T_878); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@31615.4]
assign _T_880 = _T_879[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@31616.4]
assign _T_881 = _T_877 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@31617.4]
assign _T_882 = _T_877 == 9'h1; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@31618.4]
assign _T_883 = _T_875 == 9'h0; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@31619.4]
assign _T_891 = _T_867 == 1'h0; // @[ToTL.scala 120:36:freechips.rocketchip.system.LowRiscConfig.fir@31632.4]
assign _T_907_bits_id = Queue_1_io_deq_bits_id; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@31667.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@31669.4]
assign _GEN_11 = _T_907_bits_id ? _T_927_1 : _T_927_0; // @[ToTL.scala 139:43:freechips.rocketchip.system.LowRiscConfig.fir@31677.4]
assign _GEN_13 = _T_907_bits_id ? _T_582_1 : _T_582_0; // @[ToTL.scala 139:43:freechips.rocketchip.system.LowRiscConfig.fir@31677.4]
assign _T_944 = _GEN_11 != _GEN_13; // @[ToTL.scala 139:43:freechips.rocketchip.system.LowRiscConfig.fir@31677.4]
assign _T_946 = 2'h1 << _T_907_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31679.4]
assign _T_948 = _T_946[0]; // @[ToTL.scala 142:14:freechips.rocketchip.system.LowRiscConfig.fir@31681.4]
assign _T_949 = _T_946[1]; // @[ToTL.scala 142:14:freechips.rocketchip.system.LowRiscConfig.fir@31682.4]
assign _T_907_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@31667.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@31670.4]
assign _T_958 = _T_907_valid & _T_944; // @[ToTL.scala 147:31:freechips.rocketchip.system.LowRiscConfig.fir@31698.4]
assign _T_950 = auto_in_b_ready & _T_958; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31683.4]
assign _T_951 = _T_950 & _T_948; // @[ToTL.scala 143:27:freechips.rocketchip.system.LowRiscConfig.fir@31684.4]
assign _T_953 = _T_927_0 + 3'h1; // @[ToTL.scala 143:42:freechips.rocketchip.system.LowRiscConfig.fir@31687.6]
assign _T_955 = _T_950 & _T_949; // @[ToTL.scala 143:27:freechips.rocketchip.system.LowRiscConfig.fir@31691.4]
assign _T_957 = _T_927_1 + 3'h1; // @[ToTL.scala 143:42:freechips.rocketchip.system.LowRiscConfig.fir@31694.6]
assign auto_in_aw_ready = _T_617 & auto_in_w_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_w_ready = _T_820 & auto_in_aw_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_b_valid = _T_907_valid & _T_944; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_b_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_b_bits_resp = Queue_1_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_ar_ready = auto_out_a_ready & _T_811_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_r_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_r_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_r_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_r_bits_resp = Queue_io_deq_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_in_r_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@30984.4]
assign auto_out_a_valid = _T_697 ? _T_761 : _T_825; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_opcode = _T_846[118:116]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_param = _T_846[115:113]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_size = _T_846[112:109]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_source = _T_846[108:105]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_address = _T_846[104:73]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_mask = _T_846[72:65]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_data = _T_846[64:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_a_bits_corrupt = _T_846[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign auto_out_d_ready = _T_867 ? _T_862_ready : _T_859_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@30983.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31641.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31642.4]
assign Queue_io_enq_valid = auto_out_d_valid & _T_867; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@31643.4]
assign Queue_io_enq_bits_id = auto_out_d_bits_source[3:3]; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@31647.4]
assign Queue_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@31646.4]
assign Queue_io_enq_bits_resp = _T_865 ? 2'h2 : 2'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@31645.4]
assign Queue_io_enq_bits_last = _T_882 | _T_883; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@31644.4]
assign Queue_io_deq_ready = auto_in_r_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@31655.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31661.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31662.4]
assign Queue_1_io_enq_valid = auto_out_d_valid & _T_891; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@31663.4]
assign Queue_1_io_enq_bits_id = auto_out_d_bits_source[3:3]; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@31665.4]
assign Queue_1_io_enq_bits_resp = _T_865 ? 2'h2 : 2'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@31664.4]
assign Queue_1_io_deq_ready = auto_in_b_ready & _T_944; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@31671.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_319_0 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_319_1 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_696 = _RAND_2[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_707 = _RAND_3[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_792_0 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_582_0 = _RAND_5[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_582_1 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_792_1 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_877 = _RAND_8[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_927_0 = _RAND_9[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_927_1 = _RAND_10[2:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_319_0 <= 3'h0;
end else begin
if (_T_470) begin
_T_319_0 <= _T_472;
end
end
if (reset) begin
_T_319_1 <= 3'h0;
end else begin
if (_T_474) begin
_T_319_1 <= _T_476;
end
end
if (reset) begin
_T_696 <= 8'h0;
end else begin
if (_T_698) begin
if (_T_740) begin
_T_696 <= auto_in_aw_bits_len;
end else begin
_T_696 <= 8'h0;
end
end else begin
_T_696 <= _T_774;
end
end
if (reset) begin
_T_707 <= 2'h3;
end else begin
if (_T_722) begin
_T_707 <= _T_726;
end
end
if (reset) begin
_T_792_0 <= 1'h0;
end else begin
if (_T_697) begin
_T_792_0 <= _T_739;
end
end
if (reset) begin
_T_582_0 <= 3'h0;
end else begin
if (_T_688) begin
_T_582_0 <= _T_690;
end
end
if (reset) begin
_T_582_1 <= 3'h0;
end else begin
if (_T_692) begin
_T_582_1 <= _T_694;
end
end
if (reset) begin
_T_792_1 <= 1'h0;
end else begin
if (_T_697) begin
_T_792_1 <= _T_740;
end
end
if (reset) begin
_T_877 <= 9'h0;
end else begin
if (_T_868) begin
if (_T_881) begin
if (_T_867) begin
_T_877 <= _T_873;
end else begin
_T_877 <= 9'h0;
end
end else begin
_T_877 <= _T_880;
end
end
end
if (reset) begin
_T_927_0 <= 3'h0;
end else begin
if (_T_951) begin
_T_927_0 <= _T_953;
end
end
if (reset) begin
_T_927_1 <= 3'h0;
end else begin
if (_T_955) begin
_T_927_1 <= _T_957;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_345) begin
$fwrite(32'h80000002,"Assertion failed\n at ToTL.scala:78 assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, beatCountBits)) // because aligned\n"); // @[ToTL.scala 78:14:freechips.rocketchip.system.LowRiscConfig.fir@31085.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_345) begin
$fatal; // @[ToTL.scala 78:14:freechips.rocketchip.system.LowRiscConfig.fir@31086.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_608) begin
$fwrite(32'h80000002,"Assertion failed\n at ToTL.scala:96 assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, beatCountBits)) // because aligned\n"); // @[ToTL.scala 96:14:freechips.rocketchip.system.LowRiscConfig.fir@31343.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_608) begin
$fatal; // @[ToTL.scala 96:14:freechips.rocketchip.system.LowRiscConfig.fir@31344.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_616) begin
$fwrite(32'h80000002,"Assertion failed\n at ToTL.scala:97 assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned\n"); // @[ToTL.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@31355.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_616) begin
$fatal; // @[ToTL.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@31356.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_704) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@31464.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_704) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@31465.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_760) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@31518.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_760) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@31519.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_767) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@31529.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_767) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@31530.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_35( // @[:freechips.rocketchip.system.LowRiscConfig.fir@31706.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31707.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31708.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31709.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31709.4]
input [7:0] io_enq_bits, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31709.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31709.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31709.4]
output [7:0] io_deq_bits // @[:freechips.rocketchip.system.LowRiscConfig.fir@31709.4]
);
reg [7:0] _T_35 [0:3]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
reg [31:0] _RAND_0;
wire [7:0] _T_35__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
wire [1:0] _T_35__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
wire [7:0] _T_35__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
wire [1:0] _T_35__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
wire _T_35__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
wire _T_35__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
reg [1:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@31715.4]
reg [31:0] _RAND_1;
reg [1:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@31716.4]
reg [31:0] _RAND_2;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@31717.4]
reg [31:0] _RAND_3;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@31718.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@31719.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@31720.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@31721.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31722.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31726.4]
wire [1:0] _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@31735.6]
wire [1:0] _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@31741.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@31744.4]
assign _T_35__T_58_addr = value_1;
assign _T_35__T_58_data = _T_35[_T_35__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
assign _T_35__T_50_data = io_enq_bits;
assign _T_35__T_50_addr = value;
assign _T_35__T_50_mask = 1'h1;
assign _T_35__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@31718.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@31719.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@31720.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@31721.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31722.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@31726.4]
assign _T_52 = value + 2'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@31735.6]
assign _T_54 = value_1 + 2'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@31741.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@31744.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@31751.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@31749.4]
assign io_deq_bits = _T_35__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@31753.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 4; initvar = initvar+1)
_T_35[initvar] = _RAND_0[7:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
value = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
value_1 = _RAND_2[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_39 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35__T_50_en & _T_35__T_50_mask) begin
_T_35[_T_35__T_50_addr] <= _T_35__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@31714.4]
end
if (reset) begin
value <= 2'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 2'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module AXI4UserYanker_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@31926.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31927.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31928.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [7:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [7:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [7:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [7:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@31929.4]
);
wire Queue_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire Queue_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire Queue_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire Queue_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire [7:0] Queue_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire Queue_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire Queue_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire [7:0] Queue_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
wire Queue_1_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire Queue_1_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire Queue_1_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire Queue_1_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire [7:0] Queue_1_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire Queue_1_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire Queue_1_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire [7:0] Queue_1_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
wire Queue_2_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire Queue_2_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire Queue_2_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire Queue_2_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire [7:0] Queue_2_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire Queue_2_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire Queue_2_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire [7:0] Queue_2_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
wire Queue_3_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire Queue_3_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire Queue_3_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire Queue_3_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire [7:0] Queue_3_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire Queue_3_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire Queue_3_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire [7:0] Queue_3_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
wire _T_224_0; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31956.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31958.4]
wire _T_224_1; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31956.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31959.4]
wire _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@31960.4]
wire _T_250; // @[UserYanker.scala 54:15:freechips.rocketchip.system.LowRiscConfig.fir@31973.4]
wire _T_235_0; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31965.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31967.4]
wire _T_235_1; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31965.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31968.4]
wire _GEN_3; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@31974.4]
wire _T_251; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@31974.4]
wire _T_253; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@31976.4]
wire _T_254; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@31977.4]
wire [7:0] _T_244_0; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31969.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31971.4]
wire [7:0] _T_244_1; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31969.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31972.4]
wire [1:0] _T_256; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31985.4]
wire _T_258; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@31987.4]
wire _T_259; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@31988.4]
wire [1:0] _T_261; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31990.4]
wire _T_263; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@31992.4]
wire _T_264; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@31993.4]
wire _T_265; // @[UserYanker.scala 61:37:freechips.rocketchip.system.LowRiscConfig.fir@31994.4]
wire _T_266; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@31995.4]
wire _T_268; // @[UserYanker.scala 62:37:freechips.rocketchip.system.LowRiscConfig.fir@31998.4]
wire _T_271; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@32003.4]
wire _T_278_0; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32010.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32012.4]
wire _T_278_1; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32010.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32013.4]
wire _GEN_7; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@32014.4]
wire _T_304; // @[UserYanker.scala 75:15:freechips.rocketchip.system.LowRiscConfig.fir@32027.4]
wire _T_289_0; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32019.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32021.4]
wire _T_289_1; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32019.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32022.4]
wire _GEN_9; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@32028.4]
wire _T_305; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@32028.4]
wire _T_307; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@32030.4]
wire _T_308; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@32031.4]
wire [7:0] _T_298_0; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32023.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32025.4]
wire [7:0] _T_298_1; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32023.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32026.4]
wire [1:0] _T_310; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32039.4]
wire _T_312; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@32041.4]
wire _T_313; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@32042.4]
wire [1:0] _T_315; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32044.4]
wire _T_317; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@32046.4]
wire _T_318; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@32047.4]
wire _T_319; // @[UserYanker.scala 82:37:freechips.rocketchip.system.LowRiscConfig.fir@32048.4]
wire _T_321; // @[UserYanker.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@32051.4]
Queue_35 Queue ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31940.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits(Queue_io_enq_bits),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits(Queue_io_deq_bits)
);
Queue_35 Queue_1 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31944.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits(Queue_1_io_enq_bits),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits(Queue_1_io_deq_bits)
);
Queue_35 Queue_2 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31948.4]
.clock(Queue_2_clock),
.reset(Queue_2_reset),
.io_enq_ready(Queue_2_io_enq_ready),
.io_enq_valid(Queue_2_io_enq_valid),
.io_enq_bits(Queue_2_io_enq_bits),
.io_deq_ready(Queue_2_io_deq_ready),
.io_deq_valid(Queue_2_io_deq_valid),
.io_deq_bits(Queue_2_io_deq_bits)
);
Queue_35 Queue_3 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@31952.4]
.clock(Queue_3_clock),
.reset(Queue_3_reset),
.io_enq_ready(Queue_3_io_enq_ready),
.io_enq_valid(Queue_3_io_enq_valid),
.io_enq_bits(Queue_3_io_enq_bits),
.io_deq_ready(Queue_3_io_deq_ready),
.io_deq_valid(Queue_3_io_deq_valid),
.io_deq_bits(Queue_3_io_deq_bits)
);
assign _T_224_0 = Queue_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31956.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31958.4]
assign _T_224_1 = Queue_1_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31956.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@31959.4]
assign _GEN_1 = auto_in_ar_bits_id ? _T_224_1 : _T_224_0; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@31960.4]
assign _T_250 = auto_out_r_valid == 1'h0; // @[UserYanker.scala 54:15:freechips.rocketchip.system.LowRiscConfig.fir@31973.4]
assign _T_235_0 = Queue_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31965.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31967.4]
assign _T_235_1 = Queue_1_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31965.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@31968.4]
assign _GEN_3 = auto_out_r_bits_id ? _T_235_1 : _T_235_0; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@31974.4]
assign _T_251 = _T_250 | _GEN_3; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@31974.4]
assign _T_253 = _T_251 | reset; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@31976.4]
assign _T_254 = _T_253 == 1'h0; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@31977.4]
assign _T_244_0 = Queue_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31969.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31971.4]
assign _T_244_1 = Queue_1_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31969.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@31972.4]
assign _T_256 = 2'h1 << auto_in_ar_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31985.4]
assign _T_258 = _T_256[0]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@31987.4]
assign _T_259 = _T_256[1]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@31988.4]
assign _T_261 = 2'h1 << auto_out_r_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@31990.4]
assign _T_263 = _T_261[0]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@31992.4]
assign _T_264 = _T_261[1]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@31993.4]
assign _T_265 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala 61:37:freechips.rocketchip.system.LowRiscConfig.fir@31994.4]
assign _T_266 = _T_265 & _T_263; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@31995.4]
assign _T_268 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala 62:37:freechips.rocketchip.system.LowRiscConfig.fir@31998.4]
assign _T_271 = _T_265 & _T_264; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@32003.4]
assign _T_278_0 = Queue_2_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32010.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32012.4]
assign _T_278_1 = Queue_3_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32010.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@32013.4]
assign _GEN_7 = auto_in_aw_bits_id ? _T_278_1 : _T_278_0; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@32014.4]
assign _T_304 = auto_out_b_valid == 1'h0; // @[UserYanker.scala 75:15:freechips.rocketchip.system.LowRiscConfig.fir@32027.4]
assign _T_289_0 = Queue_2_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32019.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32021.4]
assign _T_289_1 = Queue_3_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32019.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@32022.4]
assign _GEN_9 = auto_out_b_bits_id ? _T_289_1 : _T_289_0; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@32028.4]
assign _T_305 = _T_304 | _GEN_9; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@32028.4]
assign _T_307 = _T_305 | reset; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@32030.4]
assign _T_308 = _T_307 == 1'h0; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@32031.4]
assign _T_298_0 = Queue_2_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32023.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32025.4]
assign _T_298_1 = Queue_3_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32023.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@32026.4]
assign _T_310 = 2'h1 << auto_in_aw_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32039.4]
assign _T_312 = _T_310[0]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@32041.4]
assign _T_313 = _T_310[1]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@32042.4]
assign _T_315 = 2'h1 << auto_out_b_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32044.4]
assign _T_317 = _T_315[0]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@32046.4]
assign _T_318 = _T_315[1]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@32047.4]
assign _T_319 = auto_out_b_valid & auto_in_b_ready; // @[UserYanker.scala 82:37:freechips.rocketchip.system.LowRiscConfig.fir@32048.4]
assign _T_321 = auto_in_aw_valid & auto_out_aw_ready; // @[UserYanker.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@32051.4]
assign auto_in_aw_ready = auto_out_aw_ready & _GEN_7; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_b_bits_user = auto_out_b_bits_id ? _T_298_1 : _T_298_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_ar_ready = auto_out_ar_ready & _GEN_1; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_r_bits_user = auto_out_r_bits_id ? _T_244_1 : _T_244_0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@31939.4]
assign auto_out_aw_valid = auto_in_aw_valid & _GEN_7; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_ar_valid = auto_in_ar_valid & _GEN_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@31938.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31942.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31943.4]
assign Queue_io_enq_valid = _T_268 & _T_258; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@32000.4]
assign Queue_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@32001.4]
assign Queue_io_deq_ready = _T_266 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@31997.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31946.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31947.4]
assign Queue_1_io_enq_valid = _T_268 & _T_259; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@32008.4]
assign Queue_1_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@32009.4]
assign Queue_1_io_deq_ready = _T_271 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@32005.4]
assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31950.4]
assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31951.4]
assign Queue_2_io_enq_valid = _T_321 & _T_312; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@32053.4]
assign Queue_2_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@32054.4]
assign Queue_2_io_deq_ready = _T_319 & _T_317; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@32050.4]
assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31954.4]
assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@31955.4]
assign Queue_3_io_enq_valid = _T_321 & _T_313; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@32060.4]
assign Queue_3_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@32061.4]
assign Queue_3_io_deq_ready = _T_319 & _T_318; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@32057.4]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_254) begin
$fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:54 assert (!out.r.valid || r_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@31979.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_254) begin
$fatal; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@31980.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_308) begin
$fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:75 assert (!out.b.valid || b_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@32033.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_308) begin
$fatal; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@32034.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_39( // @[:freechips.rocketchip.system.LowRiscConfig.fir@32064.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32065.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32066.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input [31:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input [1:0] io_enq_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input [6:0] io_enq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output [31:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
output [6:0] io_deq_bits_user // @[:freechips.rocketchip.system.LowRiscConfig.fir@32067.4]
);
reg _T_35_id [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _RAND_0;
wire _T_35_id__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_id__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_id__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_id__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_id__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _T_35_addr [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _RAND_1;
wire [31:0] _T_35_addr__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_addr__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire [31:0] _T_35_addr__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_addr__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_addr__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_addr__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [7:0] _T_35_len [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _RAND_2;
wire [7:0] _T_35_len__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_len__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire [7:0] _T_35_len__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_len__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_len__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_len__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [2:0] _T_35_size [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _RAND_3;
wire [2:0] _T_35_size__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_size__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire [2:0] _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_size__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_size__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_size__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [1:0] _T_35_burst [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _RAND_4;
wire [1:0] _T_35_burst__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_burst__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire [1:0] _T_35_burst__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_burst__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_burst__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_burst__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [6:0] _T_35_user [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg [31:0] _RAND_5;
wire [6:0] _T_35_user__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_user__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire [6:0] _T_35_user__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_user__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_user__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
wire _T_35_user__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@32070.4]
reg [31:0] _RAND_6;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@32072.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32075.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32078.4]
wire _GEN_16; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@32130.6]
wire _GEN_28; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@32118.4]
wire _GEN_27; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@32118.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@32096.4]
wire _T_50; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@32100.4]
assign _T_35_id__T_52_addr = 1'h0;
assign _T_35_id__T_52_data = _T_35_id[_T_35_id__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
assign _T_35_id__T_48_data = io_enq_bits_id;
assign _T_35_id__T_48_addr = 1'h0;
assign _T_35_id__T_48_mask = 1'h1;
assign _T_35_id__T_48_en = _T_39 ? _GEN_16 : _T_42;
assign _T_35_addr__T_52_addr = 1'h0;
assign _T_35_addr__T_52_data = _T_35_addr[_T_35_addr__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
assign _T_35_addr__T_48_data = io_enq_bits_addr;
assign _T_35_addr__T_48_addr = 1'h0;
assign _T_35_addr__T_48_mask = 1'h1;
assign _T_35_addr__T_48_en = _T_39 ? _GEN_16 : _T_42;
assign _T_35_len__T_52_addr = 1'h0;
assign _T_35_len__T_52_data = _T_35_len[_T_35_len__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
assign _T_35_len__T_48_data = io_enq_bits_len;
assign _T_35_len__T_48_addr = 1'h0;
assign _T_35_len__T_48_mask = 1'h1;
assign _T_35_len__T_48_en = _T_39 ? _GEN_16 : _T_42;
assign _T_35_size__T_52_addr = 1'h0;
assign _T_35_size__T_52_data = _T_35_size[_T_35_size__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
assign _T_35_size__T_48_data = io_enq_bits_size;
assign _T_35_size__T_48_addr = 1'h0;
assign _T_35_size__T_48_mask = 1'h1;
assign _T_35_size__T_48_en = _T_39 ? _GEN_16 : _T_42;
assign _T_35_burst__T_52_addr = 1'h0;
assign _T_35_burst__T_52_data = _T_35_burst[_T_35_burst__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
assign _T_35_burst__T_48_data = io_enq_bits_burst;
assign _T_35_burst__T_48_addr = 1'h0;
assign _T_35_burst__T_48_mask = 1'h1;
assign _T_35_burst__T_48_en = _T_39 ? _GEN_16 : _T_42;
assign _T_35_user__T_52_addr = 1'h0;
assign _T_35_user__T_52_data = _T_35_user[_T_35_user__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
assign _T_35_user__T_48_data = io_enq_bits_user;
assign _T_35_user__T_48_addr = 1'h0;
assign _T_35_user__T_48_mask = 1'h1;
assign _T_35_user__T_48_en = _T_39 ? _GEN_16 : _T_42;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@32072.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32075.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32078.4]
assign _GEN_16 = io_deq_ready ? 1'h0 : _T_42; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@32130.6]
assign _GEN_28 = _T_39 ? _GEN_16 : _T_42; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@32118.4]
assign _GEN_27 = _T_39 ? 1'h0 : _T_45; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@32118.4]
assign _T_49 = _GEN_28 != _GEN_27; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@32096.4]
assign _T_50 = _T_39 == 1'h0; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@32100.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@32103.4]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_50; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@32101.4 Decoupled.scala 241:40:freechips.rocketchip.system.LowRiscConfig.fir@32116.6]
assign io_deq_bits_id = _T_39 ? io_enq_bits_id : _T_35_id__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@32114.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@32128.6]
assign io_deq_bits_addr = _T_39 ? io_enq_bits_addr : _T_35_addr__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@32113.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@32127.6]
assign io_deq_bits_len = _T_39 ? io_enq_bits_len : _T_35_len__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@32112.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@32126.6]
assign io_deq_bits_size = _T_39 ? io_enq_bits_size : _T_35_size__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@32111.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@32125.6]
assign io_deq_bits_burst = _T_39 ? io_enq_bits_burst : _T_35_burst__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@32110.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@32124.6]
assign io_deq_bits_user = _T_39 ? io_enq_bits_user : _T_35_user__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@32105.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@32119.6]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_addr[initvar] = _RAND_1[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_len[initvar] = _RAND_2[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_size[initvar] = _RAND_3[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_burst[initvar] = _RAND_4[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_user[initvar] = _RAND_5[6:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_37 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_48_en & _T_35_id__T_48_mask) begin
_T_35_id[_T_35_id__T_48_addr] <= _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
end
if(_T_35_addr__T_48_en & _T_35_addr__T_48_mask) begin
_T_35_addr[_T_35_addr__T_48_addr] <= _T_35_addr__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
end
if(_T_35_len__T_48_en & _T_35_len__T_48_mask) begin
_T_35_len[_T_35_len__T_48_addr] <= _T_35_len__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
end
if(_T_35_size__T_48_en & _T_35_size__T_48_mask) begin
_T_35_size[_T_35_size__T_48_addr] <= _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
end
if(_T_35_burst__T_48_en & _T_35_burst__T_48_mask) begin
_T_35_burst[_T_35_burst__T_48_addr] <= _T_35_burst__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
end
if(_T_35_user__T_48_en & _T_35_user__T_48_mask) begin
_T_35_user[_T_35_user__T_48_addr] <= _T_35_user__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@32069.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
if (_T_39) begin
if (io_deq_ready) begin
_T_37 <= 1'h0;
end else begin
_T_37 <= _T_42;
end
end else begin
_T_37 <= _T_42;
end
end
end
end
endmodule
module AXI4Fragmenter( // @[:freechips.rocketchip.system.LowRiscConfig.fir@32274.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32275.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32276.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [6:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [6:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [6:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [6:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [7:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [7:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output [7:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input [7:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@32277.4]
);
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [31:0] Queue_io_enq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [7:0] Queue_io_enq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [2:0] Queue_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [1:0] Queue_io_enq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [6:0] Queue_io_enq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [31:0] Queue_io_deq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [7:0] Queue_io_deq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [2:0] Queue_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [1:0] Queue_io_deq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire [6:0] Queue_io_deq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [31:0] Queue_1_io_enq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [7:0] Queue_1_io_enq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [1:0] Queue_1_io_enq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [6:0] Queue_1_io_enq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_1_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [31:0] Queue_1_io_deq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [7:0] Queue_1_io_deq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [1:0] Queue_1_io_deq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire [6:0] Queue_1_io_deq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
wire Queue_2_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire [63:0] Queue_2_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire [7:0] Queue_2_io_enq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_io_enq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire [63:0] Queue_2_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire [7:0] Queue_2_io_deq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
wire Queue_2_io_deq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
reg _T_234; // @[Fragmenter.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@32318.4]
reg [31:0] _RAND_0;
reg [31:0] _T_236; // @[Fragmenter.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@32319.4]
reg [31:0] _RAND_1;
reg [7:0] _T_238; // @[Fragmenter.scala 60:25:freechips.rocketchip.system.LowRiscConfig.fir@32320.4]
reg [31:0] _RAND_2;
wire [7:0] _T_225_bits_len; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32311.4]
wire [7:0] _T_239; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.LowRiscConfig.fir@32321.4]
wire [31:0] _T_225_bits_addr; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32312.4]
wire [31:0] _T_240; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.LowRiscConfig.fir@32322.4]
wire [7:0] _T_242; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.LowRiscConfig.fir@32324.4]
wire [31:0] _T_243; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32325.4]
wire [32:0] _T_244; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32326.4]
wire [32:0] _T_245; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32327.4]
wire [32:0] _T_246; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32328.4]
wire _T_247; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32329.4]
wire [31:0] _T_248; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32330.4]
wire [32:0] _T_249; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32331.4]
wire [32:0] _T_250; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32332.4]
wire [32:0] _T_251; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32333.4]
wire _T_252; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32334.4]
wire [31:0] _T_253; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32335.4]
wire [32:0] _T_254; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32336.4]
wire [32:0] _T_255; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32337.4]
wire [32:0] _T_256; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32338.4]
wire _T_257; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32339.4]
wire [32:0] _T_259; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32341.4]
wire [32:0] _T_260; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32342.4]
wire [32:0] _T_261; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32343.4]
wire _T_262; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32344.4]
wire [31:0] _T_263; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32345.4]
wire [32:0] _T_264; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32346.4]
wire [32:0] _T_265; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32347.4]
wire [32:0] _T_266; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32348.4]
wire _T_267; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32349.4]
wire [31:0] _T_268; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32350.4]
wire [32:0] _T_269; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32351.4]
wire [32:0] _T_270; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32352.4]
wire [32:0] _T_271; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32353.4]
wire _T_272; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32354.4]
wire _T_273; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32355.4]
wire _T_274; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32356.4]
wire _T_275; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32357.4]
wire _T_276; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32358.4]
wire _T_277; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32359.4]
wire [31:0] _T_278; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32360.4]
wire [32:0] _T_279; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32361.4]
wire [32:0] _T_280; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32362.4]
wire [32:0] _T_281; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32363.4]
wire _T_282; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32364.4]
wire [2:0] _T_284; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32365.4]
wire [7:0] _T_285; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32366.4]
wire [7:0] _GEN_16; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32367.4]
wire [7:0] _T_286; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32367.4]
wire [6:0] _T_289; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32370.4]
wire [7:0] _GEN_17; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32371.4]
wire [7:0] _T_290; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32371.4]
wire [5:0] _T_291; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32372.4]
wire [7:0] _GEN_18; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32373.4]
wire [7:0] _T_292; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32373.4]
wire [3:0] _T_293; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32374.4]
wire [7:0] _GEN_19; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32375.4]
wire [7:0] _T_294; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32375.4]
wire [6:0] _T_296; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@32377.4]
wire [7:0] _T_297; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.LowRiscConfig.fir@32378.4]
wire [8:0] _GEN_20; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32379.4]
wire [8:0] _T_298; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32379.4]
wire [7:0] _T_299; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32380.4]
wire [7:0] _T_300; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32381.4]
wire [9:0] _GEN_21; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32382.4]
wire [9:0] _T_301; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32382.4]
wire [7:0] _T_302; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32383.4]
wire [7:0] _T_303; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32384.4]
wire [11:0] _GEN_22; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32385.4]
wire [11:0] _T_304; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32385.4]
wire [7:0] _T_305; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32386.4]
wire [7:0] _T_306; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32387.4]
wire [7:0] _T_308; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.LowRiscConfig.fir@32389.4]
wire [7:0] _GEN_23; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32390.4]
wire [7:0] _T_309; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32390.4]
wire [8:0] _GEN_24; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32391.4]
wire [8:0] _T_310; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32391.4]
wire [7:0] _T_311; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32392.4]
wire [7:0] _T_312; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32393.4]
wire [9:0] _GEN_25; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32394.4]
wire [9:0] _T_313; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32394.4]
wire [7:0] _T_314; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32395.4]
wire [7:0] _T_315; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32396.4]
wire [11:0] _GEN_26; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32397.4]
wire [11:0] _T_316; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32397.4]
wire [7:0] _T_317; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32398.4]
wire [7:0] _T_318; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32399.4]
wire [7:0] _T_320; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@32401.4]
wire [7:0] _T_321; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.LowRiscConfig.fir@32402.4]
wire [7:0] _T_322; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.LowRiscConfig.fir@32403.4]
wire [1:0] _T_225_bits_burst; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32309.4]
wire _T_323; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.LowRiscConfig.fir@32404.4]
wire [2:0] _T_225_bits_size; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32310.4]
wire _T_324; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.LowRiscConfig.fir@32405.4]
wire _T_325; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.LowRiscConfig.fir@32406.4]
wire [7:0] _T_326; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.LowRiscConfig.fir@32407.4]
wire [8:0] _GEN_27; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32408.4]
wire [8:0] _T_327; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32408.4]
wire [8:0] _T_328; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@32409.4]
wire [8:0] _T_329; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32410.4]
wire [8:0] _T_330; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@32411.4]
wire [8:0] _T_331; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@32412.4]
wire [15:0] _GEN_28; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32413.4]
wire [15:0] _T_332; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32413.4]
wire [31:0] _GEN_29; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32414.4]
wire [31:0] _T_334; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32415.4]
wire [15:0] _T_335; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32416.4]
wire [22:0] _GEN_30; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32417.4]
wire [22:0] _T_336; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32417.4]
wire [14:0] _T_337; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@32418.4]
wire _T_340; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.LowRiscConfig.fir@32422.4]
wire [31:0] _GEN_31; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32424.6]
wire [31:0] _T_341; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32424.6]
wire [31:0] _T_342; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.LowRiscConfig.fir@32425.6]
wire [31:0] _T_343; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.LowRiscConfig.fir@32426.6]
wire [31:0] _T_344; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.LowRiscConfig.fir@32427.6]
wire [31:0] _T_345; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.LowRiscConfig.fir@32428.6]
wire _T_347; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.LowRiscConfig.fir@32435.4]
wire [31:0] _T_349; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.LowRiscConfig.fir@32441.4]
wire [9:0] _T_351; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@32443.4]
wire [2:0] _T_352; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@32444.4]
wire [2:0] _T_353; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@32445.4]
wire [31:0] _GEN_33; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32446.4]
wire [31:0] _T_354; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32446.4]
wire _T_225_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@32314.4]
wire _T_356; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32449.4]
wire _T_357; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.LowRiscConfig.fir@32451.6]
wire [8:0] _GEN_34; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32454.6]
wire [9:0] _T_358; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32454.6]
wire [9:0] _T_359; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32455.6]
wire [8:0] _T_360; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32456.6]
wire [8:0] _GEN_4; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.LowRiscConfig.fir@32450.4]
reg _T_374; // @[Fragmenter.scala 58:29:freechips.rocketchip.system.LowRiscConfig.fir@32489.4]
reg [31:0] _RAND_3;
reg [31:0] _T_376; // @[Fragmenter.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@32490.4]
reg [31:0] _RAND_4;
reg [7:0] _T_378; // @[Fragmenter.scala 60:25:freechips.rocketchip.system.LowRiscConfig.fir@32491.4]
reg [31:0] _RAND_5;
wire [7:0] _T_365_bits_len; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32482.4]
wire [7:0] _T_379; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.LowRiscConfig.fir@32492.4]
wire [31:0] _T_365_bits_addr; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32483.4]
wire [31:0] _T_380; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.LowRiscConfig.fir@32493.4]
wire [7:0] _T_382; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.LowRiscConfig.fir@32495.4]
wire [31:0] _T_383; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32496.4]
wire [32:0] _T_384; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32497.4]
wire [32:0] _T_385; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32498.4]
wire [32:0] _T_386; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32499.4]
wire _T_387; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32500.4]
wire [31:0] _T_388; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32501.4]
wire [32:0] _T_389; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32502.4]
wire [32:0] _T_390; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32503.4]
wire [32:0] _T_391; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32504.4]
wire _T_392; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32505.4]
wire [31:0] _T_393; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32506.4]
wire [32:0] _T_394; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32507.4]
wire [32:0] _T_395; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32508.4]
wire [32:0] _T_396; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32509.4]
wire _T_397; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32510.4]
wire [32:0] _T_399; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32512.4]
wire [32:0] _T_400; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32513.4]
wire [32:0] _T_401; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32514.4]
wire _T_402; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32515.4]
wire [31:0] _T_403; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32516.4]
wire [32:0] _T_404; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32517.4]
wire [32:0] _T_405; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32518.4]
wire [32:0] _T_406; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32519.4]
wire _T_407; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32520.4]
wire _T_408; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32521.4]
wire _T_409; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32522.4]
wire _T_410; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32523.4]
wire [31:0] _T_411; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32524.4]
wire [32:0] _T_412; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32525.4]
wire [32:0] _T_413; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32526.4]
wire [32:0] _T_414; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32527.4]
wire _T_415; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32528.4]
wire [4:0] _T_417; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32529.4]
wire [2:0] _T_418; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32530.4]
wire [7:0] _T_419; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32531.4]
wire [4:0] _GEN_35; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32532.4]
wire [4:0] _T_420; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32532.4]
wire [7:0] _GEN_36; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32533.4]
wire [7:0] _T_421; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32533.4]
wire [6:0] _T_424; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32536.4]
wire [7:0] _GEN_37; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32537.4]
wire [7:0] _T_425; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32537.4]
wire [5:0] _T_426; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32538.4]
wire [7:0] _GEN_38; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32539.4]
wire [7:0] _T_427; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32539.4]
wire [3:0] _T_428; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32540.4]
wire [7:0] _GEN_39; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32541.4]
wire [7:0] _T_429; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32541.4]
wire [6:0] _T_431; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@32543.4]
wire [7:0] _T_432; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.LowRiscConfig.fir@32544.4]
wire [8:0] _GEN_40; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32545.4]
wire [8:0] _T_433; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32545.4]
wire [7:0] _T_434; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32546.4]
wire [7:0] _T_435; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32547.4]
wire [9:0] _GEN_41; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32548.4]
wire [9:0] _T_436; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32548.4]
wire [7:0] _T_437; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32549.4]
wire [7:0] _T_438; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32550.4]
wire [11:0] _GEN_42; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32551.4]
wire [11:0] _T_439; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32551.4]
wire [7:0] _T_440; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32552.4]
wire [7:0] _T_441; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32553.4]
wire [7:0] _T_443; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.LowRiscConfig.fir@32555.4]
wire [7:0] _GEN_43; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32556.4]
wire [7:0] _T_444; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32556.4]
wire [8:0] _GEN_44; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32557.4]
wire [8:0] _T_445; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32557.4]
wire [7:0] _T_446; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32558.4]
wire [7:0] _T_447; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32559.4]
wire [9:0] _GEN_45; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32560.4]
wire [9:0] _T_448; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32560.4]
wire [7:0] _T_449; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32561.4]
wire [7:0] _T_450; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32562.4]
wire [11:0] _GEN_46; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32563.4]
wire [11:0] _T_451; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32563.4]
wire [7:0] _T_452; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32564.4]
wire [7:0] _T_453; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32565.4]
wire [7:0] _T_455; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@32567.4]
wire [7:0] _T_456; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.LowRiscConfig.fir@32568.4]
wire [7:0] _T_457; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.LowRiscConfig.fir@32569.4]
wire [1:0] _T_365_bits_burst; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32480.4]
wire _T_458; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.LowRiscConfig.fir@32570.4]
wire [2:0] _T_365_bits_size; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32481.4]
wire _T_459; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.LowRiscConfig.fir@32571.4]
wire _T_460; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.LowRiscConfig.fir@32572.4]
wire [7:0] _T_461; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.LowRiscConfig.fir@32573.4]
wire [8:0] _GEN_47; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32574.4]
wire [8:0] _T_462; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32574.4]
wire [8:0] _T_463; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@32575.4]
wire [8:0] _T_464; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32576.4]
wire [8:0] _T_465; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@32577.4]
wire [8:0] _T_466; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@32578.4]
wire [15:0] _GEN_48; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32579.4]
wire [15:0] _T_467; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32579.4]
wire [31:0] _GEN_49; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32580.4]
wire [31:0] _T_469; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32581.4]
wire [15:0] _T_470; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32582.4]
wire [22:0] _GEN_50; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32583.4]
wire [22:0] _T_471; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32583.4]
wire [14:0] _T_472; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@32584.4]
wire _T_475; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.LowRiscConfig.fir@32588.4]
wire [31:0] _GEN_51; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32590.6]
wire [31:0] _T_476; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32590.6]
wire [31:0] _T_477; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.LowRiscConfig.fir@32591.6]
wire [31:0] _T_478; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.LowRiscConfig.fir@32592.6]
wire [31:0] _T_479; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.LowRiscConfig.fir@32593.6]
wire [31:0] _T_480; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.LowRiscConfig.fir@32594.6]
wire _T_482; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.LowRiscConfig.fir@32601.4]
reg [8:0] _T_521; // @[Fragmenter.scala 162:30:freechips.rocketchip.system.LowRiscConfig.fir@32667.4]
reg [31:0] _RAND_6;
wire _T_522; // @[Fragmenter.scala 163:30:freechips.rocketchip.system.LowRiscConfig.fir@32668.4]
reg _T_506; // @[Fragmenter.scala 148:35:freechips.rocketchip.system.LowRiscConfig.fir@32642.4]
reg [31:0] _RAND_7;
wire _T_515; // @[Fragmenter.scala 156:52:freechips.rocketchip.system.LowRiscConfig.fir@32658.4]
wire _T_516; // @[Fragmenter.scala 156:35:freechips.rocketchip.system.LowRiscConfig.fir@32659.4]
wire [31:0] _T_484; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.LowRiscConfig.fir@32607.4]
wire [9:0] _T_486; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@32609.4]
wire [2:0] _T_487; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@32610.4]
wire [2:0] _T_488; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@32611.4]
wire [31:0] _GEN_53; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32612.4]
wire [31:0] _T_489; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32612.4]
wire _T_365_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@32485.4]
wire _T_491; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32615.4]
wire _T_492; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.LowRiscConfig.fir@32617.6]
wire [8:0] _GEN_54; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32620.6]
wire [9:0] _T_493; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32620.6]
wire [9:0] _T_494; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32621.6]
wire [8:0] _T_495; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32622.6]
wire [8:0] _GEN_9; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.LowRiscConfig.fir@32616.4]
wire [6:0] _T_225_bits_user; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32304.4]
wire _T_517; // @[Fragmenter.scala 157:38:freechips.rocketchip.system.LowRiscConfig.fir@32661.4]
wire _T_518; // @[Fragmenter.scala 157:35:freechips.rocketchip.system.LowRiscConfig.fir@32662.4]
wire _T_511; // @[Fragmenter.scala 151:26:freechips.rocketchip.system.LowRiscConfig.fir@32647.4]
wire _T_514; // @[Fragmenter.scala 155:35:freechips.rocketchip.system.LowRiscConfig.fir@32656.4]
wire _T_512; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32651.4]
wire [6:0] _T_365_bits_user; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32475.4]
wire [8:0] _T_523; // @[Fragmenter.scala 164:35:freechips.rocketchip.system.LowRiscConfig.fir@32669.4]
wire [8:0] _T_524; // @[Fragmenter.scala 164:23:freechips.rocketchip.system.LowRiscConfig.fir@32670.4]
wire _T_525; // @[Fragmenter.scala 165:27:freechips.rocketchip.system.LowRiscConfig.fir@32671.4]
wire _T_500_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32633.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@32637.4]
wire _T_537; // @[Fragmenter.scala 171:37:freechips.rocketchip.system.LowRiscConfig.fir@32689.4]
wire _T_538; // @[Fragmenter.scala 171:51:freechips.rocketchip.system.LowRiscConfig.fir@32690.4]
wire _T_539; // @[Fragmenter.scala 171:33:freechips.rocketchip.system.LowRiscConfig.fir@32691.4]
wire _T_526; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32672.4]
wire [8:0] _GEN_55; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32673.4]
wire [9:0] _T_527; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32673.4]
wire [9:0] _T_528; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32674.4]
wire [8:0] _T_529; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32675.4]
wire _T_531; // @[Fragmenter.scala 167:15:freechips.rocketchip.system.LowRiscConfig.fir@32678.4]
wire _T_532; // @[Fragmenter.scala 167:39:freechips.rocketchip.system.LowRiscConfig.fir@32679.4]
wire _T_533; // @[Fragmenter.scala 167:29:freechips.rocketchip.system.LowRiscConfig.fir@32680.4]
wire _T_535; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@32682.4]
wire _T_536; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@32683.4]
wire _T_543; // @[Fragmenter.scala 176:15:freechips.rocketchip.system.LowRiscConfig.fir@32699.4]
wire _T_500_bits_last; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32633.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32634.4]
wire _T_544; // @[Fragmenter.scala 176:31:freechips.rocketchip.system.LowRiscConfig.fir@32700.4]
wire _T_545; // @[Fragmenter.scala 176:28:freechips.rocketchip.system.LowRiscConfig.fir@32701.4]
wire _T_546; // @[Fragmenter.scala 176:47:freechips.rocketchip.system.LowRiscConfig.fir@32702.4]
wire _T_548; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@32704.4]
wire _T_549; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@32705.4]
wire _T_550; // @[Fragmenter.scala 179:39:freechips.rocketchip.system.LowRiscConfig.fir@32710.4]
wire _T_553; // @[Fragmenter.scala 185:39:freechips.rocketchip.system.LowRiscConfig.fir@32716.4]
wire _T_555; // @[Fragmenter.scala 188:36:freechips.rocketchip.system.LowRiscConfig.fir@32720.4]
wire _T_556; // @[Fragmenter.scala 188:33:freechips.rocketchip.system.LowRiscConfig.fir@32721.4]
reg [1:0] _T_574_0; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.LowRiscConfig.fir@32729.4]
reg [31:0] _RAND_8;
reg [1:0] _T_574_1; // @[Fragmenter.scala 192:26:freechips.rocketchip.system.LowRiscConfig.fir@32729.4]
reg [31:0] _RAND_9;
wire [1:0] _GEN_13; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@32730.4]
wire [1:0] _T_590; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32733.4]
wire _T_592; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.LowRiscConfig.fir@32735.4]
wire _T_593; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.LowRiscConfig.fir@32736.4]
wire _T_594; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32737.4]
wire _T_595; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.LowRiscConfig.fir@32738.4]
wire [1:0] _T_596; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.LowRiscConfig.fir@32740.6]
wire _T_599; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.LowRiscConfig.fir@32745.4]
wire [1:0] _T_600; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.LowRiscConfig.fir@32747.6]
Queue_39 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32288.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_id(Queue_io_enq_bits_id),
.io_enq_bits_addr(Queue_io_enq_bits_addr),
.io_enq_bits_len(Queue_io_enq_bits_len),
.io_enq_bits_size(Queue_io_enq_bits_size),
.io_enq_bits_burst(Queue_io_enq_bits_burst),
.io_enq_bits_user(Queue_io_enq_bits_user),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_id(Queue_io_deq_bits_id),
.io_deq_bits_addr(Queue_io_deq_bits_addr),
.io_deq_bits_len(Queue_io_deq_bits_len),
.io_deq_bits_size(Queue_io_deq_bits_size),
.io_deq_bits_burst(Queue_io_deq_bits_burst),
.io_deq_bits_user(Queue_io_deq_bits_user)
);
Queue_39 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32459.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_id(Queue_1_io_enq_bits_id),
.io_enq_bits_addr(Queue_1_io_enq_bits_addr),
.io_enq_bits_len(Queue_1_io_enq_bits_len),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_burst(Queue_1_io_enq_bits_burst),
.io_enq_bits_user(Queue_1_io_enq_bits_user),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_id(Queue_1_io_deq_bits_id),
.io_deq_bits_addr(Queue_1_io_deq_bits_addr),
.io_deq_bits_len(Queue_1_io_deq_bits_len),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_burst(Queue_1_io_deq_bits_burst),
.io_deq_bits_user(Queue_1_io_deq_bits_user)
);
Queue_29 Queue_2 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@32625.4]
.clock(Queue_2_clock),
.reset(Queue_2_reset),
.io_enq_ready(Queue_2_io_enq_ready),
.io_enq_valid(Queue_2_io_enq_valid),
.io_enq_bits_data(Queue_2_io_enq_bits_data),
.io_enq_bits_strb(Queue_2_io_enq_bits_strb),
.io_enq_bits_last(Queue_2_io_enq_bits_last),
.io_deq_ready(Queue_2_io_deq_ready),
.io_deq_valid(Queue_2_io_deq_valid),
.io_deq_bits_data(Queue_2_io_deq_bits_data),
.io_deq_bits_strb(Queue_2_io_deq_bits_strb),
.io_deq_bits_last(Queue_2_io_deq_bits_last)
);
assign _T_225_bits_len = Queue_io_deq_bits_len; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32311.4]
assign _T_239 = _T_234 ? _T_238 : _T_225_bits_len; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.LowRiscConfig.fir@32321.4]
assign _T_225_bits_addr = Queue_io_deq_bits_addr; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32312.4]
assign _T_240 = _T_234 ? _T_236 : _T_225_bits_addr; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.LowRiscConfig.fir@32322.4]
assign _T_242 = _T_240[10:3]; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.LowRiscConfig.fir@32324.4]
assign _T_243 = _T_240 ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32325.4]
assign _T_244 = {1'b0,$signed(_T_243)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32326.4]
assign _T_245 = $signed(_T_244) & $signed(33'shca000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32327.4]
assign _T_246 = $signed(_T_245); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32328.4]
assign _T_247 = $signed(_T_246) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32329.4]
assign _T_248 = _T_240 ^ 32'h8000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32330.4]
assign _T_249 = {1'b0,$signed(_T_248)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32331.4]
assign _T_250 = $signed(_T_249) & $signed(33'shc8000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32332.4]
assign _T_251 = $signed(_T_250); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32333.4]
assign _T_252 = $signed(_T_251) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32334.4]
assign _T_253 = _T_240 ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32335.4]
assign _T_254 = {1'b0,$signed(_T_253)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32336.4]
assign _T_255 = $signed(_T_254) & $signed(33'shca010000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32337.4]
assign _T_256 = $signed(_T_255); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32338.4]
assign _T_257 = $signed(_T_256) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32339.4]
assign _T_259 = {1'b0,$signed(_T_240)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32341.4]
assign _T_260 = $signed(_T_259) & $signed(33'shca012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32342.4]
assign _T_261 = $signed(_T_260); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32343.4]
assign _T_262 = $signed(_T_261) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32344.4]
assign _T_263 = _T_240 ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32345.4]
assign _T_264 = {1'b0,$signed(_T_263)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32346.4]
assign _T_265 = $signed(_T_264) & $signed(33'shca010000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32347.4]
assign _T_266 = $signed(_T_265); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32348.4]
assign _T_267 = $signed(_T_266) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32349.4]
assign _T_268 = _T_240 ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32350.4]
assign _T_269 = {1'b0,$signed(_T_268)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32351.4]
assign _T_270 = $signed(_T_269) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32352.4]
assign _T_271 = $signed(_T_270); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32353.4]
assign _T_272 = $signed(_T_271) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32354.4]
assign _T_273 = _T_247 | _T_252; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32355.4]
assign _T_274 = _T_273 | _T_257; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32356.4]
assign _T_275 = _T_274 | _T_262; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32357.4]
assign _T_276 = _T_275 | _T_267; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32358.4]
assign _T_277 = _T_276 | _T_272; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32359.4]
assign _T_278 = _T_240 ^ 32'h2000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32360.4]
assign _T_279 = {1'b0,$signed(_T_278)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32361.4]
assign _T_280 = $signed(_T_279) & $signed(33'shca012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32362.4]
assign _T_281 = $signed(_T_280); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32363.4]
assign _T_282 = $signed(_T_281) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32364.4]
assign _T_284 = _T_277 ? 3'h7 : 3'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32365.4]
assign _T_285 = _T_282 ? 8'hff : 8'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32366.4]
assign _GEN_16 = {{5'd0}, _T_284}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32367.4]
assign _T_286 = _GEN_16 | _T_285; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32367.4]
assign _T_289 = _T_239[7:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32370.4]
assign _GEN_17 = {{1'd0}, _T_289}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32371.4]
assign _T_290 = _T_239 | _GEN_17; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32371.4]
assign _T_291 = _T_290[7:2]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32372.4]
assign _GEN_18 = {{2'd0}, _T_291}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32373.4]
assign _T_292 = _T_290 | _GEN_18; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32373.4]
assign _T_293 = _T_292[7:4]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32374.4]
assign _GEN_19 = {{4'd0}, _T_293}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32375.4]
assign _T_294 = _T_292 | _GEN_19; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32375.4]
assign _T_296 = _T_294[7:1]; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@32377.4]
assign _T_297 = ~ _T_239; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.LowRiscConfig.fir@32378.4]
assign _GEN_20 = {{1'd0}, _T_297}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32379.4]
assign _T_298 = _GEN_20 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32379.4]
assign _T_299 = _T_298[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32380.4]
assign _T_300 = _T_297 | _T_299; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32381.4]
assign _GEN_21 = {{2'd0}, _T_300}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32382.4]
assign _T_301 = _GEN_21 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32382.4]
assign _T_302 = _T_301[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32383.4]
assign _T_303 = _T_300 | _T_302; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32384.4]
assign _GEN_22 = {{4'd0}, _T_303}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32385.4]
assign _T_304 = _GEN_22 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32385.4]
assign _T_305 = _T_304[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32386.4]
assign _T_306 = _T_303 | _T_305; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32387.4]
assign _T_308 = ~ _T_306; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.LowRiscConfig.fir@32389.4]
assign _GEN_23 = {{1'd0}, _T_296}; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32390.4]
assign _T_309 = _GEN_23 | _T_308; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32390.4]
assign _GEN_24 = {{1'd0}, _T_242}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32391.4]
assign _T_310 = _GEN_24 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32391.4]
assign _T_311 = _T_310[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32392.4]
assign _T_312 = _T_242 | _T_311; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32393.4]
assign _GEN_25 = {{2'd0}, _T_312}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32394.4]
assign _T_313 = _GEN_25 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32394.4]
assign _T_314 = _T_313[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32395.4]
assign _T_315 = _T_312 | _T_314; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32396.4]
assign _GEN_26 = {{4'd0}, _T_315}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32397.4]
assign _T_316 = _GEN_26 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32397.4]
assign _T_317 = _T_316[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32398.4]
assign _T_318 = _T_315 | _T_317; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32399.4]
assign _T_320 = ~ _T_318; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@32401.4]
assign _T_321 = _T_309 & _T_320; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.LowRiscConfig.fir@32402.4]
assign _T_322 = _T_321 & _T_286; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.LowRiscConfig.fir@32403.4]
assign _T_225_bits_burst = Queue_io_deq_bits_burst; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32309.4]
assign _T_323 = _T_225_bits_burst == 2'h0; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.LowRiscConfig.fir@32404.4]
assign _T_225_bits_size = Queue_io_deq_bits_size; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32310.4]
assign _T_324 = _T_225_bits_size != 3'h3; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.LowRiscConfig.fir@32405.4]
assign _T_325 = _T_323 | _T_324; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.LowRiscConfig.fir@32406.4]
assign _T_326 = _T_325 ? 8'h0 : _T_322; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.LowRiscConfig.fir@32407.4]
assign _GEN_27 = {{1'd0}, _T_326}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32408.4]
assign _T_327 = _GEN_27 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32408.4]
assign _T_328 = _T_327 | 9'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@32409.4]
assign _T_329 = {1'h0,_T_326}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32410.4]
assign _T_330 = ~ _T_329; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@32411.4]
assign _T_331 = _T_328 & _T_330; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@32412.4]
assign _GEN_28 = {{7'd0}, _T_331}; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32413.4]
assign _T_332 = _GEN_28 << _T_225_bits_size; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32413.4]
assign _GEN_29 = {{16'd0}, _T_332}; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32414.4]
assign _T_334 = _T_240 + _GEN_29; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32415.4]
assign _T_335 = {_T_225_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32416.4]
assign _GEN_30 = {{7'd0}, _T_335}; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32417.4]
assign _T_336 = _GEN_30 << _T_225_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32417.4]
assign _T_337 = _T_336[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@32418.4]
assign _T_340 = _T_225_bits_burst == 2'h2; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.LowRiscConfig.fir@32422.4]
assign _GEN_31 = {{17'd0}, _T_337}; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32424.6]
assign _T_341 = _T_334 & _GEN_31; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32424.6]
assign _T_342 = ~ _T_225_bits_addr; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.LowRiscConfig.fir@32425.6]
assign _T_343 = _T_342 | _GEN_31; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.LowRiscConfig.fir@32426.6]
assign _T_344 = ~ _T_343; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.LowRiscConfig.fir@32427.6]
assign _T_345 = _T_341 | _T_344; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.LowRiscConfig.fir@32428.6]
assign _T_347 = _T_326 == _T_239; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.LowRiscConfig.fir@32435.4]
assign _T_349 = ~ _T_240; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.LowRiscConfig.fir@32441.4]
assign _T_351 = 10'h7 << _T_225_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@32443.4]
assign _T_352 = _T_351[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@32444.4]
assign _T_353 = ~ _T_352; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@32445.4]
assign _GEN_33 = {{29'd0}, _T_353}; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32446.4]
assign _T_354 = _T_349 | _GEN_33; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32446.4]
assign _T_225_valid = Queue_io_deq_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@32314.4]
assign _T_356 = auto_out_ar_ready & _T_225_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32449.4]
assign _T_357 = _T_347 == 1'h0; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.LowRiscConfig.fir@32451.6]
assign _GEN_34 = {{1'd0}, _T_239}; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32454.6]
assign _T_358 = _GEN_34 - _T_331; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32454.6]
assign _T_359 = $unsigned(_T_358); // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32455.6]
assign _T_360 = _T_359[8:0]; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32456.6]
assign _GEN_4 = _T_356 ? _T_360 : {{1'd0}, _T_238}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.LowRiscConfig.fir@32450.4]
assign _T_365_bits_len = Queue_1_io_deq_bits_len; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32482.4]
assign _T_379 = _T_374 ? _T_378 : _T_365_bits_len; // @[Fragmenter.scala 62:23:freechips.rocketchip.system.LowRiscConfig.fir@32492.4]
assign _T_365_bits_addr = Queue_1_io_deq_bits_addr; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32483.4]
assign _T_380 = _T_374 ? _T_376 : _T_365_bits_addr; // @[Fragmenter.scala 63:23:freechips.rocketchip.system.LowRiscConfig.fir@32493.4]
assign _T_382 = _T_380[10:3]; // @[Fragmenter.scala 67:29:freechips.rocketchip.system.LowRiscConfig.fir@32495.4]
assign _T_383 = _T_380 ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32496.4]
assign _T_384 = {1'b0,$signed(_T_383)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32497.4]
assign _T_385 = $signed(_T_384) & $signed(33'shca000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32498.4]
assign _T_386 = $signed(_T_385); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32499.4]
assign _T_387 = $signed(_T_386) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32500.4]
assign _T_388 = _T_380 ^ 32'h8000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32501.4]
assign _T_389 = {1'b0,$signed(_T_388)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32502.4]
assign _T_390 = $signed(_T_389) & $signed(33'shc8000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32503.4]
assign _T_391 = $signed(_T_390); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32504.4]
assign _T_392 = $signed(_T_391) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32505.4]
assign _T_393 = _T_380 ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32506.4]
assign _T_394 = {1'b0,$signed(_T_393)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32507.4]
assign _T_395 = $signed(_T_394) & $signed(33'shca000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32508.4]
assign _T_396 = $signed(_T_395); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32509.4]
assign _T_397 = $signed(_T_396) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32510.4]
assign _T_399 = {1'b0,$signed(_T_380)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32512.4]
assign _T_400 = $signed(_T_399) & $signed(33'shca002000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32513.4]
assign _T_401 = $signed(_T_400); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32514.4]
assign _T_402 = $signed(_T_401) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32515.4]
assign _T_403 = _T_380 ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32516.4]
assign _T_404 = {1'b0,$signed(_T_403)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32517.4]
assign _T_405 = $signed(_T_404) & $signed(33'shc0000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32518.4]
assign _T_406 = $signed(_T_405); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32519.4]
assign _T_407 = $signed(_T_406) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32520.4]
assign _T_408 = _T_392 | _T_397; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32521.4]
assign _T_409 = _T_408 | _T_402; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32522.4]
assign _T_410 = _T_409 | _T_407; // @[Fragmenter.scala 74:100:freechips.rocketchip.system.LowRiscConfig.fir@32523.4]
assign _T_411 = _T_380 ^ 32'h2000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32524.4]
assign _T_412 = {1'b0,$signed(_T_411)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32525.4]
assign _T_413 = $signed(_T_412) & $signed(33'shca002000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32526.4]
assign _T_414 = $signed(_T_413); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32527.4]
assign _T_415 = $signed(_T_414) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@32528.4]
assign _T_417 = _T_387 ? 5'h1f : 5'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32529.4]
assign _T_418 = _T_410 ? 3'h7 : 3'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32530.4]
assign _T_419 = _T_415 ? 8'hff : 8'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32531.4]
assign _GEN_35 = {{2'd0}, _T_418}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32532.4]
assign _T_420 = _T_417 | _GEN_35; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32532.4]
assign _GEN_36 = {{3'd0}, _T_420}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32533.4]
assign _T_421 = _GEN_36 | _T_419; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@32533.4]
assign _T_424 = _T_379[7:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32536.4]
assign _GEN_37 = {{1'd0}, _T_424}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32537.4]
assign _T_425 = _T_379 | _GEN_37; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32537.4]
assign _T_426 = _T_425[7:2]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32538.4]
assign _GEN_38 = {{2'd0}, _T_426}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32539.4]
assign _T_427 = _T_425 | _GEN_38; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32539.4]
assign _T_428 = _T_427[7:4]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@32540.4]
assign _GEN_39 = {{4'd0}, _T_428}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32541.4]
assign _T_429 = _T_427 | _GEN_39; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@32541.4]
assign _T_431 = _T_429[7:1]; // @[Fragmenter.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@32543.4]
assign _T_432 = ~ _T_379; // @[Fragmenter.scala 84:32:freechips.rocketchip.system.LowRiscConfig.fir@32544.4]
assign _GEN_40 = {{1'd0}, _T_432}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32545.4]
assign _T_433 = _GEN_40 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32545.4]
assign _T_434 = _T_433[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32546.4]
assign _T_435 = _T_432 | _T_434; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32547.4]
assign _GEN_41 = {{2'd0}, _T_435}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32548.4]
assign _T_436 = _GEN_41 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32548.4]
assign _T_437 = _T_436[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32549.4]
assign _T_438 = _T_435 | _T_437; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32550.4]
assign _GEN_42 = {{4'd0}, _T_438}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32551.4]
assign _T_439 = _GEN_42 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32551.4]
assign _T_440 = _T_439[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32552.4]
assign _T_441 = _T_438 | _T_440; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32553.4]
assign _T_443 = ~ _T_441; // @[Fragmenter.scala 84:24:freechips.rocketchip.system.LowRiscConfig.fir@32555.4]
assign _GEN_43 = {{1'd0}, _T_431}; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32556.4]
assign _T_444 = _GEN_43 | _T_443; // @[Fragmenter.scala 85:32:freechips.rocketchip.system.LowRiscConfig.fir@32556.4]
assign _GEN_44 = {{1'd0}, _T_382}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32557.4]
assign _T_445 = _GEN_44 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32557.4]
assign _T_446 = _T_445[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32558.4]
assign _T_447 = _T_382 | _T_446; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32559.4]
assign _GEN_45 = {{2'd0}, _T_447}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32560.4]
assign _T_448 = _GEN_45 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32560.4]
assign _T_449 = _T_448[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32561.4]
assign _T_450 = _T_447 | _T_449; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32562.4]
assign _GEN_46 = {{4'd0}, _T_450}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32563.4]
assign _T_451 = _GEN_46 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@32563.4]
assign _T_452 = _T_451[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@32564.4]
assign _T_453 = _T_450 | _T_452; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@32565.4]
assign _T_455 = ~ _T_453; // @[Fragmenter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@32567.4]
assign _T_456 = _T_444 & _T_455; // @[Fragmenter.scala 87:37:freechips.rocketchip.system.LowRiscConfig.fir@32568.4]
assign _T_457 = _T_456 & _T_421; // @[Fragmenter.scala 87:46:freechips.rocketchip.system.LowRiscConfig.fir@32569.4]
assign _T_365_bits_burst = Queue_1_io_deq_bits_burst; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32480.4]
assign _T_458 = _T_365_bits_burst == 2'h0; // @[Fragmenter.scala 90:34:freechips.rocketchip.system.LowRiscConfig.fir@32570.4]
assign _T_365_bits_size = Queue_1_io_deq_bits_size; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32481.4]
assign _T_459 = _T_365_bits_size != 3'h3; // @[Fragmenter.scala 91:34:freechips.rocketchip.system.LowRiscConfig.fir@32571.4]
assign _T_460 = _T_458 | _T_459; // @[Fragmenter.scala 92:25:freechips.rocketchip.system.LowRiscConfig.fir@32572.4]
assign _T_461 = _T_460 ? 8'h0 : _T_457; // @[Fragmenter.scala 95:25:freechips.rocketchip.system.LowRiscConfig.fir@32573.4]
assign _GEN_47 = {{1'd0}, _T_461}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32574.4]
assign _T_462 = _GEN_47 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@32574.4]
assign _T_463 = _T_462 | 9'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@32575.4]
assign _T_464 = {1'h0,_T_461}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32576.4]
assign _T_465 = ~ _T_464; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@32577.4]
assign _T_466 = _T_463 & _T_465; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@32578.4]
assign _GEN_48 = {{7'd0}, _T_466}; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32579.4]
assign _T_467 = _GEN_48 << _T_365_bits_size; // @[Fragmenter.scala 98:38:freechips.rocketchip.system.LowRiscConfig.fir@32579.4]
assign _GEN_49 = {{16'd0}, _T_467}; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32580.4]
assign _T_469 = _T_380 + _GEN_49; // @[Fragmenter.scala 98:29:freechips.rocketchip.system.LowRiscConfig.fir@32581.4]
assign _T_470 = {_T_365_bits_len,8'hff}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32582.4]
assign _GEN_50 = {{7'd0}, _T_470}; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32583.4]
assign _T_471 = _GEN_50 << _T_365_bits_size; // @[Bundles.scala 29:21:freechips.rocketchip.system.LowRiscConfig.fir@32583.4]
assign _T_472 = _T_471[22:8]; // @[Bundles.scala 29:30:freechips.rocketchip.system.LowRiscConfig.fir@32584.4]
assign _T_475 = _T_365_bits_burst == 2'h2; // @[Fragmenter.scala 101:28:freechips.rocketchip.system.LowRiscConfig.fir@32588.4]
assign _GEN_51 = {{17'd0}, _T_472}; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32590.6]
assign _T_476 = _T_469 & _GEN_51; // @[Fragmenter.scala 102:33:freechips.rocketchip.system.LowRiscConfig.fir@32590.6]
assign _T_477 = ~ _T_365_bits_addr; // @[Fragmenter.scala 102:49:freechips.rocketchip.system.LowRiscConfig.fir@32591.6]
assign _T_478 = _T_477 | _GEN_51; // @[Fragmenter.scala 102:62:freechips.rocketchip.system.LowRiscConfig.fir@32592.6]
assign _T_479 = ~ _T_478; // @[Fragmenter.scala 102:47:freechips.rocketchip.system.LowRiscConfig.fir@32593.6]
assign _T_480 = _T_476 | _T_479; // @[Fragmenter.scala 102:45:freechips.rocketchip.system.LowRiscConfig.fir@32594.6]
assign _T_482 = _T_461 == _T_379; // @[Fragmenter.scala 108:27:freechips.rocketchip.system.LowRiscConfig.fir@32601.4]
assign _T_522 = _T_521 == 9'h0; // @[Fragmenter.scala 163:30:freechips.rocketchip.system.LowRiscConfig.fir@32668.4]
assign _T_515 = _T_522 | _T_506; // @[Fragmenter.scala 156:52:freechips.rocketchip.system.LowRiscConfig.fir@32658.4]
assign _T_516 = auto_out_aw_ready & _T_515; // @[Fragmenter.scala 156:35:freechips.rocketchip.system.LowRiscConfig.fir@32659.4]
assign _T_484 = ~ _T_380; // @[Fragmenter.scala 120:28:freechips.rocketchip.system.LowRiscConfig.fir@32607.4]
assign _T_486 = 10'h7 << _T_365_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@32609.4]
assign _T_487 = _T_486[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@32610.4]
assign _T_488 = ~ _T_487; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@32611.4]
assign _GEN_53 = {{29'd0}, _T_488}; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32612.4]
assign _T_489 = _T_484 | _GEN_53; // @[Fragmenter.scala 120:34:freechips.rocketchip.system.LowRiscConfig.fir@32612.4]
assign _T_365_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@32485.4]
assign _T_491 = _T_516 & _T_365_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32615.4]
assign _T_492 = _T_482 == 1'h0; // @[Fragmenter.scala 123:19:freechips.rocketchip.system.LowRiscConfig.fir@32617.6]
assign _GEN_54 = {{1'd0}, _T_379}; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32620.6]
assign _T_493 = _GEN_54 - _T_466; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32620.6]
assign _T_494 = $unsigned(_T_493); // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32621.6]
assign _T_495 = _T_494[8:0]; // @[Fragmenter.scala 125:25:freechips.rocketchip.system.LowRiscConfig.fir@32622.6]
assign _GEN_9 = _T_491 ? _T_495 : {{1'd0}, _T_378}; // @[Fragmenter.scala 122:27:freechips.rocketchip.system.LowRiscConfig.fir@32616.4]
assign _T_225_bits_user = Queue_io_deq_bits_user; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32303.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32304.4]
assign _T_517 = _T_506 == 1'h0; // @[Fragmenter.scala 157:38:freechips.rocketchip.system.LowRiscConfig.fir@32661.4]
assign _T_518 = _T_365_valid & _T_517; // @[Fragmenter.scala 157:35:freechips.rocketchip.system.LowRiscConfig.fir@32662.4]
assign _T_511 = _T_518 & _T_522; // @[Fragmenter.scala 151:26:freechips.rocketchip.system.LowRiscConfig.fir@32647.4]
assign _T_514 = _T_365_valid & _T_515; // @[Fragmenter.scala 155:35:freechips.rocketchip.system.LowRiscConfig.fir@32656.4]
assign _T_512 = auto_out_aw_ready & _T_514; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32651.4]
assign _T_365_bits_user = Queue_1_io_deq_bits_user; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32474.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32475.4]
assign _T_523 = _T_518 ? _T_466 : 9'h0; // @[Fragmenter.scala 164:35:freechips.rocketchip.system.LowRiscConfig.fir@32669.4]
assign _T_524 = _T_522 ? _T_523 : _T_521; // @[Fragmenter.scala 164:23:freechips.rocketchip.system.LowRiscConfig.fir@32670.4]
assign _T_525 = _T_524 == 9'h1; // @[Fragmenter.scala 165:27:freechips.rocketchip.system.LowRiscConfig.fir@32671.4]
assign _T_500_valid = Queue_2_io_deq_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32633.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@32637.4]
assign _T_537 = _T_522 == 1'h0; // @[Fragmenter.scala 171:37:freechips.rocketchip.system.LowRiscConfig.fir@32689.4]
assign _T_538 = _T_537 | _T_518; // @[Fragmenter.scala 171:51:freechips.rocketchip.system.LowRiscConfig.fir@32690.4]
assign _T_539 = _T_500_valid & _T_538; // @[Fragmenter.scala 171:33:freechips.rocketchip.system.LowRiscConfig.fir@32691.4]
assign _T_526 = auto_out_w_ready & _T_539; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32672.4]
assign _GEN_55 = {{8'd0}, _T_526}; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32673.4]
assign _T_527 = _T_524 - _GEN_55; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32673.4]
assign _T_528 = $unsigned(_T_527); // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32674.4]
assign _T_529 = _T_528[8:0]; // @[Fragmenter.scala 166:27:freechips.rocketchip.system.LowRiscConfig.fir@32675.4]
assign _T_531 = _T_526 == 1'h0; // @[Fragmenter.scala 167:15:freechips.rocketchip.system.LowRiscConfig.fir@32678.4]
assign _T_532 = _T_524 != 9'h0; // @[Fragmenter.scala 167:39:freechips.rocketchip.system.LowRiscConfig.fir@32679.4]
assign _T_533 = _T_531 | _T_532; // @[Fragmenter.scala 167:29:freechips.rocketchip.system.LowRiscConfig.fir@32680.4]
assign _T_535 = _T_533 | reset; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@32682.4]
assign _T_536 = _T_535 == 1'h0; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@32683.4]
assign _T_543 = _T_539 == 1'h0; // @[Fragmenter.scala 176:15:freechips.rocketchip.system.LowRiscConfig.fir@32699.4]
assign _T_500_bits_last = Queue_2_io_deq_bits_last; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@32633.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@32634.4]
assign _T_544 = _T_500_bits_last == 1'h0; // @[Fragmenter.scala 176:31:freechips.rocketchip.system.LowRiscConfig.fir@32700.4]
assign _T_545 = _T_543 | _T_544; // @[Fragmenter.scala 176:28:freechips.rocketchip.system.LowRiscConfig.fir@32701.4]
assign _T_546 = _T_545 | _T_525; // @[Fragmenter.scala 176:47:freechips.rocketchip.system.LowRiscConfig.fir@32702.4]
assign _T_548 = _T_546 | reset; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@32704.4]
assign _T_549 = _T_548 == 1'h0; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@32705.4]
assign _T_550 = auto_out_r_bits_user[0]; // @[Fragmenter.scala 179:39:freechips.rocketchip.system.LowRiscConfig.fir@32710.4]
assign _T_553 = auto_out_b_bits_user[0]; // @[Fragmenter.scala 185:39:freechips.rocketchip.system.LowRiscConfig.fir@32716.4]
assign _T_555 = _T_553 == 1'h0; // @[Fragmenter.scala 188:36:freechips.rocketchip.system.LowRiscConfig.fir@32720.4]
assign _T_556 = auto_in_b_ready | _T_555; // @[Fragmenter.scala 188:33:freechips.rocketchip.system.LowRiscConfig.fir@32721.4]
assign _GEN_13 = auto_out_b_bits_id ? _T_574_1 : _T_574_0; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@32730.4]
assign _T_590 = 2'h1 << auto_out_b_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32733.4]
assign _T_592 = _T_590[0]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.LowRiscConfig.fir@32735.4]
assign _T_593 = _T_590[1]; // @[Fragmenter.scala 194:63:freechips.rocketchip.system.LowRiscConfig.fir@32736.4]
assign _T_594 = _T_556 & auto_out_b_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@32737.4]
assign _T_595 = _T_592 & _T_594; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.LowRiscConfig.fir@32738.4]
assign _T_596 = _T_574_0 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.LowRiscConfig.fir@32740.6]
assign _T_599 = _T_593 & _T_594; // @[Fragmenter.scala 195:19:freechips.rocketchip.system.LowRiscConfig.fir@32745.4]
assign _T_600 = _T_574_1 | auto_out_b_bits_resp; // @[Fragmenter.scala 195:70:freechips.rocketchip.system.LowRiscConfig.fir@32747.6]
assign auto_in_aw_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_w_ready = Queue_2_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_b_valid = auto_out_b_valid & _T_553; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp | _GEN_13; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_b_bits_user = auto_out_b_bits_user[7:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_ar_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_r_bits_user = auto_out_r_bits_user[7:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_in_r_bits_last = auto_out_r_bits_last & _T_550; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32287.4]
assign auto_out_aw_valid = _T_365_valid & _T_515; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_aw_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_aw_bits_addr = ~ _T_489; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_aw_bits_len = _T_460 ? 8'h0 : _T_457; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_aw_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_aw_bits_user = {_T_365_bits_user,_T_482}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_w_valid = _T_500_valid & _T_538; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_w_bits_data = Queue_2_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_w_bits_strb = Queue_2_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_w_bits_last = _T_524 == 9'h1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_b_ready = auto_in_b_ready | _T_555; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_ar_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_ar_bits_id = Queue_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_ar_bits_addr = ~ _T_354; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_ar_bits_len = _T_325 ? 8'h0 : _T_322; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_ar_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_ar_bits_user = {_T_225_bits_user,_T_347}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32286.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32289.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32290.4]
assign Queue_io_enq_valid = auto_in_ar_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@32291.4]
assign Queue_io_enq_bits_id = auto_in_ar_bits_id; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32301.4]
assign Queue_io_enq_bits_addr = auto_in_ar_bits_addr; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32300.4]
assign Queue_io_enq_bits_len = auto_in_ar_bits_len; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32299.4]
assign Queue_io_enq_bits_size = auto_in_ar_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32298.4]
assign Queue_io_enq_bits_burst = auto_in_ar_bits_burst; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32297.4]
assign Queue_io_enq_bits_user = auto_in_ar_bits_user; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32292.4]
assign Queue_io_deq_ready = auto_out_ar_ready & _T_347; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@32315.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32460.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32461.4]
assign Queue_1_io_enq_valid = auto_in_aw_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@32462.4]
assign Queue_1_io_enq_bits_id = auto_in_aw_bits_id; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32472.4]
assign Queue_1_io_enq_bits_addr = auto_in_aw_bits_addr; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32471.4]
assign Queue_1_io_enq_bits_len = auto_in_aw_bits_len; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32470.4]
assign Queue_1_io_enq_bits_size = auto_in_aw_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32469.4]
assign Queue_1_io_enq_bits_burst = auto_in_aw_bits_burst; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32468.4]
assign Queue_1_io_enq_bits_user = auto_in_aw_bits_user; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32463.4]
assign Queue_1_io_deq_ready = _T_516 & _T_482; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@32486.4]
assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32626.4]
assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32627.4]
assign Queue_2_io_enq_valid = auto_in_w_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@32628.4]
assign Queue_2_io_enq_bits_data = auto_in_w_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32631.4]
assign Queue_2_io_enq_bits_strb = auto_in_w_bits_strb; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32630.4]
assign Queue_2_io_enq_bits_last = auto_in_w_bits_last; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@32629.4]
assign Queue_2_io_deq_ready = auto_out_w_ready & _T_538; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@32638.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_234 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_236 = _RAND_1[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_238 = _RAND_2[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_374 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_376 = _RAND_4[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_378 = _RAND_5[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_521 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_506 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_574_0 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_574_1 = _RAND_9[1:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_234 <= 1'h0;
end else begin
if (_T_356) begin
_T_234 <= _T_357;
end
end
if (_T_356) begin
if (_T_323) begin
_T_236 <= _T_225_bits_addr;
end else begin
if (_T_340) begin
_T_236 <= _T_345;
end else begin
_T_236 <= _T_334;
end
end
end
_T_238 <= _GEN_4[7:0];
if (reset) begin
_T_374 <= 1'h0;
end else begin
if (_T_491) begin
_T_374 <= _T_492;
end
end
if (_T_491) begin
if (_T_458) begin
_T_376 <= _T_365_bits_addr;
end else begin
if (_T_475) begin
_T_376 <= _T_480;
end else begin
_T_376 <= _T_469;
end
end
end
_T_378 <= _GEN_9[7:0];
if (reset) begin
_T_521 <= 9'h0;
end else begin
_T_521 <= _T_529;
end
if (reset) begin
_T_506 <= 1'h0;
end else begin
if (_T_512) begin
_T_506 <= 1'h0;
end else begin
if (_T_511) begin
_T_506 <= 1'h1;
end
end
end
if (reset) begin
_T_574_0 <= 2'h0;
end else begin
if (_T_595) begin
if (_T_553) begin
_T_574_0 <= 2'h0;
end else begin
_T_574_0 <= _T_596;
end
end
end
if (reset) begin
_T_574_1 <= 2'h0;
end else begin
if (_T_599) begin
if (_T_553) begin
_T_574_1 <= 2'h0;
end else begin
_T_574_1 <= _T_600;
end
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_536) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:167 assert (!out.w.fire() || w_todo =/= UInt(0)) // underflow impossible\n"); // @[Fragmenter.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@32685.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_536) begin
$fatal; // @[Fragmenter.scala 167:14:freechips.rocketchip.system.LowRiscConfig.fir@32686.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_549) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:176 assert (!out.w.valid || !in_w.bits.last || w_last)\n"); // @[Fragmenter.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@32707.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_549) begin
$fatal; // @[Fragmenter.scala 176:14:freechips.rocketchip.system.LowRiscConfig.fir@32708.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module AXI4IdIndexer_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@32752.2]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [7:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [7:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [7:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [7:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [6:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [6:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output [6:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input [6:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@32755.4]
);
assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_b_bits_id = {auto_out_b_bits_user,auto_out_b_bits_id}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_r_bits_id = {auto_out_r_bits_user,auto_out_r_bits_id}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32765.4]
assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_aw_bits_id = auto_in_aw_bits_id[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_aw_bits_user = auto_in_aw_bits_id[7:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_bits_id = auto_in_ar_bits_id[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_ar_bits_user = auto_in_ar_bits_id[7:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32764.4]
endmodule
module SimpleLazyModule_5( // @[:freechips.rocketchip.system.LowRiscConfig.fir@32780.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32781.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32782.4]
output auto_axi4index_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_axi4index_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [7:0] auto_axi4index_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [31:0] auto_axi4index_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [7:0] auto_axi4index_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [2:0] auto_axi4index_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [1:0] auto_axi4index_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_axi4index_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_axi4index_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [63:0] auto_axi4index_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [7:0] auto_axi4index_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_axi4index_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_axi4index_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_axi4index_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [7:0] auto_axi4index_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [1:0] auto_axi4index_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_axi4index_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_axi4index_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [7:0] auto_axi4index_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [31:0] auto_axi4index_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [7:0] auto_axi4index_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [2:0] auto_axi4index_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [1:0] auto_axi4index_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_axi4index_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_axi4index_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [7:0] auto_axi4index_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [63:0] auto_axi4index_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [1:0] auto_axi4index_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_axi4index_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_buffer_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_buffer_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [2:0] auto_buffer_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [2:0] auto_buffer_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [3:0] auto_buffer_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [3:0] auto_buffer_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [31:0] auto_buffer_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [7:0] auto_buffer_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output [63:0] auto_buffer_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_buffer_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
output auto_buffer_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_buffer_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [2:0] auto_buffer_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [1:0] auto_buffer_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [3:0] auto_buffer_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [3:0] auto_buffer_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [1:0] auto_buffer_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_buffer_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input [63:0] auto_buffer_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
input auto_buffer_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@32783.4]
);
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [1:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [1:0] buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
wire fixer_clock; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_reset; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [2:0] fixer_auto_in_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [2:0] fixer_auto_in_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_in_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_in_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [31:0] fixer_auto_in_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [7:0] fixer_auto_in_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [63:0] fixer_auto_in_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [2:0] fixer_auto_in_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [1:0] fixer_auto_in_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_in_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_in_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [1:0] fixer_auto_in_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [63:0] fixer_auto_in_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_in_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_a_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_a_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [2:0] fixer_auto_out_a_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [2:0] fixer_auto_out_a_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_out_a_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_out_a_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [31:0] fixer_auto_out_a_bits_address; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [7:0] fixer_auto_out_a_bits_mask; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [63:0] fixer_auto_out_a_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_a_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_d_ready; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_d_valid; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [2:0] fixer_auto_out_d_bits_opcode; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [1:0] fixer_auto_out_d_bits_param; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_out_d_bits_size; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [3:0] fixer_auto_out_d_bits_source; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [1:0] fixer_auto_out_d_bits_sink; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_d_bits_denied; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire [63:0] fixer_auto_out_d_bits_data; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire fixer_auto_out_d_bits_corrupt; // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
wire widget_clock; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_reset; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [2:0] widget_auto_in_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [2:0] widget_auto_in_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_in_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_in_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [31:0] widget_auto_in_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [7:0] widget_auto_in_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [63:0] widget_auto_in_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [2:0] widget_auto_in_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_in_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_in_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [63:0] widget_auto_in_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_in_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_a_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_a_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [2:0] widget_auto_out_a_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [2:0] widget_auto_out_a_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_out_a_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_out_a_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [31:0] widget_auto_out_a_bits_address; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [7:0] widget_auto_out_a_bits_mask; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [63:0] widget_auto_out_a_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_a_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_d_ready; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_d_valid; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [2:0] widget_auto_out_d_bits_opcode; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [1:0] widget_auto_out_d_bits_param; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_out_d_bits_size; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [3:0] widget_auto_out_d_bits_source; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [1:0] widget_auto_out_d_bits_sink; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_d_bits_denied; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire [63:0] widget_auto_out_d_bits_data; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire widget_auto_out_d_bits_corrupt; // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
wire axi42tl_clock; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_reset; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_aw_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_aw_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_aw_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [31:0] axi42tl_auto_in_aw_bits_addr; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [7:0] axi42tl_auto_in_aw_bits_len; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [2:0] axi42tl_auto_in_aw_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_w_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_w_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [63:0] axi42tl_auto_in_w_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [7:0] axi42tl_auto_in_w_bits_strb; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_w_bits_last; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_b_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_b_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_b_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [1:0] axi42tl_auto_in_b_bits_resp; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_ar_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_ar_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_ar_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [31:0] axi42tl_auto_in_ar_bits_addr; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [7:0] axi42tl_auto_in_ar_bits_len; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [2:0] axi42tl_auto_in_ar_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_r_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_r_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_r_bits_id; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [63:0] axi42tl_auto_in_r_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [1:0] axi42tl_auto_in_r_bits_resp; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_in_r_bits_last; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_a_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_a_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [2:0] axi42tl_auto_out_a_bits_opcode; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [2:0] axi42tl_auto_out_a_bits_param; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [3:0] axi42tl_auto_out_a_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [3:0] axi42tl_auto_out_a_bits_source; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [31:0] axi42tl_auto_out_a_bits_address; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [7:0] axi42tl_auto_out_a_bits_mask; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [63:0] axi42tl_auto_out_a_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_a_bits_corrupt; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_d_ready; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_d_valid; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [2:0] axi42tl_auto_out_d_bits_opcode; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [3:0] axi42tl_auto_out_d_bits_size; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [3:0] axi42tl_auto_out_d_bits_source; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_d_bits_denied; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire [63:0] axi42tl_auto_out_d_bits_data; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi42tl_auto_out_d_bits_corrupt; // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
wire axi4yank_clock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_reset; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [31:0] axi4yank_auto_in_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [2:0] axi4yank_auto_in_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_aw_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [63:0] axi4yank_auto_in_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [1:0] axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_b_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [31:0] axi4yank_auto_in_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [2:0] axi4yank_auto_in_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_ar_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [63:0] axi4yank_auto_in_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [1:0] axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_in_r_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_in_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [31:0] axi4yank_auto_out_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_out_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [2:0] axi4yank_auto_out_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [63:0] axi4yank_auto_out_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_out_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [1:0] axi4yank_auto_out_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [31:0] axi4yank_auto_out_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [7:0] axi4yank_auto_out_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [2:0] axi4yank_auto_out_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [63:0] axi4yank_auto_out_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire [1:0] axi4yank_auto_out_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4yank_auto_out_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
wire axi4frag_clock; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_reset; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_aw_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_aw_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_aw_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [31:0] axi4frag_auto_in_aw_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_in_aw_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [2:0] axi4frag_auto_in_aw_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [1:0] axi4frag_auto_in_aw_bits_burst; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [6:0] axi4frag_auto_in_aw_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_w_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_w_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [63:0] axi4frag_auto_in_w_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_in_w_bits_strb; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_w_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_b_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_b_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_b_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [1:0] axi4frag_auto_in_b_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [6:0] axi4frag_auto_in_b_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_ar_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_ar_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_ar_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [31:0] axi4frag_auto_in_ar_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_in_ar_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [2:0] axi4frag_auto_in_ar_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [1:0] axi4frag_auto_in_ar_bits_burst; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [6:0] axi4frag_auto_in_ar_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_r_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_r_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_r_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [63:0] axi4frag_auto_in_r_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [1:0] axi4frag_auto_in_r_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [6:0] axi4frag_auto_in_r_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_in_r_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_aw_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_aw_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_aw_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [31:0] axi4frag_auto_out_aw_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_aw_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [2:0] axi4frag_auto_out_aw_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_aw_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_w_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_w_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [63:0] axi4frag_auto_out_w_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_w_bits_strb; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_w_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_b_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_b_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_b_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [1:0] axi4frag_auto_out_b_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_b_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_ar_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_ar_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_ar_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [31:0] axi4frag_auto_out_ar_bits_addr; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_ar_bits_len; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [2:0] axi4frag_auto_out_ar_bits_size; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_ar_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_r_ready; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_r_valid; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_r_bits_id; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [63:0] axi4frag_auto_out_r_bits_data; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [1:0] axi4frag_auto_out_r_bits_resp; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire [7:0] axi4frag_auto_out_r_bits_user; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4frag_auto_out_r_bits_last; // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
wire axi4index_auto_in_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [31:0] axi4index_auto_in_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [2:0] axi4index_auto_in_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_in_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [63:0] axi4index_auto_in_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [31:0] axi4index_auto_in_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [2:0] axi4index_auto_in_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_in_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_in_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [63:0] axi4index_auto_in_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_in_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [31:0] axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [2:0] axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [6:0] axi4index_auto_out_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [63:0] axi4index_auto_out_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_out_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [6:0] axi4index_auto_out_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [31:0] axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [7:0] axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [2:0] axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [6:0] axi4index_auto_out_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [63:0] axi4index_auto_out_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [1:0] axi4index_auto_out_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire [6:0] axi4index_auto_out_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
wire axi4index_auto_out_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
TLBuffer_4 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@32788.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(buffer_auto_in_d_bits_param),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(buffer_auto_out_d_bits_param),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
);
TLFIFOFixer_2 fixer ( // @[FIFOFixer.scala 146:27:freechips.rocketchip.system.LowRiscConfig.fir@32794.4]
.clock(fixer_clock),
.reset(fixer_reset),
.auto_in_a_ready(fixer_auto_in_a_ready),
.auto_in_a_valid(fixer_auto_in_a_valid),
.auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fixer_auto_in_a_bits_param),
.auto_in_a_bits_size(fixer_auto_in_a_bits_size),
.auto_in_a_bits_source(fixer_auto_in_a_bits_source),
.auto_in_a_bits_address(fixer_auto_in_a_bits_address),
.auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
.auto_in_a_bits_data(fixer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
.auto_in_d_ready(fixer_auto_in_d_ready),
.auto_in_d_valid(fixer_auto_in_d_valid),
.auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(fixer_auto_in_d_bits_param),
.auto_in_d_bits_size(fixer_auto_in_d_bits_size),
.auto_in_d_bits_source(fixer_auto_in_d_bits_source),
.auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
.auto_in_d_bits_data(fixer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
.auto_out_a_ready(fixer_auto_out_a_ready),
.auto_out_a_valid(fixer_auto_out_a_valid),
.auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fixer_auto_out_a_bits_param),
.auto_out_a_bits_size(fixer_auto_out_a_bits_size),
.auto_out_a_bits_source(fixer_auto_out_a_bits_source),
.auto_out_a_bits_address(fixer_auto_out_a_bits_address),
.auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
.auto_out_a_bits_data(fixer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
.auto_out_d_ready(fixer_auto_out_d_ready),
.auto_out_d_valid(fixer_auto_out_d_valid),
.auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(fixer_auto_out_d_bits_param),
.auto_out_d_bits_size(fixer_auto_out_d_bits_size),
.auto_out_d_bits_source(fixer_auto_out_d_bits_source),
.auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
.auto_out_d_bits_data(fixer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt)
);
TLWidthWidget_3 widget ( // @[WidthWidget.scala 203:28:freechips.rocketchip.system.LowRiscConfig.fir@32800.4]
.clock(widget_clock),
.reset(widget_reset),
.auto_in_a_ready(widget_auto_in_a_ready),
.auto_in_a_valid(widget_auto_in_a_valid),
.auto_in_a_bits_opcode(widget_auto_in_a_bits_opcode),
.auto_in_a_bits_param(widget_auto_in_a_bits_param),
.auto_in_a_bits_size(widget_auto_in_a_bits_size),
.auto_in_a_bits_source(widget_auto_in_a_bits_source),
.auto_in_a_bits_address(widget_auto_in_a_bits_address),
.auto_in_a_bits_mask(widget_auto_in_a_bits_mask),
.auto_in_a_bits_data(widget_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(widget_auto_in_a_bits_corrupt),
.auto_in_d_ready(widget_auto_in_d_ready),
.auto_in_d_valid(widget_auto_in_d_valid),
.auto_in_d_bits_opcode(widget_auto_in_d_bits_opcode),
.auto_in_d_bits_size(widget_auto_in_d_bits_size),
.auto_in_d_bits_source(widget_auto_in_d_bits_source),
.auto_in_d_bits_denied(widget_auto_in_d_bits_denied),
.auto_in_d_bits_data(widget_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(widget_auto_in_d_bits_corrupt),
.auto_out_a_ready(widget_auto_out_a_ready),
.auto_out_a_valid(widget_auto_out_a_valid),
.auto_out_a_bits_opcode(widget_auto_out_a_bits_opcode),
.auto_out_a_bits_param(widget_auto_out_a_bits_param),
.auto_out_a_bits_size(widget_auto_out_a_bits_size),
.auto_out_a_bits_source(widget_auto_out_a_bits_source),
.auto_out_a_bits_address(widget_auto_out_a_bits_address),
.auto_out_a_bits_mask(widget_auto_out_a_bits_mask),
.auto_out_a_bits_data(widget_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(widget_auto_out_a_bits_corrupt),
.auto_out_d_ready(widget_auto_out_d_ready),
.auto_out_d_valid(widget_auto_out_d_valid),
.auto_out_d_bits_opcode(widget_auto_out_d_bits_opcode),
.auto_out_d_bits_param(widget_auto_out_d_bits_param),
.auto_out_d_bits_size(widget_auto_out_d_bits_size),
.auto_out_d_bits_source(widget_auto_out_d_bits_source),
.auto_out_d_bits_sink(widget_auto_out_d_bits_sink),
.auto_out_d_bits_denied(widget_auto_out_d_bits_denied),
.auto_out_d_bits_data(widget_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(widget_auto_out_d_bits_corrupt)
);
AXI4ToTL axi42tl ( // @[ToTL.scala 168:29:freechips.rocketchip.system.LowRiscConfig.fir@32806.4]
.clock(axi42tl_clock),
.reset(axi42tl_reset),
.auto_in_aw_ready(axi42tl_auto_in_aw_ready),
.auto_in_aw_valid(axi42tl_auto_in_aw_valid),
.auto_in_aw_bits_id(axi42tl_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi42tl_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi42tl_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi42tl_auto_in_aw_bits_size),
.auto_in_w_ready(axi42tl_auto_in_w_ready),
.auto_in_w_valid(axi42tl_auto_in_w_valid),
.auto_in_w_bits_data(axi42tl_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi42tl_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi42tl_auto_in_w_bits_last),
.auto_in_b_ready(axi42tl_auto_in_b_ready),
.auto_in_b_valid(axi42tl_auto_in_b_valid),
.auto_in_b_bits_id(axi42tl_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi42tl_auto_in_b_bits_resp),
.auto_in_ar_ready(axi42tl_auto_in_ar_ready),
.auto_in_ar_valid(axi42tl_auto_in_ar_valid),
.auto_in_ar_bits_id(axi42tl_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi42tl_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi42tl_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi42tl_auto_in_ar_bits_size),
.auto_in_r_ready(axi42tl_auto_in_r_ready),
.auto_in_r_valid(axi42tl_auto_in_r_valid),
.auto_in_r_bits_id(axi42tl_auto_in_r_bits_id),
.auto_in_r_bits_data(axi42tl_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi42tl_auto_in_r_bits_resp),
.auto_in_r_bits_last(axi42tl_auto_in_r_bits_last),
.auto_out_a_ready(axi42tl_auto_out_a_ready),
.auto_out_a_valid(axi42tl_auto_out_a_valid),
.auto_out_a_bits_opcode(axi42tl_auto_out_a_bits_opcode),
.auto_out_a_bits_param(axi42tl_auto_out_a_bits_param),
.auto_out_a_bits_size(axi42tl_auto_out_a_bits_size),
.auto_out_a_bits_source(axi42tl_auto_out_a_bits_source),
.auto_out_a_bits_address(axi42tl_auto_out_a_bits_address),
.auto_out_a_bits_mask(axi42tl_auto_out_a_bits_mask),
.auto_out_a_bits_data(axi42tl_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(axi42tl_auto_out_a_bits_corrupt),
.auto_out_d_ready(axi42tl_auto_out_d_ready),
.auto_out_d_valid(axi42tl_auto_out_d_valid),
.auto_out_d_bits_opcode(axi42tl_auto_out_d_bits_opcode),
.auto_out_d_bits_size(axi42tl_auto_out_d_bits_size),
.auto_out_d_bits_source(axi42tl_auto_out_d_bits_source),
.auto_out_d_bits_denied(axi42tl_auto_out_d_bits_denied),
.auto_out_d_bits_data(axi42tl_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(axi42tl_auto_out_d_bits_corrupt)
);
AXI4UserYanker_1 axi4yank ( // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@32812.4]
.clock(axi4yank_clock),
.reset(axi4yank_reset),
.auto_in_aw_ready(axi4yank_auto_in_aw_ready),
.auto_in_aw_valid(axi4yank_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4yank_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4yank_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4yank_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4yank_auto_in_aw_bits_size),
.auto_in_aw_bits_user(axi4yank_auto_in_aw_bits_user),
.auto_in_w_ready(axi4yank_auto_in_w_ready),
.auto_in_w_valid(axi4yank_auto_in_w_valid),
.auto_in_w_bits_data(axi4yank_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4yank_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4yank_auto_in_w_bits_last),
.auto_in_b_ready(axi4yank_auto_in_b_ready),
.auto_in_b_valid(axi4yank_auto_in_b_valid),
.auto_in_b_bits_id(axi4yank_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4yank_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4yank_auto_in_b_bits_user),
.auto_in_ar_ready(axi4yank_auto_in_ar_ready),
.auto_in_ar_valid(axi4yank_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4yank_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4yank_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4yank_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4yank_auto_in_ar_bits_size),
.auto_in_ar_bits_user(axi4yank_auto_in_ar_bits_user),
.auto_in_r_ready(axi4yank_auto_in_r_ready),
.auto_in_r_valid(axi4yank_auto_in_r_valid),
.auto_in_r_bits_id(axi4yank_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4yank_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4yank_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4yank_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4yank_auto_in_r_bits_last),
.auto_out_aw_ready(axi4yank_auto_out_aw_ready),
.auto_out_aw_valid(axi4yank_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4yank_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4yank_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4yank_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4yank_auto_out_aw_bits_size),
.auto_out_w_ready(axi4yank_auto_out_w_ready),
.auto_out_w_valid(axi4yank_auto_out_w_valid),
.auto_out_w_bits_data(axi4yank_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4yank_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4yank_auto_out_w_bits_last),
.auto_out_b_ready(axi4yank_auto_out_b_ready),
.auto_out_b_valid(axi4yank_auto_out_b_valid),
.auto_out_b_bits_id(axi4yank_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4yank_auto_out_b_bits_resp),
.auto_out_ar_ready(axi4yank_auto_out_ar_ready),
.auto_out_ar_valid(axi4yank_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4yank_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4yank_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4yank_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4yank_auto_out_ar_bits_size),
.auto_out_r_ready(axi4yank_auto_out_r_ready),
.auto_out_r_valid(axi4yank_auto_out_r_valid),
.auto_out_r_bits_id(axi4yank_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4yank_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4yank_auto_out_r_bits_resp),
.auto_out_r_bits_last(axi4yank_auto_out_r_bits_last)
);
AXI4Fragmenter axi4frag ( // @[Fragmenter.scala 205:30:freechips.rocketchip.system.LowRiscConfig.fir@32818.4]
.clock(axi4frag_clock),
.reset(axi4frag_reset),
.auto_in_aw_ready(axi4frag_auto_in_aw_ready),
.auto_in_aw_valid(axi4frag_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4frag_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4frag_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4frag_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4frag_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4frag_auto_in_aw_bits_burst),
.auto_in_aw_bits_user(axi4frag_auto_in_aw_bits_user),
.auto_in_w_ready(axi4frag_auto_in_w_ready),
.auto_in_w_valid(axi4frag_auto_in_w_valid),
.auto_in_w_bits_data(axi4frag_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4frag_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4frag_auto_in_w_bits_last),
.auto_in_b_ready(axi4frag_auto_in_b_ready),
.auto_in_b_valid(axi4frag_auto_in_b_valid),
.auto_in_b_bits_id(axi4frag_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4frag_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4frag_auto_in_b_bits_user),
.auto_in_ar_ready(axi4frag_auto_in_ar_ready),
.auto_in_ar_valid(axi4frag_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4frag_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4frag_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4frag_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4frag_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4frag_auto_in_ar_bits_burst),
.auto_in_ar_bits_user(axi4frag_auto_in_ar_bits_user),
.auto_in_r_ready(axi4frag_auto_in_r_ready),
.auto_in_r_valid(axi4frag_auto_in_r_valid),
.auto_in_r_bits_id(axi4frag_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4frag_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4frag_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4frag_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4frag_auto_in_r_bits_last),
.auto_out_aw_ready(axi4frag_auto_out_aw_ready),
.auto_out_aw_valid(axi4frag_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4frag_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4frag_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4frag_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4frag_auto_out_aw_bits_size),
.auto_out_aw_bits_user(axi4frag_auto_out_aw_bits_user),
.auto_out_w_ready(axi4frag_auto_out_w_ready),
.auto_out_w_valid(axi4frag_auto_out_w_valid),
.auto_out_w_bits_data(axi4frag_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4frag_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4frag_auto_out_w_bits_last),
.auto_out_b_ready(axi4frag_auto_out_b_ready),
.auto_out_b_valid(axi4frag_auto_out_b_valid),
.auto_out_b_bits_id(axi4frag_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4frag_auto_out_b_bits_resp),
.auto_out_b_bits_user(axi4frag_auto_out_b_bits_user),
.auto_out_ar_ready(axi4frag_auto_out_ar_ready),
.auto_out_ar_valid(axi4frag_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4frag_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4frag_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4frag_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4frag_auto_out_ar_bits_size),
.auto_out_ar_bits_user(axi4frag_auto_out_ar_bits_user),
.auto_out_r_ready(axi4frag_auto_out_r_ready),
.auto_out_r_valid(axi4frag_auto_out_r_valid),
.auto_out_r_bits_id(axi4frag_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4frag_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4frag_auto_out_r_bits_resp),
.auto_out_r_bits_user(axi4frag_auto_out_r_bits_user),
.auto_out_r_bits_last(axi4frag_auto_out_r_bits_last)
);
AXI4IdIndexer_1 axi4index ( // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@32824.4]
.auto_in_aw_ready(axi4index_auto_in_aw_ready),
.auto_in_aw_valid(axi4index_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4index_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4index_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4index_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4index_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4index_auto_in_aw_bits_burst),
.auto_in_w_ready(axi4index_auto_in_w_ready),
.auto_in_w_valid(axi4index_auto_in_w_valid),
.auto_in_w_bits_data(axi4index_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4index_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4index_auto_in_w_bits_last),
.auto_in_b_ready(axi4index_auto_in_b_ready),
.auto_in_b_valid(axi4index_auto_in_b_valid),
.auto_in_b_bits_id(axi4index_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4index_auto_in_b_bits_resp),
.auto_in_ar_ready(axi4index_auto_in_ar_ready),
.auto_in_ar_valid(axi4index_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4index_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4index_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4index_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4index_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4index_auto_in_ar_bits_burst),
.auto_in_r_ready(axi4index_auto_in_r_ready),
.auto_in_r_valid(axi4index_auto_in_r_valid),
.auto_in_r_bits_id(axi4index_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4index_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4index_auto_in_r_bits_resp),
.auto_in_r_bits_last(axi4index_auto_in_r_bits_last),
.auto_out_aw_ready(axi4index_auto_out_aw_ready),
.auto_out_aw_valid(axi4index_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4index_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4index_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4index_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4index_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4index_auto_out_aw_bits_burst),
.auto_out_aw_bits_user(axi4index_auto_out_aw_bits_user),
.auto_out_w_ready(axi4index_auto_out_w_ready),
.auto_out_w_valid(axi4index_auto_out_w_valid),
.auto_out_w_bits_data(axi4index_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4index_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4index_auto_out_w_bits_last),
.auto_out_b_ready(axi4index_auto_out_b_ready),
.auto_out_b_valid(axi4index_auto_out_b_valid),
.auto_out_b_bits_id(axi4index_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4index_auto_out_b_bits_resp),
.auto_out_b_bits_user(axi4index_auto_out_b_bits_user),
.auto_out_ar_ready(axi4index_auto_out_ar_ready),
.auto_out_ar_valid(axi4index_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4index_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4index_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4index_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4index_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4index_auto_out_ar_bits_burst),
.auto_out_ar_bits_user(axi4index_auto_out_ar_bits_user),
.auto_out_r_ready(axi4index_auto_out_r_ready),
.auto_out_r_valid(axi4index_auto_out_r_valid),
.auto_out_r_bits_id(axi4index_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4index_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4index_auto_out_r_bits_resp),
.auto_out_r_bits_user(axi4index_auto_out_r_bits_user),
.auto_out_r_bits_last(axi4index_auto_out_r_bits_last)
);
assign auto_axi4index_in_aw_ready = axi4index_auto_in_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_w_ready = axi4index_auto_in_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_b_valid = axi4index_auto_in_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_b_bits_id = axi4index_auto_in_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_b_bits_resp = axi4index_auto_in_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_ar_ready = axi4index_auto_in_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_r_valid = axi4index_auto_in_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_r_bits_id = axi4index_auto_in_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_r_bits_data = axi4index_auto_in_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_r_bits_resp = axi4index_auto_in_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_axi4index_in_r_bits_last = axi4index_auto_in_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign auto_buffer_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign auto_buffer_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32792.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32793.4]
assign buffer_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign buffer_auto_out_a_ready = auto_buffer_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_valid = auto_buffer_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@32836.4]
assign fixer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32798.4]
assign fixer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32799.4]
assign fixer_auto_in_a_valid = widget_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_opcode = widget_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_param = widget_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_size = widget_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_source = widget_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_address = widget_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_mask = widget_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_data = widget_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_a_bits_corrupt = widget_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_in_d_ready = widget_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign fixer_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign fixer_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32830.4]
assign widget_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32804.4]
assign widget_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32805.4]
assign widget_auto_in_a_valid = axi42tl_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_opcode = axi42tl_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_param = axi42tl_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_size = axi42tl_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_source = axi42tl_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_address = axi42tl_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_mask = axi42tl_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_data = axi42tl_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_a_bits_corrupt = axi42tl_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_in_d_ready = axi42tl_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign widget_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign widget_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32831.4]
assign axi42tl_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32810.4]
assign axi42tl_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32811.4]
assign axi42tl_auto_in_aw_valid = axi4yank_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_aw_bits_id = axi4yank_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_aw_bits_addr = axi4yank_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_aw_bits_len = axi4yank_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_aw_bits_size = axi4yank_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_w_valid = axi4yank_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_w_bits_data = axi4yank_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_w_bits_strb = axi4yank_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_w_bits_last = axi4yank_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_b_ready = axi4yank_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_ar_valid = axi4yank_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_ar_bits_id = axi4yank_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_ar_bits_addr = axi4yank_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_ar_bits_len = axi4yank_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_ar_bits_size = axi4yank_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_in_r_ready = axi4yank_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi42tl_auto_out_a_ready = widget_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_valid = widget_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_bits_opcode = widget_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_bits_size = widget_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_bits_source = widget_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_bits_denied = widget_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_bits_data = widget_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi42tl_auto_out_d_bits_corrupt = widget_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32832.4]
assign axi4yank_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32816.4]
assign axi4yank_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32817.4]
assign axi4yank_auto_in_aw_valid = axi4frag_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_aw_bits_id = axi4frag_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_aw_bits_addr = axi4frag_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_aw_bits_len = axi4frag_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_aw_bits_size = axi4frag_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_aw_bits_user = axi4frag_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_w_valid = axi4frag_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_w_bits_data = axi4frag_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_w_bits_strb = axi4frag_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_w_bits_last = axi4frag_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_b_ready = axi4frag_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_ar_valid = axi4frag_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_ar_bits_id = axi4frag_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_ar_bits_addr = axi4frag_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_ar_bits_len = axi4frag_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_ar_bits_size = axi4frag_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_ar_bits_user = axi4frag_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_in_r_ready = axi4frag_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4yank_auto_out_aw_ready = axi42tl_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_w_ready = axi42tl_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_b_valid = axi42tl_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_b_bits_id = axi42tl_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_b_bits_resp = axi42tl_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_ar_ready = axi42tl_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_r_valid = axi42tl_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_r_bits_id = axi42tl_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_r_bits_data = axi42tl_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_r_bits_resp = axi42tl_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4yank_auto_out_r_bits_last = axi42tl_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32833.4]
assign axi4frag_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32822.4]
assign axi4frag_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@32823.4]
assign axi4frag_auto_in_aw_valid = axi4index_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_aw_bits_id = axi4index_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_aw_bits_addr = axi4index_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_aw_bits_len = axi4index_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_aw_bits_size = axi4index_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_aw_bits_burst = axi4index_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_aw_bits_user = axi4index_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_w_valid = axi4index_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_w_bits_data = axi4index_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_w_bits_strb = axi4index_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_w_bits_last = axi4index_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_b_ready = axi4index_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_valid = axi4index_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_bits_id = axi4index_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_bits_addr = axi4index_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_bits_len = axi4index_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_bits_size = axi4index_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_bits_burst = axi4index_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_ar_bits_user = axi4index_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_in_r_ready = axi4index_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4frag_auto_out_aw_ready = axi4yank_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_w_ready = axi4yank_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_b_valid = axi4yank_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_b_bits_id = axi4yank_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_b_bits_resp = axi4yank_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_b_bits_user = axi4yank_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_ar_ready = axi4yank_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_r_valid = axi4yank_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_r_bits_id = axi4yank_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_r_bits_data = axi4yank_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_r_bits_resp = axi4yank_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_r_bits_user = axi4yank_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4frag_auto_out_r_bits_last = axi4yank_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32834.4]
assign axi4index_auto_in_aw_valid = auto_axi4index_in_aw_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_aw_bits_id = auto_axi4index_in_aw_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_aw_bits_addr = auto_axi4index_in_aw_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_aw_bits_len = auto_axi4index_in_aw_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_aw_bits_size = auto_axi4index_in_aw_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_aw_bits_burst = auto_axi4index_in_aw_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_w_valid = auto_axi4index_in_w_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_w_bits_data = auto_axi4index_in_w_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_w_bits_strb = auto_axi4index_in_w_bits_strb; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_w_bits_last = auto_axi4index_in_w_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_b_ready = auto_axi4index_in_b_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_ar_valid = auto_axi4index_in_ar_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_ar_bits_id = auto_axi4index_in_ar_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_ar_bits_addr = auto_axi4index_in_ar_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_ar_bits_len = auto_axi4index_in_ar_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_ar_bits_size = auto_axi4index_in_ar_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_ar_bits_burst = auto_axi4index_in_ar_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_in_r_ready = auto_axi4index_in_r_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@32837.4]
assign axi4index_auto_out_aw_ready = axi4frag_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_w_ready = axi4frag_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_b_valid = axi4frag_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_b_bits_id = axi4frag_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_b_bits_resp = axi4frag_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_b_bits_user = axi4frag_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_ar_ready = axi4frag_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_r_valid = axi4frag_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_r_bits_id = axi4frag_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_r_bits_data = axi4frag_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_r_bits_resp = axi4frag_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_r_bits_user = axi4frag_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
assign axi4index_auto_out_r_bits_last = axi4frag_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@32835.4]
endmodule
module TLMonitor_13( // @[:freechips.rocketchip.system.LowRiscConfig.fir@32846.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32847.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32848.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [3:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [3:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input [1:0] io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@32849.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@34396.4]
wire _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@32866.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@32867.6]
wire _T_44; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@32884.6]
wire [26:0] _T_46; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@32886.6]
wire [11:0] _T_47; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@32887.6]
wire [11:0] _T_48; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@32888.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@32889.6]
wire [31:0] _T_49; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@32889.6]
wire _T_50; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@32890.6]
wire [1:0] _T_52; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@32892.6]
wire [3:0] _T_53; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32893.6]
wire [2:0] _T_54; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@32894.6]
wire [2:0] _T_55; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@32895.6]
wire _T_56; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@32896.6]
wire _T_57; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@32897.6]
wire _T_58; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@32898.6]
wire _T_59; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@32899.6]
wire _T_61; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32901.6]
wire _T_62; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32902.6]
wire _T_64; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32904.6]
wire _T_65; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32905.6]
wire _T_66; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@32906.6]
wire _T_67; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@32907.6]
wire _T_68; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@32908.6]
wire _T_69; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32909.6]
wire _T_70; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32910.6]
wire _T_71; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32911.6]
wire _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32912.6]
wire _T_73; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32913.6]
wire _T_74; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32914.6]
wire _T_75; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32915.6]
wire _T_76; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32916.6]
wire _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32917.6]
wire _T_78; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32918.6]
wire _T_79; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32919.6]
wire _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32920.6]
wire _T_81; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@32921.6]
wire _T_82; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@32922.6]
wire _T_83; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@32923.6]
wire _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32924.6]
wire _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32925.6]
wire _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32926.6]
wire _T_87; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32927.6]
wire _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32928.6]
wire _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32929.6]
wire _T_90; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32930.6]
wire _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32931.6]
wire _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32932.6]
wire _T_93; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32933.6]
wire _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32934.6]
wire _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32935.6]
wire _T_96; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32936.6]
wire _T_97; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32937.6]
wire _T_98; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32938.6]
wire _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32939.6]
wire _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32940.6]
wire _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32941.6]
wire _T_102; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32942.6]
wire _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32943.6]
wire _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32944.6]
wire _T_105; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32945.6]
wire _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32946.6]
wire _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32947.6]
wire [7:0] _T_114; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32954.6]
wire [32:0] _T_125; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32965.6]
wire _T_149; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@32993.6]
wire [31:0] _T_151; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32996.8]
wire [32:0] _T_152; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32997.8]
wire [32:0] _T_153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32998.8]
wire [32:0] _T_154; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32999.8]
wire _T_155; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33000.8]
wire [31:0] _T_156; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33001.8]
wire [32:0] _T_157; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33002.8]
wire [32:0] _T_158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33003.8]
wire [32:0] _T_159; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33004.8]
wire _T_160; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33005.8]
wire [31:0] _T_161; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33006.8]
wire [32:0] _T_162; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33007.8]
wire [32:0] _T_163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33008.8]
wire [32:0] _T_164; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33009.8]
wire _T_165; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33010.8]
wire [31:0] _T_166; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33011.8]
wire [32:0] _T_167; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33012.8]
wire [32:0] _T_168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33013.8]
wire [32:0] _T_169; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33014.8]
wire _T_170; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33015.8]
wire [32:0] _T_173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33018.8]
wire [32:0] _T_174; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33019.8]
wire _T_175; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33020.8]
wire [31:0] _T_176; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33021.8]
wire [32:0] _T_177; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33022.8]
wire [32:0] _T_178; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33023.8]
wire [32:0] _T_179; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33024.8]
wire _T_180; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33025.8]
wire _T_188; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33033.8]
wire [31:0] _T_191; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33036.8]
wire [32:0] _T_192; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33037.8]
wire [32:0] _T_193; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33038.8]
wire [32:0] _T_194; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33039.8]
wire _T_195; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33040.8]
wire _T_196; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33041.8]
wire _T_200; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33045.8]
wire _T_201; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33046.8]
wire _T_204; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@33053.8]
wire _T_206; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@33059.8]
wire _T_207; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@33060.8]
wire _T_210; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@33067.8]
wire _T_211; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@33068.8]
wire _T_213; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@33074.8]
wire _T_214; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@33075.8]
wire _T_215; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@33080.8]
wire _T_217; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@33082.8]
wire _T_218; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@33083.8]
wire [7:0] _T_219; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@33088.8]
wire _T_220; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@33089.8]
wire _T_222; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@33091.8]
wire _T_223; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@33092.8]
wire _T_224; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@33097.8]
wire _T_226; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@33099.8]
wire _T_227; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@33100.8]
wire _T_228; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@33106.6]
wire _T_298; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@33201.8]
wire _T_300; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@33203.8]
wire _T_301; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@33204.8]
wire _T_311; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@33227.6]
wire _T_346; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33263.8]
wire _T_347; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33264.8]
wire _T_348; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33265.8]
wire _T_349; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33266.8]
wire _T_350; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33267.8]
wire _T_351; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33268.8]
wire _T_353; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33270.8]
wire _T_361; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33278.8]
wire _T_363; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@33280.8]
wire _T_365; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33282.8]
wire _T_366; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33283.8]
wire _T_373; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@33302.8]
wire _T_375; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@33304.8]
wire _T_376; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@33305.8]
wire _T_377; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@33310.8]
wire _T_379; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@33312.8]
wire _T_380; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@33313.8]
wire _T_385; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@33327.6]
wire _T_417; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33360.8]
wire _T_418; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33361.8]
wire _T_419; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33362.8]
wire _T_420; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33363.8]
wire _T_422; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33365.8]
wire _T_430; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33373.8]
wire _T_443; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@33386.8]
wire _T_444; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@33387.8]
wire _T_446; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33389.8]
wire _T_447; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33390.8]
wire _T_462; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@33426.6]
wire [7:0] _T_535; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@33516.8]
wire [7:0] _T_536; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@33517.8]
wire _T_537; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@33518.8]
wire _T_539; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@33520.8]
wire _T_540; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@33521.8]
wire _T_541; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@33527.6]
wire _T_562; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33549.8]
wire _T_585; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33572.8]
wire _T_586; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33573.8]
wire _T_587; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33574.8]
wire _T_588; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33575.8]
wire _T_592; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33579.8]
wire _T_593; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33580.8]
wire _T_600; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@33599.8]
wire _T_602; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@33601.8]
wire _T_603; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@33602.8]
wire _T_608; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@33616.6]
wire _T_667; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@33688.8]
wire _T_669; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@33690.8]
wire _T_670; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@33691.8]
wire _T_675; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@33705.6]
wire _T_726; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33757.8]
wire _T_727; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33758.8]
wire _T_742; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@33796.6]
wire _T_744; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@33798.6]
wire _T_745; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@33799.6]
wire _T_748; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@33806.6]
wire _T_749; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@33807.6]
wire _T_770; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@33824.6]
wire _T_772; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@33826.6]
wire _T_774; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33829.8]
wire _T_775; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33830.8]
wire _T_776; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@33835.8]
wire _T_778; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@33837.8]
wire _T_779; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@33838.8]
wire _T_780; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@33843.8]
wire _T_782; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@33845.8]
wire _T_783; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@33846.8]
wire _T_784; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@33851.8]
wire _T_786; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@33853.8]
wire _T_787; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@33854.8]
wire _T_788; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@33859.8]
wire _T_790; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@33861.8]
wire _T_791; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@33862.8]
wire _T_792; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@33868.6]
wire _T_803; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@33892.8]
wire _T_805; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@33894.8]
wire _T_806; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@33895.8]
wire _T_807; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@33900.8]
wire _T_809; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@33902.8]
wire _T_810; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@33903.8]
wire _T_820; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@33926.6]
wire _T_840; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@33967.8]
wire _T_842; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@33969.8]
wire _T_843; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@33970.8]
wire _T_849; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@33985.6]
wire _T_866; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@34020.6]
wire _T_884; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@34056.6]
wire _T_913; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@34116.4]
wire [8:0] _T_918; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@34121.4]
wire _T_919; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@34122.4]
wire _T_920; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@34123.4]
reg [8:0] _T_923; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@34125.4]
reg [31:0] _RAND_0;
wire [9:0] _T_924; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34126.4]
wire [9:0] _T_925; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34127.4]
wire [8:0] _T_926; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34128.4]
wire _T_927; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34129.4]
reg [2:0] _T_936; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@34140.4]
reg [31:0] _RAND_1;
reg [2:0] _T_938; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@34141.4]
reg [31:0] _RAND_2;
reg [3:0] _T_940; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@34142.4]
reg [31:0] _RAND_3;
reg [3:0] _T_942; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@34143.4]
reg [31:0] _RAND_4;
reg [31:0] _T_944; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@34144.4]
reg [31:0] _RAND_5;
wire _T_945; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@34145.4]
wire _T_946; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@34146.4]
wire _T_947; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@34148.6]
wire _T_949; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@34150.6]
wire _T_950; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@34151.6]
wire _T_951; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@34156.6]
wire _T_953; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@34158.6]
wire _T_954; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@34159.6]
wire _T_955; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@34164.6]
wire _T_957; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@34166.6]
wire _T_958; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@34167.6]
wire _T_959; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@34172.6]
wire _T_961; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@34174.6]
wire _T_962; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@34175.6]
wire _T_963; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@34180.6]
wire _T_965; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@34182.6]
wire _T_966; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@34183.6]
wire _T_968; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@34190.4]
wire _T_969; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@34198.4]
wire [26:0] _T_971; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@34200.4]
wire [11:0] _T_972; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@34201.4]
wire [11:0] _T_973; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@34202.4]
wire [8:0] _T_974; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@34203.4]
wire _T_975; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@34204.4]
reg [8:0] _T_978; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@34206.4]
reg [31:0] _RAND_6;
wire [9:0] _T_979; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34207.4]
wire [9:0] _T_980; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34208.4]
wire [8:0] _T_981; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34209.4]
wire _T_982; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34210.4]
reg [2:0] _T_991; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@34221.4]
reg [31:0] _RAND_7;
reg [1:0] _T_993; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@34222.4]
reg [31:0] _RAND_8;
reg [3:0] _T_995; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@34223.4]
reg [31:0] _RAND_9;
reg [3:0] _T_997; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@34224.4]
reg [31:0] _RAND_10;
reg [1:0] _T_999; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@34225.4]
reg [31:0] _RAND_11;
reg _T_1001; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@34226.4]
reg [31:0] _RAND_12;
wire _T_1002; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@34227.4]
wire _T_1003; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@34228.4]
wire _T_1004; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@34230.6]
wire _T_1006; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@34232.6]
wire _T_1007; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@34233.6]
wire _T_1008; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@34238.6]
wire _T_1010; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@34240.6]
wire _T_1011; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@34241.6]
wire _T_1012; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@34246.6]
wire _T_1014; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@34248.6]
wire _T_1015; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@34249.6]
wire _T_1016; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@34254.6]
wire _T_1018; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@34256.6]
wire _T_1019; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@34257.6]
wire _T_1020; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@34262.6]
wire _T_1022; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@34264.6]
wire _T_1023; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@34265.6]
wire _T_1024; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@34270.6]
wire _T_1026; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@34272.6]
wire _T_1027; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@34273.6]
wire _T_1029; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@34280.4]
reg [15:0] _T_1031; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@34289.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1042; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@34299.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1043; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34300.4]
wire [9:0] _T_1044; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34301.4]
wire [8:0] _T_1045; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34302.4]
wire _T_1046; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34303.4]
reg [8:0] _T_1063; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@34322.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1064; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34323.4]
wire [9:0] _T_1065; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34324.4]
wire [8:0] _T_1066; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34325.4]
wire _T_1067; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34326.4]
wire _T_1078; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@34341.4]
wire [15:0] _T_1080; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@34344.6]
wire [15:0] _T_1081; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@34346.6]
wire _T_1082; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@34347.6]
wire _T_1083; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@34348.6]
wire _T_1085; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@34350.6]
wire _T_1086; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@34351.6]
wire [15:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@34343.4]
wire _T_1091; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@34362.4]
wire _T_1093; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@34364.4]
wire _T_1094; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@34365.4]
wire [15:0] _T_1095; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@34367.6]
wire [15:0] _T_1096; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@34369.6]
wire [15:0] _T_1097; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@34370.6]
wire _T_1098; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@34371.6]
wire _T_1100; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@34373.6]
wire _T_1101; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@34374.6]
wire [15:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@34366.4]
wire _T_1102; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@34380.4]
wire _T_1103; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@34381.4]
wire _T_1104; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@34382.4]
wire _T_1105; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@34383.4]
wire _T_1107; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@34385.4]
wire _T_1108; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@34386.4]
wire [15:0] _T_1109; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@34391.4]
wire [15:0] _T_1110; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@34392.4]
wire [15:0] _T_1111; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@34393.4]
reg [31:0] _T_1113; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@34395.4]
reg [31:0] _RAND_16;
wire _T_1114; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@34398.4]
wire _T_1115; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@34399.4]
wire _T_1116; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@34400.4]
wire _T_1117; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@34401.4]
wire _T_1118; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@34402.4]
wire _T_1119; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@34403.4]
wire _T_1121; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@34405.4]
wire _T_1122; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@34406.4]
wire [31:0] _T_1124; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@34412.4]
wire _T_1127; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@34416.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33048.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@33161.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33285.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33392.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@33491.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33582.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@33671.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33760.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33832.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@33874.10]
wire _GEN_135; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@33932.10]
wire _GEN_145; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@33991.10]
wire _GEN_151; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@34026.10]
wire _GEN_157; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@34062.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@34396.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@32866.6]
assign _T_23 = _T_22 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@32867.6]
assign _T_44 = _T_23 | _T_22; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@32884.6]
assign _T_46 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@32886.6]
assign _T_47 = _T_46[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@32887.6]
assign _T_48 = ~ _T_47; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@32888.6]
assign _GEN_18 = {{20'd0}, _T_48}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@32889.6]
assign _T_49 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@32889.6]
assign _T_50 = _T_49 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@32890.6]
assign _T_52 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@32892.6]
assign _T_53 = 4'h1 << _T_52; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@32893.6]
assign _T_54 = _T_53[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@32894.6]
assign _T_55 = _T_54 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@32895.6]
assign _T_56 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@32896.6]
assign _T_57 = _T_55[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@32897.6]
assign _T_58 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@32898.6]
assign _T_59 = _T_58 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@32899.6]
assign _T_61 = _T_57 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32901.6]
assign _T_62 = _T_56 | _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32902.6]
assign _T_64 = _T_57 & _T_58; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32904.6]
assign _T_65 = _T_56 | _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32905.6]
assign _T_66 = _T_55[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@32906.6]
assign _T_67 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@32907.6]
assign _T_68 = _T_67 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@32908.6]
assign _T_69 = _T_59 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32909.6]
assign _T_70 = _T_66 & _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32910.6]
assign _T_71 = _T_62 | _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32911.6]
assign _T_72 = _T_59 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32912.6]
assign _T_73 = _T_66 & _T_72; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32913.6]
assign _T_74 = _T_62 | _T_73; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32914.6]
assign _T_75 = _T_58 & _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32915.6]
assign _T_76 = _T_66 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32916.6]
assign _T_77 = _T_65 | _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32917.6]
assign _T_78 = _T_58 & _T_67; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32918.6]
assign _T_79 = _T_66 & _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32919.6]
assign _T_80 = _T_65 | _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32920.6]
assign _T_81 = _T_55[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@32921.6]
assign _T_82 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@32922.6]
assign _T_83 = _T_82 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@32923.6]
assign _T_84 = _T_69 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32924.6]
assign _T_85 = _T_81 & _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32925.6]
assign _T_86 = _T_71 | _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32926.6]
assign _T_87 = _T_69 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32927.6]
assign _T_88 = _T_81 & _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32928.6]
assign _T_89 = _T_71 | _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32929.6]
assign _T_90 = _T_72 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32930.6]
assign _T_91 = _T_81 & _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32931.6]
assign _T_92 = _T_74 | _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32932.6]
assign _T_93 = _T_72 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32933.6]
assign _T_94 = _T_81 & _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32934.6]
assign _T_95 = _T_74 | _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32935.6]
assign _T_96 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32936.6]
assign _T_97 = _T_81 & _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32937.6]
assign _T_98 = _T_77 | _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32938.6]
assign _T_99 = _T_75 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32939.6]
assign _T_100 = _T_81 & _T_99; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32940.6]
assign _T_101 = _T_77 | _T_100; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32941.6]
assign _T_102 = _T_78 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32942.6]
assign _T_103 = _T_81 & _T_102; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32943.6]
assign _T_104 = _T_80 | _T_103; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32944.6]
assign _T_105 = _T_78 & _T_82; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@32945.6]
assign _T_106 = _T_81 & _T_105; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@32946.6]
assign _T_107 = _T_80 | _T_106; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@32947.6]
assign _T_114 = {_T_107,_T_104,_T_101,_T_98,_T_95,_T_92,_T_89,_T_86}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@32954.6]
assign _T_125 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32965.6]
assign _T_149 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@32993.6]
assign _T_151 = io_in_a_bits_address ^ 32'h40000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@32996.8]
assign _T_152 = {1'b0,$signed(_T_151)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@32997.8]
assign _T_153 = $signed(_T_152) & $signed(-33'sh100000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32998.8]
assign _T_154 = $signed(_T_153); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@32999.8]
assign _T_155 = $signed(_T_154) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33000.8]
assign _T_156 = io_in_a_bits_address ^ 32'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33001.8]
assign _T_157 = {1'b0,$signed(_T_156)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33002.8]
assign _T_158 = $signed(_T_157) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33003.8]
assign _T_159 = $signed(_T_158); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33004.8]
assign _T_160 = $signed(_T_159) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33005.8]
assign _T_161 = io_in_a_bits_address ^ 32'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33006.8]
assign _T_162 = {1'b0,$signed(_T_161)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33007.8]
assign _T_163 = $signed(_T_162) & $signed(-33'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33008.8]
assign _T_164 = $signed(_T_163); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33009.8]
assign _T_165 = $signed(_T_164) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33010.8]
assign _T_166 = io_in_a_bits_address ^ 32'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33011.8]
assign _T_167 = {1'b0,$signed(_T_166)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33012.8]
assign _T_168 = $signed(_T_167) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33013.8]
assign _T_169 = $signed(_T_168); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33014.8]
assign _T_170 = $signed(_T_169) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33015.8]
assign _T_173 = $signed(_T_125) & $signed(-33'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33018.8]
assign _T_174 = $signed(_T_173); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33019.8]
assign _T_175 = $signed(_T_174) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33020.8]
assign _T_176 = io_in_a_bits_address ^ 32'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33021.8]
assign _T_177 = {1'b0,$signed(_T_176)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33022.8]
assign _T_178 = $signed(_T_177) & $signed(-33'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33023.8]
assign _T_179 = $signed(_T_178); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33024.8]
assign _T_180 = $signed(_T_179) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33025.8]
assign _T_188 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33033.8]
assign _T_191 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@33036.8]
assign _T_192 = {1'b0,$signed(_T_191)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@33037.8]
assign _T_193 = $signed(_T_192) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33038.8]
assign _T_194 = $signed(_T_193); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@33039.8]
assign _T_195 = $signed(_T_194) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@33040.8]
assign _T_196 = _T_188 & _T_195; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33041.8]
assign _T_200 = _T_196 | reset; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33045.8]
assign _T_201 = _T_200 == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33046.8]
assign _T_204 = reset == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@33053.8]
assign _T_206 = _T_44 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@33059.8]
assign _T_207 = _T_206 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@33060.8]
assign _T_210 = _T_56 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@33067.8]
assign _T_211 = _T_210 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@33068.8]
assign _T_213 = _T_50 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@33074.8]
assign _T_214 = _T_213 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@33075.8]
assign _T_215 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@33080.8]
assign _T_217 = _T_215 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@33082.8]
assign _T_218 = _T_217 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@33083.8]
assign _T_219 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@33088.8]
assign _T_220 = _T_219 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@33089.8]
assign _T_222 = _T_220 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@33091.8]
assign _T_223 = _T_222 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@33092.8]
assign _T_224 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@33097.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@33099.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@33100.8]
assign _T_228 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@33106.6]
assign _T_298 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@33201.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@33203.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@33204.8]
assign _T_311 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@33227.6]
assign _T_346 = _T_155 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33263.8]
assign _T_347 = _T_346 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33264.8]
assign _T_348 = _T_347 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33265.8]
assign _T_349 = _T_348 | _T_180; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33266.8]
assign _T_350 = _T_349 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33267.8]
assign _T_351 = _T_188 & _T_350; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33268.8]
assign _T_353 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33270.8]
assign _T_361 = _T_353 & _T_160; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33278.8]
assign _T_363 = _T_351 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@33280.8]
assign _T_365 = _T_363 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33282.8]
assign _T_366 = _T_365 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33283.8]
assign _T_373 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@33302.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@33304.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@33305.8]
assign _T_377 = io_in_a_bits_mask == _T_114; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@33310.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@33312.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@33313.8]
assign _T_385 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@33327.6]
assign _T_417 = _T_165 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33360.8]
assign _T_418 = _T_417 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33361.8]
assign _T_419 = _T_418 | _T_195; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33362.8]
assign _T_420 = _T_188 & _T_419; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33363.8]
assign _T_422 = io_in_a_bits_size <= 4'h8; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33365.8]
assign _T_430 = _T_422 & _T_155; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33373.8]
assign _T_443 = _T_420 | _T_430; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@33386.8]
assign _T_444 = _T_443 | _T_361; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@33387.8]
assign _T_446 = _T_444 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33389.8]
assign _T_447 = _T_446 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33390.8]
assign _T_462 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@33426.6]
assign _T_535 = ~ _T_114; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@33516.8]
assign _T_536 = io_in_a_bits_mask & _T_535; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@33517.8]
assign _T_537 = _T_536 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@33518.8]
assign _T_539 = _T_537 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@33520.8]
assign _T_540 = _T_539 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@33521.8]
assign _T_541 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@33527.6]
assign _T_562 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@33549.8]
assign _T_585 = _T_160 | _T_165; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33572.8]
assign _T_586 = _T_585 | _T_170; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33573.8]
assign _T_587 = _T_586 | _T_175; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@33574.8]
assign _T_588 = _T_562 & _T_587; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@33575.8]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33579.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33580.8]
assign _T_600 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@33599.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@33601.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@33602.8]
assign _T_608 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@33616.6]
assign _T_667 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@33688.8]
assign _T_669 = _T_667 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@33690.8]
assign _T_670 = _T_669 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@33691.8]
assign _T_675 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@33705.6]
assign _T_726 = _T_361 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33757.8]
assign _T_727 = _T_726 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33758.8]
assign _T_742 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@33796.6]
assign _T_744 = _T_742 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@33798.6]
assign _T_745 = _T_744 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@33799.6]
assign _T_748 = io_in_d_bits_source[3:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@33806.6]
assign _T_749 = _T_748 == 1'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@33807.6]
assign _T_770 = _T_749 | _T_748; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@33824.6]
assign _T_772 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@33826.6]
assign _T_774 = _T_770 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33829.8]
assign _T_775 = _T_774 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33830.8]
assign _T_776 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@33835.8]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@33837.8]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@33838.8]
assign _T_780 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@33843.8]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@33845.8]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@33846.8]
assign _T_784 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@33851.8]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@33853.8]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@33854.8]
assign _T_788 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@33859.8]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@33861.8]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@33862.8]
assign _T_792 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@33868.6]
assign _T_803 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@33892.8]
assign _T_805 = _T_803 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@33894.8]
assign _T_806 = _T_805 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@33895.8]
assign _T_807 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@33900.8]
assign _T_809 = _T_807 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@33902.8]
assign _T_810 = _T_809 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@33903.8]
assign _T_820 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@33926.6]
assign _T_840 = _T_788 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@33967.8]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@33969.8]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@33970.8]
assign _T_849 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@33985.6]
assign _T_866 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@34020.6]
assign _T_884 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@34056.6]
assign _T_913 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@34116.4]
assign _T_918 = _T_48[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@34121.4]
assign _T_919 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@34122.4]
assign _T_920 = _T_919 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@34123.4]
assign _T_924 = _T_923 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34126.4]
assign _T_925 = $unsigned(_T_924); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34127.4]
assign _T_926 = _T_925[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34128.4]
assign _T_927 = _T_923 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34129.4]
assign _T_945 = _T_927 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@34145.4]
assign _T_946 = io_in_a_valid & _T_945; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@34146.4]
assign _T_947 = io_in_a_bits_opcode == _T_936; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@34148.6]
assign _T_949 = _T_947 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@34150.6]
assign _T_950 = _T_949 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@34151.6]
assign _T_951 = io_in_a_bits_param == _T_938; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@34156.6]
assign _T_953 = _T_951 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@34158.6]
assign _T_954 = _T_953 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@34159.6]
assign _T_955 = io_in_a_bits_size == _T_940; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@34164.6]
assign _T_957 = _T_955 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@34166.6]
assign _T_958 = _T_957 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@34167.6]
assign _T_959 = io_in_a_bits_source == _T_942; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@34172.6]
assign _T_961 = _T_959 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@34174.6]
assign _T_962 = _T_961 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@34175.6]
assign _T_963 = io_in_a_bits_address == _T_944; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@34180.6]
assign _T_965 = _T_963 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@34182.6]
assign _T_966 = _T_965 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@34183.6]
assign _T_968 = _T_913 & _T_927; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@34190.4]
assign _T_969 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@34198.4]
assign _T_971 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@34200.4]
assign _T_972 = _T_971[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@34201.4]
assign _T_973 = ~ _T_972; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@34202.4]
assign _T_974 = _T_973[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@34203.4]
assign _T_975 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@34204.4]
assign _T_979 = _T_978 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34207.4]
assign _T_980 = $unsigned(_T_979); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34208.4]
assign _T_981 = _T_980[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34209.4]
assign _T_982 = _T_978 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34210.4]
assign _T_1002 = _T_982 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@34227.4]
assign _T_1003 = io_in_d_valid & _T_1002; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@34228.4]
assign _T_1004 = io_in_d_bits_opcode == _T_991; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@34230.6]
assign _T_1006 = _T_1004 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@34232.6]
assign _T_1007 = _T_1006 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@34233.6]
assign _T_1008 = io_in_d_bits_param == _T_993; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@34238.6]
assign _T_1010 = _T_1008 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@34240.6]
assign _T_1011 = _T_1010 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@34241.6]
assign _T_1012 = io_in_d_bits_size == _T_995; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@34246.6]
assign _T_1014 = _T_1012 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@34248.6]
assign _T_1015 = _T_1014 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@34249.6]
assign _T_1016 = io_in_d_bits_source == _T_997; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@34254.6]
assign _T_1018 = _T_1016 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@34256.6]
assign _T_1019 = _T_1018 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@34257.6]
assign _T_1020 = io_in_d_bits_sink == _T_999; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@34262.6]
assign _T_1022 = _T_1020 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@34264.6]
assign _T_1023 = _T_1022 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@34265.6]
assign _T_1024 = io_in_d_bits_denied == _T_1001; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@34270.6]
assign _T_1026 = _T_1024 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@34272.6]
assign _T_1027 = _T_1026 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@34273.6]
assign _T_1029 = _T_969 & _T_982; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@34280.4]
assign _T_1043 = _T_1042 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34300.4]
assign _T_1044 = $unsigned(_T_1043); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34301.4]
assign _T_1045 = _T_1044[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34302.4]
assign _T_1046 = _T_1042 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34303.4]
assign _T_1064 = _T_1063 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34323.4]
assign _T_1065 = $unsigned(_T_1064); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34324.4]
assign _T_1066 = _T_1065[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@34325.4]
assign _T_1067 = _T_1063 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@34326.4]
assign _T_1078 = _T_913 & _T_1046; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@34341.4]
assign _T_1080 = 16'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@34344.6]
assign _T_1081 = _T_1031 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@34346.6]
assign _T_1082 = _T_1081[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@34347.6]
assign _T_1083 = _T_1082 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@34348.6]
assign _T_1085 = _T_1083 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@34350.6]
assign _T_1086 = _T_1085 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@34351.6]
assign _GEN_15 = _T_1078 ? _T_1080 : 16'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@34343.4]
assign _T_1091 = _T_969 & _T_1067; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@34362.4]
assign _T_1093 = _T_772 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@34364.4]
assign _T_1094 = _T_1091 & _T_1093; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@34365.4]
assign _T_1095 = 16'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@34367.6]
assign _T_1096 = _GEN_15 | _T_1031; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@34369.6]
assign _T_1097 = _T_1096 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@34370.6]
assign _T_1098 = _T_1097[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@34371.6]
assign _T_1100 = _T_1098 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@34373.6]
assign _T_1101 = _T_1100 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@34374.6]
assign _GEN_16 = _T_1094 ? _T_1095 : 16'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@34366.4]
assign _T_1102 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@34380.4]
assign _T_1103 = _GEN_15 != 16'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@34381.4]
assign _T_1104 = _T_1103 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@34382.4]
assign _T_1105 = _T_1102 | _T_1104; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@34383.4]
assign _T_1107 = _T_1105 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@34385.4]
assign _T_1108 = _T_1107 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@34386.4]
assign _T_1109 = _T_1031 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@34391.4]
assign _T_1110 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@34392.4]
assign _T_1111 = _T_1109 & _T_1110; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@34393.4]
assign _T_1114 = _T_1031 != 16'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@34398.4]
assign _T_1115 = _T_1114 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@34399.4]
assign _T_1116 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@34400.4]
assign _T_1117 = _T_1115 | _T_1116; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@34401.4]
assign _T_1118 = _T_1113 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@34402.4]
assign _T_1119 = _T_1117 | _T_1118; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@34403.4]
assign _T_1121 = _T_1119 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@34405.4]
assign _T_1122 = _T_1121 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@34406.4]
assign _T_1124 = _T_1113 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@34412.4]
assign _T_1127 = _T_913 | _T_969; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@34416.4]
assign _GEN_19 = io_in_a_valid & _T_149; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33048.10]
assign _GEN_35 = io_in_a_valid & _T_228; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@33161.10]
assign _GEN_53 = io_in_a_valid & _T_311; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33285.10]
assign _GEN_65 = io_in_a_valid & _T_385; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33392.10]
assign _GEN_75 = io_in_a_valid & _T_462; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@33491.10]
assign _GEN_85 = io_in_a_valid & _T_541; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33582.10]
assign _GEN_95 = io_in_a_valid & _T_608; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@33671.10]
assign _GEN_105 = io_in_a_valid & _T_675; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33760.10]
assign _GEN_115 = io_in_d_valid & _T_772; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33832.10]
assign _GEN_125 = io_in_d_valid & _T_792; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@33874.10]
assign _GEN_135 = io_in_d_valid & _T_820; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@33932.10]
assign _GEN_145 = io_in_d_valid & _T_849; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@33991.10]
assign _GEN_151 = io_in_d_valid & _T_866; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@34026.10]
assign _GEN_157 = io_in_d_valid & _T_884; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@34062.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_923 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_936 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_938 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_940 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_942 = _RAND_4[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_944 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_978 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_991 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_993 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_995 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_997 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_999 = _RAND_11[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1001 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1031 = _RAND_13[15:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1042 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1063 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1113 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_923 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_927) begin
if (_T_920) begin
_T_923 <= _T_918;
end else begin
_T_923 <= 9'h0;
end
end else begin
_T_923 <= _T_926;
end
end
end
if (_T_968) begin
_T_936 <= io_in_a_bits_opcode;
end
if (_T_968) begin
_T_938 <= io_in_a_bits_param;
end
if (_T_968) begin
_T_940 <= io_in_a_bits_size;
end
if (_T_968) begin
_T_942 <= io_in_a_bits_source;
end
if (_T_968) begin
_T_944 <= io_in_a_bits_address;
end
if (reset) begin
_T_978 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_982) begin
if (_T_975) begin
_T_978 <= _T_974;
end else begin
_T_978 <= 9'h0;
end
end else begin
_T_978 <= _T_981;
end
end
end
if (_T_1029) begin
_T_991 <= io_in_d_bits_opcode;
end
if (_T_1029) begin
_T_993 <= io_in_d_bits_param;
end
if (_T_1029) begin
_T_995 <= io_in_d_bits_size;
end
if (_T_1029) begin
_T_997 <= io_in_d_bits_source;
end
if (_T_1029) begin
_T_999 <= io_in_d_bits_sink;
end
if (_T_1029) begin
_T_1001 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1031 <= 16'h0;
end else begin
_T_1031 <= _T_1111;
end
if (reset) begin
_T_1042 <= 9'h0;
end else begin
if (_T_913) begin
if (_T_1046) begin
if (_T_920) begin
_T_1042 <= _T_918;
end else begin
_T_1042 <= 9'h0;
end
end else begin
_T_1042 <= _T_1045;
end
end
end
if (reset) begin
_T_1063 <= 9'h0;
end else begin
if (_T_969) begin
if (_T_1067) begin
if (_T_975) begin
_T_1063 <= _T_974;
end else begin
_T_1063 <= 9'h0;
end
end else begin
_T_1063 <= _T_1066;
end
end
end
if (reset) begin
_T_1113 <= 32'h0;
end else begin
if (_T_1127) begin
_T_1113 <= 32'h0;
end else begin
_T_1113 <= _T_1124;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@32861.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@32862.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@32990.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@32991.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33048.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_201) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@33049.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@33055.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_204) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@33056.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@33062.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_207) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@33063.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@33070.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_211) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@33071.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@33077.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_214) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@33078.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@33085.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_218) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@33086.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@33094.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_223) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@33095.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@33102.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_227) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@33103.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@33161.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_201) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@33162.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@33168.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_204) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@33169.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@33175.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_207) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@33176.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@33183.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_211) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@33184.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@33190.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_214) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@33191.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@33198.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_218) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@33199.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@33206.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@33207.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@33215.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_223) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@33216.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@33223.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_227) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@33224.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_366) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@33286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@33292.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_207) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@33293.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@33299.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_214) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@33300.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@33307.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_376) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@33308.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@33315.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_380) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@33316.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@33323.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@33324.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33392.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_447) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@33393.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@33399.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_207) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@33400.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@33406.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_214) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@33407.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@33414.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_376) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@33415.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@33422.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_380) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@33423.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@33491.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_447) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@33492.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@33498.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_207) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@33499.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@33505.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_214) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@33506.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@33513.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_376) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@33514.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@33523.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_540) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@33524.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33582.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_593) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@33583.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@33589.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_207) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@33590.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@33596.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_214) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@33597.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@33604.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_603) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@33605.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@33612.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_380) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@33613.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@33671.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_593) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@33672.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@33678.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_207) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@33679.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@33685.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_214) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@33686.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@33693.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_670) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@33694.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@33701.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_380) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@33702.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33760.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_727) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@33761.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@33767.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_207) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@33768.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@33774.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_214) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@33775.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@33782.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_380) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@33783.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@33790.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_227) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@33791.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@33801.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_745) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@33802.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33832.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_775) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@33833.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@33840.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_779) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@33841.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@33848.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_783) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@33849.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@33856.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_787) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@33857.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@33864.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_791) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@33865.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@33874.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_775) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@33875.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@33881.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@33882.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@33889.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_779) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@33890.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@33897.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_806) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@33898.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@33905.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_810) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@33906.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@33913.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_787) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@33914.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@33922.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@33923.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@33932.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_775) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@33933.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@33939.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@33940.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@33947.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_779) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@33948.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@33955.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_806) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@33956.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@33963.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_810) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@33964.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@33972.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_843) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@33973.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@33981.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@33982.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@33991.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_775) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@33992.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@33999.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_783) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@34000.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@34007.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_145 & _T_787) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@34008.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@34016.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@34017.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@34026.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_775) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@34027.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@34034.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_783) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@34035.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@34043.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_151 & _T_843) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@34044.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@34052.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@34053.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@34062.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_775) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@34063.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@34070.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_783) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@34071.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@34078.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_157 & _T_787) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@34079.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@34087.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@34088.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@34097.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@34098.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@34105.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@34106.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@34113.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@34114.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_950) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@34153.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_950) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@34154.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_954) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@34161.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_954) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@34162.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_958) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@34169.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_958) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@34170.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_962) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@34177.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_962) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@34178.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946 & _T_966) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@34185.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946 & _T_966) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@34186.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@34235.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1007) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@34236.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@34243.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1011) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@34244.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@34251.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1015) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@34252.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@34259.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1019) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@34260.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@34267.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1023) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@34268.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@34275.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1003 & _T_1027) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@34276.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@34353.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1078 & _T_1086) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@34354.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@34376.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1094 & _T_1101) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@34377.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@34388.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1108) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@34389.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1122) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:30:80)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@34408.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1122) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@34409.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLBuffer_5( // @[:freechips.rocketchip.system.LowRiscConfig.fir@34549.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34550.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34551.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [3:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [3:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [1:0] auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [3:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [3:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [1:0] auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@34552.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [3:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [3:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire [1:0] TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [3:0] Queue_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [31:0] Queue_io_enq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [7:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [3:0] Queue_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [31:0] Queue_io_deq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [7:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [3:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [1:0] Queue_1_io_enq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [63:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [3:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [1:0] Queue_1_io_deq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire [63:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
TLMonitor_13 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@34559.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_31 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34600.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_opcode(Queue_io_enq_bits_opcode),
.io_enq_bits_param(Queue_io_enq_bits_param),
.io_enq_bits_size(Queue_io_enq_bits_size),
.io_enq_bits_source(Queue_io_enq_bits_source),
.io_enq_bits_address(Queue_io_enq_bits_address),
.io_enq_bits_mask(Queue_io_enq_bits_mask),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_io_enq_bits_corrupt),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_opcode(Queue_io_deq_bits_opcode),
.io_deq_bits_param(Queue_io_deq_bits_param),
.io_deq_bits_size(Queue_io_deq_bits_size),
.io_deq_bits_source(Queue_io_deq_bits_source),
.io_deq_bits_address(Queue_io_deq_bits_address),
.io_deq_bits_mask(Queue_io_deq_bits_mask),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_io_deq_bits_corrupt)
);
Queue_32 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@34614.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_opcode(Queue_1_io_enq_bits_opcode),
.io_enq_bits_param(Queue_1_io_enq_bits_param),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_source(Queue_1_io_enq_bits_source),
.io_enq_bits_sink(Queue_1_io_enq_bits_sink),
.io_enq_bits_denied(Queue_1_io_enq_bits_denied),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_opcode(Queue_1_io_deq_bits_opcode),
.io_deq_bits_param(Queue_1_io_deq_bits_param),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_source(Queue_1_io_deq_bits_source),
.io_deq_bits_sink(Queue_1_io_deq_bits_sink),
.io_deq_bits_denied(Queue_1_io_deq_bits_denied),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt)
);
assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34599.4]
assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34598.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34561.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34562.4]
assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@34595.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34601.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34602.4]
assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@34603.4]
assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34611.4]
assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34610.4]
assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34609.4]
assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34608.4]
assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34607.4]
assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34606.4]
assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34605.4]
assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34604.4]
assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.LowRiscConfig.fir@34613.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34615.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34616.4]
assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@34617.4]
assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34625.4]
assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34624.4]
assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34623.4]
assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34622.4]
assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34621.4]
assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34620.4]
assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34619.4]
assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@34618.4]
assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.LowRiscConfig.fir@34627.4]
endmodule
module FrontBus( // @[:freechips.rocketchip.system.LowRiscConfig.fir@34635.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34636.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34637.4]
output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [31:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [2:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [63:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [31:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [2:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [7:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [63:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [1:0] auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_bus_xing_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_bus_xing_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [2:0] auto_bus_xing_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [2:0] auto_bus_xing_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [3:0] auto_bus_xing_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [3:0] auto_bus_xing_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [31:0] auto_bus_xing_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [7:0] auto_bus_xing_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output [63:0] auto_bus_xing_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_bus_xing_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
output auto_bus_xing_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_bus_xing_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [2:0] auto_bus_xing_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [1:0] auto_bus_xing_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [3:0] auto_bus_xing_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [3:0] auto_bus_xing_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [1:0] auto_bus_xing_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_bus_xing_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input [63:0] auto_bus_xing_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
input auto_bus_xing_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@34638.4]
);
wire front_bus_xbar_clock; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_reset; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [2:0] front_bus_xbar_auto_in_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [2:0] front_bus_xbar_auto_in_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_in_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_in_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [31:0] front_bus_xbar_auto_in_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [7:0] front_bus_xbar_auto_in_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [63:0] front_bus_xbar_auto_in_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [2:0] front_bus_xbar_auto_in_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [1:0] front_bus_xbar_auto_in_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_in_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_in_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [1:0] front_bus_xbar_auto_in_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [63:0] front_bus_xbar_auto_in_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_in_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_a_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_a_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [2:0] front_bus_xbar_auto_out_a_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [2:0] front_bus_xbar_auto_out_a_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_out_a_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_out_a_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [31:0] front_bus_xbar_auto_out_a_bits_address; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [7:0] front_bus_xbar_auto_out_a_bits_mask; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [63:0] front_bus_xbar_auto_out_a_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_a_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_d_ready; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_d_valid; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [2:0] front_bus_xbar_auto_out_d_bits_opcode; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [1:0] front_bus_xbar_auto_out_d_bits_param; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_out_d_bits_size; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [3:0] front_bus_xbar_auto_out_d_bits_source; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [1:0] front_bus_xbar_auto_out_d_bits_sink; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_d_bits_denied; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire [63:0] front_bus_xbar_auto_out_d_bits_data; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire front_bus_xbar_auto_out_d_bits_corrupt; // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
wire coupler_from_port_named_slave_port_axi4_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [31:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [2:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [63:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_strb; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [31:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [2:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [63:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [1:0] coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [2:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [2:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [31:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [7:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [63:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [2:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [1:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [3:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [1:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire [63:0] coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [1:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [3:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [1:0] buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
TLXbar_3 front_bus_xbar ( // @[BusWrapper.scala 179:32:freechips.rocketchip.system.LowRiscConfig.fir@34643.4]
.clock(front_bus_xbar_clock),
.reset(front_bus_xbar_reset),
.auto_in_a_ready(front_bus_xbar_auto_in_a_ready),
.auto_in_a_valid(front_bus_xbar_auto_in_a_valid),
.auto_in_a_bits_opcode(front_bus_xbar_auto_in_a_bits_opcode),
.auto_in_a_bits_param(front_bus_xbar_auto_in_a_bits_param),
.auto_in_a_bits_size(front_bus_xbar_auto_in_a_bits_size),
.auto_in_a_bits_source(front_bus_xbar_auto_in_a_bits_source),
.auto_in_a_bits_address(front_bus_xbar_auto_in_a_bits_address),
.auto_in_a_bits_mask(front_bus_xbar_auto_in_a_bits_mask),
.auto_in_a_bits_data(front_bus_xbar_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(front_bus_xbar_auto_in_a_bits_corrupt),
.auto_in_d_ready(front_bus_xbar_auto_in_d_ready),
.auto_in_d_valid(front_bus_xbar_auto_in_d_valid),
.auto_in_d_bits_opcode(front_bus_xbar_auto_in_d_bits_opcode),
.auto_in_d_bits_param(front_bus_xbar_auto_in_d_bits_param),
.auto_in_d_bits_size(front_bus_xbar_auto_in_d_bits_size),
.auto_in_d_bits_source(front_bus_xbar_auto_in_d_bits_source),
.auto_in_d_bits_sink(front_bus_xbar_auto_in_d_bits_sink),
.auto_in_d_bits_denied(front_bus_xbar_auto_in_d_bits_denied),
.auto_in_d_bits_data(front_bus_xbar_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(front_bus_xbar_auto_in_d_bits_corrupt),
.auto_out_a_ready(front_bus_xbar_auto_out_a_ready),
.auto_out_a_valid(front_bus_xbar_auto_out_a_valid),
.auto_out_a_bits_opcode(front_bus_xbar_auto_out_a_bits_opcode),
.auto_out_a_bits_param(front_bus_xbar_auto_out_a_bits_param),
.auto_out_a_bits_size(front_bus_xbar_auto_out_a_bits_size),
.auto_out_a_bits_source(front_bus_xbar_auto_out_a_bits_source),
.auto_out_a_bits_address(front_bus_xbar_auto_out_a_bits_address),
.auto_out_a_bits_mask(front_bus_xbar_auto_out_a_bits_mask),
.auto_out_a_bits_data(front_bus_xbar_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(front_bus_xbar_auto_out_a_bits_corrupt),
.auto_out_d_ready(front_bus_xbar_auto_out_d_ready),
.auto_out_d_valid(front_bus_xbar_auto_out_d_valid),
.auto_out_d_bits_opcode(front_bus_xbar_auto_out_d_bits_opcode),
.auto_out_d_bits_param(front_bus_xbar_auto_out_d_bits_param),
.auto_out_d_bits_size(front_bus_xbar_auto_out_d_bits_size),
.auto_out_d_bits_source(front_bus_xbar_auto_out_d_bits_source),
.auto_out_d_bits_sink(front_bus_xbar_auto_out_d_bits_sink),
.auto_out_d_bits_denied(front_bus_xbar_auto_out_d_bits_denied),
.auto_out_d_bits_data(front_bus_xbar_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(front_bus_xbar_auto_out_d_bits_corrupt)
);
SimpleLazyModule_5 coupler_from_port_named_slave_port_axi4 ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@34649.4]
.clock(coupler_from_port_named_slave_port_axi4_clock),
.reset(coupler_from_port_named_slave_port_axi4_reset),
.auto_axi4index_in_aw_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_ready),
.auto_axi4index_in_aw_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_valid),
.auto_axi4index_in_aw_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_id),
.auto_axi4index_in_aw_bits_addr(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_addr),
.auto_axi4index_in_aw_bits_len(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_len),
.auto_axi4index_in_aw_bits_size(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_size),
.auto_axi4index_in_aw_bits_burst(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_burst),
.auto_axi4index_in_w_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_ready),
.auto_axi4index_in_w_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_valid),
.auto_axi4index_in_w_bits_data(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_data),
.auto_axi4index_in_w_bits_strb(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_strb),
.auto_axi4index_in_w_bits_last(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_last),
.auto_axi4index_in_b_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_ready),
.auto_axi4index_in_b_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_valid),
.auto_axi4index_in_b_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_id),
.auto_axi4index_in_b_bits_resp(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_resp),
.auto_axi4index_in_ar_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_ready),
.auto_axi4index_in_ar_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_valid),
.auto_axi4index_in_ar_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_id),
.auto_axi4index_in_ar_bits_addr(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_addr),
.auto_axi4index_in_ar_bits_len(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_len),
.auto_axi4index_in_ar_bits_size(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_size),
.auto_axi4index_in_ar_bits_burst(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_burst),
.auto_axi4index_in_r_ready(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_ready),
.auto_axi4index_in_r_valid(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_valid),
.auto_axi4index_in_r_bits_id(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_id),
.auto_axi4index_in_r_bits_data(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_data),
.auto_axi4index_in_r_bits_resp(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_resp),
.auto_axi4index_in_r_bits_last(coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_last),
.auto_buffer_out_a_ready(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_ready),
.auto_buffer_out_a_valid(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_valid),
.auto_buffer_out_a_bits_opcode(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_opcode),
.auto_buffer_out_a_bits_param(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_param),
.auto_buffer_out_a_bits_size(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_size),
.auto_buffer_out_a_bits_source(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_source),
.auto_buffer_out_a_bits_address(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_address),
.auto_buffer_out_a_bits_mask(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_mask),
.auto_buffer_out_a_bits_data(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_data),
.auto_buffer_out_a_bits_corrupt(coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_corrupt),
.auto_buffer_out_d_ready(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_ready),
.auto_buffer_out_d_valid(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_valid),
.auto_buffer_out_d_bits_opcode(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_opcode),
.auto_buffer_out_d_bits_param(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_param),
.auto_buffer_out_d_bits_size(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_size),
.auto_buffer_out_d_bits_source(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_source),
.auto_buffer_out_d_bits_sink(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_sink),
.auto_buffer_out_d_bits_denied(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_denied),
.auto_buffer_out_d_bits_data(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_data),
.auto_buffer_out_d_bits_corrupt(coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_corrupt)
);
TLBuffer_5 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@34655.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(buffer_auto_in_d_bits_param),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(buffer_auto_out_d_bits_param),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
);
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_ready = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_ready = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_valid = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_id = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_bits_resp = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_ready = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_valid = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_id = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_data = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_resp = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_bits_last = coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign auto_bus_xing_out_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign auto_bus_xing_out_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@34669.4]
assign front_bus_xbar_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34647.4]
assign front_bus_xbar_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34648.4]
assign front_bus_xbar_auto_in_a_valid = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_opcode = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_param = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_size = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_source = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_address = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_mask = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_data = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_a_bits_corrupt = coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_in_d_ready = coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign front_bus_xbar_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign front_bus_xbar_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign coupler_from_port_named_slave_port_axi4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34653.4]
assign coupler_from_port_named_slave_port_axi4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34654.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_valid = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_id = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_addr = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_len = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_size = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_aw_bits_burst = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_aw_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_valid = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_data = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_strb = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_strb; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_w_bits_last = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_w_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_b_ready = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_b_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_valid = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_id = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_addr = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_addr; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_len = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_len; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_size = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_ar_bits_burst = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_ar_bits_burst; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_axi4index_in_r_ready = auto_coupler_from_port_named_slave_port_axi4_axi4index_in_r_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@34670.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_a_ready = front_bus_xbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_valid = front_bus_xbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_opcode = front_bus_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_param = front_bus_xbar_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_size = front_bus_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_source = front_bus_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_sink = front_bus_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_denied = front_bus_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_data = front_bus_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign coupler_from_port_named_slave_port_axi4_auto_buffer_out_d_bits_corrupt = front_bus_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34667.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34659.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@34660.4]
assign buffer_auto_in_a_valid = front_bus_xbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_opcode = front_bus_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_param = front_bus_xbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_size = front_bus_xbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_source = front_bus_xbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_address = front_bus_xbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_mask = front_bus_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_data = front_bus_xbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_a_bits_corrupt = front_bus_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_in_d_ready = front_bus_xbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@34666.4]
assign buffer_auto_out_a_ready = auto_bus_xing_out_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_valid = auto_bus_xing_out_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_opcode = auto_bus_xing_out_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_param = auto_bus_xing_out_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_size = auto_bus_xing_out_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_source = auto_bus_xing_out_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_sink = auto_bus_xing_out_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_denied = auto_bus_xing_out_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_data = auto_bus_xing_out_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
assign buffer_auto_out_d_bits_corrupt = auto_bus_xing_out_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@34668.4]
endmodule
module TLMonitor_14( // @[:freechips.rocketchip.system.LowRiscConfig.fir@34679.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34680.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34681.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [6:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input [6:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@34682.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@35851.4]
wire [12:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@34709.6]
wire [5:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@34710.6]
wire [5:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@34711.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@34712.6]
wire [31:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@34712.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@34713.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@34715.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@34716.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@34717.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@34718.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@34719.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@34720.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@34721.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@34722.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34724.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34725.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34727.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34728.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@34729.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@34730.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@34731.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34732.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34733.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34734.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34735.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34736.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34737.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34738.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34739.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34740.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34741.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34742.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34743.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@34744.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@34745.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@34746.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34747.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34748.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34749.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34750.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34751.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34752.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34753.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34754.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34755.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34756.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34757.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34758.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34759.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34760.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34761.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34762.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34763.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34764.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34765.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34766.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34767.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34768.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34769.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34770.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@34777.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@34800.6]
wire [31:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@34803.8]
wire [32:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@34804.8]
wire [32:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@34805.8]
wire [32:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@34806.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@34807.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@34812.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@34833.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@34834.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@34840.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@34841.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@34846.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@34848.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@34849.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@34854.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@34855.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@34857.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@34858.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@34863.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@34865.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@34866.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@34872.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@34926.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@34928.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@34929.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@34952.6]
wire _T_205; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@34955.8]
wire _T_213; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@34963.8]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34966.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34967.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@34986.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@34988.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@34989.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@34994.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@34996.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@34997.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@35011.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@35062.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@35104.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@35105.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@35106.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@35108.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@35109.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@35115.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@35146.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@35148.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@35149.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@35163.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@35194.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@35196.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@35197.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@35211.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@35261.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@35263.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@35264.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@35281.6]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@35290.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35292.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35293.8]
wire _T_406; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@35306.8]
wire _T_408; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@35308.8]
wire _T_409; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@35309.8]
wire _T_410; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@35314.8]
wire _T_412; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@35316.8]
wire _T_413; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@35317.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@35323.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@35381.6]
wire _T_462; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@35422.8]
wire _T_464; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@35424.8]
wire _T_465; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@35425.8]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@35440.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@35475.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@35511.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@35571.4]
wire [2:0] _T_540; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@35576.4]
wire _T_541; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@35577.4]
wire _T_542; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@35578.4]
reg [2:0] _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@35580.4]
reg [31:0] _RAND_0;
wire [3:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35581.4]
wire [3:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35582.4]
wire [2:0] _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35583.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35584.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@35595.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@35596.4]
reg [31:0] _RAND_2;
reg [2:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@35597.4]
reg [31:0] _RAND_3;
reg [6:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@35598.4]
reg [31:0] _RAND_4;
reg [31:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@35599.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@35600.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@35601.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@35603.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@35605.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@35606.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@35611.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@35613.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@35614.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@35619.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@35621.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@35622.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@35627.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@35629.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@35630.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@35635.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@35637.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@35638.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@35645.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@35653.4]
wire [12:0] _T_593; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@35655.4]
wire [5:0] _T_594; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@35656.4]
wire [5:0] _T_595; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@35657.4]
wire [2:0] _T_596; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@35658.4]
wire _T_597; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@35659.4]
reg [2:0] _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@35661.4]
reg [31:0] _RAND_6;
wire [3:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35662.4]
wire [3:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35663.4]
wire [2:0] _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35664.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35665.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@35676.4]
reg [31:0] _RAND_7;
reg [2:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@35678.4]
reg [31:0] _RAND_8;
reg [6:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@35679.4]
reg [31:0] _RAND_9;
reg _T_623; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@35681.4]
reg [31:0] _RAND_10;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@35682.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@35683.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@35685.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@35687.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@35688.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@35701.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@35703.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@35704.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@35709.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@35711.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@35712.6]
wire _T_646; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@35725.6]
wire _T_648; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@35727.6]
wire _T_649; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@35728.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@35735.4]
reg [127:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@35744.4]
reg [127:0] _RAND_11;
reg [2:0] _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@35754.4]
reg [31:0] _RAND_12;
wire [3:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35755.4]
wire [3:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35756.4]
wire [2:0] _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35757.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35758.4]
reg [2:0] _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@35777.4]
reg [31:0] _RAND_13;
wire [3:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35778.4]
wire [3:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35779.4]
wire [2:0] _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35780.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35781.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@35796.4]
wire [127:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@35799.6]
wire [127:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@35801.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@35802.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@35803.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@35805.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@35806.6]
wire [127:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@35798.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@35817.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@35819.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@35820.4]
wire [127:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@35822.6]
wire [127:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@35824.6]
wire [127:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@35825.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@35826.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@35828.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@35829.6]
wire [127:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@35821.4]
wire _T_724; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@35835.4]
wire _T_725; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@35836.4]
wire _T_726; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@35837.4]
wire _T_727; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@35838.4]
wire _T_729; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@35840.4]
wire _T_730; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@35841.4]
wire [127:0] _T_731; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@35846.4]
wire [127:0] _T_732; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@35847.4]
wire [127:0] _T_733; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@35848.4]
reg [31:0] _T_735; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@35850.4]
reg [31:0] _RAND_14;
wire _T_736; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@35853.4]
wire _T_737; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@35854.4]
wire _T_738; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@35855.4]
wire _T_739; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@35856.4]
wire _T_740; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@35857.4]
wire _T_741; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@35858.4]
wire _T_743; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@35860.4]
wire _T_744; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@35861.4]
wire [31:0] _T_746; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@35867.4]
wire _T_749; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@35871.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@34814.10]
wire _GEN_33; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@34886.10]
wire _GEN_49; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34969.10]
wire _GEN_59; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@35028.10]
wire _GEN_67; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@35079.10]
wire _GEN_75; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@35129.10]
wire _GEN_83; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@35177.10]
wire _GEN_91; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@35225.10]
wire _GEN_99; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35295.10]
wire _GEN_105; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@35336.10]
wire _GEN_111; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@35394.10]
wire _GEN_117; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@35462.10]
wire _GEN_119; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@35498.10]
wire _GEN_121; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@35533.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@35851.4]
.out(plusarg_reader_out)
);
assign _T_36 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@34709.6]
assign _T_37 = _T_36[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@34710.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@34711.6]
assign _GEN_18 = {{26'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@34712.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@34712.6]
assign _T_40 = _T_39 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@34713.6]
assign _T_42 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@34715.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@34716.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@34717.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@34718.6]
assign _T_46 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@34719.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@34720.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@34721.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@34722.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34724.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34725.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34727.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34728.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@34729.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@34730.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@34731.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34732.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34733.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34734.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34735.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34736.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34737.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34738.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34739.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34740.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34741.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34742.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34743.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@34744.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@34745.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@34746.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34747.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34748.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34749.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34750.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34751.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34752.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34753.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34754.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34755.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34756.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34757.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34758.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34759.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34760.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34761.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34762.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34763.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34764.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34765.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34766.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34767.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@34768.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@34769.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@34770.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@34777.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@34800.6]
assign _T_125 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@34803.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@34804.8]
assign _T_127 = $signed(_T_126) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@34805.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@34806.8]
assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@34807.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@34812.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@34833.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@34834.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@34840.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@34841.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@34846.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@34848.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@34849.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@34854.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@34855.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@34857.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@34858.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@34863.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@34865.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@34866.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@34872.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@34926.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@34928.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@34929.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@34952.6]
assign _T_205 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@34955.8]
assign _T_213 = _T_205 & _T_129; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@34963.8]
assign _T_216 = _T_213 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34966.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34967.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@34986.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@34988.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@34989.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@34994.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@34996.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@34997.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@35011.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@35062.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@35104.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@35105.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@35106.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@35108.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@35109.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@35115.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@35146.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@35148.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@35149.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@35163.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@35194.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@35196.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@35197.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@35211.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@35261.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@35263.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@35264.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@35281.6]
assign _T_398 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@35290.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35292.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35293.8]
assign _T_406 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@35306.8]
assign _T_408 = _T_406 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@35308.8]
assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@35309.8]
assign _T_410 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@35314.8]
assign _T_412 = _T_410 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@35316.8]
assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@35317.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@35323.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@35381.6]
assign _T_462 = _T_410 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@35422.8]
assign _T_464 = _T_462 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@35424.8]
assign _T_465 = _T_464 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@35425.8]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@35440.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@35475.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@35511.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@35571.4]
assign _T_540 = _T_38[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@35576.4]
assign _T_541 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@35577.4]
assign _T_542 = _T_541 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@35578.4]
assign _T_546 = _T_545 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35581.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35582.4]
assign _T_548 = _T_547[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35583.4]
assign _T_549 = _T_545 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35584.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@35600.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@35601.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@35603.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@35605.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@35606.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@35611.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@35613.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@35614.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@35619.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@35621.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@35622.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@35627.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@35629.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@35630.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@35635.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@35637.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@35638.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@35645.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@35653.4]
assign _T_593 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@35655.4]
assign _T_594 = _T_593[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@35656.4]
assign _T_595 = ~ _T_594; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@35657.4]
assign _T_596 = _T_595[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@35658.4]
assign _T_597 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@35659.4]
assign _T_601 = _T_600 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35662.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35663.4]
assign _T_603 = _T_602[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35664.4]
assign _T_604 = _T_600 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35665.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@35682.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@35683.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@35685.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@35687.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@35688.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@35701.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@35703.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@35704.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@35709.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@35711.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@35712.6]
assign _T_646 = io_in_d_bits_denied == _T_623; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@35725.6]
assign _T_648 = _T_646 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@35727.6]
assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@35728.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@35735.4]
assign _T_665 = _T_664 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35755.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35756.4]
assign _T_667 = _T_666[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35757.4]
assign _T_668 = _T_664 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35758.4]
assign _T_686 = _T_685 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35778.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35779.4]
assign _T_688 = _T_687[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@35780.4]
assign _T_689 = _T_685 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@35781.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@35796.4]
assign _T_702 = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@35799.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@35801.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@35802.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@35803.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@35805.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@35806.6]
assign _GEN_15 = _T_700 ? _T_702 : 128'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@35798.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@35817.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@35819.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@35820.4]
assign _T_717 = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@35822.6]
assign _T_718 = _GEN_15 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@35824.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@35825.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@35826.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@35828.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@35829.6]
assign _GEN_16 = _T_716 ? _T_717 : 128'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@35821.4]
assign _T_724 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@35835.4]
assign _T_725 = _GEN_15 != 128'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@35836.4]
assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@35837.4]
assign _T_727 = _T_724 | _T_726; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@35838.4]
assign _T_729 = _T_727 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@35840.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@35841.4]
assign _T_731 = _T_653 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@35846.4]
assign _T_732 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@35847.4]
assign _T_733 = _T_731 & _T_732; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@35848.4]
assign _T_736 = _T_653 != 128'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@35853.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@35854.4]
assign _T_738 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@35855.4]
assign _T_739 = _T_737 | _T_738; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@35856.4]
assign _T_740 = _T_735 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@35857.4]
assign _T_741 = _T_739 | _T_740; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@35858.4]
assign _T_743 = _T_741 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@35860.4]
assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@35861.4]
assign _T_746 = _T_735 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@35867.4]
assign _T_749 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@35871.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@34814.10]
assign _GEN_33 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@34886.10]
assign _GEN_49 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34969.10]
assign _GEN_59 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@35028.10]
assign _GEN_67 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@35079.10]
assign _GEN_75 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@35129.10]
assign _GEN_83 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@35177.10]
assign _GEN_91 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@35225.10]
assign _GEN_99 = io_in_d_valid & _T_394; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35295.10]
assign _GEN_105 = io_in_d_valid & _T_414; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@35336.10]
assign _GEN_111 = io_in_d_valid & _T_442; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@35394.10]
assign _GEN_117 = io_in_d_valid & _T_471; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@35462.10]
assign _GEN_119 = io_in_d_valid & _T_488; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@35498.10]
assign _GEN_121 = io_in_d_valid & _T_506; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@35533.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_623 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {4{`RANDOM}};
_T_653 = _RAND_11[127:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_664 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_685 = _RAND_13[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_735 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
if (_T_542) begin
_T_545 <= _T_540;
end else begin
_T_545 <= 3'h0;
end
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
if (_T_597) begin
_T_600 <= _T_596;
end else begin
_T_600 <= 3'h0;
end
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (_T_651) begin
_T_623 <= io_in_d_bits_denied;
end
if (reset) begin
_T_653 <= 128'h0;
end else begin
_T_653 <= _T_733;
end
if (reset) begin
_T_664 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
if (_T_542) begin
_T_664 <= _T_540;
end else begin
_T_664 <= 3'h0;
end
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
if (_T_597) begin
_T_685 <= _T_596;
end else begin
_T_685 <= 3'h0;
end
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_735 <= 32'h0;
end else begin
if (_T_749) begin
_T_735 <= 32'h0;
end else begin
_T_735 <= _T_746;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@34694.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@34695.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@34797.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@34798.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@34814.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@34815.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@34821.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@34822.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@34828.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@34829.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@34836.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@34837.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@34843.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@34844.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@34851.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@34852.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@34860.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@34861.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@34868.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@34869.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@34886.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@34887.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@34893.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@34894.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@34900.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@34901.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@34908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@34909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@34915.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@34916.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@34923.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@34924.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@34931.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@34932.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@34940.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@34941.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@34948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@34949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34969.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@34970.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@34976.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@34977.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@34983.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@34984.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@34991.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@34992.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@34999.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@35000.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@35007.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@35008.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@35028.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@35029.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@35035.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@35036.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@35042.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@35043.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@35050.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@35051.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@35058.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@35059.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@35079.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@35080.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@35086.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@35087.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@35093.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@35094.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@35101.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@35102.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@35111.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@35112.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@35129.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@35130.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@35136.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@35137.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@35143.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@35144.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@35151.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@35152.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@35159.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@35160.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@35177.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@35178.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@35184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@35185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@35191.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@35192.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@35199.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@35200.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@35207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@35208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@35225.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@35226.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@35232.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@35233.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@35239.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@35240.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@35247.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@35248.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@35255.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@35256.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@35266.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@35267.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@35287.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@35288.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35295.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@35296.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@35303.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@35304.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@35311.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@35312.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@35319.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@35320.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@35329.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@35330.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@35336.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@35337.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@35344.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@35345.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@35352.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@35353.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@35360.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@35361.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@35368.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@35369.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@35377.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@35378.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@35387.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@35388.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@35394.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@35395.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@35402.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@35403.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@35410.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@35411.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@35418.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@35419.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@35427.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@35428.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@35436.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@35437.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@35446.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@35447.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@35454.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@35455.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@35462.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@35463.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@35471.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@35472.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@35481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@35482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@35489.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@35490.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@35498.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@35499.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@35507.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@35508.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@35517.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@35518.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@35525.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@35526.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@35533.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@35534.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@35542.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@35543.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@35552.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@35553.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@35560.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@35561.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@35568.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@35569.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@35608.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@35609.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@35616.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@35617.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@35624.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@35625.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@35632.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@35633.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@35640.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@35641.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@35690.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@35691.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@35698.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@35699.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@35706.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@35707.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@35714.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@35715.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@35722.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@35723.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_649) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@35730.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_649) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@35731.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@35808.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@35809.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@35831.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@35832.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_730) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@35843.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_730) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@35844.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_744) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at ExampleRocketSystem.scala:40:46)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@35863.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_744) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@35864.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLXbar_4( // @[:freechips.rocketchip.system.LowRiscConfig.fir@35876.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35877.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35878.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [6:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [6:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [6:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [6:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@35879.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [6:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire [6:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
TLMonitor_14 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@35886.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@35926.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@35925.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@35888.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@35889.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@35922.4]
endmodule
module Queue_44( // @[:freechips.rocketchip.system.LowRiscConfig.fir@36052.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36053.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36054.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36055.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36055.4]
input [13:0] io_enq_bits, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36055.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36055.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@36055.4]
output [13:0] io_deq_bits // @[:freechips.rocketchip.system.LowRiscConfig.fir@36055.4]
);
reg [13:0] _T_35 [0:7]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
reg [31:0] _RAND_0;
wire [13:0] _T_35__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
wire [2:0] _T_35__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
wire [13:0] _T_35__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
wire [2:0] _T_35__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
wire _T_35__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
wire _T_35__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
reg [2:0] value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@36061.4]
reg [31:0] _RAND_1;
reg [2:0] value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@36062.4]
reg [31:0] _RAND_2;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@36063.4]
reg [31:0] _RAND_3;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@36064.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@36065.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@36066.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@36067.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@36068.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@36072.4]
wire [2:0] _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@36081.6]
wire [2:0] _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@36087.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@36090.4]
assign _T_35__T_58_addr = value_1;
assign _T_35__T_58_data = _T_35[_T_35__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
assign _T_35__T_50_data = io_enq_bits;
assign _T_35__T_50_addr = value;
assign _T_35__T_50_mask = 1'h1;
assign _T_35__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@36064.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@36065.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@36066.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@36067.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@36068.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@36072.4]
assign _T_52 = value + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@36081.6]
assign _T_54 = value_1 + 3'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@36087.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@36090.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@36097.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@36095.4]
assign io_deq_bits = _T_35__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@36099.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 8; initvar = initvar+1)
_T_35[initvar] = _RAND_0[13:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
value = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
value_1 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_39 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35__T_50_en & _T_35__T_50_mask) begin
_T_35[_T_35__T_50_addr] <= _T_35__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@36060.4]
end
if (reset) begin
value <= 3'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 3'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module AXI4UserYanker_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@37812.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37813.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37814.4]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [13:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [13:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [13:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [13:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@37815.4]
);
wire Queue_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire Queue_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire Queue_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire Queue_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire [13:0] Queue_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire Queue_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire Queue_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire [13:0] Queue_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
wire Queue_1_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire Queue_1_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire Queue_1_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire Queue_1_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire [13:0] Queue_1_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire Queue_1_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire Queue_1_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire [13:0] Queue_1_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
wire Queue_2_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire Queue_2_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire Queue_2_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire Queue_2_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire [13:0] Queue_2_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire Queue_2_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire Queue_2_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire [13:0] Queue_2_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
wire Queue_3_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire Queue_3_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire Queue_3_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire Queue_3_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire [13:0] Queue_3_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire Queue_3_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire Queue_3_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire [13:0] Queue_3_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
wire Queue_4_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire Queue_4_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire Queue_4_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire Queue_4_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire [13:0] Queue_4_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire Queue_4_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire Queue_4_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire [13:0] Queue_4_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
wire Queue_5_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire Queue_5_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire Queue_5_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire Queue_5_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire [13:0] Queue_5_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire Queue_5_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire Queue_5_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire [13:0] Queue_5_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
wire Queue_6_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire Queue_6_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire Queue_6_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire Queue_6_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire [13:0] Queue_6_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire Queue_6_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire Queue_6_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire [13:0] Queue_6_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
wire Queue_7_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire Queue_7_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire Queue_7_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire Queue_7_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire [13:0] Queue_7_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire Queue_7_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire Queue_7_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire [13:0] Queue_7_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
wire Queue_8_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire Queue_8_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire Queue_8_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire Queue_8_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire [13:0] Queue_8_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire Queue_8_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire Queue_8_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire [13:0] Queue_8_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
wire Queue_9_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire Queue_9_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire Queue_9_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire Queue_9_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire [13:0] Queue_9_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire Queue_9_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire Queue_9_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire [13:0] Queue_9_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
wire Queue_10_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire Queue_10_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire Queue_10_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire Queue_10_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire [13:0] Queue_10_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire Queue_10_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire Queue_10_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire [13:0] Queue_10_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
wire Queue_11_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire Queue_11_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire Queue_11_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire Queue_11_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire [13:0] Queue_11_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire Queue_11_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire Queue_11_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire [13:0] Queue_11_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
wire Queue_12_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire Queue_12_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire Queue_12_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire Queue_12_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire [13:0] Queue_12_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire Queue_12_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire Queue_12_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire [13:0] Queue_12_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
wire Queue_13_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire Queue_13_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire Queue_13_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire Queue_13_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire [13:0] Queue_13_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire Queue_13_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire Queue_13_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire [13:0] Queue_13_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
wire Queue_14_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire Queue_14_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire Queue_14_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire Queue_14_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire [13:0] Queue_14_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire Queue_14_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire Queue_14_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire [13:0] Queue_14_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
wire Queue_15_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire Queue_15_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire Queue_15_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire Queue_15_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire [13:0] Queue_15_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire Queue_15_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire Queue_15_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire [13:0] Queue_15_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
wire Queue_16_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire Queue_16_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire Queue_16_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire Queue_16_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire [13:0] Queue_16_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire Queue_16_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire Queue_16_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire [13:0] Queue_16_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
wire Queue_17_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire Queue_17_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire Queue_17_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire Queue_17_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire [13:0] Queue_17_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire Queue_17_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire Queue_17_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire [13:0] Queue_17_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
wire Queue_18_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire Queue_18_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire Queue_18_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire Queue_18_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire [13:0] Queue_18_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire Queue_18_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire Queue_18_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire [13:0] Queue_18_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
wire Queue_19_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire Queue_19_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire Queue_19_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire Queue_19_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire [13:0] Queue_19_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire Queue_19_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire Queue_19_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire [13:0] Queue_19_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
wire Queue_20_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire Queue_20_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire Queue_20_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire Queue_20_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire [13:0] Queue_20_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire Queue_20_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire Queue_20_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire [13:0] Queue_20_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
wire Queue_21_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire Queue_21_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire Queue_21_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire Queue_21_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire [13:0] Queue_21_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire Queue_21_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire Queue_21_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire [13:0] Queue_21_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
wire Queue_22_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire Queue_22_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire Queue_22_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire Queue_22_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire [13:0] Queue_22_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire Queue_22_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire Queue_22_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire [13:0] Queue_22_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
wire Queue_23_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire Queue_23_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire Queue_23_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire Queue_23_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire [13:0] Queue_23_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire Queue_23_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire Queue_23_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire [13:0] Queue_23_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
wire Queue_24_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire Queue_24_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire Queue_24_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire Queue_24_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire [13:0] Queue_24_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire Queue_24_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire Queue_24_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire [13:0] Queue_24_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
wire Queue_25_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire Queue_25_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire Queue_25_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire Queue_25_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire [13:0] Queue_25_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire Queue_25_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire Queue_25_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire [13:0] Queue_25_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
wire Queue_26_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire Queue_26_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire Queue_26_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire Queue_26_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire [13:0] Queue_26_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire Queue_26_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire Queue_26_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire [13:0] Queue_26_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
wire Queue_27_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire Queue_27_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire Queue_27_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire Queue_27_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire [13:0] Queue_27_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire Queue_27_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire Queue_27_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire [13:0] Queue_27_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
wire Queue_28_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire Queue_28_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire Queue_28_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire Queue_28_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire [13:0] Queue_28_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire Queue_28_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire Queue_28_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire [13:0] Queue_28_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
wire Queue_29_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire Queue_29_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire Queue_29_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire Queue_29_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire [13:0] Queue_29_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire Queue_29_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire Queue_29_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire [13:0] Queue_29_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
wire Queue_30_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire Queue_30_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire Queue_30_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire Queue_30_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire [13:0] Queue_30_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire Queue_30_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire Queue_30_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire [13:0] Queue_30_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
wire Queue_31_clock; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire Queue_31_reset; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire Queue_31_io_enq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire Queue_31_io_enq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire [13:0] Queue_31_io_enq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire Queue_31_io_deq_ready; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire Queue_31_io_deq_valid; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire [13:0] Queue_31_io_deq_bits; // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
wire _T_224_0; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37956.4]
wire _T_224_1; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37957.4]
wire _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_2; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37958.4]
wire _GEN_2; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_3; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37959.4]
wire _GEN_3; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_4; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37960.4]
wire _GEN_4; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_5; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37961.4]
wire _GEN_5; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_6; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37962.4]
wire _GEN_6; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_7; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37963.4]
wire _GEN_7; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_8; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37964.4]
wire _GEN_8; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_9; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37965.4]
wire _GEN_9; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_10; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37966.4]
wire _GEN_10; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_11; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37967.4]
wire _GEN_11; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_12; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37968.4]
wire _GEN_12; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_13; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37969.4]
wire _GEN_13; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_14; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37970.4]
wire _GEN_14; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_224_15; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37971.4]
wire _GEN_15; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
wire _T_292; // @[UserYanker.scala 54:15:freechips.rocketchip.system.LowRiscConfig.fir@38013.4]
wire _T_249_0; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37979.4]
wire _T_249_1; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37980.4]
wire _GEN_17; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_2; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37981.4]
wire _GEN_18; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_3; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37982.4]
wire _GEN_19; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_4; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37983.4]
wire _GEN_20; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_5; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37984.4]
wire _GEN_21; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_6; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37985.4]
wire _GEN_22; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_7; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37986.4]
wire _GEN_23; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_8; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37987.4]
wire _GEN_24; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_9; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37988.4]
wire _GEN_25; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_10; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37989.4]
wire _GEN_26; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_11; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37990.4]
wire _GEN_27; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_12; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37991.4]
wire _GEN_28; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_13; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37992.4]
wire _GEN_29; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_14; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37993.4]
wire _GEN_30; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_249_15; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37994.4]
wire _GEN_31; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_293; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
wire _T_295; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38016.4]
wire _T_296; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38017.4]
wire [13:0] _T_272_0; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37997.4]
wire [13:0] _T_272_1; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37998.4]
wire [13:0] _GEN_33; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_2; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37999.4]
wire [13:0] _GEN_34; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_3; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38000.4]
wire [13:0] _GEN_35; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_4; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38001.4]
wire [13:0] _GEN_36; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_5; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38002.4]
wire [13:0] _GEN_37; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_6; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38003.4]
wire [13:0] _GEN_38; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_7; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38004.4]
wire [13:0] _GEN_39; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_8; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38005.4]
wire [13:0] _GEN_40; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_9; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38006.4]
wire [13:0] _GEN_41; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_10; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38007.4]
wire [13:0] _GEN_42; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_11; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38008.4]
wire [13:0] _GEN_43; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_12; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38009.4]
wire [13:0] _GEN_44; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_13; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38010.4]
wire [13:0] _GEN_45; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_14; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38011.4]
wire [13:0] _GEN_46; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
wire [13:0] _T_272_15; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38012.4]
wire [15:0] _T_298; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38025.4]
wire _T_300; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38027.4]
wire _T_301; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38028.4]
wire _T_302; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38029.4]
wire _T_303; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38030.4]
wire _T_304; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38031.4]
wire _T_305; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38032.4]
wire _T_306; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38033.4]
wire _T_307; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38034.4]
wire _T_308; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38035.4]
wire _T_309; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38036.4]
wire _T_310; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38037.4]
wire _T_311; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38038.4]
wire _T_312; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38039.4]
wire _T_313; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38040.4]
wire _T_314; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38041.4]
wire _T_315; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38042.4]
wire [15:0] _T_317; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38044.4]
wire _T_319; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38046.4]
wire _T_320; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38047.4]
wire _T_321; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38048.4]
wire _T_322; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38049.4]
wire _T_323; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38050.4]
wire _T_324; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38051.4]
wire _T_325; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38052.4]
wire _T_326; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38053.4]
wire _T_327; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38054.4]
wire _T_328; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38055.4]
wire _T_329; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38056.4]
wire _T_330; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38057.4]
wire _T_331; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38058.4]
wire _T_332; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38059.4]
wire _T_333; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38060.4]
wire _T_334; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38061.4]
wire _T_335; // @[UserYanker.scala 61:37:freechips.rocketchip.system.LowRiscConfig.fir@38062.4]
wire _T_336; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38063.4]
wire _T_338; // @[UserYanker.scala 62:37:freechips.rocketchip.system.LowRiscConfig.fir@38066.4]
wire _T_341; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38071.4]
wire _T_346; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38079.4]
wire _T_351; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38087.4]
wire _T_356; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38095.4]
wire _T_361; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38103.4]
wire _T_366; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38111.4]
wire _T_371; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38119.4]
wire _T_376; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38127.4]
wire _T_381; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38135.4]
wire _T_386; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38143.4]
wire _T_391; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38151.4]
wire _T_396; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38159.4]
wire _T_401; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38167.4]
wire _T_406; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38175.4]
wire _T_411; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38183.4]
wire _T_418_0; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38192.4]
wire _T_418_1; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38193.4]
wire _GEN_49; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_2; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38194.4]
wire _GEN_50; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_3; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38195.4]
wire _GEN_51; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_4; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38196.4]
wire _GEN_52; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_5; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38197.4]
wire _GEN_53; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_6; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38198.4]
wire _GEN_54; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_7; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38199.4]
wire _GEN_55; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_8; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38200.4]
wire _GEN_56; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_9; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38201.4]
wire _GEN_57; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_10; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38202.4]
wire _GEN_58; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_11; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38203.4]
wire _GEN_59; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_12; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38204.4]
wire _GEN_60; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_13; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38205.4]
wire _GEN_61; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_14; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38206.4]
wire _GEN_62; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_418_15; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38207.4]
wire _GEN_63; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
wire _T_486; // @[UserYanker.scala 75:15:freechips.rocketchip.system.LowRiscConfig.fir@38249.4]
wire _T_443_0; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38215.4]
wire _T_443_1; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38216.4]
wire _GEN_65; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_2; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38217.4]
wire _GEN_66; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_3; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38218.4]
wire _GEN_67; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_4; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38219.4]
wire _GEN_68; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_5; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38220.4]
wire _GEN_69; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_6; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38221.4]
wire _GEN_70; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_7; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38222.4]
wire _GEN_71; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_8; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38223.4]
wire _GEN_72; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_9; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38224.4]
wire _GEN_73; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_10; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38225.4]
wire _GEN_74; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_11; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38226.4]
wire _GEN_75; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_12; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38227.4]
wire _GEN_76; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_13; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38228.4]
wire _GEN_77; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_14; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38229.4]
wire _GEN_78; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_443_15; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38230.4]
wire _GEN_79; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_487; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
wire _T_489; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38252.4]
wire _T_490; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38253.4]
wire [13:0] _T_466_0; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38233.4]
wire [13:0] _T_466_1; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38234.4]
wire [13:0] _GEN_81; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_2; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38235.4]
wire [13:0] _GEN_82; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_3; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38236.4]
wire [13:0] _GEN_83; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_4; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38237.4]
wire [13:0] _GEN_84; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_5; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38238.4]
wire [13:0] _GEN_85; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_6; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38239.4]
wire [13:0] _GEN_86; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_7; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38240.4]
wire [13:0] _GEN_87; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_8; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38241.4]
wire [13:0] _GEN_88; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_9; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38242.4]
wire [13:0] _GEN_89; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_10; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38243.4]
wire [13:0] _GEN_90; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_11; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38244.4]
wire [13:0] _GEN_91; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_12; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38245.4]
wire [13:0] _GEN_92; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_13; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38246.4]
wire [13:0] _GEN_93; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_14; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38247.4]
wire [13:0] _GEN_94; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
wire [13:0] _T_466_15; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38248.4]
wire [15:0] _T_492; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38261.4]
wire _T_494; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38263.4]
wire _T_495; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38264.4]
wire _T_496; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38265.4]
wire _T_497; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38266.4]
wire _T_498; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38267.4]
wire _T_499; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38268.4]
wire _T_500; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38269.4]
wire _T_501; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38270.4]
wire _T_502; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38271.4]
wire _T_503; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38272.4]
wire _T_504; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38273.4]
wire _T_505; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38274.4]
wire _T_506; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38275.4]
wire _T_507; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38276.4]
wire _T_508; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38277.4]
wire _T_509; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38278.4]
wire [15:0] _T_511; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38280.4]
wire _T_513; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38282.4]
wire _T_514; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38283.4]
wire _T_515; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38284.4]
wire _T_516; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38285.4]
wire _T_517; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38286.4]
wire _T_518; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38287.4]
wire _T_519; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38288.4]
wire _T_520; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38289.4]
wire _T_521; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38290.4]
wire _T_522; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38291.4]
wire _T_523; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38292.4]
wire _T_524; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38293.4]
wire _T_525; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38294.4]
wire _T_526; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38295.4]
wire _T_527; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38296.4]
wire _T_528; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38297.4]
wire _T_529; // @[UserYanker.scala 82:37:freechips.rocketchip.system.LowRiscConfig.fir@38298.4]
wire _T_531; // @[UserYanker.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@38301.4]
Queue_44 Queue ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37826.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits(Queue_io_enq_bits),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits(Queue_io_deq_bits)
);
Queue_44 Queue_1 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37830.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits(Queue_1_io_enq_bits),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits(Queue_1_io_deq_bits)
);
Queue_44 Queue_2 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37834.4]
.clock(Queue_2_clock),
.reset(Queue_2_reset),
.io_enq_ready(Queue_2_io_enq_ready),
.io_enq_valid(Queue_2_io_enq_valid),
.io_enq_bits(Queue_2_io_enq_bits),
.io_deq_ready(Queue_2_io_deq_ready),
.io_deq_valid(Queue_2_io_deq_valid),
.io_deq_bits(Queue_2_io_deq_bits)
);
Queue_44 Queue_3 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37838.4]
.clock(Queue_3_clock),
.reset(Queue_3_reset),
.io_enq_ready(Queue_3_io_enq_ready),
.io_enq_valid(Queue_3_io_enq_valid),
.io_enq_bits(Queue_3_io_enq_bits),
.io_deq_ready(Queue_3_io_deq_ready),
.io_deq_valid(Queue_3_io_deq_valid),
.io_deq_bits(Queue_3_io_deq_bits)
);
Queue_44 Queue_4 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37842.4]
.clock(Queue_4_clock),
.reset(Queue_4_reset),
.io_enq_ready(Queue_4_io_enq_ready),
.io_enq_valid(Queue_4_io_enq_valid),
.io_enq_bits(Queue_4_io_enq_bits),
.io_deq_ready(Queue_4_io_deq_ready),
.io_deq_valid(Queue_4_io_deq_valid),
.io_deq_bits(Queue_4_io_deq_bits)
);
Queue_44 Queue_5 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37846.4]
.clock(Queue_5_clock),
.reset(Queue_5_reset),
.io_enq_ready(Queue_5_io_enq_ready),
.io_enq_valid(Queue_5_io_enq_valid),
.io_enq_bits(Queue_5_io_enq_bits),
.io_deq_ready(Queue_5_io_deq_ready),
.io_deq_valid(Queue_5_io_deq_valid),
.io_deq_bits(Queue_5_io_deq_bits)
);
Queue_44 Queue_6 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37850.4]
.clock(Queue_6_clock),
.reset(Queue_6_reset),
.io_enq_ready(Queue_6_io_enq_ready),
.io_enq_valid(Queue_6_io_enq_valid),
.io_enq_bits(Queue_6_io_enq_bits),
.io_deq_ready(Queue_6_io_deq_ready),
.io_deq_valid(Queue_6_io_deq_valid),
.io_deq_bits(Queue_6_io_deq_bits)
);
Queue_44 Queue_7 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37854.4]
.clock(Queue_7_clock),
.reset(Queue_7_reset),
.io_enq_ready(Queue_7_io_enq_ready),
.io_enq_valid(Queue_7_io_enq_valid),
.io_enq_bits(Queue_7_io_enq_bits),
.io_deq_ready(Queue_7_io_deq_ready),
.io_deq_valid(Queue_7_io_deq_valid),
.io_deq_bits(Queue_7_io_deq_bits)
);
Queue_44 Queue_8 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37858.4]
.clock(Queue_8_clock),
.reset(Queue_8_reset),
.io_enq_ready(Queue_8_io_enq_ready),
.io_enq_valid(Queue_8_io_enq_valid),
.io_enq_bits(Queue_8_io_enq_bits),
.io_deq_ready(Queue_8_io_deq_ready),
.io_deq_valid(Queue_8_io_deq_valid),
.io_deq_bits(Queue_8_io_deq_bits)
);
Queue_44 Queue_9 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37862.4]
.clock(Queue_9_clock),
.reset(Queue_9_reset),
.io_enq_ready(Queue_9_io_enq_ready),
.io_enq_valid(Queue_9_io_enq_valid),
.io_enq_bits(Queue_9_io_enq_bits),
.io_deq_ready(Queue_9_io_deq_ready),
.io_deq_valid(Queue_9_io_deq_valid),
.io_deq_bits(Queue_9_io_deq_bits)
);
Queue_44 Queue_10 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37866.4]
.clock(Queue_10_clock),
.reset(Queue_10_reset),
.io_enq_ready(Queue_10_io_enq_ready),
.io_enq_valid(Queue_10_io_enq_valid),
.io_enq_bits(Queue_10_io_enq_bits),
.io_deq_ready(Queue_10_io_deq_ready),
.io_deq_valid(Queue_10_io_deq_valid),
.io_deq_bits(Queue_10_io_deq_bits)
);
Queue_44 Queue_11 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37870.4]
.clock(Queue_11_clock),
.reset(Queue_11_reset),
.io_enq_ready(Queue_11_io_enq_ready),
.io_enq_valid(Queue_11_io_enq_valid),
.io_enq_bits(Queue_11_io_enq_bits),
.io_deq_ready(Queue_11_io_deq_ready),
.io_deq_valid(Queue_11_io_deq_valid),
.io_deq_bits(Queue_11_io_deq_bits)
);
Queue_44 Queue_12 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37874.4]
.clock(Queue_12_clock),
.reset(Queue_12_reset),
.io_enq_ready(Queue_12_io_enq_ready),
.io_enq_valid(Queue_12_io_enq_valid),
.io_enq_bits(Queue_12_io_enq_bits),
.io_deq_ready(Queue_12_io_deq_ready),
.io_deq_valid(Queue_12_io_deq_valid),
.io_deq_bits(Queue_12_io_deq_bits)
);
Queue_44 Queue_13 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37878.4]
.clock(Queue_13_clock),
.reset(Queue_13_reset),
.io_enq_ready(Queue_13_io_enq_ready),
.io_enq_valid(Queue_13_io_enq_valid),
.io_enq_bits(Queue_13_io_enq_bits),
.io_deq_ready(Queue_13_io_deq_ready),
.io_deq_valid(Queue_13_io_deq_valid),
.io_deq_bits(Queue_13_io_deq_bits)
);
Queue_44 Queue_14 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37882.4]
.clock(Queue_14_clock),
.reset(Queue_14_reset),
.io_enq_ready(Queue_14_io_enq_ready),
.io_enq_valid(Queue_14_io_enq_valid),
.io_enq_bits(Queue_14_io_enq_bits),
.io_deq_ready(Queue_14_io_deq_ready),
.io_deq_valid(Queue_14_io_deq_valid),
.io_deq_bits(Queue_14_io_deq_bits)
);
Queue_44 Queue_15 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37886.4]
.clock(Queue_15_clock),
.reset(Queue_15_reset),
.io_enq_ready(Queue_15_io_enq_ready),
.io_enq_valid(Queue_15_io_enq_valid),
.io_enq_bits(Queue_15_io_enq_bits),
.io_deq_ready(Queue_15_io_deq_ready),
.io_deq_valid(Queue_15_io_deq_valid),
.io_deq_bits(Queue_15_io_deq_bits)
);
Queue_44 Queue_16 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37890.4]
.clock(Queue_16_clock),
.reset(Queue_16_reset),
.io_enq_ready(Queue_16_io_enq_ready),
.io_enq_valid(Queue_16_io_enq_valid),
.io_enq_bits(Queue_16_io_enq_bits),
.io_deq_ready(Queue_16_io_deq_ready),
.io_deq_valid(Queue_16_io_deq_valid),
.io_deq_bits(Queue_16_io_deq_bits)
);
Queue_44 Queue_17 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37894.4]
.clock(Queue_17_clock),
.reset(Queue_17_reset),
.io_enq_ready(Queue_17_io_enq_ready),
.io_enq_valid(Queue_17_io_enq_valid),
.io_enq_bits(Queue_17_io_enq_bits),
.io_deq_ready(Queue_17_io_deq_ready),
.io_deq_valid(Queue_17_io_deq_valid),
.io_deq_bits(Queue_17_io_deq_bits)
);
Queue_44 Queue_18 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37898.4]
.clock(Queue_18_clock),
.reset(Queue_18_reset),
.io_enq_ready(Queue_18_io_enq_ready),
.io_enq_valid(Queue_18_io_enq_valid),
.io_enq_bits(Queue_18_io_enq_bits),
.io_deq_ready(Queue_18_io_deq_ready),
.io_deq_valid(Queue_18_io_deq_valid),
.io_deq_bits(Queue_18_io_deq_bits)
);
Queue_44 Queue_19 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37902.4]
.clock(Queue_19_clock),
.reset(Queue_19_reset),
.io_enq_ready(Queue_19_io_enq_ready),
.io_enq_valid(Queue_19_io_enq_valid),
.io_enq_bits(Queue_19_io_enq_bits),
.io_deq_ready(Queue_19_io_deq_ready),
.io_deq_valid(Queue_19_io_deq_valid),
.io_deq_bits(Queue_19_io_deq_bits)
);
Queue_44 Queue_20 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37906.4]
.clock(Queue_20_clock),
.reset(Queue_20_reset),
.io_enq_ready(Queue_20_io_enq_ready),
.io_enq_valid(Queue_20_io_enq_valid),
.io_enq_bits(Queue_20_io_enq_bits),
.io_deq_ready(Queue_20_io_deq_ready),
.io_deq_valid(Queue_20_io_deq_valid),
.io_deq_bits(Queue_20_io_deq_bits)
);
Queue_44 Queue_21 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37910.4]
.clock(Queue_21_clock),
.reset(Queue_21_reset),
.io_enq_ready(Queue_21_io_enq_ready),
.io_enq_valid(Queue_21_io_enq_valid),
.io_enq_bits(Queue_21_io_enq_bits),
.io_deq_ready(Queue_21_io_deq_ready),
.io_deq_valid(Queue_21_io_deq_valid),
.io_deq_bits(Queue_21_io_deq_bits)
);
Queue_44 Queue_22 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37914.4]
.clock(Queue_22_clock),
.reset(Queue_22_reset),
.io_enq_ready(Queue_22_io_enq_ready),
.io_enq_valid(Queue_22_io_enq_valid),
.io_enq_bits(Queue_22_io_enq_bits),
.io_deq_ready(Queue_22_io_deq_ready),
.io_deq_valid(Queue_22_io_deq_valid),
.io_deq_bits(Queue_22_io_deq_bits)
);
Queue_44 Queue_23 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37918.4]
.clock(Queue_23_clock),
.reset(Queue_23_reset),
.io_enq_ready(Queue_23_io_enq_ready),
.io_enq_valid(Queue_23_io_enq_valid),
.io_enq_bits(Queue_23_io_enq_bits),
.io_deq_ready(Queue_23_io_deq_ready),
.io_deq_valid(Queue_23_io_deq_valid),
.io_deq_bits(Queue_23_io_deq_bits)
);
Queue_44 Queue_24 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37922.4]
.clock(Queue_24_clock),
.reset(Queue_24_reset),
.io_enq_ready(Queue_24_io_enq_ready),
.io_enq_valid(Queue_24_io_enq_valid),
.io_enq_bits(Queue_24_io_enq_bits),
.io_deq_ready(Queue_24_io_deq_ready),
.io_deq_valid(Queue_24_io_deq_valid),
.io_deq_bits(Queue_24_io_deq_bits)
);
Queue_44 Queue_25 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37926.4]
.clock(Queue_25_clock),
.reset(Queue_25_reset),
.io_enq_ready(Queue_25_io_enq_ready),
.io_enq_valid(Queue_25_io_enq_valid),
.io_enq_bits(Queue_25_io_enq_bits),
.io_deq_ready(Queue_25_io_deq_ready),
.io_deq_valid(Queue_25_io_deq_valid),
.io_deq_bits(Queue_25_io_deq_bits)
);
Queue_44 Queue_26 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37930.4]
.clock(Queue_26_clock),
.reset(Queue_26_reset),
.io_enq_ready(Queue_26_io_enq_ready),
.io_enq_valid(Queue_26_io_enq_valid),
.io_enq_bits(Queue_26_io_enq_bits),
.io_deq_ready(Queue_26_io_deq_ready),
.io_deq_valid(Queue_26_io_deq_valid),
.io_deq_bits(Queue_26_io_deq_bits)
);
Queue_44 Queue_27 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37934.4]
.clock(Queue_27_clock),
.reset(Queue_27_reset),
.io_enq_ready(Queue_27_io_enq_ready),
.io_enq_valid(Queue_27_io_enq_valid),
.io_enq_bits(Queue_27_io_enq_bits),
.io_deq_ready(Queue_27_io_deq_ready),
.io_deq_valid(Queue_27_io_deq_valid),
.io_deq_bits(Queue_27_io_deq_bits)
);
Queue_44 Queue_28 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37938.4]
.clock(Queue_28_clock),
.reset(Queue_28_reset),
.io_enq_ready(Queue_28_io_enq_ready),
.io_enq_valid(Queue_28_io_enq_valid),
.io_enq_bits(Queue_28_io_enq_bits),
.io_deq_ready(Queue_28_io_deq_ready),
.io_deq_valid(Queue_28_io_deq_valid),
.io_deq_bits(Queue_28_io_deq_bits)
);
Queue_44 Queue_29 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37942.4]
.clock(Queue_29_clock),
.reset(Queue_29_reset),
.io_enq_ready(Queue_29_io_enq_ready),
.io_enq_valid(Queue_29_io_enq_valid),
.io_enq_bits(Queue_29_io_enq_bits),
.io_deq_ready(Queue_29_io_deq_ready),
.io_deq_valid(Queue_29_io_deq_valid),
.io_deq_bits(Queue_29_io_deq_bits)
);
Queue_44 Queue_30 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37946.4]
.clock(Queue_30_clock),
.reset(Queue_30_reset),
.io_enq_ready(Queue_30_io_enq_ready),
.io_enq_valid(Queue_30_io_enq_valid),
.io_enq_bits(Queue_30_io_enq_bits),
.io_deq_ready(Queue_30_io_deq_ready),
.io_deq_valid(Queue_30_io_deq_valid),
.io_deq_bits(Queue_30_io_deq_bits)
);
Queue_44 Queue_31 ( // @[UserYanker.scala 38:17:freechips.rocketchip.system.LowRiscConfig.fir@37950.4]
.clock(Queue_31_clock),
.reset(Queue_31_reset),
.io_enq_ready(Queue_31_io_enq_ready),
.io_enq_valid(Queue_31_io_enq_valid),
.io_enq_bits(Queue_31_io_enq_bits),
.io_deq_ready(Queue_31_io_deq_ready),
.io_deq_valid(Queue_31_io_deq_valid),
.io_deq_bits(Queue_31_io_deq_bits)
);
assign _T_224_0 = Queue_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37956.4]
assign _T_224_1 = Queue_1_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37957.4]
assign _GEN_1 = 4'h1 == auto_in_ar_bits_id ? _T_224_1 : _T_224_0; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_2 = Queue_2_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37958.4]
assign _GEN_2 = 4'h2 == auto_in_ar_bits_id ? _T_224_2 : _GEN_1; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_3 = Queue_3_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37959.4]
assign _GEN_3 = 4'h3 == auto_in_ar_bits_id ? _T_224_3 : _GEN_2; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_4 = Queue_4_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37960.4]
assign _GEN_4 = 4'h4 == auto_in_ar_bits_id ? _T_224_4 : _GEN_3; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_5 = Queue_5_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37961.4]
assign _GEN_5 = 4'h5 == auto_in_ar_bits_id ? _T_224_5 : _GEN_4; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_6 = Queue_6_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37962.4]
assign _GEN_6 = 4'h6 == auto_in_ar_bits_id ? _T_224_6 : _GEN_5; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_7 = Queue_7_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37963.4]
assign _GEN_7 = 4'h7 == auto_in_ar_bits_id ? _T_224_7 : _GEN_6; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_8 = Queue_8_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37964.4]
assign _GEN_8 = 4'h8 == auto_in_ar_bits_id ? _T_224_8 : _GEN_7; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_9 = Queue_9_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37965.4]
assign _GEN_9 = 4'h9 == auto_in_ar_bits_id ? _T_224_9 : _GEN_8; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_10 = Queue_10_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37966.4]
assign _GEN_10 = 4'ha == auto_in_ar_bits_id ? _T_224_10 : _GEN_9; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_11 = Queue_11_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37967.4]
assign _GEN_11 = 4'hb == auto_in_ar_bits_id ? _T_224_11 : _GEN_10; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_12 = Queue_12_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37968.4]
assign _GEN_12 = 4'hc == auto_in_ar_bits_id ? _T_224_12 : _GEN_11; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_13 = Queue_13_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37969.4]
assign _GEN_13 = 4'hd == auto_in_ar_bits_id ? _T_224_13 : _GEN_12; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_14 = Queue_14_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37970.4]
assign _GEN_14 = 4'he == auto_in_ar_bits_id ? _T_224_14 : _GEN_13; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_224_15 = Queue_15_io_enq_ready; // @[UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37954.4 UserYanker.scala 46:25:freechips.rocketchip.system.LowRiscConfig.fir@37971.4]
assign _GEN_15 = 4'hf == auto_in_ar_bits_id ? _T_224_15 : _GEN_14; // @[UserYanker.scala 47:36:freechips.rocketchip.system.LowRiscConfig.fir@37972.4]
assign _T_292 = auto_out_r_valid == 1'h0; // @[UserYanker.scala 54:15:freechips.rocketchip.system.LowRiscConfig.fir@38013.4]
assign _T_249_0 = Queue_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37979.4]
assign _T_249_1 = Queue_1_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37980.4]
assign _GEN_17 = 4'h1 == auto_out_r_bits_id ? _T_249_1 : _T_249_0; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_2 = Queue_2_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37981.4]
assign _GEN_18 = 4'h2 == auto_out_r_bits_id ? _T_249_2 : _GEN_17; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_3 = Queue_3_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37982.4]
assign _GEN_19 = 4'h3 == auto_out_r_bits_id ? _T_249_3 : _GEN_18; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_4 = Queue_4_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37983.4]
assign _GEN_20 = 4'h4 == auto_out_r_bits_id ? _T_249_4 : _GEN_19; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_5 = Queue_5_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37984.4]
assign _GEN_21 = 4'h5 == auto_out_r_bits_id ? _T_249_5 : _GEN_20; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_6 = Queue_6_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37985.4]
assign _GEN_22 = 4'h6 == auto_out_r_bits_id ? _T_249_6 : _GEN_21; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_7 = Queue_7_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37986.4]
assign _GEN_23 = 4'h7 == auto_out_r_bits_id ? _T_249_7 : _GEN_22; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_8 = Queue_8_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37987.4]
assign _GEN_24 = 4'h8 == auto_out_r_bits_id ? _T_249_8 : _GEN_23; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_9 = Queue_9_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37988.4]
assign _GEN_25 = 4'h9 == auto_out_r_bits_id ? _T_249_9 : _GEN_24; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_10 = Queue_10_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37989.4]
assign _GEN_26 = 4'ha == auto_out_r_bits_id ? _T_249_10 : _GEN_25; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_11 = Queue_11_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37990.4]
assign _GEN_27 = 4'hb == auto_out_r_bits_id ? _T_249_11 : _GEN_26; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_12 = Queue_12_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37991.4]
assign _GEN_28 = 4'hc == auto_out_r_bits_id ? _T_249_12 : _GEN_27; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_13 = Queue_13_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37992.4]
assign _GEN_29 = 4'hd == auto_out_r_bits_id ? _T_249_13 : _GEN_28; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_14 = Queue_14_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37993.4]
assign _GEN_30 = 4'he == auto_out_r_bits_id ? _T_249_14 : _GEN_29; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_249_15 = Queue_15_io_deq_valid; // @[UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37977.4 UserYanker.scala 52:24:freechips.rocketchip.system.LowRiscConfig.fir@37994.4]
assign _GEN_31 = 4'hf == auto_out_r_bits_id ? _T_249_15 : _GEN_30; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_293 = _T_292 | _GEN_31; // @[UserYanker.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@38014.4]
assign _T_295 = _T_293 | reset; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38016.4]
assign _T_296 = _T_295 == 1'h0; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38017.4]
assign _T_272_0 = Queue_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37997.4]
assign _T_272_1 = Queue_1_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37998.4]
assign _GEN_33 = 4'h1 == auto_out_r_bits_id ? _T_272_1 : _T_272_0; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_2 = Queue_2_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37999.4]
assign _GEN_34 = 4'h2 == auto_out_r_bits_id ? _T_272_2 : _GEN_33; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_3 = Queue_3_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38000.4]
assign _GEN_35 = 4'h3 == auto_out_r_bits_id ? _T_272_3 : _GEN_34; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_4 = Queue_4_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38001.4]
assign _GEN_36 = 4'h4 == auto_out_r_bits_id ? _T_272_4 : _GEN_35; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_5 = Queue_5_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38002.4]
assign _GEN_37 = 4'h5 == auto_out_r_bits_id ? _T_272_5 : _GEN_36; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_6 = Queue_6_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38003.4]
assign _GEN_38 = 4'h6 == auto_out_r_bits_id ? _T_272_6 : _GEN_37; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_7 = Queue_7_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38004.4]
assign _GEN_39 = 4'h7 == auto_out_r_bits_id ? _T_272_7 : _GEN_38; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_8 = Queue_8_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38005.4]
assign _GEN_40 = 4'h8 == auto_out_r_bits_id ? _T_272_8 : _GEN_39; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_9 = Queue_9_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38006.4]
assign _GEN_41 = 4'h9 == auto_out_r_bits_id ? _T_272_9 : _GEN_40; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_10 = Queue_10_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38007.4]
assign _GEN_42 = 4'ha == auto_out_r_bits_id ? _T_272_10 : _GEN_41; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_11 = Queue_11_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38008.4]
assign _GEN_43 = 4'hb == auto_out_r_bits_id ? _T_272_11 : _GEN_42; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_12 = Queue_12_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38009.4]
assign _GEN_44 = 4'hc == auto_out_r_bits_id ? _T_272_12 : _GEN_43; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_13 = Queue_13_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38010.4]
assign _GEN_45 = 4'hd == auto_out_r_bits_id ? _T_272_13 : _GEN_44; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_14 = Queue_14_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38011.4]
assign _GEN_46 = 4'he == auto_out_r_bits_id ? _T_272_14 : _GEN_45; // @[UserYanker.scala 56:26:freechips.rocketchip.system.LowRiscConfig.fir@38023.4]
assign _T_272_15 = Queue_15_io_deq_bits; // @[UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@37995.4 UserYanker.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@38012.4]
assign _T_298 = 16'h1 << auto_in_ar_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38025.4]
assign _T_300 = _T_298[0]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38027.4]
assign _T_301 = _T_298[1]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38028.4]
assign _T_302 = _T_298[2]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38029.4]
assign _T_303 = _T_298[3]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38030.4]
assign _T_304 = _T_298[4]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38031.4]
assign _T_305 = _T_298[5]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38032.4]
assign _T_306 = _T_298[6]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38033.4]
assign _T_307 = _T_298[7]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38034.4]
assign _T_308 = _T_298[8]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38035.4]
assign _T_309 = _T_298[9]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38036.4]
assign _T_310 = _T_298[10]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38037.4]
assign _T_311 = _T_298[11]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38038.4]
assign _T_312 = _T_298[12]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38039.4]
assign _T_313 = _T_298[13]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38040.4]
assign _T_314 = _T_298[14]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38041.4]
assign _T_315 = _T_298[15]; // @[UserYanker.scala 58:55:freechips.rocketchip.system.LowRiscConfig.fir@38042.4]
assign _T_317 = 16'h1 << auto_out_r_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38044.4]
assign _T_319 = _T_317[0]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38046.4]
assign _T_320 = _T_317[1]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38047.4]
assign _T_321 = _T_317[2]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38048.4]
assign _T_322 = _T_317[3]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38049.4]
assign _T_323 = _T_317[4]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38050.4]
assign _T_324 = _T_317[5]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38051.4]
assign _T_325 = _T_317[6]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38052.4]
assign _T_326 = _T_317[7]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38053.4]
assign _T_327 = _T_317[8]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38054.4]
assign _T_328 = _T_317[9]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38055.4]
assign _T_329 = _T_317[10]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38056.4]
assign _T_330 = _T_317[11]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38057.4]
assign _T_331 = _T_317[12]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38058.4]
assign _T_332 = _T_317[13]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38059.4]
assign _T_333 = _T_317[14]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38060.4]
assign _T_334 = _T_317[15]; // @[UserYanker.scala 59:55:freechips.rocketchip.system.LowRiscConfig.fir@38061.4]
assign _T_335 = auto_out_r_valid & auto_in_r_ready; // @[UserYanker.scala 61:37:freechips.rocketchip.system.LowRiscConfig.fir@38062.4]
assign _T_336 = _T_335 & _T_319; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38063.4]
assign _T_338 = auto_in_ar_valid & auto_out_ar_ready; // @[UserYanker.scala 62:37:freechips.rocketchip.system.LowRiscConfig.fir@38066.4]
assign _T_341 = _T_335 & _T_320; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38071.4]
assign _T_346 = _T_335 & _T_321; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38079.4]
assign _T_351 = _T_335 & _T_322; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38087.4]
assign _T_356 = _T_335 & _T_323; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38095.4]
assign _T_361 = _T_335 & _T_324; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38103.4]
assign _T_366 = _T_335 & _T_325; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38111.4]
assign _T_371 = _T_335 & _T_326; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38119.4]
assign _T_376 = _T_335 & _T_327; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38127.4]
assign _T_381 = _T_335 & _T_328; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38135.4]
assign _T_386 = _T_335 & _T_329; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38143.4]
assign _T_391 = _T_335 & _T_330; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38151.4]
assign _T_396 = _T_335 & _T_331; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38159.4]
assign _T_401 = _T_335 & _T_332; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38167.4]
assign _T_406 = _T_335 & _T_333; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38175.4]
assign _T_411 = _T_335 & _T_334; // @[UserYanker.scala 61:53:freechips.rocketchip.system.LowRiscConfig.fir@38183.4]
assign _T_418_0 = Queue_16_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38192.4]
assign _T_418_1 = Queue_17_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38193.4]
assign _GEN_49 = 4'h1 == auto_in_aw_bits_id ? _T_418_1 : _T_418_0; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_2 = Queue_18_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38194.4]
assign _GEN_50 = 4'h2 == auto_in_aw_bits_id ? _T_418_2 : _GEN_49; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_3 = Queue_19_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38195.4]
assign _GEN_51 = 4'h3 == auto_in_aw_bits_id ? _T_418_3 : _GEN_50; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_4 = Queue_20_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38196.4]
assign _GEN_52 = 4'h4 == auto_in_aw_bits_id ? _T_418_4 : _GEN_51; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_5 = Queue_21_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38197.4]
assign _GEN_53 = 4'h5 == auto_in_aw_bits_id ? _T_418_5 : _GEN_52; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_6 = Queue_22_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38198.4]
assign _GEN_54 = 4'h6 == auto_in_aw_bits_id ? _T_418_6 : _GEN_53; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_7 = Queue_23_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38199.4]
assign _GEN_55 = 4'h7 == auto_in_aw_bits_id ? _T_418_7 : _GEN_54; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_8 = Queue_24_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38200.4]
assign _GEN_56 = 4'h8 == auto_in_aw_bits_id ? _T_418_8 : _GEN_55; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_9 = Queue_25_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38201.4]
assign _GEN_57 = 4'h9 == auto_in_aw_bits_id ? _T_418_9 : _GEN_56; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_10 = Queue_26_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38202.4]
assign _GEN_58 = 4'ha == auto_in_aw_bits_id ? _T_418_10 : _GEN_57; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_11 = Queue_27_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38203.4]
assign _GEN_59 = 4'hb == auto_in_aw_bits_id ? _T_418_11 : _GEN_58; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_12 = Queue_28_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38204.4]
assign _GEN_60 = 4'hc == auto_in_aw_bits_id ? _T_418_12 : _GEN_59; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_13 = Queue_29_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38205.4]
assign _GEN_61 = 4'hd == auto_in_aw_bits_id ? _T_418_13 : _GEN_60; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_14 = Queue_30_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38206.4]
assign _GEN_62 = 4'he == auto_in_aw_bits_id ? _T_418_14 : _GEN_61; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_418_15 = Queue_31_io_enq_ready; // @[UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38190.4 UserYanker.scala 67:25:freechips.rocketchip.system.LowRiscConfig.fir@38207.4]
assign _GEN_63 = 4'hf == auto_in_aw_bits_id ? _T_418_15 : _GEN_62; // @[UserYanker.scala 68:36:freechips.rocketchip.system.LowRiscConfig.fir@38208.4]
assign _T_486 = auto_out_b_valid == 1'h0; // @[UserYanker.scala 75:15:freechips.rocketchip.system.LowRiscConfig.fir@38249.4]
assign _T_443_0 = Queue_16_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38215.4]
assign _T_443_1 = Queue_17_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38216.4]
assign _GEN_65 = 4'h1 == auto_out_b_bits_id ? _T_443_1 : _T_443_0; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_2 = Queue_18_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38217.4]
assign _GEN_66 = 4'h2 == auto_out_b_bits_id ? _T_443_2 : _GEN_65; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_3 = Queue_19_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38218.4]
assign _GEN_67 = 4'h3 == auto_out_b_bits_id ? _T_443_3 : _GEN_66; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_4 = Queue_20_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38219.4]
assign _GEN_68 = 4'h4 == auto_out_b_bits_id ? _T_443_4 : _GEN_67; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_5 = Queue_21_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38220.4]
assign _GEN_69 = 4'h5 == auto_out_b_bits_id ? _T_443_5 : _GEN_68; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_6 = Queue_22_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38221.4]
assign _GEN_70 = 4'h6 == auto_out_b_bits_id ? _T_443_6 : _GEN_69; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_7 = Queue_23_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38222.4]
assign _GEN_71 = 4'h7 == auto_out_b_bits_id ? _T_443_7 : _GEN_70; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_8 = Queue_24_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38223.4]
assign _GEN_72 = 4'h8 == auto_out_b_bits_id ? _T_443_8 : _GEN_71; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_9 = Queue_25_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38224.4]
assign _GEN_73 = 4'h9 == auto_out_b_bits_id ? _T_443_9 : _GEN_72; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_10 = Queue_26_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38225.4]
assign _GEN_74 = 4'ha == auto_out_b_bits_id ? _T_443_10 : _GEN_73; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_11 = Queue_27_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38226.4]
assign _GEN_75 = 4'hb == auto_out_b_bits_id ? _T_443_11 : _GEN_74; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_12 = Queue_28_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38227.4]
assign _GEN_76 = 4'hc == auto_out_b_bits_id ? _T_443_12 : _GEN_75; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_13 = Queue_29_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38228.4]
assign _GEN_77 = 4'hd == auto_out_b_bits_id ? _T_443_13 : _GEN_76; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_14 = Queue_30_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38229.4]
assign _GEN_78 = 4'he == auto_out_b_bits_id ? _T_443_14 : _GEN_77; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_443_15 = Queue_31_io_deq_valid; // @[UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38213.4 UserYanker.scala 73:24:freechips.rocketchip.system.LowRiscConfig.fir@38230.4]
assign _GEN_79 = 4'hf == auto_out_b_bits_id ? _T_443_15 : _GEN_78; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_487 = _T_486 | _GEN_79; // @[UserYanker.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38250.4]
assign _T_489 = _T_487 | reset; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38252.4]
assign _T_490 = _T_489 == 1'h0; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38253.4]
assign _T_466_0 = Queue_16_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38233.4]
assign _T_466_1 = Queue_17_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38234.4]
assign _GEN_81 = 4'h1 == auto_out_b_bits_id ? _T_466_1 : _T_466_0; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_2 = Queue_18_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38235.4]
assign _GEN_82 = 4'h2 == auto_out_b_bits_id ? _T_466_2 : _GEN_81; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_3 = Queue_19_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38236.4]
assign _GEN_83 = 4'h3 == auto_out_b_bits_id ? _T_466_3 : _GEN_82; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_4 = Queue_20_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38237.4]
assign _GEN_84 = 4'h4 == auto_out_b_bits_id ? _T_466_4 : _GEN_83; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_5 = Queue_21_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38238.4]
assign _GEN_85 = 4'h5 == auto_out_b_bits_id ? _T_466_5 : _GEN_84; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_6 = Queue_22_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38239.4]
assign _GEN_86 = 4'h6 == auto_out_b_bits_id ? _T_466_6 : _GEN_85; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_7 = Queue_23_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38240.4]
assign _GEN_87 = 4'h7 == auto_out_b_bits_id ? _T_466_7 : _GEN_86; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_8 = Queue_24_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38241.4]
assign _GEN_88 = 4'h8 == auto_out_b_bits_id ? _T_466_8 : _GEN_87; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_9 = Queue_25_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38242.4]
assign _GEN_89 = 4'h9 == auto_out_b_bits_id ? _T_466_9 : _GEN_88; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_10 = Queue_26_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38243.4]
assign _GEN_90 = 4'ha == auto_out_b_bits_id ? _T_466_10 : _GEN_89; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_11 = Queue_27_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38244.4]
assign _GEN_91 = 4'hb == auto_out_b_bits_id ? _T_466_11 : _GEN_90; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_12 = Queue_28_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38245.4]
assign _GEN_92 = 4'hc == auto_out_b_bits_id ? _T_466_12 : _GEN_91; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_13 = Queue_29_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38246.4]
assign _GEN_93 = 4'hd == auto_out_b_bits_id ? _T_466_13 : _GEN_92; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_14 = Queue_30_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38247.4]
assign _GEN_94 = 4'he == auto_out_b_bits_id ? _T_466_14 : _GEN_93; // @[UserYanker.scala 77:26:freechips.rocketchip.system.LowRiscConfig.fir@38259.4]
assign _T_466_15 = Queue_31_io_deq_bits; // @[UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38231.4 UserYanker.scala 74:23:freechips.rocketchip.system.LowRiscConfig.fir@38248.4]
assign _T_492 = 16'h1 << auto_in_aw_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38261.4]
assign _T_494 = _T_492[0]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38263.4]
assign _T_495 = _T_492[1]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38264.4]
assign _T_496 = _T_492[2]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38265.4]
assign _T_497 = _T_492[3]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38266.4]
assign _T_498 = _T_492[4]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38267.4]
assign _T_499 = _T_492[5]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38268.4]
assign _T_500 = _T_492[6]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38269.4]
assign _T_501 = _T_492[7]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38270.4]
assign _T_502 = _T_492[8]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38271.4]
assign _T_503 = _T_492[9]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38272.4]
assign _T_504 = _T_492[10]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38273.4]
assign _T_505 = _T_492[11]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38274.4]
assign _T_506 = _T_492[12]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38275.4]
assign _T_507 = _T_492[13]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38276.4]
assign _T_508 = _T_492[14]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38277.4]
assign _T_509 = _T_492[15]; // @[UserYanker.scala 79:55:freechips.rocketchip.system.LowRiscConfig.fir@38278.4]
assign _T_511 = 16'h1 << auto_out_b_bits_id; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38280.4]
assign _T_513 = _T_511[0]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38282.4]
assign _T_514 = _T_511[1]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38283.4]
assign _T_515 = _T_511[2]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38284.4]
assign _T_516 = _T_511[3]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38285.4]
assign _T_517 = _T_511[4]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38286.4]
assign _T_518 = _T_511[5]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38287.4]
assign _T_519 = _T_511[6]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38288.4]
assign _T_520 = _T_511[7]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38289.4]
assign _T_521 = _T_511[8]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38290.4]
assign _T_522 = _T_511[9]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38291.4]
assign _T_523 = _T_511[10]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38292.4]
assign _T_524 = _T_511[11]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38293.4]
assign _T_525 = _T_511[12]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38294.4]
assign _T_526 = _T_511[13]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38295.4]
assign _T_527 = _T_511[14]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38296.4]
assign _T_528 = _T_511[15]; // @[UserYanker.scala 80:55:freechips.rocketchip.system.LowRiscConfig.fir@38297.4]
assign _T_529 = auto_out_b_valid & auto_in_b_ready; // @[UserYanker.scala 82:37:freechips.rocketchip.system.LowRiscConfig.fir@38298.4]
assign _T_531 = auto_in_aw_valid & auto_out_aw_ready; // @[UserYanker.scala 83:37:freechips.rocketchip.system.LowRiscConfig.fir@38301.4]
assign auto_in_aw_ready = auto_out_aw_ready & _GEN_63; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_b_bits_id = auto_out_b_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_b_bits_user = 4'hf == auto_out_b_bits_id ? _T_466_15 : _GEN_94; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_ar_ready = auto_out_ar_ready & _GEN_15; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_r_bits_id = auto_out_r_bits_id; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_r_bits_user = 4'hf == auto_out_r_bits_id ? _T_272_15 : _GEN_46; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@37825.4]
assign auto_out_aw_valid = auto_in_aw_valid & _GEN_63; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_id = auto_in_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_valid = auto_in_ar_valid & _GEN_15; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_id = auto_in_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@37824.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37828.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37829.4]
assign Queue_io_enq_valid = _T_338 & _T_300; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38068.4]
assign Queue_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38069.4]
assign Queue_io_deq_ready = _T_336 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38065.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37832.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37833.4]
assign Queue_1_io_enq_valid = _T_338 & _T_301; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38076.4]
assign Queue_1_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38077.4]
assign Queue_1_io_deq_ready = _T_341 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38073.4]
assign Queue_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37836.4]
assign Queue_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37837.4]
assign Queue_2_io_enq_valid = _T_338 & _T_302; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38084.4]
assign Queue_2_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38085.4]
assign Queue_2_io_deq_ready = _T_346 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38081.4]
assign Queue_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37840.4]
assign Queue_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37841.4]
assign Queue_3_io_enq_valid = _T_338 & _T_303; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38092.4]
assign Queue_3_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38093.4]
assign Queue_3_io_deq_ready = _T_351 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38089.4]
assign Queue_4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37844.4]
assign Queue_4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37845.4]
assign Queue_4_io_enq_valid = _T_338 & _T_304; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38100.4]
assign Queue_4_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38101.4]
assign Queue_4_io_deq_ready = _T_356 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38097.4]
assign Queue_5_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37848.4]
assign Queue_5_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37849.4]
assign Queue_5_io_enq_valid = _T_338 & _T_305; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38108.4]
assign Queue_5_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38109.4]
assign Queue_5_io_deq_ready = _T_361 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38105.4]
assign Queue_6_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37852.4]
assign Queue_6_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37853.4]
assign Queue_6_io_enq_valid = _T_338 & _T_306; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38116.4]
assign Queue_6_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38117.4]
assign Queue_6_io_deq_ready = _T_366 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38113.4]
assign Queue_7_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37856.4]
assign Queue_7_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37857.4]
assign Queue_7_io_enq_valid = _T_338 & _T_307; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38124.4]
assign Queue_7_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38125.4]
assign Queue_7_io_deq_ready = _T_371 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38121.4]
assign Queue_8_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37860.4]
assign Queue_8_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37861.4]
assign Queue_8_io_enq_valid = _T_338 & _T_308; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38132.4]
assign Queue_8_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38133.4]
assign Queue_8_io_deq_ready = _T_376 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38129.4]
assign Queue_9_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37864.4]
assign Queue_9_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37865.4]
assign Queue_9_io_enq_valid = _T_338 & _T_309; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38140.4]
assign Queue_9_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38141.4]
assign Queue_9_io_deq_ready = _T_381 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38137.4]
assign Queue_10_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37868.4]
assign Queue_10_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37869.4]
assign Queue_10_io_enq_valid = _T_338 & _T_310; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38148.4]
assign Queue_10_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38149.4]
assign Queue_10_io_deq_ready = _T_386 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38145.4]
assign Queue_11_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37872.4]
assign Queue_11_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37873.4]
assign Queue_11_io_enq_valid = _T_338 & _T_311; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38156.4]
assign Queue_11_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38157.4]
assign Queue_11_io_deq_ready = _T_391 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38153.4]
assign Queue_12_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37876.4]
assign Queue_12_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37877.4]
assign Queue_12_io_enq_valid = _T_338 & _T_312; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38164.4]
assign Queue_12_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38165.4]
assign Queue_12_io_deq_ready = _T_396 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38161.4]
assign Queue_13_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37880.4]
assign Queue_13_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37881.4]
assign Queue_13_io_enq_valid = _T_338 & _T_313; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38172.4]
assign Queue_13_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38173.4]
assign Queue_13_io_deq_ready = _T_401 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38169.4]
assign Queue_14_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37884.4]
assign Queue_14_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37885.4]
assign Queue_14_io_enq_valid = _T_338 & _T_314; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38180.4]
assign Queue_14_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38181.4]
assign Queue_14_io_deq_ready = _T_406 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38177.4]
assign Queue_15_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37888.4]
assign Queue_15_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37889.4]
assign Queue_15_io_enq_valid = _T_338 & _T_315; // @[UserYanker.scala 62:21:freechips.rocketchip.system.LowRiscConfig.fir@38188.4]
assign Queue_15_io_enq_bits = auto_in_ar_bits_user; // @[UserYanker.scala 63:21:freechips.rocketchip.system.LowRiscConfig.fir@38189.4]
assign Queue_15_io_deq_ready = _T_411 & auto_out_r_bits_last; // @[UserYanker.scala 61:21:freechips.rocketchip.system.LowRiscConfig.fir@38185.4]
assign Queue_16_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37892.4]
assign Queue_16_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37893.4]
assign Queue_16_io_enq_valid = _T_531 & _T_494; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38303.4]
assign Queue_16_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38304.4]
assign Queue_16_io_deq_ready = _T_529 & _T_513; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38300.4]
assign Queue_17_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37896.4]
assign Queue_17_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37897.4]
assign Queue_17_io_enq_valid = _T_531 & _T_495; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38310.4]
assign Queue_17_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38311.4]
assign Queue_17_io_deq_ready = _T_529 & _T_514; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38307.4]
assign Queue_18_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37900.4]
assign Queue_18_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37901.4]
assign Queue_18_io_enq_valid = _T_531 & _T_496; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38317.4]
assign Queue_18_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38318.4]
assign Queue_18_io_deq_ready = _T_529 & _T_515; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38314.4]
assign Queue_19_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37904.4]
assign Queue_19_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37905.4]
assign Queue_19_io_enq_valid = _T_531 & _T_497; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38324.4]
assign Queue_19_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38325.4]
assign Queue_19_io_deq_ready = _T_529 & _T_516; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38321.4]
assign Queue_20_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37908.4]
assign Queue_20_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37909.4]
assign Queue_20_io_enq_valid = _T_531 & _T_498; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38331.4]
assign Queue_20_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38332.4]
assign Queue_20_io_deq_ready = _T_529 & _T_517; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38328.4]
assign Queue_21_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37912.4]
assign Queue_21_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37913.4]
assign Queue_21_io_enq_valid = _T_531 & _T_499; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38338.4]
assign Queue_21_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38339.4]
assign Queue_21_io_deq_ready = _T_529 & _T_518; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38335.4]
assign Queue_22_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37916.4]
assign Queue_22_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37917.4]
assign Queue_22_io_enq_valid = _T_531 & _T_500; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38345.4]
assign Queue_22_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38346.4]
assign Queue_22_io_deq_ready = _T_529 & _T_519; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38342.4]
assign Queue_23_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37920.4]
assign Queue_23_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37921.4]
assign Queue_23_io_enq_valid = _T_531 & _T_501; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38352.4]
assign Queue_23_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38353.4]
assign Queue_23_io_deq_ready = _T_529 & _T_520; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38349.4]
assign Queue_24_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37924.4]
assign Queue_24_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37925.4]
assign Queue_24_io_enq_valid = _T_531 & _T_502; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38359.4]
assign Queue_24_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38360.4]
assign Queue_24_io_deq_ready = _T_529 & _T_521; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38356.4]
assign Queue_25_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37928.4]
assign Queue_25_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37929.4]
assign Queue_25_io_enq_valid = _T_531 & _T_503; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38366.4]
assign Queue_25_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38367.4]
assign Queue_25_io_deq_ready = _T_529 & _T_522; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38363.4]
assign Queue_26_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37932.4]
assign Queue_26_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37933.4]
assign Queue_26_io_enq_valid = _T_531 & _T_504; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38373.4]
assign Queue_26_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38374.4]
assign Queue_26_io_deq_ready = _T_529 & _T_523; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38370.4]
assign Queue_27_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37936.4]
assign Queue_27_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37937.4]
assign Queue_27_io_enq_valid = _T_531 & _T_505; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38380.4]
assign Queue_27_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38381.4]
assign Queue_27_io_deq_ready = _T_529 & _T_524; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38377.4]
assign Queue_28_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37940.4]
assign Queue_28_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37941.4]
assign Queue_28_io_enq_valid = _T_531 & _T_506; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38387.4]
assign Queue_28_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38388.4]
assign Queue_28_io_deq_ready = _T_529 & _T_525; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38384.4]
assign Queue_29_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37944.4]
assign Queue_29_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37945.4]
assign Queue_29_io_enq_valid = _T_531 & _T_507; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38394.4]
assign Queue_29_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38395.4]
assign Queue_29_io_deq_ready = _T_529 & _T_526; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38391.4]
assign Queue_30_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37948.4]
assign Queue_30_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37949.4]
assign Queue_30_io_enq_valid = _T_531 & _T_508; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38401.4]
assign Queue_30_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38402.4]
assign Queue_30_io_deq_ready = _T_529 & _T_527; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38398.4]
assign Queue_31_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37952.4]
assign Queue_31_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@37953.4]
assign Queue_31_io_enq_valid = _T_531 & _T_509; // @[UserYanker.scala 83:21:freechips.rocketchip.system.LowRiscConfig.fir@38408.4]
assign Queue_31_io_enq_bits = auto_in_aw_bits_user; // @[UserYanker.scala 84:21:freechips.rocketchip.system.LowRiscConfig.fir@38409.4]
assign Queue_31_io_deq_ready = _T_529 & _T_528; // @[UserYanker.scala 82:21:freechips.rocketchip.system.LowRiscConfig.fir@38405.4]
always @(posedge clock) begin
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_296) begin
$fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:54 assert (!out.r.valid || r_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38019.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_296) begin
$fatal; // @[UserYanker.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38020.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_490) begin
$fwrite(32'h80000002,"Assertion failed\n at UserYanker.scala:75 assert (!out.b.valid || b_valid) // Q must be ready faster than the response\n"); // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38255.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_490) begin
$fatal; // @[UserYanker.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38256.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module AXI4IdIndexer_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@38412.2]
output auto_in_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [6:0] auto_in_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [31:0] auto_in_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [7:0] auto_in_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [2:0] auto_in_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [1:0] auto_in_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [3:0] auto_in_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [2:0] auto_in_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [3:0] auto_in_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [10:0] auto_in_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_in_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [63:0] auto_in_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [7:0] auto_in_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_in_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [6:0] auto_in_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [1:0] auto_in_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [10:0] auto_in_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_in_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [6:0] auto_in_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [31:0] auto_in_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [7:0] auto_in_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [2:0] auto_in_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [1:0] auto_in_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [3:0] auto_in_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [2:0] auto_in_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [3:0] auto_in_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [10:0] auto_in_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_in_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_in_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [6:0] auto_in_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [63:0] auto_in_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [1:0] auto_in_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [10:0] auto_in_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_in_r_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [3:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [13:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [3:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [13:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [3:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output [13:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [3:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input [13:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@38415.4]
);
wire [2:0] _T_221; // @[IdIndexer.scala 56:81:freechips.rocketchip.system.LowRiscConfig.fir@38431.4]
wire [2:0] _T_223; // @[IdIndexer.scala 57:81:freechips.rocketchip.system.LowRiscConfig.fir@38434.4]
wire [17:0] _T_227; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@38441.4]
wire [17:0] _T_228; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@38443.4]
assign _T_221 = auto_in_ar_bits_id[6:4]; // @[IdIndexer.scala 56:81:freechips.rocketchip.system.LowRiscConfig.fir@38431.4]
assign _T_223 = auto_in_aw_bits_id[6:4]; // @[IdIndexer.scala 57:81:freechips.rocketchip.system.LowRiscConfig.fir@38434.4]
assign _T_227 = {auto_out_r_bits_user,auto_out_r_bits_id}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@38441.4]
assign _T_228 = {auto_out_b_bits_user,auto_out_b_bits_id}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@38443.4]
assign auto_in_aw_ready = auto_out_aw_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_w_ready = auto_out_w_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_b_valid = auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_b_bits_id = _T_228[6:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_b_bits_user = auto_out_b_bits_user[13:3]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_ar_ready = auto_out_ar_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_r_valid = auto_out_r_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_r_bits_id = _T_227[6:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_r_bits_user = auto_out_r_bits_user[13:3]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@38425.4]
assign auto_out_aw_valid = auto_in_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_id = auto_in_aw_bits_id[3:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_aw_bits_user = {auto_in_aw_bits_user,_T_223}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_w_valid = auto_in_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_b_ready = auto_in_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_valid = auto_in_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_id = auto_in_ar_bits_id[3:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_ar_bits_user = {auto_in_ar_bits_user,_T_221}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
assign auto_out_r_ready = auto_in_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@38424.4]
endmodule
module TLMonitor_15( // @[:freechips.rocketchip.system.LowRiscConfig.fir@38453.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38454.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38455.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [6:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input [6:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@38456.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@39625.4]
wire [12:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@38483.6]
wire [5:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@38484.6]
wire [5:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@38485.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@38486.6]
wire [31:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@38486.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@38487.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@38489.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38490.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@38491.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@38492.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@38493.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@38494.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@38495.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@38496.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38498.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38499.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38501.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38502.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@38503.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@38504.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@38505.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38506.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38507.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38508.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38509.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38510.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38511.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38512.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38513.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38514.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38515.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38516.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38517.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@38518.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@38519.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@38520.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38521.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38522.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38523.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38524.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38525.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38526.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38527.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38528.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38529.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38530.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38531.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38532.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38533.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38534.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38535.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38536.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38537.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38538.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38539.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38540.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38541.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38542.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38543.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38544.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@38551.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@38574.6]
wire [31:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@38577.8]
wire [32:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@38578.8]
wire [32:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@38579.8]
wire [32:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@38580.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@38581.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@38586.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@38607.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@38608.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@38614.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@38615.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@38620.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38622.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38623.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@38628.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@38629.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@38631.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@38632.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@38637.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@38639.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@38640.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@38646.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@38700.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@38702.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@38703.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@38726.6]
wire _T_205; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@38729.8]
wire _T_213; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@38737.8]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38740.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38741.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38760.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38762.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38763.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@38768.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@38770.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@38771.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@38785.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@38836.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@38878.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@38879.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@38880.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@38882.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@38883.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@38889.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@38920.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@38922.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@38923.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@38937.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@38968.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@38970.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@38971.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@38985.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@39035.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@39037.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@39038.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@39055.6]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@39064.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39066.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39067.8]
wire _T_406; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@39080.8]
wire _T_408; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@39082.8]
wire _T_409; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@39083.8]
wire _T_410; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@39088.8]
wire _T_412; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@39090.8]
wire _T_413; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@39091.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@39097.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@39155.6]
wire _T_462; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@39196.8]
wire _T_464; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@39198.8]
wire _T_465; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@39199.8]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@39214.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@39249.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@39285.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@39345.4]
wire [2:0] _T_540; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@39350.4]
wire _T_541; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@39351.4]
wire _T_542; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@39352.4]
reg [2:0] _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@39354.4]
reg [31:0] _RAND_0;
wire [3:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39355.4]
wire [3:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39356.4]
wire [2:0] _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39357.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39358.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@39369.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@39370.4]
reg [31:0] _RAND_2;
reg [2:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@39371.4]
reg [31:0] _RAND_3;
reg [6:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@39372.4]
reg [31:0] _RAND_4;
reg [31:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@39373.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@39374.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@39375.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@39377.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@39379.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@39380.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@39385.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@39387.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@39388.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@39393.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@39395.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@39396.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@39401.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@39403.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@39404.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@39409.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@39411.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@39412.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@39419.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@39427.4]
wire [12:0] _T_593; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@39429.4]
wire [5:0] _T_594; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@39430.4]
wire [5:0] _T_595; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@39431.4]
wire [2:0] _T_596; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@39432.4]
wire _T_597; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@39433.4]
reg [2:0] _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@39435.4]
reg [31:0] _RAND_6;
wire [3:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39436.4]
wire [3:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39437.4]
wire [2:0] _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39438.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39439.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@39450.4]
reg [31:0] _RAND_7;
reg [2:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@39452.4]
reg [31:0] _RAND_8;
reg [6:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@39453.4]
reg [31:0] _RAND_9;
reg _T_623; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@39455.4]
reg [31:0] _RAND_10;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@39456.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@39457.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@39459.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@39461.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@39462.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@39475.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@39477.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@39478.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@39483.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@39485.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@39486.6]
wire _T_646; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@39499.6]
wire _T_648; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@39501.6]
wire _T_649; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@39502.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@39509.4]
reg [127:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@39518.4]
reg [127:0] _RAND_11;
reg [2:0] _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@39528.4]
reg [31:0] _RAND_12;
wire [3:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39529.4]
wire [3:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39530.4]
wire [2:0] _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39531.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39532.4]
reg [2:0] _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@39551.4]
reg [31:0] _RAND_13;
wire [3:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39552.4]
wire [3:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39553.4]
wire [2:0] _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39554.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39555.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@39570.4]
wire [127:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@39573.6]
wire [127:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@39575.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@39576.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@39577.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@39579.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@39580.6]
wire [127:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@39572.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@39591.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@39593.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@39594.4]
wire [127:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@39596.6]
wire [127:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@39598.6]
wire [127:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@39599.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@39600.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@39602.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@39603.6]
wire [127:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@39595.4]
wire _T_724; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@39609.4]
wire _T_725; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@39610.4]
wire _T_726; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@39611.4]
wire _T_727; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@39612.4]
wire _T_729; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@39614.4]
wire _T_730; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@39615.4]
wire [127:0] _T_731; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@39620.4]
wire [127:0] _T_732; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@39621.4]
wire [127:0] _T_733; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@39622.4]
reg [31:0] _T_735; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@39624.4]
reg [31:0] _RAND_14;
wire _T_736; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@39627.4]
wire _T_737; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@39628.4]
wire _T_738; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@39629.4]
wire _T_739; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@39630.4]
wire _T_740; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@39631.4]
wire _T_741; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@39632.4]
wire _T_743; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@39634.4]
wire _T_744; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@39635.4]
wire [31:0] _T_746; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@39641.4]
wire _T_749; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@39645.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@38588.10]
wire _GEN_33; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@38660.10]
wire _GEN_49; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38743.10]
wire _GEN_59; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@38802.10]
wire _GEN_67; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@38853.10]
wire _GEN_75; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@38903.10]
wire _GEN_83; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@38951.10]
wire _GEN_91; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@38999.10]
wire _GEN_99; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39069.10]
wire _GEN_105; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@39110.10]
wire _GEN_111; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@39168.10]
wire _GEN_117; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@39236.10]
wire _GEN_119; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@39272.10]
wire _GEN_121; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@39307.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@39625.4]
.out(plusarg_reader_out)
);
assign _T_36 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@38483.6]
assign _T_37 = _T_36[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@38484.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@38485.6]
assign _GEN_18 = {{26'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@38486.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@38486.6]
assign _T_40 = _T_39 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@38487.6]
assign _T_42 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@38489.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@38490.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@38491.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@38492.6]
assign _T_46 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@38493.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@38494.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@38495.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@38496.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38498.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38499.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38501.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38502.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@38503.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@38504.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@38505.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38506.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38507.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38508.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38509.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38510.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38511.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38512.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38513.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38514.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38515.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38516.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38517.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@38518.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@38519.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@38520.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38521.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38522.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38523.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38524.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38525.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38526.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38527.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38528.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38529.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38530.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38531.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38532.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38533.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38534.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38535.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38536.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38537.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38538.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38539.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38540.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38541.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@38542.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@38543.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@38544.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@38551.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@38574.6]
assign _T_125 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@38577.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@38578.8]
assign _T_127 = $signed(_T_126) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@38579.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@38580.8]
assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@38581.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@38586.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@38607.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@38608.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@38614.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@38615.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@38620.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38622.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38623.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@38628.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@38629.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@38631.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@38632.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@38637.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@38639.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@38640.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@38646.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@38700.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@38702.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@38703.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@38726.6]
assign _T_205 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@38729.8]
assign _T_213 = _T_205 & _T_129; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@38737.8]
assign _T_216 = _T_213 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38740.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38741.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@38760.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38762.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38763.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@38768.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@38770.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@38771.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@38785.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@38836.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@38878.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@38879.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@38880.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@38882.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@38883.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@38889.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@38920.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@38922.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@38923.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@38937.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@38968.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@38970.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@38971.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@38985.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@39035.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@39037.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@39038.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@39055.6]
assign _T_398 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@39064.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39066.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39067.8]
assign _T_406 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@39080.8]
assign _T_408 = _T_406 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@39082.8]
assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@39083.8]
assign _T_410 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@39088.8]
assign _T_412 = _T_410 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@39090.8]
assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@39091.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@39097.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@39155.6]
assign _T_462 = _T_410 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@39196.8]
assign _T_464 = _T_462 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@39198.8]
assign _T_465 = _T_464 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@39199.8]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@39214.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@39249.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@39285.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@39345.4]
assign _T_540 = _T_38[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@39350.4]
assign _T_541 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@39351.4]
assign _T_542 = _T_541 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@39352.4]
assign _T_546 = _T_545 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39355.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39356.4]
assign _T_548 = _T_547[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39357.4]
assign _T_549 = _T_545 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39358.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@39374.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@39375.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@39377.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@39379.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@39380.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@39385.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@39387.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@39388.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@39393.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@39395.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@39396.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@39401.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@39403.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@39404.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@39409.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@39411.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@39412.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@39419.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@39427.4]
assign _T_593 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@39429.4]
assign _T_594 = _T_593[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@39430.4]
assign _T_595 = ~ _T_594; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@39431.4]
assign _T_596 = _T_595[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@39432.4]
assign _T_597 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@39433.4]
assign _T_601 = _T_600 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39436.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39437.4]
assign _T_603 = _T_602[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39438.4]
assign _T_604 = _T_600 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39439.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@39456.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@39457.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@39459.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@39461.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@39462.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@39475.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@39477.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@39478.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@39483.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@39485.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@39486.6]
assign _T_646 = io_in_d_bits_denied == _T_623; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@39499.6]
assign _T_648 = _T_646 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@39501.6]
assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@39502.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@39509.4]
assign _T_665 = _T_664 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39529.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39530.4]
assign _T_667 = _T_666[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39531.4]
assign _T_668 = _T_664 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39532.4]
assign _T_686 = _T_685 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39552.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39553.4]
assign _T_688 = _T_687[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@39554.4]
assign _T_689 = _T_685 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@39555.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@39570.4]
assign _T_702 = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@39573.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@39575.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@39576.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@39577.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@39579.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@39580.6]
assign _GEN_15 = _T_700 ? _T_702 : 128'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@39572.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@39591.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@39593.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@39594.4]
assign _T_717 = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@39596.6]
assign _T_718 = _GEN_15 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@39598.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@39599.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@39600.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@39602.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@39603.6]
assign _GEN_16 = _T_716 ? _T_717 : 128'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@39595.4]
assign _T_724 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@39609.4]
assign _T_725 = _GEN_15 != 128'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@39610.4]
assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@39611.4]
assign _T_727 = _T_724 | _T_726; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@39612.4]
assign _T_729 = _T_727 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@39614.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@39615.4]
assign _T_731 = _T_653 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@39620.4]
assign _T_732 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@39621.4]
assign _T_733 = _T_731 & _T_732; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@39622.4]
assign _T_736 = _T_653 != 128'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@39627.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@39628.4]
assign _T_738 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@39629.4]
assign _T_739 = _T_737 | _T_738; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@39630.4]
assign _T_740 = _T_735 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@39631.4]
assign _T_741 = _T_739 | _T_740; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@39632.4]
assign _T_743 = _T_741 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@39634.4]
assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@39635.4]
assign _T_746 = _T_735 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@39641.4]
assign _T_749 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@39645.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@38588.10]
assign _GEN_33 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@38660.10]
assign _GEN_49 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38743.10]
assign _GEN_59 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@38802.10]
assign _GEN_67 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@38853.10]
assign _GEN_75 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@38903.10]
assign _GEN_83 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@38951.10]
assign _GEN_91 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@38999.10]
assign _GEN_99 = io_in_d_valid & _T_394; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39069.10]
assign _GEN_105 = io_in_d_valid & _T_414; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@39110.10]
assign _GEN_111 = io_in_d_valid & _T_442; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@39168.10]
assign _GEN_117 = io_in_d_valid & _T_471; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@39236.10]
assign _GEN_119 = io_in_d_valid & _T_488; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@39272.10]
assign _GEN_121 = io_in_d_valid & _T_506; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@39307.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_623 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {4{`RANDOM}};
_T_653 = _RAND_11[127:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_664 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_685 = _RAND_13[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_735 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
if (_T_542) begin
_T_545 <= _T_540;
end else begin
_T_545 <= 3'h0;
end
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
if (_T_597) begin
_T_600 <= _T_596;
end else begin
_T_600 <= 3'h0;
end
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (_T_651) begin
_T_623 <= io_in_d_bits_denied;
end
if (reset) begin
_T_653 <= 128'h0;
end else begin
_T_653 <= _T_733;
end
if (reset) begin
_T_664 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
if (_T_542) begin
_T_664 <= _T_540;
end else begin
_T_664 <= 3'h0;
end
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
if (_T_597) begin
_T_685 <= _T_596;
end else begin
_T_685 <= 3'h0;
end
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_735 <= 32'h0;
end else begin
if (_T_749) begin
_T_735 <= 32'h0;
end else begin
_T_735 <= _T_746;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at MemoryBus.scala:65:46)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@38468.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@38469.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@38571.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@38572.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@38588.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@38589.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MemoryBus.scala:65:46)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@38595.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@38596.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@38602.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@38603.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MemoryBus.scala:65:46)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@38610.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@38611.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@38617.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@38618.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38625.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@38626.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@38634.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@38635.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@38642.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@38643.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@38660.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@38661.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MemoryBus.scala:65:46)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@38667.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@38668.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@38674.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@38675.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MemoryBus.scala:65:46)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@38682.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@38683.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@38689.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@38690.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@38697.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@38698.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MemoryBus.scala:65:46)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@38705.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@38706.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@38714.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@38715.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@38722.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@38723.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38743.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@38744.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@38750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@38751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@38757.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@38758.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38765.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@38766.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@38773.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@38774.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@38781.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@38782.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@38802.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@38803.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@38809.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@38810.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@38816.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@38817.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@38824.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@38825.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@38832.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@38833.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@38853.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@38854.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@38860.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@38861.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@38867.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@38868.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@38875.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@38876.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@38885.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@38886.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@38903.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@38904.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@38910.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@38911.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@38917.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@38918.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@38925.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@38926.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@38933.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@38934.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@38951.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@38952.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@38958.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@38959.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@38965.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@38966.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@38973.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@38974.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@38981.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@38982.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at MemoryBus.scala:65:46)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@38999.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@39000.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@39006.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@39007.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at MemoryBus.scala:65:46)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@39013.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@39014.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at MemoryBus.scala:65:46)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@39021.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@39022.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@39029.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@39030.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at MemoryBus.scala:65:46)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@39040.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@39041.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@39061.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@39062.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MemoryBus.scala:65:46)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39069.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@39070.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@39077.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@39078.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@39085.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@39086.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at MemoryBus.scala:65:46)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@39093.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@39094.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@39103.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@39104.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@39110.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@39111.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at MemoryBus.scala:65:46)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@39118.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@39119.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@39126.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@39127.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@39134.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@39135.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@39142.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@39143.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at MemoryBus.scala:65:46)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@39151.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@39152.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@39161.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@39162.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@39168.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@39169.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at MemoryBus.scala:65:46)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@39176.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@39177.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@39184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@39185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@39192.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@39193.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@39201.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@39202.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at MemoryBus.scala:65:46)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@39210.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@39211.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@39220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@39221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@39228.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@39229.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@39236.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@39237.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at MemoryBus.scala:65:46)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@39245.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@39246.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@39255.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@39256.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@39263.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@39264.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@39272.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@39273.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at MemoryBus.scala:65:46)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@39281.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@39282.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@39291.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@39292.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at MemoryBus.scala:65:46)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@39299.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@39300.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at MemoryBus.scala:65:46)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@39307.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@39308.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at MemoryBus.scala:65:46)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@39316.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@39317.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at MemoryBus.scala:65:46)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@39326.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@39327.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at MemoryBus.scala:65:46)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@39334.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@39335.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at MemoryBus.scala:65:46)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@39342.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@39343.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@39382.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@39383.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@39390.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@39391.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@39398.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@39399.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@39406.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@39407.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@39414.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@39415.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@39464.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@39465.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@39472.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@39473.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@39480.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@39481.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@39488.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@39489.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@39496.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@39497.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_649) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at MemoryBus.scala:65:46)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@39504.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_649) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@39505.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at MemoryBus.scala:65:46)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@39582.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@39583.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MemoryBus.scala:65:46)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@39605.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@39606.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_730) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at MemoryBus.scala:65:46)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@39617.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_730) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@39618.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_744) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at MemoryBus.scala:65:46)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@39637.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_744) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@39638.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_77( // @[:freechips.rocketchip.system.LowRiscConfig.fir@39706.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39707.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39708.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input [6:0] io_enq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input [31:0] io_enq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input [7:0] io_enq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input [10:0] io_enq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input io_enq_bits_wen, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [6:0] io_deq_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [31:0] io_deq_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [7:0] io_deq_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [1:0] io_deq_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output io_deq_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [3:0] io_deq_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [2:0] io_deq_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [3:0] io_deq_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output [10:0] io_deq_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
output io_deq_bits_wen // @[:freechips.rocketchip.system.LowRiscConfig.fir@39709.4]
);
reg [6:0] _T_35_id [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_0;
wire [6:0] _T_35_id__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_id__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [6:0] _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_id__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_id__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_id__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _T_35_addr [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_1;
wire [31:0] _T_35_addr__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_addr__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [31:0] _T_35_addr__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_addr__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_addr__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_addr__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [7:0] _T_35_len [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_2;
wire [7:0] _T_35_len__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_len__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [7:0] _T_35_len__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_len__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_len__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_len__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [2:0] _T_35_size [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_3;
wire [2:0] _T_35_size__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_size__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [2:0] _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_size__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_size__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_size__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [1:0] _T_35_burst [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_4;
wire [1:0] _T_35_burst__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_burst__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [1:0] _T_35_burst__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_burst__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_burst__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_burst__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg _T_35_lock [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_5;
wire _T_35_lock__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_lock__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_lock__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_lock__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_lock__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_lock__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [3:0] _T_35_cache [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_6;
wire [3:0] _T_35_cache__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_cache__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [3:0] _T_35_cache__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_cache__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_cache__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_cache__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [2:0] _T_35_prot [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_7;
wire [2:0] _T_35_prot__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_prot__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [2:0] _T_35_prot__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_prot__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_prot__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_prot__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [3:0] _T_35_qos [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_8;
wire [3:0] _T_35_qos__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_qos__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [3:0] _T_35_qos__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_qos__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_qos__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_qos__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [10:0] _T_35_user [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_9;
wire [10:0] _T_35_user__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_user__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire [10:0] _T_35_user__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_user__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_user__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_user__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg _T_35_wen [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg [31:0] _RAND_10;
wire _T_35_wen__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_wen__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_wen__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_wen__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_wen__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
wire _T_35_wen__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@39712.4]
reg [31:0] _RAND_11;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@39714.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@39717.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@39720.4]
wire _GEN_17; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@39775.6]
wire _GEN_30; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@39762.4]
wire _GEN_29; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@39762.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@39739.4]
wire _T_50; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@39743.4]
assign _T_35_id__T_52_addr = 1'h0;
assign _T_35_id__T_52_data = _T_35_id[_T_35_id__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_id__T_48_data = io_enq_bits_id;
assign _T_35_id__T_48_addr = 1'h0;
assign _T_35_id__T_48_mask = 1'h1;
assign _T_35_id__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_addr__T_52_addr = 1'h0;
assign _T_35_addr__T_52_data = _T_35_addr[_T_35_addr__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_addr__T_48_data = io_enq_bits_addr;
assign _T_35_addr__T_48_addr = 1'h0;
assign _T_35_addr__T_48_mask = 1'h1;
assign _T_35_addr__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_len__T_52_addr = 1'h0;
assign _T_35_len__T_52_data = _T_35_len[_T_35_len__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_len__T_48_data = io_enq_bits_len;
assign _T_35_len__T_48_addr = 1'h0;
assign _T_35_len__T_48_mask = 1'h1;
assign _T_35_len__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_size__T_52_addr = 1'h0;
assign _T_35_size__T_52_data = _T_35_size[_T_35_size__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_size__T_48_data = io_enq_bits_size;
assign _T_35_size__T_48_addr = 1'h0;
assign _T_35_size__T_48_mask = 1'h1;
assign _T_35_size__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_burst__T_52_addr = 1'h0;
assign _T_35_burst__T_52_data = _T_35_burst[_T_35_burst__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_burst__T_48_data = 2'h1;
assign _T_35_burst__T_48_addr = 1'h0;
assign _T_35_burst__T_48_mask = 1'h1;
assign _T_35_burst__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_lock__T_52_addr = 1'h0;
assign _T_35_lock__T_52_data = _T_35_lock[_T_35_lock__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_lock__T_48_data = 1'h0;
assign _T_35_lock__T_48_addr = 1'h0;
assign _T_35_lock__T_48_mask = 1'h1;
assign _T_35_lock__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_cache__T_52_addr = 1'h0;
assign _T_35_cache__T_52_data = _T_35_cache[_T_35_cache__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_cache__T_48_data = 4'h0;
assign _T_35_cache__T_48_addr = 1'h0;
assign _T_35_cache__T_48_mask = 1'h1;
assign _T_35_cache__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_prot__T_52_addr = 1'h0;
assign _T_35_prot__T_52_data = _T_35_prot[_T_35_prot__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_prot__T_48_data = 3'h1;
assign _T_35_prot__T_48_addr = 1'h0;
assign _T_35_prot__T_48_mask = 1'h1;
assign _T_35_prot__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_qos__T_52_addr = 1'h0;
assign _T_35_qos__T_52_data = _T_35_qos[_T_35_qos__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_qos__T_48_data = 4'h0;
assign _T_35_qos__T_48_addr = 1'h0;
assign _T_35_qos__T_48_mask = 1'h1;
assign _T_35_qos__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_user__T_52_addr = 1'h0;
assign _T_35_user__T_52_data = _T_35_user[_T_35_user__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_user__T_48_data = io_enq_bits_user;
assign _T_35_user__T_48_addr = 1'h0;
assign _T_35_user__T_48_mask = 1'h1;
assign _T_35_user__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_35_wen__T_52_addr = 1'h0;
assign _T_35_wen__T_52_data = _T_35_wen[_T_35_wen__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
assign _T_35_wen__T_48_data = io_enq_bits_wen;
assign _T_35_wen__T_48_addr = 1'h0;
assign _T_35_wen__T_48_mask = 1'h1;
assign _T_35_wen__T_48_en = _T_39 ? _GEN_17 : _T_42;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@39714.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@39717.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@39720.4]
assign _GEN_17 = io_deq_ready ? 1'h0 : _T_42; // @[Decoupled.scala 245:27:freechips.rocketchip.system.LowRiscConfig.fir@39775.6]
assign _GEN_30 = _T_39 ? _GEN_17 : _T_42; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@39762.4]
assign _GEN_29 = _T_39 ? 1'h0 : _T_45; // @[Decoupled.scala 242:18:freechips.rocketchip.system.LowRiscConfig.fir@39762.4]
assign _T_49 = _GEN_30 != _GEN_29; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@39739.4]
assign _T_50 = _T_39 == 1'h0; // @[Decoupled.scala 236:19:freechips.rocketchip.system.LowRiscConfig.fir@39743.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@39746.4]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_50; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@39744.4 Decoupled.scala 241:40:freechips.rocketchip.system.LowRiscConfig.fir@39760.6]
assign io_deq_bits_id = _T_39 ? io_enq_bits_id : _T_35_id__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39758.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39773.6]
assign io_deq_bits_addr = _T_39 ? io_enq_bits_addr : _T_35_addr__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39757.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39772.6]
assign io_deq_bits_len = _T_39 ? io_enq_bits_len : _T_35_len__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39756.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39771.6]
assign io_deq_bits_size = _T_39 ? io_enq_bits_size : _T_35_size__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39755.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39770.6]
assign io_deq_bits_burst = _T_39 ? 2'h1 : _T_35_burst__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39754.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39769.6]
assign io_deq_bits_lock = _T_39 ? 1'h0 : _T_35_lock__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39753.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39768.6]
assign io_deq_bits_cache = _T_39 ? 4'h0 : _T_35_cache__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39752.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39767.6]
assign io_deq_bits_prot = _T_39 ? 3'h1 : _T_35_prot__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39751.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39766.6]
assign io_deq_bits_qos = _T_39 ? 4'h0 : _T_35_qos__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39750.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39765.6]
assign io_deq_bits_user = _T_39 ? io_enq_bits_user : _T_35_user__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39749.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39764.6]
assign io_deq_bits_wen = _T_39 ? io_enq_bits_wen : _T_35_wen__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@39748.4 Decoupled.scala 243:19:freechips.rocketchip.system.LowRiscConfig.fir@39763.6]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_id[initvar] = _RAND_0[6:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_addr[initvar] = _RAND_1[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_len[initvar] = _RAND_2[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_size[initvar] = _RAND_3[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_burst[initvar] = _RAND_4[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_lock[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_cache[initvar] = _RAND_6[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_prot[initvar] = _RAND_7[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_8 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_qos[initvar] = _RAND_8[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_9 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_user[initvar] = _RAND_9[10:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_10 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_wen[initvar] = _RAND_10[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_37 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_id__T_48_en & _T_35_id__T_48_mask) begin
_T_35_id[_T_35_id__T_48_addr] <= _T_35_id__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_addr__T_48_en & _T_35_addr__T_48_mask) begin
_T_35_addr[_T_35_addr__T_48_addr] <= _T_35_addr__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_len__T_48_en & _T_35_len__T_48_mask) begin
_T_35_len[_T_35_len__T_48_addr] <= _T_35_len__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_size__T_48_en & _T_35_size__T_48_mask) begin
_T_35_size[_T_35_size__T_48_addr] <= _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_burst__T_48_en & _T_35_burst__T_48_mask) begin
_T_35_burst[_T_35_burst__T_48_addr] <= _T_35_burst__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_lock__T_48_en & _T_35_lock__T_48_mask) begin
_T_35_lock[_T_35_lock__T_48_addr] <= _T_35_lock__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_cache__T_48_en & _T_35_cache__T_48_mask) begin
_T_35_cache[_T_35_cache__T_48_addr] <= _T_35_cache__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_prot__T_48_en & _T_35_prot__T_48_mask) begin
_T_35_prot[_T_35_prot__T_48_addr] <= _T_35_prot__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_qos__T_48_en & _T_35_qos__T_48_mask) begin
_T_35_qos[_T_35_qos__T_48_addr] <= _T_35_qos__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_user__T_48_en & _T_35_user__T_48_mask) begin
_T_35_user[_T_35_user__T_48_addr] <= _T_35_user__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if(_T_35_wen__T_48_en & _T_35_wen__T_48_mask) begin
_T_35_wen[_T_35_wen__T_48_addr] <= _T_35_wen__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@39711.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
if (_T_39) begin
if (io_deq_ready) begin
_T_37 <= 1'h0;
end else begin
_T_37 <= _T_42;
end
end else begin
_T_37 <= _T_42;
end
end
end
end
endmodule
module TLToAXI4_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@39786.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39787.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39788.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [6:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [6:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [6:0] auto_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [31:0] auto_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [7:0] auto_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [2:0] auto_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [1:0] auto_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [3:0] auto_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [2:0] auto_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [3:0] auto_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [10:0] auto_out_aw_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [63:0] auto_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [7:0] auto_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [6:0] auto_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [1:0] auto_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [10:0] auto_out_b_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [6:0] auto_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [31:0] auto_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [7:0] auto_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [2:0] auto_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [1:0] auto_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [3:0] auto_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [2:0] auto_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [3:0] auto_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output [10:0] auto_out_ar_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
output auto_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [6:0] auto_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [63:0] auto_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [1:0] auto_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input [10:0] auto_out_r_bits_user, // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
input auto_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@39789.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [6:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire [6:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire [7:0] Queue_io_enq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_io_enq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire [7:0] Queue_io_deq_bits_strb; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_io_deq_bits_last; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [6:0] Queue_1_io_enq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [31:0] Queue_1_io_enq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [7:0] Queue_1_io_enq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [2:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [10:0] Queue_1_io_enq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_enq_bits_wen; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [6:0] Queue_1_io_deq_bits_id; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [31:0] Queue_1_io_deq_bits_addr; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [7:0] Queue_1_io_deq_bits_len; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [2:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [1:0] Queue_1_io_deq_bits_burst; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_deq_bits_lock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [3:0] Queue_1_io_deq_bits_cache; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [2:0] Queue_1_io_deq_bits_prot; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [3:0] Queue_1_io_deq_bits_qos; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire [10:0] Queue_1_io_deq_bits_user; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire Queue_1_io_deq_bits_wen; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
wire _T_1293; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@40230.4]
wire _T_1294; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@40231.4]
reg _T_5617; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@46032.4]
reg [31:0] _RAND_0;
reg _T_5586; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45990.4]
reg [31:0] _RAND_1;
reg _T_5555; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45948.4]
reg [31:0] _RAND_2;
reg _T_5524; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45906.4]
reg [31:0] _RAND_3;
reg _T_5493; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45864.4]
reg [31:0] _RAND_4;
reg _T_5462; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45822.4]
reg [31:0] _RAND_5;
reg _T_5431; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45780.4]
reg [31:0] _RAND_6;
reg _T_5400; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45738.4]
reg [31:0] _RAND_7;
reg _T_5369; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45696.4]
reg [31:0] _RAND_8;
reg _T_5338; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45654.4]
reg [31:0] _RAND_9;
reg _T_5307; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45612.4]
reg [31:0] _RAND_10;
reg _T_5276; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45570.4]
reg [31:0] _RAND_11;
reg _T_5245; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45528.4]
reg [31:0] _RAND_12;
reg _T_5214; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45486.4]
reg [31:0] _RAND_13;
reg _T_5183; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45444.4]
reg [31:0] _RAND_14;
reg _T_5152; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45402.4]
reg [31:0] _RAND_15;
reg _T_5121; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45360.4]
reg [31:0] _RAND_16;
reg _T_5090; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45318.4]
reg [31:0] _RAND_17;
reg _T_5059; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45276.4]
reg [31:0] _RAND_18;
reg _T_5028; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45234.4]
reg [31:0] _RAND_19;
reg _T_4997; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45192.4]
reg [31:0] _RAND_20;
reg _T_4966; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45150.4]
reg [31:0] _RAND_21;
reg _T_4935; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45108.4]
reg [31:0] _RAND_22;
reg _T_4904; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45066.4]
reg [31:0] _RAND_23;
reg _T_4873; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@45024.4]
reg [31:0] _RAND_24;
reg _T_4842; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44982.4]
reg [31:0] _RAND_25;
reg _T_4811; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44940.4]
reg [31:0] _RAND_26;
reg _T_4780; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44898.4]
reg [31:0] _RAND_27;
reg _T_4749; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44856.4]
reg [31:0] _RAND_28;
reg _T_4718; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44814.4]
reg [31:0] _RAND_29;
reg _T_4687; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44772.4]
reg [31:0] _RAND_30;
reg _T_4656; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44730.4]
reg [31:0] _RAND_31;
reg _T_4625; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44688.4]
reg [31:0] _RAND_32;
reg _T_4594; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44646.4]
reg [31:0] _RAND_33;
reg _T_4563; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44604.4]
reg [31:0] _RAND_34;
reg _T_4532; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44562.4]
reg [31:0] _RAND_35;
reg _T_4501; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44520.4]
reg [31:0] _RAND_36;
reg _T_4470; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44478.4]
reg [31:0] _RAND_37;
reg _T_4439; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44436.4]
reg [31:0] _RAND_38;
reg _T_4408; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44394.4]
reg [31:0] _RAND_39;
reg _T_4377; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44352.4]
reg [31:0] _RAND_40;
reg _T_4346; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44310.4]
reg [31:0] _RAND_41;
reg _T_4315; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44268.4]
reg [31:0] _RAND_42;
reg _T_4284; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44226.4]
reg [31:0] _RAND_43;
reg _T_4253; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44184.4]
reg [31:0] _RAND_44;
reg _T_4222; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44142.4]
reg [31:0] _RAND_45;
reg _T_4191; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44100.4]
reg [31:0] _RAND_46;
reg _T_4160; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44058.4]
reg [31:0] _RAND_47;
reg _T_4129; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@44016.4]
reg [31:0] _RAND_48;
reg _T_4098; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43974.4]
reg [31:0] _RAND_49;
reg _T_4067; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43932.4]
reg [31:0] _RAND_50;
reg _T_4036; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43890.4]
reg [31:0] _RAND_51;
reg _T_4005; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43848.4]
reg [31:0] _RAND_52;
reg _T_3974; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43806.4]
reg [31:0] _RAND_53;
reg _T_3943; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43764.4]
reg [31:0] _RAND_54;
reg _T_3912; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43722.4]
reg [31:0] _RAND_55;
reg _T_3881; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43680.4]
reg [31:0] _RAND_56;
reg _T_3850; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43638.4]
reg [31:0] _RAND_57;
reg _T_3819; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43596.4]
reg [31:0] _RAND_58;
reg _T_3788; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43554.4]
reg [31:0] _RAND_59;
reg _T_3757; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43512.4]
reg [31:0] _RAND_60;
reg _T_3726; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43470.4]
reg [31:0] _RAND_61;
reg _T_3695; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43428.4]
reg [31:0] _RAND_62;
reg _T_3664; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43386.4]
reg [31:0] _RAND_63;
reg _T_3633; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43344.4]
reg [31:0] _RAND_64;
reg _T_3602; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43302.4]
reg [31:0] _RAND_65;
reg _T_3571; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43260.4]
reg [31:0] _RAND_66;
reg _T_3540; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43218.4]
reg [31:0] _RAND_67;
reg _T_3509; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43176.4]
reg [31:0] _RAND_68;
reg _T_3478; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43134.4]
reg [31:0] _RAND_69;
reg _T_3447; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43092.4]
reg [31:0] _RAND_70;
reg _T_3416; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43050.4]
reg [31:0] _RAND_71;
reg _T_3385; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@43008.4]
reg [31:0] _RAND_72;
reg _T_3354; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42966.4]
reg [31:0] _RAND_73;
reg _T_3323; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42924.4]
reg [31:0] _RAND_74;
reg _T_3292; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42882.4]
reg [31:0] _RAND_75;
reg _T_3261; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42840.4]
reg [31:0] _RAND_76;
reg _T_3230; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42798.4]
reg [31:0] _RAND_77;
reg _T_3199; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42756.4]
reg [31:0] _RAND_78;
reg _T_3168; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42714.4]
reg [31:0] _RAND_79;
reg _T_3137; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42672.4]
reg [31:0] _RAND_80;
reg _T_3106; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42630.4]
reg [31:0] _RAND_81;
reg _T_3075; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42588.4]
reg [31:0] _RAND_82;
reg _T_3044; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42546.4]
reg [31:0] _RAND_83;
reg _T_3013; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42504.4]
reg [31:0] _RAND_84;
reg _T_2982; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42462.4]
reg [31:0] _RAND_85;
reg _T_2951; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42420.4]
reg [31:0] _RAND_86;
reg _T_2920; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42378.4]
reg [31:0] _RAND_87;
reg _T_2889; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42336.4]
reg [31:0] _RAND_88;
reg _T_2858; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42294.4]
reg [31:0] _RAND_89;
reg _T_2827; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42252.4]
reg [31:0] _RAND_90;
reg _T_2796; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42210.4]
reg [31:0] _RAND_91;
reg _T_2765; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42168.4]
reg [31:0] _RAND_92;
reg _T_2734; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42126.4]
reg [31:0] _RAND_93;
reg _T_2703; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42084.4]
reg [31:0] _RAND_94;
reg _T_2672; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42042.4]
reg [31:0] _RAND_95;
reg _T_2641; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@42000.4]
reg [31:0] _RAND_96;
reg _T_2610; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41958.4]
reg [31:0] _RAND_97;
reg _T_2579; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41916.4]
reg [31:0] _RAND_98;
reg _T_2548; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41874.4]
reg [31:0] _RAND_99;
reg _T_2517; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41832.4]
reg [31:0] _RAND_100;
reg _T_2486; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41790.4]
reg [31:0] _RAND_101;
reg _T_2455; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41748.4]
reg [31:0] _RAND_102;
reg _T_2424; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41706.4]
reg [31:0] _RAND_103;
reg _T_2393; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41664.4]
reg [31:0] _RAND_104;
reg _T_2362; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41622.4]
reg [31:0] _RAND_105;
reg _T_2331; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41580.4]
reg [31:0] _RAND_106;
reg _T_2300; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41538.4]
reg [31:0] _RAND_107;
reg _T_2269; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41496.4]
reg [31:0] _RAND_108;
reg _T_2238; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41454.4]
reg [31:0] _RAND_109;
reg _T_2207; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41412.4]
reg [31:0] _RAND_110;
reg _T_2176; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41370.4]
reg [31:0] _RAND_111;
reg _T_2145; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41328.4]
reg [31:0] _RAND_112;
reg _T_2114; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41286.4]
reg [31:0] _RAND_113;
reg _T_2083; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41244.4]
reg [31:0] _RAND_114;
reg _T_2052; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41202.4]
reg [31:0] _RAND_115;
reg _T_2021; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41160.4]
reg [31:0] _RAND_116;
reg _T_1990; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41118.4]
reg [31:0] _RAND_117;
reg _T_1959; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41076.4]
reg [31:0] _RAND_118;
reg _T_1928; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@41034.4]
reg [31:0] _RAND_119;
reg _T_1897; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40992.4]
reg [31:0] _RAND_120;
reg _T_1866; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40950.4]
reg [31:0] _RAND_121;
reg _T_1835; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40908.4]
reg [31:0] _RAND_122;
reg _T_1804; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40866.4]
reg [31:0] _RAND_123;
reg _T_1773; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40824.4]
reg [31:0] _RAND_124;
reg _T_1742; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40782.4]
reg [31:0] _RAND_125;
reg _T_1711; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40740.4]
reg [31:0] _RAND_126;
reg _T_1680; // @[ToAXI4.scala 225:28:freechips.rocketchip.system.LowRiscConfig.fir@40698.4]
reg [31:0] _RAND_127;
wire _GEN_131; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_132; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_133; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_134; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_135; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_136; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_137; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_138; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_139; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_140; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_141; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_142; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_143; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_144; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_145; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_146; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_147; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_148; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_149; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_150; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_151; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_152; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_153; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_154; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_155; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_156; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_157; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_158; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_159; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_160; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_161; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_162; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_163; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_164; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_165; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_166; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_167; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_168; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_169; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_170; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_171; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_172; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_173; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_174; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_175; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_176; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_177; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_178; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_179; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_180; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_181; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_182; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_183; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_184; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_185; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_186; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_187; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_188; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_189; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_190; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_191; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_192; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_193; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_194; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_195; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_196; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_197; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_198; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_199; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_200; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_201; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_202; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_203; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_204; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_205; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_206; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_207; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_208; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_209; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_210; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_211; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_212; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_213; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_214; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_215; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_216; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_217; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_218; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_219; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_220; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_221; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_222; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_223; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_224; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_225; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_226; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_227; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_228; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_229; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_230; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_231; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_232; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_233; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_234; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_235; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_236; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_237; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_238; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_239; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_240; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_241; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_242; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_243; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_244; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_245; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_246; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_247; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_248; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_249; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_250; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_251; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_252; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_253; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_254; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_255; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_256; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _GEN_257; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
reg [2:0] _T_1305; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@40241.4]
reg [31:0] _RAND_128;
wire _T_1309; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@40245.4]
wire _T_1375; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
wire _T_1376; // @[ToAXI4.scala 177:21:freechips.rocketchip.system.LowRiscConfig.fir@40362.4]
reg _T_1363; // @[ToAXI4.scala 160:30:freechips.rocketchip.system.LowRiscConfig.fir@40337.4]
reg [31:0] _RAND_129;
wire _T_1336_ready; // @[ToAXI4.scala 146:25:freechips.rocketchip.system.LowRiscConfig.fir@40279.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@40313.4]
wire _T_1377; // @[ToAXI4.scala 177:52:freechips.rocketchip.system.LowRiscConfig.fir@40363.4]
wire _T_1339_ready; // @[ToAXI4.scala 147:23:freechips.rocketchip.system.LowRiscConfig.fir@40281.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@40290.4]
wire _T_1378; // @[ToAXI4.scala 177:70:freechips.rocketchip.system.LowRiscConfig.fir@40364.4]
wire _T_1379; // @[ToAXI4.scala 177:34:freechips.rocketchip.system.LowRiscConfig.fir@40365.4]
wire _T_1380; // @[ToAXI4.scala 177:28:freechips.rocketchip.system.LowRiscConfig.fir@40366.4]
wire _T_1295; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40232.4]
wire [12:0] _T_1297; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@40234.4]
wire [5:0] _T_1298; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@40235.4]
wire [5:0] _T_1299; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@40236.4]
wire [2:0] _T_1300; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@40237.4]
wire [2:0] _T_1303; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@40240.4]
wire [3:0] _T_1306; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@40242.4]
wire [3:0] _T_1307; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@40243.4]
wire [2:0] _T_1308; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@40244.4]
wire _T_1310; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@40246.4]
wire _T_1311; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@40247.4]
wire _T_1312; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@40248.4]
wire [9:0] _GEN_389; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@40273.4]
wire [9:0] _T_1326; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@40273.4]
wire [9:0] _GEN_390; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.LowRiscConfig.fir@40274.4]
wire [9:0] _T_1327; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.LowRiscConfig.fir@40274.4]
wire [6:0] _T_1328; // @[ToAXI4.scala 137:50:freechips.rocketchip.system.LowRiscConfig.fir@40275.4]
wire [2:0] _T_1329; // @[ToAXI4.scala 138:50:freechips.rocketchip.system.LowRiscConfig.fir@40276.4]
wire [6:0] _T_1330; // @[ToAXI4.scala 141:50:freechips.rocketchip.system.LowRiscConfig.fir@40277.4]
wire [2:0] _T_1331; // @[ToAXI4.scala 142:50:freechips.rocketchip.system.LowRiscConfig.fir@40278.4]
wire _T_1354_bits_wen; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@40314.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@40315.4]
wire _T_1358; // @[ToAXI4.scala 154:42:freechips.rocketchip.system.LowRiscConfig.fir@40330.4]
wire _T_1354_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@40314.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@40326.4]
wire _T_1365; // @[ToAXI4.scala 161:38:freechips.rocketchip.system.LowRiscConfig.fir@40340.6]
wire [6:0] _GEN_3; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_4; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_5; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_6; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_7; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_8; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_9; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_10; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_11; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_12; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_13; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_14; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_15; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_16; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_17; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_18; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_19; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_20; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_21; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_22; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_23; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_24; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_25; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_26; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_27; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_28; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_29; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_30; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_31; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_32; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_33; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_34; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_35; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_36; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_37; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_38; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_39; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_40; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_41; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_42; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_43; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_44; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_45; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_46; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_47; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_48; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_49; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_50; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_51; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_52; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_53; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_54; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_55; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_56; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_57; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_58; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_59; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_60; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_61; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_62; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_63; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_64; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_65; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_66; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_67; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_68; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_69; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_70; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_71; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_72; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_73; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_74; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_75; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_76; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_77; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_78; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_79; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_80; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_81; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_82; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_83; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_84; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_85; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_86; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_87; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_88; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_89; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_90; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_91; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_92; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_93; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_94; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_95; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_96; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_97; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_98; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_99; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_100; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_101; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_102; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_103; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_104; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_105; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_106; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_107; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_108; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_109; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_110; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_111; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_112; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_113; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_114; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_115; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_116; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_117; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_118; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_119; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_120; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_121; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_122; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_123; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_124; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_125; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_126; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_127; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_128; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [6:0] _GEN_129; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
wire [17:0] _T_1368; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@40347.4]
wire [10:0] _T_1369; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@40348.4]
wire [10:0] _T_1370; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@40349.4]
wire _T_1372; // @[ToAXI4.scala 168:31:freechips.rocketchip.system.LowRiscConfig.fir@40352.4]
wire _T_1382; // @[ToAXI4.scala 178:31:freechips.rocketchip.system.LowRiscConfig.fir@40369.4]
wire _T_1383; // @[ToAXI4.scala 178:61:freechips.rocketchip.system.LowRiscConfig.fir@40370.4]
wire _T_1384; // @[ToAXI4.scala 178:69:freechips.rocketchip.system.LowRiscConfig.fir@40371.4]
wire _T_1385; // @[ToAXI4.scala 178:51:freechips.rocketchip.system.LowRiscConfig.fir@40372.4]
wire _T_1386; // @[ToAXI4.scala 178:45:freechips.rocketchip.system.LowRiscConfig.fir@40373.4]
wire _T_1389; // @[ToAXI4.scala 180:43:freechips.rocketchip.system.LowRiscConfig.fir@40377.4]
reg _T_1393; // @[ToAXI4.scala 187:30:freechips.rocketchip.system.LowRiscConfig.fir@40384.4]
reg [31:0] _RAND_130;
wire _T_1394; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40385.4]
wire _T_1395; // @[ToAXI4.scala 188:42:freechips.rocketchip.system.LowRiscConfig.fir@40387.6]
wire _T_1396; // @[ToAXI4.scala 190:32:freechips.rocketchip.system.LowRiscConfig.fir@40390.4]
wire _T_1397; // @[ToAXI4.scala 193:36:freechips.rocketchip.system.LowRiscConfig.fir@40392.4]
wire _T_1399; // @[ToAXI4.scala 194:24:freechips.rocketchip.system.LowRiscConfig.fir@40395.4]
reg _T_1401; // @[ToAXI4.scala 199:28:freechips.rocketchip.system.LowRiscConfig.fir@40397.4]
reg [31:0] _RAND_131;
wire _T_1403; // @[ToAXI4.scala 201:39:freechips.rocketchip.system.LowRiscConfig.fir@40402.4]
reg _T_1405; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@40403.4]
reg [31:0] _RAND_132;
wire _GEN_260; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@40404.4]
wire _T_1407; // @[ToAXI4.scala 202:39:freechips.rocketchip.system.LowRiscConfig.fir@40408.4]
wire _T_1408; // @[ToAXI4.scala 203:39:freechips.rocketchip.system.LowRiscConfig.fir@40409.4]
wire _T_1409; // @[ToAXI4.scala 205:100:freechips.rocketchip.system.LowRiscConfig.fir@40410.4]
wire [127:0] _T_1416; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@40435.4]
wire _T_1418; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40437.4]
wire _T_1419; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40438.4]
wire _T_1420; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40439.4]
wire _T_1421; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40440.4]
wire _T_1422; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40441.4]
wire _T_1423; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40442.4]
wire _T_1424; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40443.4]
wire _T_1425; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40444.4]
wire _T_1426; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40445.4]
wire _T_1427; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40446.4]
wire _T_1428; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40447.4]
wire _T_1429; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40448.4]
wire _T_1430; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40449.4]
wire _T_1431; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40450.4]
wire _T_1432; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40451.4]
wire _T_1433; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40452.4]
wire _T_1434; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40453.4]
wire _T_1435; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40454.4]
wire _T_1436; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40455.4]
wire _T_1437; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40456.4]
wire _T_1438; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40457.4]
wire _T_1439; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40458.4]
wire _T_1440; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40459.4]
wire _T_1441; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40460.4]
wire _T_1442; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40461.4]
wire _T_1443; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40462.4]
wire _T_1444; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40463.4]
wire _T_1445; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40464.4]
wire _T_1446; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40465.4]
wire _T_1447; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40466.4]
wire _T_1448; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40467.4]
wire _T_1449; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40468.4]
wire _T_1450; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40469.4]
wire _T_1451; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40470.4]
wire _T_1452; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40471.4]
wire _T_1453; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40472.4]
wire _T_1454; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40473.4]
wire _T_1455; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40474.4]
wire _T_1456; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40475.4]
wire _T_1457; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40476.4]
wire _T_1458; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40477.4]
wire _T_1459; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40478.4]
wire _T_1460; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40479.4]
wire _T_1461; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40480.4]
wire _T_1462; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40481.4]
wire _T_1463; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40482.4]
wire _T_1464; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40483.4]
wire _T_1465; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40484.4]
wire _T_1466; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40485.4]
wire _T_1467; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40486.4]
wire _T_1468; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40487.4]
wire _T_1469; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40488.4]
wire _T_1470; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40489.4]
wire _T_1471; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40490.4]
wire _T_1472; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40491.4]
wire _T_1473; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40492.4]
wire _T_1474; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40493.4]
wire _T_1475; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40494.4]
wire _T_1476; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40495.4]
wire _T_1477; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40496.4]
wire _T_1478; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40497.4]
wire _T_1479; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40498.4]
wire _T_1480; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40499.4]
wire _T_1481; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40500.4]
wire _T_1482; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40501.4]
wire _T_1483; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40502.4]
wire _T_1484; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40503.4]
wire _T_1485; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40504.4]
wire _T_1486; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40505.4]
wire _T_1487; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40506.4]
wire _T_1488; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40507.4]
wire _T_1489; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40508.4]
wire _T_1490; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40509.4]
wire _T_1491; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40510.4]
wire _T_1492; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40511.4]
wire _T_1493; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40512.4]
wire _T_1494; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40513.4]
wire _T_1495; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40514.4]
wire _T_1496; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40515.4]
wire _T_1497; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40516.4]
wire _T_1498; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40517.4]
wire _T_1499; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40518.4]
wire _T_1500; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40519.4]
wire _T_1501; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40520.4]
wire _T_1502; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40521.4]
wire _T_1503; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40522.4]
wire _T_1504; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40523.4]
wire _T_1505; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40524.4]
wire _T_1506; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40525.4]
wire _T_1507; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40526.4]
wire _T_1508; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40527.4]
wire _T_1509; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40528.4]
wire _T_1510; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40529.4]
wire _T_1511; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40530.4]
wire _T_1512; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40531.4]
wire _T_1513; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40532.4]
wire _T_1514; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40533.4]
wire _T_1515; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40534.4]
wire _T_1516; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40535.4]
wire _T_1517; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40536.4]
wire _T_1518; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40537.4]
wire _T_1519; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40538.4]
wire _T_1520; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40539.4]
wire _T_1521; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40540.4]
wire _T_1522; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40541.4]
wire _T_1523; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40542.4]
wire _T_1524; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40543.4]
wire _T_1525; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40544.4]
wire _T_1526; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40545.4]
wire _T_1527; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40546.4]
wire _T_1528; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40547.4]
wire _T_1529; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40548.4]
wire _T_1530; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40549.4]
wire _T_1531; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40550.4]
wire _T_1532; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40551.4]
wire _T_1533; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40552.4]
wire _T_1534; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40553.4]
wire _T_1535; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40554.4]
wire _T_1536; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40555.4]
wire _T_1537; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40556.4]
wire _T_1538; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40557.4]
wire _T_1539; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40558.4]
wire _T_1540; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40559.4]
wire _T_1541; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40560.4]
wire _T_1542; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40561.4]
wire _T_1543; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40562.4]
wire _T_1544; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40563.4]
wire _T_1545; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40564.4]
wire [6:0] _T_1546; // @[ToAXI4.scala 214:31:freechips.rocketchip.system.LowRiscConfig.fir@40565.4]
wire [127:0] _T_1548; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@40567.4]
wire _T_1550; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40569.4]
wire _T_1551; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40570.4]
wire _T_1552; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40571.4]
wire _T_1553; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40572.4]
wire _T_1554; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40573.4]
wire _T_1555; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40574.4]
wire _T_1556; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40575.4]
wire _T_1557; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40576.4]
wire _T_1558; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40577.4]
wire _T_1559; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40578.4]
wire _T_1560; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40579.4]
wire _T_1561; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40580.4]
wire _T_1562; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40581.4]
wire _T_1563; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40582.4]
wire _T_1564; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40583.4]
wire _T_1565; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40584.4]
wire _T_1566; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40585.4]
wire _T_1567; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40586.4]
wire _T_1568; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40587.4]
wire _T_1569; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40588.4]
wire _T_1570; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40589.4]
wire _T_1571; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40590.4]
wire _T_1572; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40591.4]
wire _T_1573; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40592.4]
wire _T_1574; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40593.4]
wire _T_1575; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40594.4]
wire _T_1576; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40595.4]
wire _T_1577; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40596.4]
wire _T_1578; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40597.4]
wire _T_1579; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40598.4]
wire _T_1580; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40599.4]
wire _T_1581; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40600.4]
wire _T_1582; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40601.4]
wire _T_1583; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40602.4]
wire _T_1584; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40603.4]
wire _T_1585; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40604.4]
wire _T_1586; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40605.4]
wire _T_1587; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40606.4]
wire _T_1588; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40607.4]
wire _T_1589; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40608.4]
wire _T_1590; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40609.4]
wire _T_1591; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40610.4]
wire _T_1592; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40611.4]
wire _T_1593; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40612.4]
wire _T_1594; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40613.4]
wire _T_1595; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40614.4]
wire _T_1596; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40615.4]
wire _T_1597; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40616.4]
wire _T_1598; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40617.4]
wire _T_1599; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40618.4]
wire _T_1600; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40619.4]
wire _T_1601; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40620.4]
wire _T_1602; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40621.4]
wire _T_1603; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40622.4]
wire _T_1604; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40623.4]
wire _T_1605; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40624.4]
wire _T_1606; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40625.4]
wire _T_1607; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40626.4]
wire _T_1608; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40627.4]
wire _T_1609; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40628.4]
wire _T_1610; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40629.4]
wire _T_1611; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40630.4]
wire _T_1612; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40631.4]
wire _T_1613; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40632.4]
wire _T_1614; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40633.4]
wire _T_1615; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40634.4]
wire _T_1616; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40635.4]
wire _T_1617; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40636.4]
wire _T_1618; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40637.4]
wire _T_1619; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40638.4]
wire _T_1620; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40639.4]
wire _T_1621; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40640.4]
wire _T_1622; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40641.4]
wire _T_1623; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40642.4]
wire _T_1624; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40643.4]
wire _T_1625; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40644.4]
wire _T_1626; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40645.4]
wire _T_1627; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40646.4]
wire _T_1628; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40647.4]
wire _T_1629; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40648.4]
wire _T_1630; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40649.4]
wire _T_1631; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40650.4]
wire _T_1632; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40651.4]
wire _T_1633; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40652.4]
wire _T_1634; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40653.4]
wire _T_1635; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40654.4]
wire _T_1636; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40655.4]
wire _T_1637; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40656.4]
wire _T_1638; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40657.4]
wire _T_1639; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40658.4]
wire _T_1640; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40659.4]
wire _T_1641; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40660.4]
wire _T_1642; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40661.4]
wire _T_1643; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40662.4]
wire _T_1644; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40663.4]
wire _T_1645; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40664.4]
wire _T_1646; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40665.4]
wire _T_1647; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40666.4]
wire _T_1648; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40667.4]
wire _T_1649; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40668.4]
wire _T_1650; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40669.4]
wire _T_1651; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40670.4]
wire _T_1652; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40671.4]
wire _T_1653; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40672.4]
wire _T_1654; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40673.4]
wire _T_1655; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40674.4]
wire _T_1656; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40675.4]
wire _T_1657; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40676.4]
wire _T_1658; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40677.4]
wire _T_1659; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40678.4]
wire _T_1660; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40679.4]
wire _T_1661; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40680.4]
wire _T_1662; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40681.4]
wire _T_1663; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40682.4]
wire _T_1664; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40683.4]
wire _T_1665; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40684.4]
wire _T_1666; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40685.4]
wire _T_1667; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40686.4]
wire _T_1668; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40687.4]
wire _T_1669; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40688.4]
wire _T_1670; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40689.4]
wire _T_1671; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40690.4]
wire _T_1672; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40691.4]
wire _T_1673; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40692.4]
wire _T_1674; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40693.4]
wire _T_1675; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40694.4]
wire _T_1676; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40695.4]
wire _T_1677; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40696.4]
wire _T_1678; // @[ToAXI4.scala 215:23:freechips.rocketchip.system.LowRiscConfig.fir@40697.4]
wire _T_1684; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40701.4]
wire _T_1685; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40702.4]
wire _T_1686; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40703.4]
wire _T_1687; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40704.4]
wire _T_1688; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40705.4]
wire _T_1690; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40707.4]
wire [1:0] _T_1691; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40708.4]
wire [1:0] _T_1692; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40709.4]
wire _T_1693; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40710.4]
wire _T_1694; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40712.4]
wire _T_1696; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40714.4]
wire _T_1698; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40716.4]
wire _T_1699; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40717.4]
wire _T_1700; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40722.4]
wire _T_1701; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40723.4]
wire _T_1702; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40724.4]
wire _T_1704; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40726.4]
wire _T_1705; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40727.4]
wire _T_1716; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40744.4]
wire _T_1717; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40745.4]
wire _T_1719; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40747.4]
wire _T_1721; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40749.4]
wire [1:0] _T_1722; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40750.4]
wire [1:0] _T_1723; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40751.4]
wire _T_1724; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40752.4]
wire _T_1725; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40754.4]
wire _T_1727; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40756.4]
wire _T_1729; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40758.4]
wire _T_1730; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40759.4]
wire _T_1731; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40764.4]
wire _T_1732; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40765.4]
wire _T_1733; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40766.4]
wire _T_1735; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40768.4]
wire _T_1736; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40769.4]
wire _T_1747; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40786.4]
wire _T_1748; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40787.4]
wire _T_1750; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40789.4]
wire _T_1752; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40791.4]
wire [1:0] _T_1753; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40792.4]
wire [1:0] _T_1754; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40793.4]
wire _T_1755; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40794.4]
wire _T_1756; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40796.4]
wire _T_1758; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40798.4]
wire _T_1760; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40800.4]
wire _T_1761; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40801.4]
wire _T_1762; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40806.4]
wire _T_1763; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40807.4]
wire _T_1764; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40808.4]
wire _T_1766; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40810.4]
wire _T_1767; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40811.4]
wire _T_1778; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40828.4]
wire _T_1779; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40829.4]
wire _T_1781; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40831.4]
wire _T_1783; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40833.4]
wire [1:0] _T_1784; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40834.4]
wire [1:0] _T_1785; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40835.4]
wire _T_1786; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40836.4]
wire _T_1787; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40838.4]
wire _T_1789; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40840.4]
wire _T_1791; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40842.4]
wire _T_1792; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40843.4]
wire _T_1793; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40848.4]
wire _T_1794; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40849.4]
wire _T_1795; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40850.4]
wire _T_1797; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40852.4]
wire _T_1798; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40853.4]
wire _T_1809; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40870.4]
wire _T_1810; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40871.4]
wire _T_1812; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40873.4]
wire _T_1814; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40875.4]
wire [1:0] _T_1815; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40876.4]
wire [1:0] _T_1816; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40877.4]
wire _T_1817; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40878.4]
wire _T_1818; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40880.4]
wire _T_1820; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40882.4]
wire _T_1822; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40884.4]
wire _T_1823; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40885.4]
wire _T_1824; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40890.4]
wire _T_1825; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40891.4]
wire _T_1826; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40892.4]
wire _T_1828; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40894.4]
wire _T_1829; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40895.4]
wire _T_1840; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40912.4]
wire _T_1841; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40913.4]
wire _T_1843; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40915.4]
wire _T_1845; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40917.4]
wire [1:0] _T_1846; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40918.4]
wire [1:0] _T_1847; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40919.4]
wire _T_1848; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40920.4]
wire _T_1849; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40922.4]
wire _T_1851; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40924.4]
wire _T_1853; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40926.4]
wire _T_1854; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40927.4]
wire _T_1855; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40932.4]
wire _T_1856; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40933.4]
wire _T_1857; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40934.4]
wire _T_1859; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40936.4]
wire _T_1860; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40937.4]
wire _T_1871; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40954.4]
wire _T_1872; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40955.4]
wire _T_1874; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40957.4]
wire _T_1876; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40959.4]
wire [1:0] _T_1877; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40960.4]
wire [1:0] _T_1878; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40961.4]
wire _T_1879; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40962.4]
wire _T_1880; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40964.4]
wire _T_1882; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40966.4]
wire _T_1884; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40968.4]
wire _T_1885; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40969.4]
wire _T_1886; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40974.4]
wire _T_1887; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40975.4]
wire _T_1888; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40976.4]
wire _T_1890; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40978.4]
wire _T_1891; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40979.4]
wire _T_1902; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40996.4]
wire _T_1903; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40997.4]
wire _T_1905; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40999.4]
wire _T_1907; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41001.4]
wire [1:0] _T_1908; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41002.4]
wire [1:0] _T_1909; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41003.4]
wire _T_1910; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41004.4]
wire _T_1911; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41006.4]
wire _T_1913; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41008.4]
wire _T_1915; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41010.4]
wire _T_1916; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41011.4]
wire _T_1917; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41016.4]
wire _T_1918; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41017.4]
wire _T_1919; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41018.4]
wire _T_1921; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41020.4]
wire _T_1922; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41021.4]
wire _T_1933; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41038.4]
wire _T_1934; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41039.4]
wire _T_1936; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41041.4]
wire _T_1938; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41043.4]
wire [1:0] _T_1939; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41044.4]
wire [1:0] _T_1940; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41045.4]
wire _T_1941; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41046.4]
wire _T_1942; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41048.4]
wire _T_1944; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41050.4]
wire _T_1946; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41052.4]
wire _T_1947; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41053.4]
wire _T_1948; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41058.4]
wire _T_1949; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41059.4]
wire _T_1950; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41060.4]
wire _T_1952; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41062.4]
wire _T_1953; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41063.4]
wire _T_1964; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41080.4]
wire _T_1965; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41081.4]
wire _T_1967; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41083.4]
wire _T_1969; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41085.4]
wire [1:0] _T_1970; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41086.4]
wire [1:0] _T_1971; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41087.4]
wire _T_1972; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41088.4]
wire _T_1973; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41090.4]
wire _T_1975; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41092.4]
wire _T_1977; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41094.4]
wire _T_1978; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41095.4]
wire _T_1979; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41100.4]
wire _T_1980; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41101.4]
wire _T_1981; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41102.4]
wire _T_1983; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41104.4]
wire _T_1984; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41105.4]
wire _T_1995; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41122.4]
wire _T_1996; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41123.4]
wire _T_1998; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41125.4]
wire _T_2000; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41127.4]
wire [1:0] _T_2001; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41128.4]
wire [1:0] _T_2002; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41129.4]
wire _T_2003; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41130.4]
wire _T_2004; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41132.4]
wire _T_2006; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41134.4]
wire _T_2008; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41136.4]
wire _T_2009; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41137.4]
wire _T_2010; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41142.4]
wire _T_2011; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41143.4]
wire _T_2012; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41144.4]
wire _T_2014; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41146.4]
wire _T_2015; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41147.4]
wire _T_2026; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41164.4]
wire _T_2027; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41165.4]
wire _T_2029; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41167.4]
wire _T_2031; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41169.4]
wire [1:0] _T_2032; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41170.4]
wire [1:0] _T_2033; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41171.4]
wire _T_2034; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41172.4]
wire _T_2035; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41174.4]
wire _T_2037; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41176.4]
wire _T_2039; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41178.4]
wire _T_2040; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41179.4]
wire _T_2041; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41184.4]
wire _T_2042; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41185.4]
wire _T_2043; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41186.4]
wire _T_2045; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41188.4]
wire _T_2046; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41189.4]
wire _T_2057; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41206.4]
wire _T_2058; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41207.4]
wire _T_2060; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41209.4]
wire _T_2062; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41211.4]
wire [1:0] _T_2063; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41212.4]
wire [1:0] _T_2064; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41213.4]
wire _T_2065; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41214.4]
wire _T_2066; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41216.4]
wire _T_2068; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41218.4]
wire _T_2070; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41220.4]
wire _T_2071; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41221.4]
wire _T_2072; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41226.4]
wire _T_2073; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41227.4]
wire _T_2074; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41228.4]
wire _T_2076; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41230.4]
wire _T_2077; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41231.4]
wire _T_2088; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41248.4]
wire _T_2089; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41249.4]
wire _T_2091; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41251.4]
wire _T_2093; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41253.4]
wire [1:0] _T_2094; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41254.4]
wire [1:0] _T_2095; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41255.4]
wire _T_2096; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41256.4]
wire _T_2097; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41258.4]
wire _T_2099; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41260.4]
wire _T_2101; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41262.4]
wire _T_2102; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41263.4]
wire _T_2103; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41268.4]
wire _T_2104; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41269.4]
wire _T_2105; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41270.4]
wire _T_2107; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41272.4]
wire _T_2108; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41273.4]
wire _T_2119; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41290.4]
wire _T_2120; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41291.4]
wire _T_2122; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41293.4]
wire _T_2124; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41295.4]
wire [1:0] _T_2125; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41296.4]
wire [1:0] _T_2126; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41297.4]
wire _T_2127; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41298.4]
wire _T_2128; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41300.4]
wire _T_2130; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41302.4]
wire _T_2132; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41304.4]
wire _T_2133; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41305.4]
wire _T_2134; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41310.4]
wire _T_2135; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41311.4]
wire _T_2136; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41312.4]
wire _T_2138; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41314.4]
wire _T_2139; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41315.4]
wire _T_2150; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41332.4]
wire _T_2151; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41333.4]
wire _T_2153; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41335.4]
wire _T_2155; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41337.4]
wire [1:0] _T_2156; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41338.4]
wire [1:0] _T_2157; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41339.4]
wire _T_2158; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41340.4]
wire _T_2159; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41342.4]
wire _T_2161; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41344.4]
wire _T_2163; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41346.4]
wire _T_2164; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41347.4]
wire _T_2165; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41352.4]
wire _T_2166; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41353.4]
wire _T_2167; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41354.4]
wire _T_2169; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41356.4]
wire _T_2170; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41357.4]
wire _T_2181; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41374.4]
wire _T_2182; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41375.4]
wire _T_2184; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41377.4]
wire _T_2186; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41379.4]
wire [1:0] _T_2187; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41380.4]
wire [1:0] _T_2188; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41381.4]
wire _T_2189; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41382.4]
wire _T_2190; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41384.4]
wire _T_2192; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41386.4]
wire _T_2194; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41388.4]
wire _T_2195; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41389.4]
wire _T_2196; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41394.4]
wire _T_2197; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41395.4]
wire _T_2198; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41396.4]
wire _T_2200; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41398.4]
wire _T_2201; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41399.4]
wire _T_2212; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41416.4]
wire _T_2213; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41417.4]
wire _T_2215; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41419.4]
wire _T_2217; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41421.4]
wire [1:0] _T_2218; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41422.4]
wire [1:0] _T_2219; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41423.4]
wire _T_2220; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41424.4]
wire _T_2221; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41426.4]
wire _T_2223; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41428.4]
wire _T_2225; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41430.4]
wire _T_2226; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41431.4]
wire _T_2227; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41436.4]
wire _T_2228; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41437.4]
wire _T_2229; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41438.4]
wire _T_2231; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41440.4]
wire _T_2232; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41441.4]
wire _T_2243; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41458.4]
wire _T_2244; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41459.4]
wire _T_2246; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41461.4]
wire _T_2248; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41463.4]
wire [1:0] _T_2249; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41464.4]
wire [1:0] _T_2250; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41465.4]
wire _T_2251; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41466.4]
wire _T_2252; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41468.4]
wire _T_2254; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41470.4]
wire _T_2256; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41472.4]
wire _T_2257; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41473.4]
wire _T_2258; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41478.4]
wire _T_2259; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41479.4]
wire _T_2260; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41480.4]
wire _T_2262; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41482.4]
wire _T_2263; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41483.4]
wire _T_2274; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41500.4]
wire _T_2275; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41501.4]
wire _T_2277; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41503.4]
wire _T_2279; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41505.4]
wire [1:0] _T_2280; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41506.4]
wire [1:0] _T_2281; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41507.4]
wire _T_2282; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41508.4]
wire _T_2283; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41510.4]
wire _T_2285; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41512.4]
wire _T_2287; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41514.4]
wire _T_2288; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41515.4]
wire _T_2289; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41520.4]
wire _T_2290; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41521.4]
wire _T_2291; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41522.4]
wire _T_2293; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41524.4]
wire _T_2294; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41525.4]
wire _T_2305; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41542.4]
wire _T_2306; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41543.4]
wire _T_2308; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41545.4]
wire _T_2310; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41547.4]
wire [1:0] _T_2311; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41548.4]
wire [1:0] _T_2312; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41549.4]
wire _T_2313; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41550.4]
wire _T_2314; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41552.4]
wire _T_2316; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41554.4]
wire _T_2318; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41556.4]
wire _T_2319; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41557.4]
wire _T_2320; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41562.4]
wire _T_2321; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41563.4]
wire _T_2322; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41564.4]
wire _T_2324; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41566.4]
wire _T_2325; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41567.4]
wire _T_2336; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41584.4]
wire _T_2337; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41585.4]
wire _T_2339; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41587.4]
wire _T_2341; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41589.4]
wire [1:0] _T_2342; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41590.4]
wire [1:0] _T_2343; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41591.4]
wire _T_2344; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41592.4]
wire _T_2345; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41594.4]
wire _T_2347; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41596.4]
wire _T_2349; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41598.4]
wire _T_2350; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41599.4]
wire _T_2351; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41604.4]
wire _T_2352; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41605.4]
wire _T_2353; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41606.4]
wire _T_2355; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41608.4]
wire _T_2356; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41609.4]
wire _T_2367; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41626.4]
wire _T_2368; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41627.4]
wire _T_2370; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41629.4]
wire _T_2372; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41631.4]
wire [1:0] _T_2373; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41632.4]
wire [1:0] _T_2374; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41633.4]
wire _T_2375; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41634.4]
wire _T_2376; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41636.4]
wire _T_2378; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41638.4]
wire _T_2380; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41640.4]
wire _T_2381; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41641.4]
wire _T_2382; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41646.4]
wire _T_2383; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41647.4]
wire _T_2384; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41648.4]
wire _T_2386; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41650.4]
wire _T_2387; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41651.4]
wire _T_2398; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41668.4]
wire _T_2399; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41669.4]
wire _T_2401; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41671.4]
wire _T_2403; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41673.4]
wire [1:0] _T_2404; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41674.4]
wire [1:0] _T_2405; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41675.4]
wire _T_2406; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41676.4]
wire _T_2407; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41678.4]
wire _T_2409; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41680.4]
wire _T_2411; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41682.4]
wire _T_2412; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41683.4]
wire _T_2413; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41688.4]
wire _T_2414; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41689.4]
wire _T_2415; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41690.4]
wire _T_2417; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41692.4]
wire _T_2418; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41693.4]
wire _T_2429; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41710.4]
wire _T_2430; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41711.4]
wire _T_2432; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41713.4]
wire _T_2434; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41715.4]
wire [1:0] _T_2435; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41716.4]
wire [1:0] _T_2436; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41717.4]
wire _T_2437; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41718.4]
wire _T_2438; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41720.4]
wire _T_2440; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41722.4]
wire _T_2442; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41724.4]
wire _T_2443; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41725.4]
wire _T_2444; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41730.4]
wire _T_2445; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41731.4]
wire _T_2446; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41732.4]
wire _T_2448; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41734.4]
wire _T_2449; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41735.4]
wire _T_2460; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41752.4]
wire _T_2461; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41753.4]
wire _T_2463; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41755.4]
wire _T_2465; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41757.4]
wire [1:0] _T_2466; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41758.4]
wire [1:0] _T_2467; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41759.4]
wire _T_2468; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41760.4]
wire _T_2469; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41762.4]
wire _T_2471; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41764.4]
wire _T_2473; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41766.4]
wire _T_2474; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41767.4]
wire _T_2475; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41772.4]
wire _T_2476; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41773.4]
wire _T_2477; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41774.4]
wire _T_2479; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41776.4]
wire _T_2480; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41777.4]
wire _T_2491; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41794.4]
wire _T_2492; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41795.4]
wire _T_2494; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41797.4]
wire _T_2496; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41799.4]
wire [1:0] _T_2497; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41800.4]
wire [1:0] _T_2498; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41801.4]
wire _T_2499; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41802.4]
wire _T_2500; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41804.4]
wire _T_2502; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41806.4]
wire _T_2504; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41808.4]
wire _T_2505; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41809.4]
wire _T_2506; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41814.4]
wire _T_2507; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41815.4]
wire _T_2508; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41816.4]
wire _T_2510; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41818.4]
wire _T_2511; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41819.4]
wire _T_2522; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41836.4]
wire _T_2523; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41837.4]
wire _T_2525; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41839.4]
wire _T_2527; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41841.4]
wire [1:0] _T_2528; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41842.4]
wire [1:0] _T_2529; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41843.4]
wire _T_2530; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41844.4]
wire _T_2531; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41846.4]
wire _T_2533; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41848.4]
wire _T_2535; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41850.4]
wire _T_2536; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41851.4]
wire _T_2537; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41856.4]
wire _T_2538; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41857.4]
wire _T_2539; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41858.4]
wire _T_2541; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41860.4]
wire _T_2542; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41861.4]
wire _T_2553; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41878.4]
wire _T_2554; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41879.4]
wire _T_2556; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41881.4]
wire _T_2558; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41883.4]
wire [1:0] _T_2559; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41884.4]
wire [1:0] _T_2560; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41885.4]
wire _T_2561; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41886.4]
wire _T_2562; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41888.4]
wire _T_2564; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41890.4]
wire _T_2566; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41892.4]
wire _T_2567; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41893.4]
wire _T_2568; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41898.4]
wire _T_2569; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41899.4]
wire _T_2570; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41900.4]
wire _T_2572; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41902.4]
wire _T_2573; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41903.4]
wire _T_2584; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41920.4]
wire _T_2585; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41921.4]
wire _T_2587; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41923.4]
wire _T_2589; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41925.4]
wire [1:0] _T_2590; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41926.4]
wire [1:0] _T_2591; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41927.4]
wire _T_2592; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41928.4]
wire _T_2593; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41930.4]
wire _T_2595; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41932.4]
wire _T_2597; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41934.4]
wire _T_2598; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41935.4]
wire _T_2599; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41940.4]
wire _T_2600; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41941.4]
wire _T_2601; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41942.4]
wire _T_2603; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41944.4]
wire _T_2604; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41945.4]
wire _T_2615; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41962.4]
wire _T_2616; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41963.4]
wire _T_2618; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41965.4]
wire _T_2620; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41967.4]
wire [1:0] _T_2621; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41968.4]
wire [1:0] _T_2622; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41969.4]
wire _T_2623; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41970.4]
wire _T_2624; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41972.4]
wire _T_2626; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41974.4]
wire _T_2628; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41976.4]
wire _T_2629; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41977.4]
wire _T_2630; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41982.4]
wire _T_2631; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41983.4]
wire _T_2632; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41984.4]
wire _T_2634; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41986.4]
wire _T_2635; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41987.4]
wire _T_2646; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42004.4]
wire _T_2647; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42005.4]
wire _T_2649; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42007.4]
wire _T_2651; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42009.4]
wire [1:0] _T_2652; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42010.4]
wire [1:0] _T_2653; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42011.4]
wire _T_2654; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42012.4]
wire _T_2655; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42014.4]
wire _T_2657; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42016.4]
wire _T_2659; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42018.4]
wire _T_2660; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42019.4]
wire _T_2661; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42024.4]
wire _T_2662; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42025.4]
wire _T_2663; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42026.4]
wire _T_2665; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42028.4]
wire _T_2666; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42029.4]
wire _T_2677; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42046.4]
wire _T_2678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42047.4]
wire _T_2680; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42049.4]
wire _T_2682; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42051.4]
wire [1:0] _T_2683; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42052.4]
wire [1:0] _T_2684; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42053.4]
wire _T_2685; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42054.4]
wire _T_2686; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42056.4]
wire _T_2688; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42058.4]
wire _T_2690; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42060.4]
wire _T_2691; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42061.4]
wire _T_2692; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42066.4]
wire _T_2693; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42067.4]
wire _T_2694; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42068.4]
wire _T_2696; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42070.4]
wire _T_2697; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42071.4]
wire _T_2708; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42088.4]
wire _T_2709; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42089.4]
wire _T_2711; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42091.4]
wire _T_2713; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42093.4]
wire [1:0] _T_2714; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42094.4]
wire [1:0] _T_2715; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42095.4]
wire _T_2716; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42096.4]
wire _T_2717; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42098.4]
wire _T_2719; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42100.4]
wire _T_2721; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42102.4]
wire _T_2722; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42103.4]
wire _T_2723; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42108.4]
wire _T_2724; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42109.4]
wire _T_2725; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42110.4]
wire _T_2727; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42112.4]
wire _T_2728; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42113.4]
wire _T_2739; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42130.4]
wire _T_2740; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42131.4]
wire _T_2742; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42133.4]
wire _T_2744; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42135.4]
wire [1:0] _T_2745; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42136.4]
wire [1:0] _T_2746; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42137.4]
wire _T_2747; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42138.4]
wire _T_2748; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42140.4]
wire _T_2750; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42142.4]
wire _T_2752; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42144.4]
wire _T_2753; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42145.4]
wire _T_2754; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42150.4]
wire _T_2755; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42151.4]
wire _T_2756; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42152.4]
wire _T_2758; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42154.4]
wire _T_2759; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42155.4]
wire _T_2770; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42172.4]
wire _T_2771; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42173.4]
wire _T_2773; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42175.4]
wire _T_2775; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42177.4]
wire [1:0] _T_2776; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42178.4]
wire [1:0] _T_2777; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42179.4]
wire _T_2778; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42180.4]
wire _T_2779; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42182.4]
wire _T_2781; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42184.4]
wire _T_2783; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42186.4]
wire _T_2784; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42187.4]
wire _T_2785; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42192.4]
wire _T_2786; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42193.4]
wire _T_2787; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42194.4]
wire _T_2789; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42196.4]
wire _T_2790; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42197.4]
wire _T_2801; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42214.4]
wire _T_2802; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42215.4]
wire _T_2804; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42217.4]
wire _T_2806; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42219.4]
wire [1:0] _T_2807; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42220.4]
wire [1:0] _T_2808; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42221.4]
wire _T_2809; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42222.4]
wire _T_2810; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42224.4]
wire _T_2812; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42226.4]
wire _T_2814; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42228.4]
wire _T_2815; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42229.4]
wire _T_2816; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42234.4]
wire _T_2817; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42235.4]
wire _T_2818; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42236.4]
wire _T_2820; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42238.4]
wire _T_2821; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42239.4]
wire _T_2832; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42256.4]
wire _T_2833; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42257.4]
wire _T_2835; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42259.4]
wire _T_2837; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42261.4]
wire [1:0] _T_2838; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42262.4]
wire [1:0] _T_2839; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42263.4]
wire _T_2840; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42264.4]
wire _T_2841; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42266.4]
wire _T_2843; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42268.4]
wire _T_2845; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42270.4]
wire _T_2846; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42271.4]
wire _T_2847; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42276.4]
wire _T_2848; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42277.4]
wire _T_2849; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42278.4]
wire _T_2851; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42280.4]
wire _T_2852; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42281.4]
wire _T_2863; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42298.4]
wire _T_2864; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42299.4]
wire _T_2866; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42301.4]
wire _T_2868; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42303.4]
wire [1:0] _T_2869; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42304.4]
wire [1:0] _T_2870; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42305.4]
wire _T_2871; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42306.4]
wire _T_2872; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42308.4]
wire _T_2874; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42310.4]
wire _T_2876; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42312.4]
wire _T_2877; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42313.4]
wire _T_2878; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42318.4]
wire _T_2879; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42319.4]
wire _T_2880; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42320.4]
wire _T_2882; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42322.4]
wire _T_2883; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42323.4]
wire _T_2894; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42340.4]
wire _T_2895; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42341.4]
wire _T_2897; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42343.4]
wire _T_2899; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42345.4]
wire [1:0] _T_2900; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42346.4]
wire [1:0] _T_2901; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42347.4]
wire _T_2902; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42348.4]
wire _T_2903; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42350.4]
wire _T_2905; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42352.4]
wire _T_2907; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42354.4]
wire _T_2908; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42355.4]
wire _T_2909; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42360.4]
wire _T_2910; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42361.4]
wire _T_2911; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42362.4]
wire _T_2913; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42364.4]
wire _T_2914; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42365.4]
wire _T_2925; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42382.4]
wire _T_2926; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42383.4]
wire _T_2928; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42385.4]
wire _T_2930; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42387.4]
wire [1:0] _T_2931; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42388.4]
wire [1:0] _T_2932; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42389.4]
wire _T_2933; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42390.4]
wire _T_2934; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42392.4]
wire _T_2936; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42394.4]
wire _T_2938; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42396.4]
wire _T_2939; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42397.4]
wire _T_2940; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42402.4]
wire _T_2941; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42403.4]
wire _T_2942; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42404.4]
wire _T_2944; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42406.4]
wire _T_2945; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42407.4]
wire _T_2956; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42424.4]
wire _T_2957; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42425.4]
wire _T_2959; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42427.4]
wire _T_2961; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42429.4]
wire [1:0] _T_2962; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42430.4]
wire [1:0] _T_2963; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42431.4]
wire _T_2964; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42432.4]
wire _T_2965; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42434.4]
wire _T_2967; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42436.4]
wire _T_2969; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42438.4]
wire _T_2970; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42439.4]
wire _T_2971; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42444.4]
wire _T_2972; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42445.4]
wire _T_2973; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42446.4]
wire _T_2975; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42448.4]
wire _T_2976; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42449.4]
wire _T_2987; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42466.4]
wire _T_2988; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42467.4]
wire _T_2990; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42469.4]
wire _T_2992; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42471.4]
wire [1:0] _T_2993; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42472.4]
wire [1:0] _T_2994; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42473.4]
wire _T_2995; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42474.4]
wire _T_2996; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42476.4]
wire _T_2998; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42478.4]
wire _T_3000; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42480.4]
wire _T_3001; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42481.4]
wire _T_3002; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42486.4]
wire _T_3003; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42487.4]
wire _T_3004; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42488.4]
wire _T_3006; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42490.4]
wire _T_3007; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42491.4]
wire _T_3018; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42508.4]
wire _T_3019; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42509.4]
wire _T_3021; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42511.4]
wire _T_3023; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42513.4]
wire [1:0] _T_3024; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42514.4]
wire [1:0] _T_3025; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42515.4]
wire _T_3026; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42516.4]
wire _T_3027; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42518.4]
wire _T_3029; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42520.4]
wire _T_3031; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42522.4]
wire _T_3032; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42523.4]
wire _T_3033; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42528.4]
wire _T_3034; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42529.4]
wire _T_3035; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42530.4]
wire _T_3037; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42532.4]
wire _T_3038; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42533.4]
wire _T_3049; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42550.4]
wire _T_3050; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42551.4]
wire _T_3052; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42553.4]
wire _T_3054; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42555.4]
wire [1:0] _T_3055; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42556.4]
wire [1:0] _T_3056; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42557.4]
wire _T_3057; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42558.4]
wire _T_3058; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42560.4]
wire _T_3060; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42562.4]
wire _T_3062; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42564.4]
wire _T_3063; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42565.4]
wire _T_3064; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42570.4]
wire _T_3065; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42571.4]
wire _T_3066; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42572.4]
wire _T_3068; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42574.4]
wire _T_3069; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42575.4]
wire _T_3080; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42592.4]
wire _T_3081; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42593.4]
wire _T_3083; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42595.4]
wire _T_3085; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42597.4]
wire [1:0] _T_3086; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42598.4]
wire [1:0] _T_3087; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42599.4]
wire _T_3088; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42600.4]
wire _T_3089; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42602.4]
wire _T_3091; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42604.4]
wire _T_3093; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42606.4]
wire _T_3094; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42607.4]
wire _T_3095; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42612.4]
wire _T_3096; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42613.4]
wire _T_3097; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42614.4]
wire _T_3099; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42616.4]
wire _T_3100; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42617.4]
wire _T_3111; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42634.4]
wire _T_3112; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42635.4]
wire _T_3114; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42637.4]
wire _T_3116; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42639.4]
wire [1:0] _T_3117; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42640.4]
wire [1:0] _T_3118; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42641.4]
wire _T_3119; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42642.4]
wire _T_3120; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42644.4]
wire _T_3122; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42646.4]
wire _T_3124; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42648.4]
wire _T_3125; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42649.4]
wire _T_3126; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42654.4]
wire _T_3127; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42655.4]
wire _T_3128; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42656.4]
wire _T_3130; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42658.4]
wire _T_3131; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42659.4]
wire _T_3142; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42676.4]
wire _T_3143; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42677.4]
wire _T_3145; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42679.4]
wire _T_3147; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42681.4]
wire [1:0] _T_3148; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42682.4]
wire [1:0] _T_3149; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42683.4]
wire _T_3150; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42684.4]
wire _T_3151; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42686.4]
wire _T_3153; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42688.4]
wire _T_3155; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42690.4]
wire _T_3156; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42691.4]
wire _T_3157; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42696.4]
wire _T_3158; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42697.4]
wire _T_3159; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42698.4]
wire _T_3161; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42700.4]
wire _T_3162; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42701.4]
wire _T_3173; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42718.4]
wire _T_3174; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42719.4]
wire _T_3176; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42721.4]
wire _T_3178; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42723.4]
wire [1:0] _T_3179; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42724.4]
wire [1:0] _T_3180; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42725.4]
wire _T_3181; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42726.4]
wire _T_3182; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42728.4]
wire _T_3184; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42730.4]
wire _T_3186; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42732.4]
wire _T_3187; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42733.4]
wire _T_3188; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42738.4]
wire _T_3189; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42739.4]
wire _T_3190; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42740.4]
wire _T_3192; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42742.4]
wire _T_3193; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42743.4]
wire _T_3204; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42760.4]
wire _T_3205; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42761.4]
wire _T_3207; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42763.4]
wire _T_3209; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42765.4]
wire [1:0] _T_3210; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42766.4]
wire [1:0] _T_3211; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42767.4]
wire _T_3212; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42768.4]
wire _T_3213; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42770.4]
wire _T_3215; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42772.4]
wire _T_3217; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42774.4]
wire _T_3218; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42775.4]
wire _T_3219; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42780.4]
wire _T_3220; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42781.4]
wire _T_3221; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42782.4]
wire _T_3223; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42784.4]
wire _T_3224; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42785.4]
wire _T_3235; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42802.4]
wire _T_3236; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42803.4]
wire _T_3238; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42805.4]
wire _T_3240; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42807.4]
wire [1:0] _T_3241; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42808.4]
wire [1:0] _T_3242; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42809.4]
wire _T_3243; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42810.4]
wire _T_3244; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42812.4]
wire _T_3246; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42814.4]
wire _T_3248; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42816.4]
wire _T_3249; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42817.4]
wire _T_3250; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42822.4]
wire _T_3251; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42823.4]
wire _T_3252; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42824.4]
wire _T_3254; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42826.4]
wire _T_3255; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42827.4]
wire _T_3266; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42844.4]
wire _T_3267; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42845.4]
wire _T_3269; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42847.4]
wire _T_3271; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42849.4]
wire [1:0] _T_3272; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42850.4]
wire [1:0] _T_3273; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42851.4]
wire _T_3274; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42852.4]
wire _T_3275; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42854.4]
wire _T_3277; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42856.4]
wire _T_3279; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42858.4]
wire _T_3280; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42859.4]
wire _T_3281; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42864.4]
wire _T_3282; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42865.4]
wire _T_3283; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42866.4]
wire _T_3285; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42868.4]
wire _T_3286; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42869.4]
wire _T_3297; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42886.4]
wire _T_3298; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42887.4]
wire _T_3300; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42889.4]
wire _T_3302; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42891.4]
wire [1:0] _T_3303; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42892.4]
wire [1:0] _T_3304; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42893.4]
wire _T_3305; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42894.4]
wire _T_3306; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42896.4]
wire _T_3308; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42898.4]
wire _T_3310; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42900.4]
wire _T_3311; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42901.4]
wire _T_3312; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42906.4]
wire _T_3313; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42907.4]
wire _T_3314; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42908.4]
wire _T_3316; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42910.4]
wire _T_3317; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42911.4]
wire _T_3328; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42928.4]
wire _T_3329; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42929.4]
wire _T_3331; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42931.4]
wire _T_3333; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42933.4]
wire [1:0] _T_3334; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42934.4]
wire [1:0] _T_3335; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42935.4]
wire _T_3336; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42936.4]
wire _T_3337; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42938.4]
wire _T_3339; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42940.4]
wire _T_3341; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42942.4]
wire _T_3342; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42943.4]
wire _T_3343; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42948.4]
wire _T_3344; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42949.4]
wire _T_3345; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42950.4]
wire _T_3347; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42952.4]
wire _T_3348; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42953.4]
wire _T_3359; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42970.4]
wire _T_3360; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42971.4]
wire _T_3362; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42973.4]
wire _T_3364; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42975.4]
wire [1:0] _T_3365; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42976.4]
wire [1:0] _T_3366; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42977.4]
wire _T_3367; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42978.4]
wire _T_3368; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42980.4]
wire _T_3370; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42982.4]
wire _T_3372; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42984.4]
wire _T_3373; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42985.4]
wire _T_3374; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42990.4]
wire _T_3375; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42991.4]
wire _T_3376; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42992.4]
wire _T_3378; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42994.4]
wire _T_3379; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42995.4]
wire _T_3390; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43012.4]
wire _T_3391; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43013.4]
wire _T_3393; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43015.4]
wire _T_3395; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43017.4]
wire [1:0] _T_3396; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43018.4]
wire [1:0] _T_3397; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43019.4]
wire _T_3398; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43020.4]
wire _T_3399; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43022.4]
wire _T_3401; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43024.4]
wire _T_3403; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43026.4]
wire _T_3404; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43027.4]
wire _T_3405; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43032.4]
wire _T_3406; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43033.4]
wire _T_3407; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43034.4]
wire _T_3409; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43036.4]
wire _T_3410; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43037.4]
wire _T_3421; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43054.4]
wire _T_3422; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43055.4]
wire _T_3424; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43057.4]
wire _T_3426; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43059.4]
wire [1:0] _T_3427; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43060.4]
wire [1:0] _T_3428; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43061.4]
wire _T_3429; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43062.4]
wire _T_3430; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43064.4]
wire _T_3432; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43066.4]
wire _T_3434; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43068.4]
wire _T_3435; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43069.4]
wire _T_3436; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43074.4]
wire _T_3437; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43075.4]
wire _T_3438; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43076.4]
wire _T_3440; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43078.4]
wire _T_3441; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43079.4]
wire _T_3452; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43096.4]
wire _T_3453; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43097.4]
wire _T_3455; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43099.4]
wire _T_3457; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43101.4]
wire [1:0] _T_3458; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43102.4]
wire [1:0] _T_3459; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43103.4]
wire _T_3460; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43104.4]
wire _T_3461; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43106.4]
wire _T_3463; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43108.4]
wire _T_3465; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43110.4]
wire _T_3466; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43111.4]
wire _T_3467; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43116.4]
wire _T_3468; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43117.4]
wire _T_3469; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43118.4]
wire _T_3471; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43120.4]
wire _T_3472; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43121.4]
wire _T_3483; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43138.4]
wire _T_3484; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43139.4]
wire _T_3486; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43141.4]
wire _T_3488; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43143.4]
wire [1:0] _T_3489; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43144.4]
wire [1:0] _T_3490; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43145.4]
wire _T_3491; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43146.4]
wire _T_3492; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43148.4]
wire _T_3494; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43150.4]
wire _T_3496; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43152.4]
wire _T_3497; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43153.4]
wire _T_3498; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43158.4]
wire _T_3499; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43159.4]
wire _T_3500; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43160.4]
wire _T_3502; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43162.4]
wire _T_3503; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43163.4]
wire _T_3514; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43180.4]
wire _T_3515; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43181.4]
wire _T_3517; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43183.4]
wire _T_3519; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43185.4]
wire [1:0] _T_3520; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43186.4]
wire [1:0] _T_3521; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43187.4]
wire _T_3522; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43188.4]
wire _T_3523; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43190.4]
wire _T_3525; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43192.4]
wire _T_3527; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43194.4]
wire _T_3528; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43195.4]
wire _T_3529; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43200.4]
wire _T_3530; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43201.4]
wire _T_3531; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43202.4]
wire _T_3533; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43204.4]
wire _T_3534; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43205.4]
wire _T_3545; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43222.4]
wire _T_3546; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43223.4]
wire _T_3548; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43225.4]
wire _T_3550; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43227.4]
wire [1:0] _T_3551; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43228.4]
wire [1:0] _T_3552; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43229.4]
wire _T_3553; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43230.4]
wire _T_3554; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43232.4]
wire _T_3556; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43234.4]
wire _T_3558; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43236.4]
wire _T_3559; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43237.4]
wire _T_3560; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43242.4]
wire _T_3561; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43243.4]
wire _T_3562; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43244.4]
wire _T_3564; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43246.4]
wire _T_3565; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43247.4]
wire _T_3576; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43264.4]
wire _T_3577; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43265.4]
wire _T_3579; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43267.4]
wire _T_3581; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43269.4]
wire [1:0] _T_3582; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43270.4]
wire [1:0] _T_3583; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43271.4]
wire _T_3584; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43272.4]
wire _T_3585; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43274.4]
wire _T_3587; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43276.4]
wire _T_3589; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43278.4]
wire _T_3590; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43279.4]
wire _T_3591; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43284.4]
wire _T_3592; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43285.4]
wire _T_3593; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43286.4]
wire _T_3595; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43288.4]
wire _T_3596; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43289.4]
wire _T_3607; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43306.4]
wire _T_3608; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43307.4]
wire _T_3610; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43309.4]
wire _T_3612; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43311.4]
wire [1:0] _T_3613; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43312.4]
wire [1:0] _T_3614; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43313.4]
wire _T_3615; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43314.4]
wire _T_3616; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43316.4]
wire _T_3618; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43318.4]
wire _T_3620; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43320.4]
wire _T_3621; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43321.4]
wire _T_3622; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43326.4]
wire _T_3623; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43327.4]
wire _T_3624; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43328.4]
wire _T_3626; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43330.4]
wire _T_3627; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43331.4]
wire _T_3638; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43348.4]
wire _T_3639; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43349.4]
wire _T_3641; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43351.4]
wire _T_3643; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43353.4]
wire [1:0] _T_3644; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43354.4]
wire [1:0] _T_3645; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43355.4]
wire _T_3646; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43356.4]
wire _T_3647; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43358.4]
wire _T_3649; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43360.4]
wire _T_3651; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43362.4]
wire _T_3652; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43363.4]
wire _T_3653; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43368.4]
wire _T_3654; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43369.4]
wire _T_3655; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43370.4]
wire _T_3657; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43372.4]
wire _T_3658; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43373.4]
wire _T_3669; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43390.4]
wire _T_3670; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43391.4]
wire _T_3672; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43393.4]
wire _T_3674; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43395.4]
wire [1:0] _T_3675; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43396.4]
wire [1:0] _T_3676; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43397.4]
wire _T_3677; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43398.4]
wire _T_3678; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43400.4]
wire _T_3680; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43402.4]
wire _T_3682; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43404.4]
wire _T_3683; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43405.4]
wire _T_3684; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43410.4]
wire _T_3685; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43411.4]
wire _T_3686; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43412.4]
wire _T_3688; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43414.4]
wire _T_3689; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43415.4]
wire _T_3700; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43432.4]
wire _T_3701; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43433.4]
wire _T_3703; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43435.4]
wire _T_3705; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43437.4]
wire [1:0] _T_3706; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43438.4]
wire [1:0] _T_3707; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43439.4]
wire _T_3708; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43440.4]
wire _T_3709; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43442.4]
wire _T_3711; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43444.4]
wire _T_3713; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43446.4]
wire _T_3714; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43447.4]
wire _T_3715; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43452.4]
wire _T_3716; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43453.4]
wire _T_3717; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43454.4]
wire _T_3719; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43456.4]
wire _T_3720; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43457.4]
wire _T_3731; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43474.4]
wire _T_3732; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43475.4]
wire _T_3734; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43477.4]
wire _T_3736; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43479.4]
wire [1:0] _T_3737; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43480.4]
wire [1:0] _T_3738; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43481.4]
wire _T_3739; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43482.4]
wire _T_3740; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43484.4]
wire _T_3742; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43486.4]
wire _T_3744; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43488.4]
wire _T_3745; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43489.4]
wire _T_3746; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43494.4]
wire _T_3747; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43495.4]
wire _T_3748; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43496.4]
wire _T_3750; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43498.4]
wire _T_3751; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43499.4]
wire _T_3762; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43516.4]
wire _T_3763; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43517.4]
wire _T_3765; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43519.4]
wire _T_3767; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43521.4]
wire [1:0] _T_3768; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43522.4]
wire [1:0] _T_3769; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43523.4]
wire _T_3770; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43524.4]
wire _T_3771; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43526.4]
wire _T_3773; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43528.4]
wire _T_3775; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43530.4]
wire _T_3776; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43531.4]
wire _T_3777; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43536.4]
wire _T_3778; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43537.4]
wire _T_3779; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43538.4]
wire _T_3781; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43540.4]
wire _T_3782; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43541.4]
wire _T_3793; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43558.4]
wire _T_3794; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43559.4]
wire _T_3796; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43561.4]
wire _T_3798; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43563.4]
wire [1:0] _T_3799; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43564.4]
wire [1:0] _T_3800; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43565.4]
wire _T_3801; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43566.4]
wire _T_3802; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43568.4]
wire _T_3804; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43570.4]
wire _T_3806; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43572.4]
wire _T_3807; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43573.4]
wire _T_3808; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43578.4]
wire _T_3809; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43579.4]
wire _T_3810; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43580.4]
wire _T_3812; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43582.4]
wire _T_3813; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43583.4]
wire _T_3824; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43600.4]
wire _T_3825; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43601.4]
wire _T_3827; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43603.4]
wire _T_3829; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43605.4]
wire [1:0] _T_3830; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43606.4]
wire [1:0] _T_3831; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43607.4]
wire _T_3832; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43608.4]
wire _T_3833; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43610.4]
wire _T_3835; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43612.4]
wire _T_3837; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43614.4]
wire _T_3838; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43615.4]
wire _T_3839; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43620.4]
wire _T_3840; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43621.4]
wire _T_3841; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43622.4]
wire _T_3843; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43624.4]
wire _T_3844; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43625.4]
wire _T_3855; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43642.4]
wire _T_3856; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43643.4]
wire _T_3858; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43645.4]
wire _T_3860; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43647.4]
wire [1:0] _T_3861; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43648.4]
wire [1:0] _T_3862; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43649.4]
wire _T_3863; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43650.4]
wire _T_3864; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43652.4]
wire _T_3866; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43654.4]
wire _T_3868; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43656.4]
wire _T_3869; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43657.4]
wire _T_3870; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43662.4]
wire _T_3871; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43663.4]
wire _T_3872; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43664.4]
wire _T_3874; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43666.4]
wire _T_3875; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43667.4]
wire _T_3886; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43684.4]
wire _T_3887; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43685.4]
wire _T_3889; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43687.4]
wire _T_3891; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43689.4]
wire [1:0] _T_3892; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43690.4]
wire [1:0] _T_3893; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43691.4]
wire _T_3894; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43692.4]
wire _T_3895; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43694.4]
wire _T_3897; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43696.4]
wire _T_3899; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43698.4]
wire _T_3900; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43699.4]
wire _T_3901; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43704.4]
wire _T_3902; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43705.4]
wire _T_3903; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43706.4]
wire _T_3905; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43708.4]
wire _T_3906; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43709.4]
wire _T_3917; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43726.4]
wire _T_3918; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43727.4]
wire _T_3920; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43729.4]
wire _T_3922; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43731.4]
wire [1:0] _T_3923; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43732.4]
wire [1:0] _T_3924; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43733.4]
wire _T_3925; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43734.4]
wire _T_3926; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43736.4]
wire _T_3928; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43738.4]
wire _T_3930; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43740.4]
wire _T_3931; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43741.4]
wire _T_3932; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43746.4]
wire _T_3933; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43747.4]
wire _T_3934; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43748.4]
wire _T_3936; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43750.4]
wire _T_3937; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43751.4]
wire _T_3948; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43768.4]
wire _T_3949; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43769.4]
wire _T_3951; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43771.4]
wire _T_3953; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43773.4]
wire [1:0] _T_3954; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43774.4]
wire [1:0] _T_3955; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43775.4]
wire _T_3956; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43776.4]
wire _T_3957; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43778.4]
wire _T_3959; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43780.4]
wire _T_3961; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43782.4]
wire _T_3962; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43783.4]
wire _T_3963; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43788.4]
wire _T_3964; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43789.4]
wire _T_3965; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43790.4]
wire _T_3967; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43792.4]
wire _T_3968; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43793.4]
wire _T_3979; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43810.4]
wire _T_3980; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43811.4]
wire _T_3982; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43813.4]
wire _T_3984; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43815.4]
wire [1:0] _T_3985; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43816.4]
wire [1:0] _T_3986; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43817.4]
wire _T_3987; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43818.4]
wire _T_3988; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43820.4]
wire _T_3990; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43822.4]
wire _T_3992; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43824.4]
wire _T_3993; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43825.4]
wire _T_3994; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43830.4]
wire _T_3995; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43831.4]
wire _T_3996; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43832.4]
wire _T_3998; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43834.4]
wire _T_3999; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43835.4]
wire _T_4010; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43852.4]
wire _T_4011; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43853.4]
wire _T_4013; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43855.4]
wire _T_4015; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43857.4]
wire [1:0] _T_4016; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43858.4]
wire [1:0] _T_4017; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43859.4]
wire _T_4018; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43860.4]
wire _T_4019; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43862.4]
wire _T_4021; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43864.4]
wire _T_4023; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43866.4]
wire _T_4024; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43867.4]
wire _T_4025; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43872.4]
wire _T_4026; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43873.4]
wire _T_4027; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43874.4]
wire _T_4029; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43876.4]
wire _T_4030; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43877.4]
wire _T_4041; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43894.4]
wire _T_4042; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43895.4]
wire _T_4044; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43897.4]
wire _T_4046; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43899.4]
wire [1:0] _T_4047; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43900.4]
wire [1:0] _T_4048; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43901.4]
wire _T_4049; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43902.4]
wire _T_4050; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43904.4]
wire _T_4052; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43906.4]
wire _T_4054; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43908.4]
wire _T_4055; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43909.4]
wire _T_4056; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43914.4]
wire _T_4057; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43915.4]
wire _T_4058; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43916.4]
wire _T_4060; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43918.4]
wire _T_4061; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43919.4]
wire _T_4072; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43936.4]
wire _T_4073; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43937.4]
wire _T_4075; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43939.4]
wire _T_4077; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43941.4]
wire [1:0] _T_4078; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43942.4]
wire [1:0] _T_4079; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43943.4]
wire _T_4080; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43944.4]
wire _T_4081; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43946.4]
wire _T_4083; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43948.4]
wire _T_4085; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43950.4]
wire _T_4086; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43951.4]
wire _T_4087; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43956.4]
wire _T_4088; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43957.4]
wire _T_4089; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43958.4]
wire _T_4091; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43960.4]
wire _T_4092; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43961.4]
wire _T_4103; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43978.4]
wire _T_4104; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43979.4]
wire _T_4106; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43981.4]
wire _T_4108; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43983.4]
wire [1:0] _T_4109; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43984.4]
wire [1:0] _T_4110; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43985.4]
wire _T_4111; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43986.4]
wire _T_4112; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43988.4]
wire _T_4114; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43990.4]
wire _T_4116; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43992.4]
wire _T_4117; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43993.4]
wire _T_4118; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43998.4]
wire _T_4119; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43999.4]
wire _T_4120; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44000.4]
wire _T_4122; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44002.4]
wire _T_4123; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44003.4]
wire _T_4134; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44020.4]
wire _T_4135; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44021.4]
wire _T_4137; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44023.4]
wire _T_4139; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44025.4]
wire [1:0] _T_4140; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44026.4]
wire [1:0] _T_4141; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44027.4]
wire _T_4142; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44028.4]
wire _T_4143; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44030.4]
wire _T_4145; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44032.4]
wire _T_4147; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44034.4]
wire _T_4148; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44035.4]
wire _T_4149; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44040.4]
wire _T_4150; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44041.4]
wire _T_4151; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44042.4]
wire _T_4153; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44044.4]
wire _T_4154; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44045.4]
wire _T_4165; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44062.4]
wire _T_4166; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44063.4]
wire _T_4168; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44065.4]
wire _T_4170; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44067.4]
wire [1:0] _T_4171; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44068.4]
wire [1:0] _T_4172; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44069.4]
wire _T_4173; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44070.4]
wire _T_4174; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44072.4]
wire _T_4176; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44074.4]
wire _T_4178; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44076.4]
wire _T_4179; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44077.4]
wire _T_4180; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44082.4]
wire _T_4181; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44083.4]
wire _T_4182; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44084.4]
wire _T_4184; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44086.4]
wire _T_4185; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44087.4]
wire _T_4196; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44104.4]
wire _T_4197; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44105.4]
wire _T_4199; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44107.4]
wire _T_4201; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44109.4]
wire [1:0] _T_4202; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44110.4]
wire [1:0] _T_4203; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44111.4]
wire _T_4204; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44112.4]
wire _T_4205; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44114.4]
wire _T_4207; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44116.4]
wire _T_4209; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44118.4]
wire _T_4210; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44119.4]
wire _T_4211; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44124.4]
wire _T_4212; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44125.4]
wire _T_4213; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44126.4]
wire _T_4215; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44128.4]
wire _T_4216; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44129.4]
wire _T_4227; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44146.4]
wire _T_4228; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44147.4]
wire _T_4230; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44149.4]
wire _T_4232; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44151.4]
wire [1:0] _T_4233; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44152.4]
wire [1:0] _T_4234; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44153.4]
wire _T_4235; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44154.4]
wire _T_4236; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44156.4]
wire _T_4238; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44158.4]
wire _T_4240; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44160.4]
wire _T_4241; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44161.4]
wire _T_4242; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44166.4]
wire _T_4243; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44167.4]
wire _T_4244; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44168.4]
wire _T_4246; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44170.4]
wire _T_4247; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44171.4]
wire _T_4258; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44188.4]
wire _T_4259; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44189.4]
wire _T_4261; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44191.4]
wire _T_4263; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44193.4]
wire [1:0] _T_4264; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44194.4]
wire [1:0] _T_4265; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44195.4]
wire _T_4266; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44196.4]
wire _T_4267; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44198.4]
wire _T_4269; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44200.4]
wire _T_4271; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44202.4]
wire _T_4272; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44203.4]
wire _T_4273; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44208.4]
wire _T_4274; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44209.4]
wire _T_4275; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44210.4]
wire _T_4277; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44212.4]
wire _T_4278; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44213.4]
wire _T_4289; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44230.4]
wire _T_4290; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44231.4]
wire _T_4292; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44233.4]
wire _T_4294; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44235.4]
wire [1:0] _T_4295; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44236.4]
wire [1:0] _T_4296; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44237.4]
wire _T_4297; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44238.4]
wire _T_4298; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44240.4]
wire _T_4300; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44242.4]
wire _T_4302; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44244.4]
wire _T_4303; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44245.4]
wire _T_4304; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44250.4]
wire _T_4305; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44251.4]
wire _T_4306; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44252.4]
wire _T_4308; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44254.4]
wire _T_4309; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44255.4]
wire _T_4320; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44272.4]
wire _T_4321; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44273.4]
wire _T_4323; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44275.4]
wire _T_4325; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44277.4]
wire [1:0] _T_4326; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44278.4]
wire [1:0] _T_4327; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44279.4]
wire _T_4328; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44280.4]
wire _T_4329; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44282.4]
wire _T_4331; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44284.4]
wire _T_4333; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44286.4]
wire _T_4334; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44287.4]
wire _T_4335; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44292.4]
wire _T_4336; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44293.4]
wire _T_4337; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44294.4]
wire _T_4339; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44296.4]
wire _T_4340; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44297.4]
wire _T_4351; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44314.4]
wire _T_4352; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44315.4]
wire _T_4354; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44317.4]
wire _T_4356; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44319.4]
wire [1:0] _T_4357; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44320.4]
wire [1:0] _T_4358; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44321.4]
wire _T_4359; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44322.4]
wire _T_4360; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44324.4]
wire _T_4362; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44326.4]
wire _T_4364; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44328.4]
wire _T_4365; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44329.4]
wire _T_4366; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44334.4]
wire _T_4367; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44335.4]
wire _T_4368; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44336.4]
wire _T_4370; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44338.4]
wire _T_4371; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44339.4]
wire _T_4382; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44356.4]
wire _T_4383; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44357.4]
wire _T_4385; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44359.4]
wire _T_4387; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44361.4]
wire [1:0] _T_4388; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44362.4]
wire [1:0] _T_4389; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44363.4]
wire _T_4390; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44364.4]
wire _T_4391; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44366.4]
wire _T_4393; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44368.4]
wire _T_4395; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44370.4]
wire _T_4396; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44371.4]
wire _T_4397; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44376.4]
wire _T_4398; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44377.4]
wire _T_4399; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44378.4]
wire _T_4401; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44380.4]
wire _T_4402; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44381.4]
wire _T_4413; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44398.4]
wire _T_4414; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44399.4]
wire _T_4416; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44401.4]
wire _T_4418; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44403.4]
wire [1:0] _T_4419; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44404.4]
wire [1:0] _T_4420; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44405.4]
wire _T_4421; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44406.4]
wire _T_4422; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44408.4]
wire _T_4424; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44410.4]
wire _T_4426; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44412.4]
wire _T_4427; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44413.4]
wire _T_4428; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44418.4]
wire _T_4429; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44419.4]
wire _T_4430; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44420.4]
wire _T_4432; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44422.4]
wire _T_4433; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44423.4]
wire _T_4444; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44440.4]
wire _T_4445; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44441.4]
wire _T_4447; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44443.4]
wire _T_4449; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44445.4]
wire [1:0] _T_4450; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44446.4]
wire [1:0] _T_4451; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44447.4]
wire _T_4452; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44448.4]
wire _T_4453; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44450.4]
wire _T_4455; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44452.4]
wire _T_4457; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44454.4]
wire _T_4458; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44455.4]
wire _T_4459; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44460.4]
wire _T_4460; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44461.4]
wire _T_4461; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44462.4]
wire _T_4463; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44464.4]
wire _T_4464; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44465.4]
wire _T_4475; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44482.4]
wire _T_4476; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44483.4]
wire _T_4478; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44485.4]
wire _T_4480; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44487.4]
wire [1:0] _T_4481; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44488.4]
wire [1:0] _T_4482; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44489.4]
wire _T_4483; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44490.4]
wire _T_4484; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44492.4]
wire _T_4486; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44494.4]
wire _T_4488; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44496.4]
wire _T_4489; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44497.4]
wire _T_4490; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44502.4]
wire _T_4491; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44503.4]
wire _T_4492; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44504.4]
wire _T_4494; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44506.4]
wire _T_4495; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44507.4]
wire _T_4506; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44524.4]
wire _T_4507; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44525.4]
wire _T_4509; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44527.4]
wire _T_4511; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44529.4]
wire [1:0] _T_4512; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44530.4]
wire [1:0] _T_4513; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44531.4]
wire _T_4514; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44532.4]
wire _T_4515; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44534.4]
wire _T_4517; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44536.4]
wire _T_4519; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44538.4]
wire _T_4520; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44539.4]
wire _T_4521; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44544.4]
wire _T_4522; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44545.4]
wire _T_4523; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44546.4]
wire _T_4525; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44548.4]
wire _T_4526; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44549.4]
wire _T_4537; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44566.4]
wire _T_4538; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44567.4]
wire _T_4540; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44569.4]
wire _T_4542; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44571.4]
wire [1:0] _T_4543; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44572.4]
wire [1:0] _T_4544; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44573.4]
wire _T_4545; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44574.4]
wire _T_4546; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44576.4]
wire _T_4548; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44578.4]
wire _T_4550; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44580.4]
wire _T_4551; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44581.4]
wire _T_4552; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44586.4]
wire _T_4553; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44587.4]
wire _T_4554; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44588.4]
wire _T_4556; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44590.4]
wire _T_4557; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44591.4]
wire _T_4568; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44608.4]
wire _T_4569; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44609.4]
wire _T_4571; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44611.4]
wire _T_4573; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44613.4]
wire [1:0] _T_4574; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44614.4]
wire [1:0] _T_4575; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44615.4]
wire _T_4576; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44616.4]
wire _T_4577; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44618.4]
wire _T_4579; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44620.4]
wire _T_4581; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44622.4]
wire _T_4582; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44623.4]
wire _T_4583; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44628.4]
wire _T_4584; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44629.4]
wire _T_4585; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44630.4]
wire _T_4587; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44632.4]
wire _T_4588; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44633.4]
wire _T_4599; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44650.4]
wire _T_4600; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44651.4]
wire _T_4602; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44653.4]
wire _T_4604; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44655.4]
wire [1:0] _T_4605; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44656.4]
wire [1:0] _T_4606; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44657.4]
wire _T_4607; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44658.4]
wire _T_4608; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44660.4]
wire _T_4610; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44662.4]
wire _T_4612; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44664.4]
wire _T_4613; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44665.4]
wire _T_4614; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44670.4]
wire _T_4615; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44671.4]
wire _T_4616; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44672.4]
wire _T_4618; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44674.4]
wire _T_4619; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44675.4]
wire _T_4630; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44692.4]
wire _T_4631; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44693.4]
wire _T_4633; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44695.4]
wire _T_4635; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44697.4]
wire [1:0] _T_4636; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44698.4]
wire [1:0] _T_4637; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44699.4]
wire _T_4638; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44700.4]
wire _T_4639; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44702.4]
wire _T_4641; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44704.4]
wire _T_4643; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44706.4]
wire _T_4644; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44707.4]
wire _T_4645; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44712.4]
wire _T_4646; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44713.4]
wire _T_4647; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44714.4]
wire _T_4649; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44716.4]
wire _T_4650; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44717.4]
wire _T_4661; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44734.4]
wire _T_4662; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44735.4]
wire _T_4664; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44737.4]
wire _T_4666; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44739.4]
wire [1:0] _T_4667; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44740.4]
wire [1:0] _T_4668; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44741.4]
wire _T_4669; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44742.4]
wire _T_4670; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44744.4]
wire _T_4672; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44746.4]
wire _T_4674; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44748.4]
wire _T_4675; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44749.4]
wire _T_4676; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44754.4]
wire _T_4677; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44755.4]
wire _T_4678; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44756.4]
wire _T_4680; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44758.4]
wire _T_4681; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44759.4]
wire _T_4692; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44776.4]
wire _T_4693; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44777.4]
wire _T_4695; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44779.4]
wire _T_4697; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44781.4]
wire [1:0] _T_4698; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44782.4]
wire [1:0] _T_4699; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44783.4]
wire _T_4700; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44784.4]
wire _T_4701; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44786.4]
wire _T_4703; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44788.4]
wire _T_4705; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44790.4]
wire _T_4706; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44791.4]
wire _T_4707; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44796.4]
wire _T_4708; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44797.4]
wire _T_4709; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44798.4]
wire _T_4711; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44800.4]
wire _T_4712; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44801.4]
wire _T_4723; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44818.4]
wire _T_4724; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44819.4]
wire _T_4726; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44821.4]
wire _T_4728; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44823.4]
wire [1:0] _T_4729; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44824.4]
wire [1:0] _T_4730; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44825.4]
wire _T_4731; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44826.4]
wire _T_4732; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44828.4]
wire _T_4734; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44830.4]
wire _T_4736; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44832.4]
wire _T_4737; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44833.4]
wire _T_4738; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44838.4]
wire _T_4739; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44839.4]
wire _T_4740; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44840.4]
wire _T_4742; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44842.4]
wire _T_4743; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44843.4]
wire _T_4754; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44860.4]
wire _T_4755; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44861.4]
wire _T_4757; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44863.4]
wire _T_4759; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44865.4]
wire [1:0] _T_4760; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44866.4]
wire [1:0] _T_4761; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44867.4]
wire _T_4762; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44868.4]
wire _T_4763; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44870.4]
wire _T_4765; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44872.4]
wire _T_4767; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44874.4]
wire _T_4768; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44875.4]
wire _T_4769; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44880.4]
wire _T_4770; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44881.4]
wire _T_4771; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44882.4]
wire _T_4773; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44884.4]
wire _T_4774; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44885.4]
wire _T_4785; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44902.4]
wire _T_4786; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44903.4]
wire _T_4788; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44905.4]
wire _T_4790; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44907.4]
wire [1:0] _T_4791; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44908.4]
wire [1:0] _T_4792; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44909.4]
wire _T_4793; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44910.4]
wire _T_4794; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44912.4]
wire _T_4796; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44914.4]
wire _T_4798; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44916.4]
wire _T_4799; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44917.4]
wire _T_4800; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44922.4]
wire _T_4801; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44923.4]
wire _T_4802; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44924.4]
wire _T_4804; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44926.4]
wire _T_4805; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44927.4]
wire _T_4816; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44944.4]
wire _T_4817; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44945.4]
wire _T_4819; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44947.4]
wire _T_4821; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44949.4]
wire [1:0] _T_4822; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44950.4]
wire [1:0] _T_4823; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44951.4]
wire _T_4824; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44952.4]
wire _T_4825; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44954.4]
wire _T_4827; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44956.4]
wire _T_4829; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44958.4]
wire _T_4830; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44959.4]
wire _T_4831; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44964.4]
wire _T_4832; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44965.4]
wire _T_4833; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44966.4]
wire _T_4835; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44968.4]
wire _T_4836; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44969.4]
wire _T_4847; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44986.4]
wire _T_4848; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44987.4]
wire _T_4850; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44989.4]
wire _T_4852; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44991.4]
wire [1:0] _T_4853; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44992.4]
wire [1:0] _T_4854; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44993.4]
wire _T_4855; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44994.4]
wire _T_4856; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44996.4]
wire _T_4858; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44998.4]
wire _T_4860; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45000.4]
wire _T_4861; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45001.4]
wire _T_4862; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45006.4]
wire _T_4863; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45007.4]
wire _T_4864; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45008.4]
wire _T_4866; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45010.4]
wire _T_4867; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45011.4]
wire _T_4878; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45028.4]
wire _T_4879; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45029.4]
wire _T_4881; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45031.4]
wire _T_4883; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45033.4]
wire [1:0] _T_4884; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45034.4]
wire [1:0] _T_4885; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45035.4]
wire _T_4886; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45036.4]
wire _T_4887; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45038.4]
wire _T_4889; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45040.4]
wire _T_4891; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45042.4]
wire _T_4892; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45043.4]
wire _T_4893; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45048.4]
wire _T_4894; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45049.4]
wire _T_4895; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45050.4]
wire _T_4897; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45052.4]
wire _T_4898; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45053.4]
wire _T_4909; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45070.4]
wire _T_4910; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45071.4]
wire _T_4912; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45073.4]
wire _T_4914; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45075.4]
wire [1:0] _T_4915; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45076.4]
wire [1:0] _T_4916; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45077.4]
wire _T_4917; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45078.4]
wire _T_4918; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45080.4]
wire _T_4920; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45082.4]
wire _T_4922; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45084.4]
wire _T_4923; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45085.4]
wire _T_4924; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45090.4]
wire _T_4925; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45091.4]
wire _T_4926; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45092.4]
wire _T_4928; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45094.4]
wire _T_4929; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45095.4]
wire _T_4940; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45112.4]
wire _T_4941; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45113.4]
wire _T_4943; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45115.4]
wire _T_4945; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45117.4]
wire [1:0] _T_4946; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45118.4]
wire [1:0] _T_4947; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45119.4]
wire _T_4948; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45120.4]
wire _T_4949; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45122.4]
wire _T_4951; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45124.4]
wire _T_4953; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45126.4]
wire _T_4954; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45127.4]
wire _T_4955; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45132.4]
wire _T_4956; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45133.4]
wire _T_4957; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45134.4]
wire _T_4959; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45136.4]
wire _T_4960; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45137.4]
wire _T_4971; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45154.4]
wire _T_4972; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45155.4]
wire _T_4974; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45157.4]
wire _T_4976; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45159.4]
wire [1:0] _T_4977; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45160.4]
wire [1:0] _T_4978; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45161.4]
wire _T_4979; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45162.4]
wire _T_4980; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45164.4]
wire _T_4982; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45166.4]
wire _T_4984; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45168.4]
wire _T_4985; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45169.4]
wire _T_4986; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45174.4]
wire _T_4987; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45175.4]
wire _T_4988; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45176.4]
wire _T_4990; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45178.4]
wire _T_4991; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45179.4]
wire _T_5002; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45196.4]
wire _T_5003; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45197.4]
wire _T_5005; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45199.4]
wire _T_5007; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45201.4]
wire [1:0] _T_5008; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45202.4]
wire [1:0] _T_5009; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45203.4]
wire _T_5010; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45204.4]
wire _T_5011; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45206.4]
wire _T_5013; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45208.4]
wire _T_5015; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45210.4]
wire _T_5016; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45211.4]
wire _T_5017; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45216.4]
wire _T_5018; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45217.4]
wire _T_5019; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45218.4]
wire _T_5021; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45220.4]
wire _T_5022; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45221.4]
wire _T_5033; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45238.4]
wire _T_5034; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45239.4]
wire _T_5036; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45241.4]
wire _T_5038; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45243.4]
wire [1:0] _T_5039; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45244.4]
wire [1:0] _T_5040; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45245.4]
wire _T_5041; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45246.4]
wire _T_5042; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45248.4]
wire _T_5044; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45250.4]
wire _T_5046; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45252.4]
wire _T_5047; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45253.4]
wire _T_5048; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45258.4]
wire _T_5049; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45259.4]
wire _T_5050; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45260.4]
wire _T_5052; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45262.4]
wire _T_5053; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45263.4]
wire _T_5064; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45280.4]
wire _T_5065; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45281.4]
wire _T_5067; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45283.4]
wire _T_5069; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45285.4]
wire [1:0] _T_5070; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45286.4]
wire [1:0] _T_5071; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45287.4]
wire _T_5072; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45288.4]
wire _T_5073; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45290.4]
wire _T_5075; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45292.4]
wire _T_5077; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45294.4]
wire _T_5078; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45295.4]
wire _T_5079; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45300.4]
wire _T_5080; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45301.4]
wire _T_5081; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45302.4]
wire _T_5083; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45304.4]
wire _T_5084; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45305.4]
wire _T_5095; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45322.4]
wire _T_5096; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45323.4]
wire _T_5098; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45325.4]
wire _T_5100; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45327.4]
wire [1:0] _T_5101; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45328.4]
wire [1:0] _T_5102; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45329.4]
wire _T_5103; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45330.4]
wire _T_5104; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45332.4]
wire _T_5106; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45334.4]
wire _T_5108; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45336.4]
wire _T_5109; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45337.4]
wire _T_5110; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45342.4]
wire _T_5111; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45343.4]
wire _T_5112; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45344.4]
wire _T_5114; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45346.4]
wire _T_5115; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45347.4]
wire _T_5126; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45364.4]
wire _T_5127; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45365.4]
wire _T_5129; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45367.4]
wire _T_5131; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45369.4]
wire [1:0] _T_5132; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45370.4]
wire [1:0] _T_5133; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45371.4]
wire _T_5134; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45372.4]
wire _T_5135; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45374.4]
wire _T_5137; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45376.4]
wire _T_5139; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45378.4]
wire _T_5140; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45379.4]
wire _T_5141; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45384.4]
wire _T_5142; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45385.4]
wire _T_5143; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45386.4]
wire _T_5145; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45388.4]
wire _T_5146; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45389.4]
wire _T_5157; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45406.4]
wire _T_5158; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45407.4]
wire _T_5160; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45409.4]
wire _T_5162; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45411.4]
wire [1:0] _T_5163; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45412.4]
wire [1:0] _T_5164; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45413.4]
wire _T_5165; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45414.4]
wire _T_5166; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45416.4]
wire _T_5168; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45418.4]
wire _T_5170; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45420.4]
wire _T_5171; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45421.4]
wire _T_5172; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45426.4]
wire _T_5173; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45427.4]
wire _T_5174; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45428.4]
wire _T_5176; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45430.4]
wire _T_5177; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45431.4]
wire _T_5188; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45448.4]
wire _T_5189; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45449.4]
wire _T_5191; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45451.4]
wire _T_5193; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45453.4]
wire [1:0] _T_5194; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45454.4]
wire [1:0] _T_5195; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45455.4]
wire _T_5196; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45456.4]
wire _T_5197; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45458.4]
wire _T_5199; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45460.4]
wire _T_5201; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45462.4]
wire _T_5202; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45463.4]
wire _T_5203; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45468.4]
wire _T_5204; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45469.4]
wire _T_5205; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45470.4]
wire _T_5207; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45472.4]
wire _T_5208; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45473.4]
wire _T_5219; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45490.4]
wire _T_5220; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45491.4]
wire _T_5222; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45493.4]
wire _T_5224; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45495.4]
wire [1:0] _T_5225; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45496.4]
wire [1:0] _T_5226; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45497.4]
wire _T_5227; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45498.4]
wire _T_5228; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45500.4]
wire _T_5230; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45502.4]
wire _T_5232; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45504.4]
wire _T_5233; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45505.4]
wire _T_5234; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45510.4]
wire _T_5235; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45511.4]
wire _T_5236; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45512.4]
wire _T_5238; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45514.4]
wire _T_5239; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45515.4]
wire _T_5250; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45532.4]
wire _T_5251; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45533.4]
wire _T_5253; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45535.4]
wire _T_5255; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45537.4]
wire [1:0] _T_5256; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45538.4]
wire [1:0] _T_5257; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45539.4]
wire _T_5258; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45540.4]
wire _T_5259; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45542.4]
wire _T_5261; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45544.4]
wire _T_5263; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45546.4]
wire _T_5264; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45547.4]
wire _T_5265; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45552.4]
wire _T_5266; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45553.4]
wire _T_5267; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45554.4]
wire _T_5269; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45556.4]
wire _T_5270; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45557.4]
wire _T_5281; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45574.4]
wire _T_5282; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45575.4]
wire _T_5284; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45577.4]
wire _T_5286; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45579.4]
wire [1:0] _T_5287; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45580.4]
wire [1:0] _T_5288; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45581.4]
wire _T_5289; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45582.4]
wire _T_5290; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45584.4]
wire _T_5292; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45586.4]
wire _T_5294; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45588.4]
wire _T_5295; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45589.4]
wire _T_5296; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45594.4]
wire _T_5297; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45595.4]
wire _T_5298; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45596.4]
wire _T_5300; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45598.4]
wire _T_5301; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45599.4]
wire _T_5312; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45616.4]
wire _T_5313; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45617.4]
wire _T_5315; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45619.4]
wire _T_5317; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45621.4]
wire [1:0] _T_5318; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45622.4]
wire [1:0] _T_5319; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45623.4]
wire _T_5320; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45624.4]
wire _T_5321; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45626.4]
wire _T_5323; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45628.4]
wire _T_5325; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45630.4]
wire _T_5326; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45631.4]
wire _T_5327; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45636.4]
wire _T_5328; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45637.4]
wire _T_5329; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45638.4]
wire _T_5331; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45640.4]
wire _T_5332; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45641.4]
wire _T_5343; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45658.4]
wire _T_5344; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45659.4]
wire _T_5346; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45661.4]
wire _T_5348; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45663.4]
wire [1:0] _T_5349; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45664.4]
wire [1:0] _T_5350; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45665.4]
wire _T_5351; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45666.4]
wire _T_5352; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45668.4]
wire _T_5354; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45670.4]
wire _T_5356; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45672.4]
wire _T_5357; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45673.4]
wire _T_5358; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45678.4]
wire _T_5359; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45679.4]
wire _T_5360; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45680.4]
wire _T_5362; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45682.4]
wire _T_5363; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45683.4]
wire _T_5374; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45700.4]
wire _T_5375; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45701.4]
wire _T_5377; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45703.4]
wire _T_5379; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45705.4]
wire [1:0] _T_5380; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45706.4]
wire [1:0] _T_5381; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45707.4]
wire _T_5382; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45708.4]
wire _T_5383; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45710.4]
wire _T_5385; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45712.4]
wire _T_5387; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45714.4]
wire _T_5388; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45715.4]
wire _T_5389; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45720.4]
wire _T_5390; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45721.4]
wire _T_5391; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45722.4]
wire _T_5393; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45724.4]
wire _T_5394; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45725.4]
wire _T_5405; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45742.4]
wire _T_5406; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45743.4]
wire _T_5408; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45745.4]
wire _T_5410; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45747.4]
wire [1:0] _T_5411; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45748.4]
wire [1:0] _T_5412; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45749.4]
wire _T_5413; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45750.4]
wire _T_5414; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45752.4]
wire _T_5416; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45754.4]
wire _T_5418; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45756.4]
wire _T_5419; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45757.4]
wire _T_5420; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45762.4]
wire _T_5421; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45763.4]
wire _T_5422; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45764.4]
wire _T_5424; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45766.4]
wire _T_5425; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45767.4]
wire _T_5436; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45784.4]
wire _T_5437; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45785.4]
wire _T_5439; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45787.4]
wire _T_5441; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45789.4]
wire [1:0] _T_5442; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45790.4]
wire [1:0] _T_5443; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45791.4]
wire _T_5444; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45792.4]
wire _T_5445; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45794.4]
wire _T_5447; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45796.4]
wire _T_5449; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45798.4]
wire _T_5450; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45799.4]
wire _T_5451; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45804.4]
wire _T_5452; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45805.4]
wire _T_5453; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45806.4]
wire _T_5455; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45808.4]
wire _T_5456; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45809.4]
wire _T_5467; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45826.4]
wire _T_5468; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45827.4]
wire _T_5470; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45829.4]
wire _T_5472; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45831.4]
wire [1:0] _T_5473; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45832.4]
wire [1:0] _T_5474; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45833.4]
wire _T_5475; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45834.4]
wire _T_5476; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45836.4]
wire _T_5478; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45838.4]
wire _T_5480; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45840.4]
wire _T_5481; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45841.4]
wire _T_5482; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45846.4]
wire _T_5483; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45847.4]
wire _T_5484; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45848.4]
wire _T_5486; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45850.4]
wire _T_5487; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45851.4]
wire _T_5498; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45868.4]
wire _T_5499; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45869.4]
wire _T_5501; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45871.4]
wire _T_5503; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45873.4]
wire [1:0] _T_5504; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45874.4]
wire [1:0] _T_5505; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45875.4]
wire _T_5506; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45876.4]
wire _T_5507; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45878.4]
wire _T_5509; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45880.4]
wire _T_5511; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45882.4]
wire _T_5512; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45883.4]
wire _T_5513; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45888.4]
wire _T_5514; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45889.4]
wire _T_5515; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45890.4]
wire _T_5517; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45892.4]
wire _T_5518; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45893.4]
wire _T_5529; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45910.4]
wire _T_5530; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45911.4]
wire _T_5532; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45913.4]
wire _T_5534; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45915.4]
wire [1:0] _T_5535; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45916.4]
wire [1:0] _T_5536; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45917.4]
wire _T_5537; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45918.4]
wire _T_5538; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45920.4]
wire _T_5540; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45922.4]
wire _T_5542; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45924.4]
wire _T_5543; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45925.4]
wire _T_5544; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45930.4]
wire _T_5545; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45931.4]
wire _T_5546; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45932.4]
wire _T_5548; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45934.4]
wire _T_5549; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45935.4]
wire _T_5560; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45952.4]
wire _T_5561; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45953.4]
wire _T_5563; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45955.4]
wire _T_5565; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45957.4]
wire [1:0] _T_5566; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45958.4]
wire [1:0] _T_5567; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45959.4]
wire _T_5568; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45960.4]
wire _T_5569; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45962.4]
wire _T_5571; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45964.4]
wire _T_5573; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45966.4]
wire _T_5574; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45967.4]
wire _T_5575; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45972.4]
wire _T_5576; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45973.4]
wire _T_5577; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45974.4]
wire _T_5579; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45976.4]
wire _T_5580; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45977.4]
wire _T_5591; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45994.4]
wire _T_5592; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45995.4]
wire _T_5594; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45997.4]
wire _T_5596; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45999.4]
wire [1:0] _T_5597; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46000.4]
wire [1:0] _T_5598; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46001.4]
wire _T_5599; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46002.4]
wire _T_5600; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@46004.4]
wire _T_5602; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@46006.4]
wire _T_5604; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46008.4]
wire _T_5605; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46009.4]
wire _T_5606; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@46014.4]
wire _T_5607; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@46015.4]
wire _T_5608; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@46016.4]
wire _T_5610; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46018.4]
wire _T_5611; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46019.4]
wire _T_5622; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@46036.4]
wire _T_5623; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@46037.4]
wire _T_5625; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@46039.4]
wire _T_5627; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@46041.4]
wire [1:0] _T_5628; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46042.4]
wire [1:0] _T_5629; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46043.4]
wire _T_5630; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46044.4]
wire _T_5631; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@46046.4]
wire _T_5633; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@46048.4]
wire _T_5635; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46050.4]
wire _T_5636; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46051.4]
wire _T_5637; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@46056.4]
wire _T_5638; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@46057.4]
wire _T_5639; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@46058.4]
wire _T_5641; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46060.4]
wire _T_5642; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46061.4]
TLMonitor_15 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@39796.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_29 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40283.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_strb(Queue_io_enq_bits_strb),
.io_enq_bits_last(Queue_io_enq_bits_last),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_strb(Queue_io_deq_bits_strb),
.io_deq_bits_last(Queue_io_deq_bits_last)
);
Queue_77 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@40298.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_id(Queue_1_io_enq_bits_id),
.io_enq_bits_addr(Queue_1_io_enq_bits_addr),
.io_enq_bits_len(Queue_1_io_enq_bits_len),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_user(Queue_1_io_enq_bits_user),
.io_enq_bits_wen(Queue_1_io_enq_bits_wen),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_id(Queue_1_io_deq_bits_id),
.io_deq_bits_addr(Queue_1_io_deq_bits_addr),
.io_deq_bits_len(Queue_1_io_deq_bits_len),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_burst(Queue_1_io_deq_bits_burst),
.io_deq_bits_lock(Queue_1_io_deq_bits_lock),
.io_deq_bits_cache(Queue_1_io_deq_bits_cache),
.io_deq_bits_prot(Queue_1_io_deq_bits_prot),
.io_deq_bits_qos(Queue_1_io_deq_bits_qos),
.io_deq_bits_user(Queue_1_io_deq_bits_user),
.io_deq_bits_wen(Queue_1_io_deq_bits_wen)
);
assign _T_1293 = auto_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@40230.4]
assign _T_1294 = _T_1293 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@40231.4]
assign _GEN_131 = 7'h1 == auto_in_a_bits_source ? _T_1711 : _T_1680; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_132 = 7'h2 == auto_in_a_bits_source ? _T_1742 : _GEN_131; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_133 = 7'h3 == auto_in_a_bits_source ? _T_1773 : _GEN_132; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_134 = 7'h4 == auto_in_a_bits_source ? _T_1804 : _GEN_133; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_135 = 7'h5 == auto_in_a_bits_source ? _T_1835 : _GEN_134; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_136 = 7'h6 == auto_in_a_bits_source ? _T_1866 : _GEN_135; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_137 = 7'h7 == auto_in_a_bits_source ? _T_1897 : _GEN_136; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_138 = 7'h8 == auto_in_a_bits_source ? _T_1928 : _GEN_137; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_139 = 7'h9 == auto_in_a_bits_source ? _T_1959 : _GEN_138; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_140 = 7'ha == auto_in_a_bits_source ? _T_1990 : _GEN_139; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_141 = 7'hb == auto_in_a_bits_source ? _T_2021 : _GEN_140; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_142 = 7'hc == auto_in_a_bits_source ? _T_2052 : _GEN_141; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_143 = 7'hd == auto_in_a_bits_source ? _T_2083 : _GEN_142; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_144 = 7'he == auto_in_a_bits_source ? _T_2114 : _GEN_143; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_145 = 7'hf == auto_in_a_bits_source ? _T_2145 : _GEN_144; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_146 = 7'h10 == auto_in_a_bits_source ? _T_2176 : _GEN_145; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_147 = 7'h11 == auto_in_a_bits_source ? _T_2207 : _GEN_146; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_148 = 7'h12 == auto_in_a_bits_source ? _T_2238 : _GEN_147; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_149 = 7'h13 == auto_in_a_bits_source ? _T_2269 : _GEN_148; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_150 = 7'h14 == auto_in_a_bits_source ? _T_2300 : _GEN_149; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_151 = 7'h15 == auto_in_a_bits_source ? _T_2331 : _GEN_150; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_152 = 7'h16 == auto_in_a_bits_source ? _T_2362 : _GEN_151; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_153 = 7'h17 == auto_in_a_bits_source ? _T_2393 : _GEN_152; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_154 = 7'h18 == auto_in_a_bits_source ? _T_2424 : _GEN_153; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_155 = 7'h19 == auto_in_a_bits_source ? _T_2455 : _GEN_154; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_156 = 7'h1a == auto_in_a_bits_source ? _T_2486 : _GEN_155; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_157 = 7'h1b == auto_in_a_bits_source ? _T_2517 : _GEN_156; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_158 = 7'h1c == auto_in_a_bits_source ? _T_2548 : _GEN_157; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_159 = 7'h1d == auto_in_a_bits_source ? _T_2579 : _GEN_158; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_160 = 7'h1e == auto_in_a_bits_source ? _T_2610 : _GEN_159; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_161 = 7'h1f == auto_in_a_bits_source ? _T_2641 : _GEN_160; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_162 = 7'h20 == auto_in_a_bits_source ? _T_2672 : _GEN_161; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_163 = 7'h21 == auto_in_a_bits_source ? _T_2703 : _GEN_162; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_164 = 7'h22 == auto_in_a_bits_source ? _T_2734 : _GEN_163; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_165 = 7'h23 == auto_in_a_bits_source ? _T_2765 : _GEN_164; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_166 = 7'h24 == auto_in_a_bits_source ? _T_2796 : _GEN_165; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_167 = 7'h25 == auto_in_a_bits_source ? _T_2827 : _GEN_166; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_168 = 7'h26 == auto_in_a_bits_source ? _T_2858 : _GEN_167; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_169 = 7'h27 == auto_in_a_bits_source ? _T_2889 : _GEN_168; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_170 = 7'h28 == auto_in_a_bits_source ? _T_2920 : _GEN_169; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_171 = 7'h29 == auto_in_a_bits_source ? _T_2951 : _GEN_170; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_172 = 7'h2a == auto_in_a_bits_source ? _T_2982 : _GEN_171; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_173 = 7'h2b == auto_in_a_bits_source ? _T_3013 : _GEN_172; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_174 = 7'h2c == auto_in_a_bits_source ? _T_3044 : _GEN_173; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_175 = 7'h2d == auto_in_a_bits_source ? _T_3075 : _GEN_174; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_176 = 7'h2e == auto_in_a_bits_source ? _T_3106 : _GEN_175; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_177 = 7'h2f == auto_in_a_bits_source ? _T_3137 : _GEN_176; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_178 = 7'h30 == auto_in_a_bits_source ? _T_3168 : _GEN_177; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_179 = 7'h31 == auto_in_a_bits_source ? _T_3199 : _GEN_178; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_180 = 7'h32 == auto_in_a_bits_source ? _T_3230 : _GEN_179; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_181 = 7'h33 == auto_in_a_bits_source ? _T_3261 : _GEN_180; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_182 = 7'h34 == auto_in_a_bits_source ? _T_3292 : _GEN_181; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_183 = 7'h35 == auto_in_a_bits_source ? _T_3323 : _GEN_182; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_184 = 7'h36 == auto_in_a_bits_source ? _T_3354 : _GEN_183; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_185 = 7'h37 == auto_in_a_bits_source ? _T_3385 : _GEN_184; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_186 = 7'h38 == auto_in_a_bits_source ? _T_3416 : _GEN_185; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_187 = 7'h39 == auto_in_a_bits_source ? _T_3447 : _GEN_186; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_188 = 7'h3a == auto_in_a_bits_source ? _T_3478 : _GEN_187; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_189 = 7'h3b == auto_in_a_bits_source ? _T_3509 : _GEN_188; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_190 = 7'h3c == auto_in_a_bits_source ? _T_3540 : _GEN_189; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_191 = 7'h3d == auto_in_a_bits_source ? _T_3571 : _GEN_190; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_192 = 7'h3e == auto_in_a_bits_source ? _T_3602 : _GEN_191; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_193 = 7'h3f == auto_in_a_bits_source ? _T_3633 : _GEN_192; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_194 = 7'h40 == auto_in_a_bits_source ? _T_3664 : _GEN_193; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_195 = 7'h41 == auto_in_a_bits_source ? _T_3695 : _GEN_194; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_196 = 7'h42 == auto_in_a_bits_source ? _T_3726 : _GEN_195; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_197 = 7'h43 == auto_in_a_bits_source ? _T_3757 : _GEN_196; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_198 = 7'h44 == auto_in_a_bits_source ? _T_3788 : _GEN_197; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_199 = 7'h45 == auto_in_a_bits_source ? _T_3819 : _GEN_198; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_200 = 7'h46 == auto_in_a_bits_source ? _T_3850 : _GEN_199; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_201 = 7'h47 == auto_in_a_bits_source ? _T_3881 : _GEN_200; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_202 = 7'h48 == auto_in_a_bits_source ? _T_3912 : _GEN_201; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_203 = 7'h49 == auto_in_a_bits_source ? _T_3943 : _GEN_202; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_204 = 7'h4a == auto_in_a_bits_source ? _T_3974 : _GEN_203; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_205 = 7'h4b == auto_in_a_bits_source ? _T_4005 : _GEN_204; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_206 = 7'h4c == auto_in_a_bits_source ? _T_4036 : _GEN_205; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_207 = 7'h4d == auto_in_a_bits_source ? _T_4067 : _GEN_206; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_208 = 7'h4e == auto_in_a_bits_source ? _T_4098 : _GEN_207; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_209 = 7'h4f == auto_in_a_bits_source ? _T_4129 : _GEN_208; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_210 = 7'h50 == auto_in_a_bits_source ? _T_4160 : _GEN_209; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_211 = 7'h51 == auto_in_a_bits_source ? _T_4191 : _GEN_210; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_212 = 7'h52 == auto_in_a_bits_source ? _T_4222 : _GEN_211; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_213 = 7'h53 == auto_in_a_bits_source ? _T_4253 : _GEN_212; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_214 = 7'h54 == auto_in_a_bits_source ? _T_4284 : _GEN_213; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_215 = 7'h55 == auto_in_a_bits_source ? _T_4315 : _GEN_214; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_216 = 7'h56 == auto_in_a_bits_source ? _T_4346 : _GEN_215; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_217 = 7'h57 == auto_in_a_bits_source ? _T_4377 : _GEN_216; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_218 = 7'h58 == auto_in_a_bits_source ? _T_4408 : _GEN_217; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_219 = 7'h59 == auto_in_a_bits_source ? _T_4439 : _GEN_218; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_220 = 7'h5a == auto_in_a_bits_source ? _T_4470 : _GEN_219; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_221 = 7'h5b == auto_in_a_bits_source ? _T_4501 : _GEN_220; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_222 = 7'h5c == auto_in_a_bits_source ? _T_4532 : _GEN_221; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_223 = 7'h5d == auto_in_a_bits_source ? _T_4563 : _GEN_222; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_224 = 7'h5e == auto_in_a_bits_source ? _T_4594 : _GEN_223; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_225 = 7'h5f == auto_in_a_bits_source ? _T_4625 : _GEN_224; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_226 = 7'h60 == auto_in_a_bits_source ? _T_4656 : _GEN_225; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_227 = 7'h61 == auto_in_a_bits_source ? _T_4687 : _GEN_226; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_228 = 7'h62 == auto_in_a_bits_source ? _T_4718 : _GEN_227; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_229 = 7'h63 == auto_in_a_bits_source ? _T_4749 : _GEN_228; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_230 = 7'h64 == auto_in_a_bits_source ? _T_4780 : _GEN_229; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_231 = 7'h65 == auto_in_a_bits_source ? _T_4811 : _GEN_230; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_232 = 7'h66 == auto_in_a_bits_source ? _T_4842 : _GEN_231; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_233 = 7'h67 == auto_in_a_bits_source ? _T_4873 : _GEN_232; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_234 = 7'h68 == auto_in_a_bits_source ? _T_4904 : _GEN_233; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_235 = 7'h69 == auto_in_a_bits_source ? _T_4935 : _GEN_234; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_236 = 7'h6a == auto_in_a_bits_source ? _T_4966 : _GEN_235; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_237 = 7'h6b == auto_in_a_bits_source ? _T_4997 : _GEN_236; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_238 = 7'h6c == auto_in_a_bits_source ? _T_5028 : _GEN_237; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_239 = 7'h6d == auto_in_a_bits_source ? _T_5059 : _GEN_238; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_240 = 7'h6e == auto_in_a_bits_source ? _T_5090 : _GEN_239; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_241 = 7'h6f == auto_in_a_bits_source ? _T_5121 : _GEN_240; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_242 = 7'h70 == auto_in_a_bits_source ? _T_5152 : _GEN_241; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_243 = 7'h71 == auto_in_a_bits_source ? _T_5183 : _GEN_242; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_244 = 7'h72 == auto_in_a_bits_source ? _T_5214 : _GEN_243; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_245 = 7'h73 == auto_in_a_bits_source ? _T_5245 : _GEN_244; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_246 = 7'h74 == auto_in_a_bits_source ? _T_5276 : _GEN_245; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_247 = 7'h75 == auto_in_a_bits_source ? _T_5307 : _GEN_246; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_248 = 7'h76 == auto_in_a_bits_source ? _T_5338 : _GEN_247; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_249 = 7'h77 == auto_in_a_bits_source ? _T_5369 : _GEN_248; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_250 = 7'h78 == auto_in_a_bits_source ? _T_5400 : _GEN_249; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_251 = 7'h79 == auto_in_a_bits_source ? _T_5431 : _GEN_250; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_252 = 7'h7a == auto_in_a_bits_source ? _T_5462 : _GEN_251; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_253 = 7'h7b == auto_in_a_bits_source ? _T_5493 : _GEN_252; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_254 = 7'h7c == auto_in_a_bits_source ? _T_5524 : _GEN_253; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_255 = 7'h7d == auto_in_a_bits_source ? _T_5555 : _GEN_254; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_256 = 7'h7e == auto_in_a_bits_source ? _T_5586 : _GEN_255; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _GEN_257 = 7'h7f == auto_in_a_bits_source ? _T_5617 : _GEN_256; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _T_1309 = _T_1305 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@40245.4]
assign _T_1375 = _GEN_257 & _T_1309; // @[ToAXI4.scala 176:49:freechips.rocketchip.system.LowRiscConfig.fir@40361.4]
assign _T_1376 = _T_1375 == 1'h0; // @[ToAXI4.scala 177:21:freechips.rocketchip.system.LowRiscConfig.fir@40362.4]
assign _T_1336_ready = Queue_1_io_enq_ready; // @[ToAXI4.scala 146:25:freechips.rocketchip.system.LowRiscConfig.fir@40279.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@40313.4]
assign _T_1377 = _T_1363 | _T_1336_ready; // @[ToAXI4.scala 177:52:freechips.rocketchip.system.LowRiscConfig.fir@40363.4]
assign _T_1339_ready = Queue_io_enq_ready; // @[ToAXI4.scala 147:23:freechips.rocketchip.system.LowRiscConfig.fir@40281.4 Decoupled.scala 296:17:freechips.rocketchip.system.LowRiscConfig.fir@40290.4]
assign _T_1378 = _T_1377 & _T_1339_ready; // @[ToAXI4.scala 177:70:freechips.rocketchip.system.LowRiscConfig.fir@40364.4]
assign _T_1379 = _T_1294 ? _T_1378 : _T_1336_ready; // @[ToAXI4.scala 177:34:freechips.rocketchip.system.LowRiscConfig.fir@40365.4]
assign _T_1380 = _T_1376 & _T_1379; // @[ToAXI4.scala 177:28:freechips.rocketchip.system.LowRiscConfig.fir@40366.4]
assign _T_1295 = _T_1380 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40232.4]
assign _T_1297 = 13'h3f << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@40234.4]
assign _T_1298 = _T_1297[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@40235.4]
assign _T_1299 = ~ _T_1298; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@40236.4]
assign _T_1300 = _T_1299[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@40237.4]
assign _T_1303 = _T_1294 ? _T_1300 : 3'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@40240.4]
assign _T_1306 = _T_1305 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@40242.4]
assign _T_1307 = $unsigned(_T_1306); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@40243.4]
assign _T_1308 = _T_1307[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@40244.4]
assign _T_1310 = _T_1305 == 3'h1; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@40246.4]
assign _T_1311 = _T_1303 == 3'h0; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@40247.4]
assign _T_1312 = _T_1310 | _T_1311; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@40248.4]
assign _GEN_389 = {{7'd0}, auto_in_a_bits_size}; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@40273.4]
assign _T_1326 = _GEN_389 << 7; // @[ToAXI4.scala 134:55:freechips.rocketchip.system.LowRiscConfig.fir@40273.4]
assign _GEN_390 = {{3'd0}, auto_in_a_bits_source}; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.LowRiscConfig.fir@40274.4]
assign _T_1327 = _GEN_390 | _T_1326; // @[ToAXI4.scala 134:45:freechips.rocketchip.system.LowRiscConfig.fir@40274.4]
assign _T_1328 = auto_out_r_bits_user[6:0]; // @[ToAXI4.scala 137:50:freechips.rocketchip.system.LowRiscConfig.fir@40275.4]
assign _T_1329 = auto_out_r_bits_user[9:7]; // @[ToAXI4.scala 138:50:freechips.rocketchip.system.LowRiscConfig.fir@40276.4]
assign _T_1330 = auto_out_b_bits_user[6:0]; // @[ToAXI4.scala 141:50:freechips.rocketchip.system.LowRiscConfig.fir@40277.4]
assign _T_1331 = auto_out_b_bits_user[9:7]; // @[ToAXI4.scala 142:50:freechips.rocketchip.system.LowRiscConfig.fir@40278.4]
assign _T_1354_bits_wen = Queue_1_io_deq_bits_wen; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@40314.4 Decoupled.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@40315.4]
assign _T_1358 = _T_1354_bits_wen == 1'h0; // @[ToAXI4.scala 154:42:freechips.rocketchip.system.LowRiscConfig.fir@40330.4]
assign _T_1354_valid = Queue_1_io_deq_valid; // @[Decoupled.scala 314:19:freechips.rocketchip.system.LowRiscConfig.fir@40314.4 Decoupled.scala 316:15:freechips.rocketchip.system.LowRiscConfig.fir@40326.4]
assign _T_1365 = _T_1312 == 1'h0; // @[ToAXI4.scala 161:38:freechips.rocketchip.system.LowRiscConfig.fir@40340.6]
assign _GEN_3 = 7'h1 == auto_in_a_bits_source ? 7'h1 : 7'h0; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_4 = 7'h2 == auto_in_a_bits_source ? 7'h2 : _GEN_3; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_5 = 7'h3 == auto_in_a_bits_source ? 7'h3 : _GEN_4; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_6 = 7'h4 == auto_in_a_bits_source ? 7'h4 : _GEN_5; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_7 = 7'h5 == auto_in_a_bits_source ? 7'h5 : _GEN_6; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_8 = 7'h6 == auto_in_a_bits_source ? 7'h6 : _GEN_7; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_9 = 7'h7 == auto_in_a_bits_source ? 7'h7 : _GEN_8; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_10 = 7'h8 == auto_in_a_bits_source ? 7'h8 : _GEN_9; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_11 = 7'h9 == auto_in_a_bits_source ? 7'h9 : _GEN_10; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_12 = 7'ha == auto_in_a_bits_source ? 7'ha : _GEN_11; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_13 = 7'hb == auto_in_a_bits_source ? 7'hb : _GEN_12; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_14 = 7'hc == auto_in_a_bits_source ? 7'hc : _GEN_13; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_15 = 7'hd == auto_in_a_bits_source ? 7'hd : _GEN_14; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_16 = 7'he == auto_in_a_bits_source ? 7'he : _GEN_15; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_17 = 7'hf == auto_in_a_bits_source ? 7'hf : _GEN_16; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_18 = 7'h10 == auto_in_a_bits_source ? 7'h10 : _GEN_17; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_19 = 7'h11 == auto_in_a_bits_source ? 7'h11 : _GEN_18; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_20 = 7'h12 == auto_in_a_bits_source ? 7'h12 : _GEN_19; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_21 = 7'h13 == auto_in_a_bits_source ? 7'h13 : _GEN_20; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_22 = 7'h14 == auto_in_a_bits_source ? 7'h14 : _GEN_21; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_23 = 7'h15 == auto_in_a_bits_source ? 7'h15 : _GEN_22; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_24 = 7'h16 == auto_in_a_bits_source ? 7'h16 : _GEN_23; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_25 = 7'h17 == auto_in_a_bits_source ? 7'h17 : _GEN_24; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_26 = 7'h18 == auto_in_a_bits_source ? 7'h18 : _GEN_25; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_27 = 7'h19 == auto_in_a_bits_source ? 7'h19 : _GEN_26; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_28 = 7'h1a == auto_in_a_bits_source ? 7'h1a : _GEN_27; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_29 = 7'h1b == auto_in_a_bits_source ? 7'h1b : _GEN_28; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_30 = 7'h1c == auto_in_a_bits_source ? 7'h1c : _GEN_29; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_31 = 7'h1d == auto_in_a_bits_source ? 7'h1d : _GEN_30; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_32 = 7'h1e == auto_in_a_bits_source ? 7'h1e : _GEN_31; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_33 = 7'h1f == auto_in_a_bits_source ? 7'h1f : _GEN_32; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_34 = 7'h20 == auto_in_a_bits_source ? 7'h20 : _GEN_33; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_35 = 7'h21 == auto_in_a_bits_source ? 7'h21 : _GEN_34; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_36 = 7'h22 == auto_in_a_bits_source ? 7'h22 : _GEN_35; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_37 = 7'h23 == auto_in_a_bits_source ? 7'h23 : _GEN_36; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_38 = 7'h24 == auto_in_a_bits_source ? 7'h24 : _GEN_37; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_39 = 7'h25 == auto_in_a_bits_source ? 7'h25 : _GEN_38; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_40 = 7'h26 == auto_in_a_bits_source ? 7'h26 : _GEN_39; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_41 = 7'h27 == auto_in_a_bits_source ? 7'h27 : _GEN_40; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_42 = 7'h28 == auto_in_a_bits_source ? 7'h28 : _GEN_41; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_43 = 7'h29 == auto_in_a_bits_source ? 7'h29 : _GEN_42; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_44 = 7'h2a == auto_in_a_bits_source ? 7'h2a : _GEN_43; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_45 = 7'h2b == auto_in_a_bits_source ? 7'h2b : _GEN_44; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_46 = 7'h2c == auto_in_a_bits_source ? 7'h2c : _GEN_45; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_47 = 7'h2d == auto_in_a_bits_source ? 7'h2d : _GEN_46; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_48 = 7'h2e == auto_in_a_bits_source ? 7'h2e : _GEN_47; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_49 = 7'h2f == auto_in_a_bits_source ? 7'h2f : _GEN_48; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_50 = 7'h30 == auto_in_a_bits_source ? 7'h30 : _GEN_49; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_51 = 7'h31 == auto_in_a_bits_source ? 7'h31 : _GEN_50; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_52 = 7'h32 == auto_in_a_bits_source ? 7'h32 : _GEN_51; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_53 = 7'h33 == auto_in_a_bits_source ? 7'h33 : _GEN_52; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_54 = 7'h34 == auto_in_a_bits_source ? 7'h34 : _GEN_53; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_55 = 7'h35 == auto_in_a_bits_source ? 7'h35 : _GEN_54; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_56 = 7'h36 == auto_in_a_bits_source ? 7'h36 : _GEN_55; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_57 = 7'h37 == auto_in_a_bits_source ? 7'h37 : _GEN_56; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_58 = 7'h38 == auto_in_a_bits_source ? 7'h38 : _GEN_57; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_59 = 7'h39 == auto_in_a_bits_source ? 7'h39 : _GEN_58; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_60 = 7'h3a == auto_in_a_bits_source ? 7'h3a : _GEN_59; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_61 = 7'h3b == auto_in_a_bits_source ? 7'h3b : _GEN_60; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_62 = 7'h3c == auto_in_a_bits_source ? 7'h3c : _GEN_61; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_63 = 7'h3d == auto_in_a_bits_source ? 7'h3d : _GEN_62; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_64 = 7'h3e == auto_in_a_bits_source ? 7'h3e : _GEN_63; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_65 = 7'h3f == auto_in_a_bits_source ? 7'h3f : _GEN_64; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_66 = 7'h40 == auto_in_a_bits_source ? 7'h40 : _GEN_65; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_67 = 7'h41 == auto_in_a_bits_source ? 7'h41 : _GEN_66; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_68 = 7'h42 == auto_in_a_bits_source ? 7'h42 : _GEN_67; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_69 = 7'h43 == auto_in_a_bits_source ? 7'h43 : _GEN_68; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_70 = 7'h44 == auto_in_a_bits_source ? 7'h44 : _GEN_69; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_71 = 7'h45 == auto_in_a_bits_source ? 7'h45 : _GEN_70; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_72 = 7'h46 == auto_in_a_bits_source ? 7'h46 : _GEN_71; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_73 = 7'h47 == auto_in_a_bits_source ? 7'h47 : _GEN_72; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_74 = 7'h48 == auto_in_a_bits_source ? 7'h48 : _GEN_73; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_75 = 7'h49 == auto_in_a_bits_source ? 7'h49 : _GEN_74; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_76 = 7'h4a == auto_in_a_bits_source ? 7'h4a : _GEN_75; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_77 = 7'h4b == auto_in_a_bits_source ? 7'h4b : _GEN_76; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_78 = 7'h4c == auto_in_a_bits_source ? 7'h4c : _GEN_77; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_79 = 7'h4d == auto_in_a_bits_source ? 7'h4d : _GEN_78; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_80 = 7'h4e == auto_in_a_bits_source ? 7'h4e : _GEN_79; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_81 = 7'h4f == auto_in_a_bits_source ? 7'h4f : _GEN_80; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_82 = 7'h50 == auto_in_a_bits_source ? 7'h50 : _GEN_81; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_83 = 7'h51 == auto_in_a_bits_source ? 7'h51 : _GEN_82; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_84 = 7'h52 == auto_in_a_bits_source ? 7'h52 : _GEN_83; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_85 = 7'h53 == auto_in_a_bits_source ? 7'h53 : _GEN_84; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_86 = 7'h54 == auto_in_a_bits_source ? 7'h54 : _GEN_85; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_87 = 7'h55 == auto_in_a_bits_source ? 7'h55 : _GEN_86; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_88 = 7'h56 == auto_in_a_bits_source ? 7'h56 : _GEN_87; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_89 = 7'h57 == auto_in_a_bits_source ? 7'h57 : _GEN_88; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_90 = 7'h58 == auto_in_a_bits_source ? 7'h58 : _GEN_89; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_91 = 7'h59 == auto_in_a_bits_source ? 7'h59 : _GEN_90; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_92 = 7'h5a == auto_in_a_bits_source ? 7'h5a : _GEN_91; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_93 = 7'h5b == auto_in_a_bits_source ? 7'h5b : _GEN_92; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_94 = 7'h5c == auto_in_a_bits_source ? 7'h5c : _GEN_93; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_95 = 7'h5d == auto_in_a_bits_source ? 7'h5d : _GEN_94; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_96 = 7'h5e == auto_in_a_bits_source ? 7'h5e : _GEN_95; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_97 = 7'h5f == auto_in_a_bits_source ? 7'h5f : _GEN_96; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_98 = 7'h60 == auto_in_a_bits_source ? 7'h60 : _GEN_97; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_99 = 7'h61 == auto_in_a_bits_source ? 7'h61 : _GEN_98; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_100 = 7'h62 == auto_in_a_bits_source ? 7'h62 : _GEN_99; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_101 = 7'h63 == auto_in_a_bits_source ? 7'h63 : _GEN_100; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_102 = 7'h64 == auto_in_a_bits_source ? 7'h64 : _GEN_101; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_103 = 7'h65 == auto_in_a_bits_source ? 7'h65 : _GEN_102; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_104 = 7'h66 == auto_in_a_bits_source ? 7'h66 : _GEN_103; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_105 = 7'h67 == auto_in_a_bits_source ? 7'h67 : _GEN_104; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_106 = 7'h68 == auto_in_a_bits_source ? 7'h68 : _GEN_105; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_107 = 7'h69 == auto_in_a_bits_source ? 7'h69 : _GEN_106; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_108 = 7'h6a == auto_in_a_bits_source ? 7'h6a : _GEN_107; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_109 = 7'h6b == auto_in_a_bits_source ? 7'h6b : _GEN_108; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_110 = 7'h6c == auto_in_a_bits_source ? 7'h6c : _GEN_109; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_111 = 7'h6d == auto_in_a_bits_source ? 7'h6d : _GEN_110; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_112 = 7'h6e == auto_in_a_bits_source ? 7'h6e : _GEN_111; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_113 = 7'h6f == auto_in_a_bits_source ? 7'h6f : _GEN_112; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_114 = 7'h70 == auto_in_a_bits_source ? 7'h70 : _GEN_113; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_115 = 7'h71 == auto_in_a_bits_source ? 7'h71 : _GEN_114; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_116 = 7'h72 == auto_in_a_bits_source ? 7'h72 : _GEN_115; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_117 = 7'h73 == auto_in_a_bits_source ? 7'h73 : _GEN_116; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_118 = 7'h74 == auto_in_a_bits_source ? 7'h74 : _GEN_117; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_119 = 7'h75 == auto_in_a_bits_source ? 7'h75 : _GEN_118; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_120 = 7'h76 == auto_in_a_bits_source ? 7'h76 : _GEN_119; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_121 = 7'h77 == auto_in_a_bits_source ? 7'h77 : _GEN_120; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_122 = 7'h78 == auto_in_a_bits_source ? 7'h78 : _GEN_121; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_123 = 7'h79 == auto_in_a_bits_source ? 7'h79 : _GEN_122; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_124 = 7'h7a == auto_in_a_bits_source ? 7'h7a : _GEN_123; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_125 = 7'h7b == auto_in_a_bits_source ? 7'h7b : _GEN_124; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_126 = 7'h7c == auto_in_a_bits_source ? 7'h7c : _GEN_125; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_127 = 7'h7d == auto_in_a_bits_source ? 7'h7d : _GEN_126; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_128 = 7'h7e == auto_in_a_bits_source ? 7'h7e : _GEN_127; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _GEN_129 = 7'h7f == auto_in_a_bits_source ? 7'h7f : _GEN_128; // @[ToAXI4.scala 165:17:freechips.rocketchip.system.LowRiscConfig.fir@40344.4]
assign _T_1368 = 18'h7ff << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@40347.4]
assign _T_1369 = _T_1368[10:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@40348.4]
assign _T_1370 = ~ _T_1369; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@40349.4]
assign _T_1372 = auto_in_a_bits_size >= 3'h3; // @[ToAXI4.scala 168:31:freechips.rocketchip.system.LowRiscConfig.fir@40352.4]
assign _T_1382 = _T_1376 & auto_in_a_valid; // @[ToAXI4.scala 178:31:freechips.rocketchip.system.LowRiscConfig.fir@40369.4]
assign _T_1383 = _T_1363 == 1'h0; // @[ToAXI4.scala 178:61:freechips.rocketchip.system.LowRiscConfig.fir@40370.4]
assign _T_1384 = _T_1383 & _T_1339_ready; // @[ToAXI4.scala 178:69:freechips.rocketchip.system.LowRiscConfig.fir@40371.4]
assign _T_1385 = _T_1294 ? _T_1384 : 1'h1; // @[ToAXI4.scala 178:51:freechips.rocketchip.system.LowRiscConfig.fir@40372.4]
assign _T_1386 = _T_1382 & _T_1385; // @[ToAXI4.scala 178:45:freechips.rocketchip.system.LowRiscConfig.fir@40373.4]
assign _T_1389 = _T_1382 & _T_1294; // @[ToAXI4.scala 180:43:freechips.rocketchip.system.LowRiscConfig.fir@40377.4]
assign _T_1394 = auto_in_d_ready & auto_out_r_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40385.4]
assign _T_1395 = auto_out_r_bits_last == 1'h0; // @[ToAXI4.scala 188:42:freechips.rocketchip.system.LowRiscConfig.fir@40387.6]
assign _T_1396 = auto_out_r_valid | _T_1393; // @[ToAXI4.scala 190:32:freechips.rocketchip.system.LowRiscConfig.fir@40390.4]
assign _T_1397 = _T_1396 == 1'h0; // @[ToAXI4.scala 193:36:freechips.rocketchip.system.LowRiscConfig.fir@40392.4]
assign _T_1399 = _T_1396 ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala 194:24:freechips.rocketchip.system.LowRiscConfig.fir@40395.4]
assign _T_1403 = auto_out_r_bits_resp == 2'h3; // @[ToAXI4.scala 201:39:freechips.rocketchip.system.LowRiscConfig.fir@40402.4]
assign _GEN_260 = _T_1401 ? _T_1403 : _T_1405; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@40404.4]
assign _T_1407 = auto_out_r_bits_resp != 2'h0; // @[ToAXI4.scala 202:39:freechips.rocketchip.system.LowRiscConfig.fir@40408.4]
assign _T_1408 = auto_out_b_bits_resp != 2'h0; // @[ToAXI4.scala 203:39:freechips.rocketchip.system.LowRiscConfig.fir@40409.4]
assign _T_1409 = _T_1407 | _GEN_260; // @[ToAXI4.scala 205:100:freechips.rocketchip.system.LowRiscConfig.fir@40410.4]
assign _T_1416 = 128'h1 << _GEN_129; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@40435.4]
assign _T_1418 = _T_1416[0]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40437.4]
assign _T_1419 = _T_1416[1]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40438.4]
assign _T_1420 = _T_1416[2]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40439.4]
assign _T_1421 = _T_1416[3]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40440.4]
assign _T_1422 = _T_1416[4]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40441.4]
assign _T_1423 = _T_1416[5]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40442.4]
assign _T_1424 = _T_1416[6]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40443.4]
assign _T_1425 = _T_1416[7]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40444.4]
assign _T_1426 = _T_1416[8]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40445.4]
assign _T_1427 = _T_1416[9]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40446.4]
assign _T_1428 = _T_1416[10]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40447.4]
assign _T_1429 = _T_1416[11]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40448.4]
assign _T_1430 = _T_1416[12]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40449.4]
assign _T_1431 = _T_1416[13]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40450.4]
assign _T_1432 = _T_1416[14]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40451.4]
assign _T_1433 = _T_1416[15]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40452.4]
assign _T_1434 = _T_1416[16]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40453.4]
assign _T_1435 = _T_1416[17]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40454.4]
assign _T_1436 = _T_1416[18]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40455.4]
assign _T_1437 = _T_1416[19]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40456.4]
assign _T_1438 = _T_1416[20]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40457.4]
assign _T_1439 = _T_1416[21]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40458.4]
assign _T_1440 = _T_1416[22]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40459.4]
assign _T_1441 = _T_1416[23]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40460.4]
assign _T_1442 = _T_1416[24]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40461.4]
assign _T_1443 = _T_1416[25]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40462.4]
assign _T_1444 = _T_1416[26]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40463.4]
assign _T_1445 = _T_1416[27]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40464.4]
assign _T_1446 = _T_1416[28]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40465.4]
assign _T_1447 = _T_1416[29]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40466.4]
assign _T_1448 = _T_1416[30]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40467.4]
assign _T_1449 = _T_1416[31]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40468.4]
assign _T_1450 = _T_1416[32]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40469.4]
assign _T_1451 = _T_1416[33]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40470.4]
assign _T_1452 = _T_1416[34]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40471.4]
assign _T_1453 = _T_1416[35]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40472.4]
assign _T_1454 = _T_1416[36]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40473.4]
assign _T_1455 = _T_1416[37]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40474.4]
assign _T_1456 = _T_1416[38]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40475.4]
assign _T_1457 = _T_1416[39]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40476.4]
assign _T_1458 = _T_1416[40]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40477.4]
assign _T_1459 = _T_1416[41]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40478.4]
assign _T_1460 = _T_1416[42]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40479.4]
assign _T_1461 = _T_1416[43]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40480.4]
assign _T_1462 = _T_1416[44]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40481.4]
assign _T_1463 = _T_1416[45]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40482.4]
assign _T_1464 = _T_1416[46]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40483.4]
assign _T_1465 = _T_1416[47]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40484.4]
assign _T_1466 = _T_1416[48]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40485.4]
assign _T_1467 = _T_1416[49]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40486.4]
assign _T_1468 = _T_1416[50]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40487.4]
assign _T_1469 = _T_1416[51]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40488.4]
assign _T_1470 = _T_1416[52]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40489.4]
assign _T_1471 = _T_1416[53]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40490.4]
assign _T_1472 = _T_1416[54]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40491.4]
assign _T_1473 = _T_1416[55]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40492.4]
assign _T_1474 = _T_1416[56]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40493.4]
assign _T_1475 = _T_1416[57]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40494.4]
assign _T_1476 = _T_1416[58]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40495.4]
assign _T_1477 = _T_1416[59]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40496.4]
assign _T_1478 = _T_1416[60]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40497.4]
assign _T_1479 = _T_1416[61]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40498.4]
assign _T_1480 = _T_1416[62]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40499.4]
assign _T_1481 = _T_1416[63]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40500.4]
assign _T_1482 = _T_1416[64]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40501.4]
assign _T_1483 = _T_1416[65]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40502.4]
assign _T_1484 = _T_1416[66]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40503.4]
assign _T_1485 = _T_1416[67]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40504.4]
assign _T_1486 = _T_1416[68]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40505.4]
assign _T_1487 = _T_1416[69]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40506.4]
assign _T_1488 = _T_1416[70]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40507.4]
assign _T_1489 = _T_1416[71]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40508.4]
assign _T_1490 = _T_1416[72]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40509.4]
assign _T_1491 = _T_1416[73]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40510.4]
assign _T_1492 = _T_1416[74]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40511.4]
assign _T_1493 = _T_1416[75]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40512.4]
assign _T_1494 = _T_1416[76]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40513.4]
assign _T_1495 = _T_1416[77]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40514.4]
assign _T_1496 = _T_1416[78]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40515.4]
assign _T_1497 = _T_1416[79]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40516.4]
assign _T_1498 = _T_1416[80]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40517.4]
assign _T_1499 = _T_1416[81]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40518.4]
assign _T_1500 = _T_1416[82]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40519.4]
assign _T_1501 = _T_1416[83]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40520.4]
assign _T_1502 = _T_1416[84]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40521.4]
assign _T_1503 = _T_1416[85]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40522.4]
assign _T_1504 = _T_1416[86]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40523.4]
assign _T_1505 = _T_1416[87]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40524.4]
assign _T_1506 = _T_1416[88]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40525.4]
assign _T_1507 = _T_1416[89]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40526.4]
assign _T_1508 = _T_1416[90]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40527.4]
assign _T_1509 = _T_1416[91]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40528.4]
assign _T_1510 = _T_1416[92]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40529.4]
assign _T_1511 = _T_1416[93]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40530.4]
assign _T_1512 = _T_1416[94]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40531.4]
assign _T_1513 = _T_1416[95]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40532.4]
assign _T_1514 = _T_1416[96]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40533.4]
assign _T_1515 = _T_1416[97]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40534.4]
assign _T_1516 = _T_1416[98]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40535.4]
assign _T_1517 = _T_1416[99]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40536.4]
assign _T_1518 = _T_1416[100]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40537.4]
assign _T_1519 = _T_1416[101]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40538.4]
assign _T_1520 = _T_1416[102]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40539.4]
assign _T_1521 = _T_1416[103]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40540.4]
assign _T_1522 = _T_1416[104]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40541.4]
assign _T_1523 = _T_1416[105]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40542.4]
assign _T_1524 = _T_1416[106]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40543.4]
assign _T_1525 = _T_1416[107]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40544.4]
assign _T_1526 = _T_1416[108]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40545.4]
assign _T_1527 = _T_1416[109]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40546.4]
assign _T_1528 = _T_1416[110]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40547.4]
assign _T_1529 = _T_1416[111]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40548.4]
assign _T_1530 = _T_1416[112]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40549.4]
assign _T_1531 = _T_1416[113]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40550.4]
assign _T_1532 = _T_1416[114]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40551.4]
assign _T_1533 = _T_1416[115]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40552.4]
assign _T_1534 = _T_1416[116]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40553.4]
assign _T_1535 = _T_1416[117]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40554.4]
assign _T_1536 = _T_1416[118]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40555.4]
assign _T_1537 = _T_1416[119]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40556.4]
assign _T_1538 = _T_1416[120]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40557.4]
assign _T_1539 = _T_1416[121]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40558.4]
assign _T_1540 = _T_1416[122]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40559.4]
assign _T_1541 = _T_1416[123]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40560.4]
assign _T_1542 = _T_1416[124]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40561.4]
assign _T_1543 = _T_1416[125]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40562.4]
assign _T_1544 = _T_1416[126]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40563.4]
assign _T_1545 = _T_1416[127]; // @[ToAXI4.scala 213:58:freechips.rocketchip.system.LowRiscConfig.fir@40564.4]
assign _T_1546 = _T_1396 ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala 214:31:freechips.rocketchip.system.LowRiscConfig.fir@40565.4]
assign _T_1548 = 128'h1 << _T_1546; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@40567.4]
assign _T_1550 = _T_1548[0]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40569.4]
assign _T_1551 = _T_1548[1]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40570.4]
assign _T_1552 = _T_1548[2]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40571.4]
assign _T_1553 = _T_1548[3]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40572.4]
assign _T_1554 = _T_1548[4]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40573.4]
assign _T_1555 = _T_1548[5]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40574.4]
assign _T_1556 = _T_1548[6]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40575.4]
assign _T_1557 = _T_1548[7]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40576.4]
assign _T_1558 = _T_1548[8]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40577.4]
assign _T_1559 = _T_1548[9]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40578.4]
assign _T_1560 = _T_1548[10]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40579.4]
assign _T_1561 = _T_1548[11]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40580.4]
assign _T_1562 = _T_1548[12]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40581.4]
assign _T_1563 = _T_1548[13]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40582.4]
assign _T_1564 = _T_1548[14]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40583.4]
assign _T_1565 = _T_1548[15]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40584.4]
assign _T_1566 = _T_1548[16]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40585.4]
assign _T_1567 = _T_1548[17]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40586.4]
assign _T_1568 = _T_1548[18]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40587.4]
assign _T_1569 = _T_1548[19]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40588.4]
assign _T_1570 = _T_1548[20]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40589.4]
assign _T_1571 = _T_1548[21]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40590.4]
assign _T_1572 = _T_1548[22]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40591.4]
assign _T_1573 = _T_1548[23]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40592.4]
assign _T_1574 = _T_1548[24]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40593.4]
assign _T_1575 = _T_1548[25]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40594.4]
assign _T_1576 = _T_1548[26]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40595.4]
assign _T_1577 = _T_1548[27]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40596.4]
assign _T_1578 = _T_1548[28]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40597.4]
assign _T_1579 = _T_1548[29]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40598.4]
assign _T_1580 = _T_1548[30]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40599.4]
assign _T_1581 = _T_1548[31]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40600.4]
assign _T_1582 = _T_1548[32]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40601.4]
assign _T_1583 = _T_1548[33]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40602.4]
assign _T_1584 = _T_1548[34]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40603.4]
assign _T_1585 = _T_1548[35]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40604.4]
assign _T_1586 = _T_1548[36]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40605.4]
assign _T_1587 = _T_1548[37]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40606.4]
assign _T_1588 = _T_1548[38]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40607.4]
assign _T_1589 = _T_1548[39]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40608.4]
assign _T_1590 = _T_1548[40]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40609.4]
assign _T_1591 = _T_1548[41]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40610.4]
assign _T_1592 = _T_1548[42]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40611.4]
assign _T_1593 = _T_1548[43]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40612.4]
assign _T_1594 = _T_1548[44]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40613.4]
assign _T_1595 = _T_1548[45]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40614.4]
assign _T_1596 = _T_1548[46]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40615.4]
assign _T_1597 = _T_1548[47]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40616.4]
assign _T_1598 = _T_1548[48]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40617.4]
assign _T_1599 = _T_1548[49]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40618.4]
assign _T_1600 = _T_1548[50]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40619.4]
assign _T_1601 = _T_1548[51]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40620.4]
assign _T_1602 = _T_1548[52]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40621.4]
assign _T_1603 = _T_1548[53]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40622.4]
assign _T_1604 = _T_1548[54]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40623.4]
assign _T_1605 = _T_1548[55]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40624.4]
assign _T_1606 = _T_1548[56]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40625.4]
assign _T_1607 = _T_1548[57]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40626.4]
assign _T_1608 = _T_1548[58]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40627.4]
assign _T_1609 = _T_1548[59]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40628.4]
assign _T_1610 = _T_1548[60]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40629.4]
assign _T_1611 = _T_1548[61]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40630.4]
assign _T_1612 = _T_1548[62]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40631.4]
assign _T_1613 = _T_1548[63]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40632.4]
assign _T_1614 = _T_1548[64]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40633.4]
assign _T_1615 = _T_1548[65]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40634.4]
assign _T_1616 = _T_1548[66]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40635.4]
assign _T_1617 = _T_1548[67]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40636.4]
assign _T_1618 = _T_1548[68]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40637.4]
assign _T_1619 = _T_1548[69]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40638.4]
assign _T_1620 = _T_1548[70]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40639.4]
assign _T_1621 = _T_1548[71]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40640.4]
assign _T_1622 = _T_1548[72]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40641.4]
assign _T_1623 = _T_1548[73]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40642.4]
assign _T_1624 = _T_1548[74]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40643.4]
assign _T_1625 = _T_1548[75]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40644.4]
assign _T_1626 = _T_1548[76]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40645.4]
assign _T_1627 = _T_1548[77]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40646.4]
assign _T_1628 = _T_1548[78]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40647.4]
assign _T_1629 = _T_1548[79]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40648.4]
assign _T_1630 = _T_1548[80]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40649.4]
assign _T_1631 = _T_1548[81]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40650.4]
assign _T_1632 = _T_1548[82]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40651.4]
assign _T_1633 = _T_1548[83]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40652.4]
assign _T_1634 = _T_1548[84]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40653.4]
assign _T_1635 = _T_1548[85]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40654.4]
assign _T_1636 = _T_1548[86]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40655.4]
assign _T_1637 = _T_1548[87]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40656.4]
assign _T_1638 = _T_1548[88]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40657.4]
assign _T_1639 = _T_1548[89]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40658.4]
assign _T_1640 = _T_1548[90]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40659.4]
assign _T_1641 = _T_1548[91]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40660.4]
assign _T_1642 = _T_1548[92]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40661.4]
assign _T_1643 = _T_1548[93]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40662.4]
assign _T_1644 = _T_1548[94]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40663.4]
assign _T_1645 = _T_1548[95]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40664.4]
assign _T_1646 = _T_1548[96]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40665.4]
assign _T_1647 = _T_1548[97]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40666.4]
assign _T_1648 = _T_1548[98]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40667.4]
assign _T_1649 = _T_1548[99]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40668.4]
assign _T_1650 = _T_1548[100]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40669.4]
assign _T_1651 = _T_1548[101]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40670.4]
assign _T_1652 = _T_1548[102]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40671.4]
assign _T_1653 = _T_1548[103]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40672.4]
assign _T_1654 = _T_1548[104]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40673.4]
assign _T_1655 = _T_1548[105]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40674.4]
assign _T_1656 = _T_1548[106]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40675.4]
assign _T_1657 = _T_1548[107]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40676.4]
assign _T_1658 = _T_1548[108]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40677.4]
assign _T_1659 = _T_1548[109]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40678.4]
assign _T_1660 = _T_1548[110]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40679.4]
assign _T_1661 = _T_1548[111]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40680.4]
assign _T_1662 = _T_1548[112]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40681.4]
assign _T_1663 = _T_1548[113]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40682.4]
assign _T_1664 = _T_1548[114]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40683.4]
assign _T_1665 = _T_1548[115]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40684.4]
assign _T_1666 = _T_1548[116]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40685.4]
assign _T_1667 = _T_1548[117]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40686.4]
assign _T_1668 = _T_1548[118]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40687.4]
assign _T_1669 = _T_1548[119]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40688.4]
assign _T_1670 = _T_1548[120]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40689.4]
assign _T_1671 = _T_1548[121]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40690.4]
assign _T_1672 = _T_1548[122]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40691.4]
assign _T_1673 = _T_1548[123]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40692.4]
assign _T_1674 = _T_1548[124]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40693.4]
assign _T_1675 = _T_1548[125]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40694.4]
assign _T_1676 = _T_1548[126]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40695.4]
assign _T_1677 = _T_1548[127]; // @[ToAXI4.scala 214:93:freechips.rocketchip.system.LowRiscConfig.fir@40696.4]
assign _T_1678 = _T_1396 ? auto_out_r_bits_last : 1'h1; // @[ToAXI4.scala 215:23:freechips.rocketchip.system.LowRiscConfig.fir@40697.4]
assign _T_1684 = _T_1336_ready & _T_1386; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40701.4]
assign _T_1685 = _T_1418 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40702.4]
assign _T_1686 = _T_1550 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40703.4]
assign _T_1687 = auto_in_d_ready & _T_1399; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@40704.4]
assign _T_1688 = _T_1686 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40705.4]
assign _T_1690 = _T_1680 + _T_1685; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40707.4]
assign _T_1691 = _T_1690 - _T_1688; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40708.4]
assign _T_1692 = $unsigned(_T_1691); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40709.4]
assign _T_1693 = _T_1692[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40710.4]
assign _T_1694 = _T_1688 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40712.4]
assign _T_1696 = _T_1694 | _T_1680; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40714.4]
assign _T_1698 = _T_1696 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40716.4]
assign _T_1699 = _T_1698 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40717.4]
assign _T_1700 = _T_1685 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40722.4]
assign _T_1701 = _T_1680 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40723.4]
assign _T_1702 = _T_1700 | _T_1701; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40724.4]
assign _T_1704 = _T_1702 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40726.4]
assign _T_1705 = _T_1704 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40727.4]
assign _T_1716 = _T_1419 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40744.4]
assign _T_1717 = _T_1551 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40745.4]
assign _T_1719 = _T_1717 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40747.4]
assign _T_1721 = _T_1711 + _T_1716; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40749.4]
assign _T_1722 = _T_1721 - _T_1719; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40750.4]
assign _T_1723 = $unsigned(_T_1722); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40751.4]
assign _T_1724 = _T_1723[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40752.4]
assign _T_1725 = _T_1719 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40754.4]
assign _T_1727 = _T_1725 | _T_1711; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40756.4]
assign _T_1729 = _T_1727 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40758.4]
assign _T_1730 = _T_1729 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40759.4]
assign _T_1731 = _T_1716 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40764.4]
assign _T_1732 = _T_1711 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40765.4]
assign _T_1733 = _T_1731 | _T_1732; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40766.4]
assign _T_1735 = _T_1733 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40768.4]
assign _T_1736 = _T_1735 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40769.4]
assign _T_1747 = _T_1420 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40786.4]
assign _T_1748 = _T_1552 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40787.4]
assign _T_1750 = _T_1748 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40789.4]
assign _T_1752 = _T_1742 + _T_1747; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40791.4]
assign _T_1753 = _T_1752 - _T_1750; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40792.4]
assign _T_1754 = $unsigned(_T_1753); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40793.4]
assign _T_1755 = _T_1754[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40794.4]
assign _T_1756 = _T_1750 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40796.4]
assign _T_1758 = _T_1756 | _T_1742; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40798.4]
assign _T_1760 = _T_1758 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40800.4]
assign _T_1761 = _T_1760 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40801.4]
assign _T_1762 = _T_1747 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40806.4]
assign _T_1763 = _T_1742 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40807.4]
assign _T_1764 = _T_1762 | _T_1763; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40808.4]
assign _T_1766 = _T_1764 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40810.4]
assign _T_1767 = _T_1766 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40811.4]
assign _T_1778 = _T_1421 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40828.4]
assign _T_1779 = _T_1553 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40829.4]
assign _T_1781 = _T_1779 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40831.4]
assign _T_1783 = _T_1773 + _T_1778; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40833.4]
assign _T_1784 = _T_1783 - _T_1781; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40834.4]
assign _T_1785 = $unsigned(_T_1784); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40835.4]
assign _T_1786 = _T_1785[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40836.4]
assign _T_1787 = _T_1781 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40838.4]
assign _T_1789 = _T_1787 | _T_1773; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40840.4]
assign _T_1791 = _T_1789 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40842.4]
assign _T_1792 = _T_1791 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40843.4]
assign _T_1793 = _T_1778 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40848.4]
assign _T_1794 = _T_1773 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40849.4]
assign _T_1795 = _T_1793 | _T_1794; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40850.4]
assign _T_1797 = _T_1795 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40852.4]
assign _T_1798 = _T_1797 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40853.4]
assign _T_1809 = _T_1422 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40870.4]
assign _T_1810 = _T_1554 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40871.4]
assign _T_1812 = _T_1810 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40873.4]
assign _T_1814 = _T_1804 + _T_1809; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40875.4]
assign _T_1815 = _T_1814 - _T_1812; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40876.4]
assign _T_1816 = $unsigned(_T_1815); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40877.4]
assign _T_1817 = _T_1816[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40878.4]
assign _T_1818 = _T_1812 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40880.4]
assign _T_1820 = _T_1818 | _T_1804; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40882.4]
assign _T_1822 = _T_1820 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40884.4]
assign _T_1823 = _T_1822 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40885.4]
assign _T_1824 = _T_1809 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40890.4]
assign _T_1825 = _T_1804 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40891.4]
assign _T_1826 = _T_1824 | _T_1825; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40892.4]
assign _T_1828 = _T_1826 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40894.4]
assign _T_1829 = _T_1828 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40895.4]
assign _T_1840 = _T_1423 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40912.4]
assign _T_1841 = _T_1555 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40913.4]
assign _T_1843 = _T_1841 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40915.4]
assign _T_1845 = _T_1835 + _T_1840; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40917.4]
assign _T_1846 = _T_1845 - _T_1843; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40918.4]
assign _T_1847 = $unsigned(_T_1846); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40919.4]
assign _T_1848 = _T_1847[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40920.4]
assign _T_1849 = _T_1843 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40922.4]
assign _T_1851 = _T_1849 | _T_1835; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40924.4]
assign _T_1853 = _T_1851 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40926.4]
assign _T_1854 = _T_1853 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40927.4]
assign _T_1855 = _T_1840 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40932.4]
assign _T_1856 = _T_1835 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40933.4]
assign _T_1857 = _T_1855 | _T_1856; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40934.4]
assign _T_1859 = _T_1857 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40936.4]
assign _T_1860 = _T_1859 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40937.4]
assign _T_1871 = _T_1424 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40954.4]
assign _T_1872 = _T_1556 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40955.4]
assign _T_1874 = _T_1872 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40957.4]
assign _T_1876 = _T_1866 + _T_1871; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@40959.4]
assign _T_1877 = _T_1876 - _T_1874; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40960.4]
assign _T_1878 = $unsigned(_T_1877); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40961.4]
assign _T_1879 = _T_1878[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@40962.4]
assign _T_1880 = _T_1874 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@40964.4]
assign _T_1882 = _T_1880 | _T_1866; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@40966.4]
assign _T_1884 = _T_1882 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40968.4]
assign _T_1885 = _T_1884 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40969.4]
assign _T_1886 = _T_1871 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@40974.4]
assign _T_1887 = _T_1866 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@40975.4]
assign _T_1888 = _T_1886 | _T_1887; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@40976.4]
assign _T_1890 = _T_1888 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40978.4]
assign _T_1891 = _T_1890 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40979.4]
assign _T_1902 = _T_1425 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@40996.4]
assign _T_1903 = _T_1557 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@40997.4]
assign _T_1905 = _T_1903 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@40999.4]
assign _T_1907 = _T_1897 + _T_1902; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41001.4]
assign _T_1908 = _T_1907 - _T_1905; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41002.4]
assign _T_1909 = $unsigned(_T_1908); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41003.4]
assign _T_1910 = _T_1909[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41004.4]
assign _T_1911 = _T_1905 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41006.4]
assign _T_1913 = _T_1911 | _T_1897; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41008.4]
assign _T_1915 = _T_1913 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41010.4]
assign _T_1916 = _T_1915 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41011.4]
assign _T_1917 = _T_1902 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41016.4]
assign _T_1918 = _T_1897 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41017.4]
assign _T_1919 = _T_1917 | _T_1918; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41018.4]
assign _T_1921 = _T_1919 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41020.4]
assign _T_1922 = _T_1921 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41021.4]
assign _T_1933 = _T_1426 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41038.4]
assign _T_1934 = _T_1558 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41039.4]
assign _T_1936 = _T_1934 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41041.4]
assign _T_1938 = _T_1928 + _T_1933; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41043.4]
assign _T_1939 = _T_1938 - _T_1936; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41044.4]
assign _T_1940 = $unsigned(_T_1939); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41045.4]
assign _T_1941 = _T_1940[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41046.4]
assign _T_1942 = _T_1936 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41048.4]
assign _T_1944 = _T_1942 | _T_1928; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41050.4]
assign _T_1946 = _T_1944 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41052.4]
assign _T_1947 = _T_1946 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41053.4]
assign _T_1948 = _T_1933 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41058.4]
assign _T_1949 = _T_1928 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41059.4]
assign _T_1950 = _T_1948 | _T_1949; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41060.4]
assign _T_1952 = _T_1950 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41062.4]
assign _T_1953 = _T_1952 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41063.4]
assign _T_1964 = _T_1427 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41080.4]
assign _T_1965 = _T_1559 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41081.4]
assign _T_1967 = _T_1965 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41083.4]
assign _T_1969 = _T_1959 + _T_1964; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41085.4]
assign _T_1970 = _T_1969 - _T_1967; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41086.4]
assign _T_1971 = $unsigned(_T_1970); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41087.4]
assign _T_1972 = _T_1971[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41088.4]
assign _T_1973 = _T_1967 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41090.4]
assign _T_1975 = _T_1973 | _T_1959; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41092.4]
assign _T_1977 = _T_1975 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41094.4]
assign _T_1978 = _T_1977 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41095.4]
assign _T_1979 = _T_1964 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41100.4]
assign _T_1980 = _T_1959 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41101.4]
assign _T_1981 = _T_1979 | _T_1980; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41102.4]
assign _T_1983 = _T_1981 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41104.4]
assign _T_1984 = _T_1983 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41105.4]
assign _T_1995 = _T_1428 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41122.4]
assign _T_1996 = _T_1560 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41123.4]
assign _T_1998 = _T_1996 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41125.4]
assign _T_2000 = _T_1990 + _T_1995; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41127.4]
assign _T_2001 = _T_2000 - _T_1998; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41128.4]
assign _T_2002 = $unsigned(_T_2001); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41129.4]
assign _T_2003 = _T_2002[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41130.4]
assign _T_2004 = _T_1998 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41132.4]
assign _T_2006 = _T_2004 | _T_1990; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41134.4]
assign _T_2008 = _T_2006 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41136.4]
assign _T_2009 = _T_2008 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41137.4]
assign _T_2010 = _T_1995 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41142.4]
assign _T_2011 = _T_1990 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41143.4]
assign _T_2012 = _T_2010 | _T_2011; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41144.4]
assign _T_2014 = _T_2012 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41146.4]
assign _T_2015 = _T_2014 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41147.4]
assign _T_2026 = _T_1429 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41164.4]
assign _T_2027 = _T_1561 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41165.4]
assign _T_2029 = _T_2027 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41167.4]
assign _T_2031 = _T_2021 + _T_2026; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41169.4]
assign _T_2032 = _T_2031 - _T_2029; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41170.4]
assign _T_2033 = $unsigned(_T_2032); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41171.4]
assign _T_2034 = _T_2033[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41172.4]
assign _T_2035 = _T_2029 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41174.4]
assign _T_2037 = _T_2035 | _T_2021; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41176.4]
assign _T_2039 = _T_2037 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41178.4]
assign _T_2040 = _T_2039 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41179.4]
assign _T_2041 = _T_2026 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41184.4]
assign _T_2042 = _T_2021 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41185.4]
assign _T_2043 = _T_2041 | _T_2042; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41186.4]
assign _T_2045 = _T_2043 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41188.4]
assign _T_2046 = _T_2045 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41189.4]
assign _T_2057 = _T_1430 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41206.4]
assign _T_2058 = _T_1562 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41207.4]
assign _T_2060 = _T_2058 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41209.4]
assign _T_2062 = _T_2052 + _T_2057; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41211.4]
assign _T_2063 = _T_2062 - _T_2060; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41212.4]
assign _T_2064 = $unsigned(_T_2063); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41213.4]
assign _T_2065 = _T_2064[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41214.4]
assign _T_2066 = _T_2060 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41216.4]
assign _T_2068 = _T_2066 | _T_2052; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41218.4]
assign _T_2070 = _T_2068 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41220.4]
assign _T_2071 = _T_2070 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41221.4]
assign _T_2072 = _T_2057 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41226.4]
assign _T_2073 = _T_2052 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41227.4]
assign _T_2074 = _T_2072 | _T_2073; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41228.4]
assign _T_2076 = _T_2074 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41230.4]
assign _T_2077 = _T_2076 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41231.4]
assign _T_2088 = _T_1431 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41248.4]
assign _T_2089 = _T_1563 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41249.4]
assign _T_2091 = _T_2089 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41251.4]
assign _T_2093 = _T_2083 + _T_2088; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41253.4]
assign _T_2094 = _T_2093 - _T_2091; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41254.4]
assign _T_2095 = $unsigned(_T_2094); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41255.4]
assign _T_2096 = _T_2095[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41256.4]
assign _T_2097 = _T_2091 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41258.4]
assign _T_2099 = _T_2097 | _T_2083; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41260.4]
assign _T_2101 = _T_2099 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41262.4]
assign _T_2102 = _T_2101 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41263.4]
assign _T_2103 = _T_2088 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41268.4]
assign _T_2104 = _T_2083 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41269.4]
assign _T_2105 = _T_2103 | _T_2104; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41270.4]
assign _T_2107 = _T_2105 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41272.4]
assign _T_2108 = _T_2107 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41273.4]
assign _T_2119 = _T_1432 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41290.4]
assign _T_2120 = _T_1564 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41291.4]
assign _T_2122 = _T_2120 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41293.4]
assign _T_2124 = _T_2114 + _T_2119; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41295.4]
assign _T_2125 = _T_2124 - _T_2122; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41296.4]
assign _T_2126 = $unsigned(_T_2125); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41297.4]
assign _T_2127 = _T_2126[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41298.4]
assign _T_2128 = _T_2122 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41300.4]
assign _T_2130 = _T_2128 | _T_2114; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41302.4]
assign _T_2132 = _T_2130 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41304.4]
assign _T_2133 = _T_2132 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41305.4]
assign _T_2134 = _T_2119 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41310.4]
assign _T_2135 = _T_2114 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41311.4]
assign _T_2136 = _T_2134 | _T_2135; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41312.4]
assign _T_2138 = _T_2136 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41314.4]
assign _T_2139 = _T_2138 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41315.4]
assign _T_2150 = _T_1433 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41332.4]
assign _T_2151 = _T_1565 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41333.4]
assign _T_2153 = _T_2151 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41335.4]
assign _T_2155 = _T_2145 + _T_2150; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41337.4]
assign _T_2156 = _T_2155 - _T_2153; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41338.4]
assign _T_2157 = $unsigned(_T_2156); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41339.4]
assign _T_2158 = _T_2157[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41340.4]
assign _T_2159 = _T_2153 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41342.4]
assign _T_2161 = _T_2159 | _T_2145; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41344.4]
assign _T_2163 = _T_2161 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41346.4]
assign _T_2164 = _T_2163 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41347.4]
assign _T_2165 = _T_2150 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41352.4]
assign _T_2166 = _T_2145 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41353.4]
assign _T_2167 = _T_2165 | _T_2166; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41354.4]
assign _T_2169 = _T_2167 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41356.4]
assign _T_2170 = _T_2169 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41357.4]
assign _T_2181 = _T_1434 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41374.4]
assign _T_2182 = _T_1566 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41375.4]
assign _T_2184 = _T_2182 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41377.4]
assign _T_2186 = _T_2176 + _T_2181; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41379.4]
assign _T_2187 = _T_2186 - _T_2184; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41380.4]
assign _T_2188 = $unsigned(_T_2187); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41381.4]
assign _T_2189 = _T_2188[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41382.4]
assign _T_2190 = _T_2184 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41384.4]
assign _T_2192 = _T_2190 | _T_2176; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41386.4]
assign _T_2194 = _T_2192 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41388.4]
assign _T_2195 = _T_2194 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41389.4]
assign _T_2196 = _T_2181 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41394.4]
assign _T_2197 = _T_2176 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41395.4]
assign _T_2198 = _T_2196 | _T_2197; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41396.4]
assign _T_2200 = _T_2198 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41398.4]
assign _T_2201 = _T_2200 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41399.4]
assign _T_2212 = _T_1435 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41416.4]
assign _T_2213 = _T_1567 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41417.4]
assign _T_2215 = _T_2213 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41419.4]
assign _T_2217 = _T_2207 + _T_2212; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41421.4]
assign _T_2218 = _T_2217 - _T_2215; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41422.4]
assign _T_2219 = $unsigned(_T_2218); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41423.4]
assign _T_2220 = _T_2219[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41424.4]
assign _T_2221 = _T_2215 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41426.4]
assign _T_2223 = _T_2221 | _T_2207; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41428.4]
assign _T_2225 = _T_2223 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41430.4]
assign _T_2226 = _T_2225 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41431.4]
assign _T_2227 = _T_2212 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41436.4]
assign _T_2228 = _T_2207 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41437.4]
assign _T_2229 = _T_2227 | _T_2228; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41438.4]
assign _T_2231 = _T_2229 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41440.4]
assign _T_2232 = _T_2231 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41441.4]
assign _T_2243 = _T_1436 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41458.4]
assign _T_2244 = _T_1568 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41459.4]
assign _T_2246 = _T_2244 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41461.4]
assign _T_2248 = _T_2238 + _T_2243; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41463.4]
assign _T_2249 = _T_2248 - _T_2246; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41464.4]
assign _T_2250 = $unsigned(_T_2249); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41465.4]
assign _T_2251 = _T_2250[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41466.4]
assign _T_2252 = _T_2246 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41468.4]
assign _T_2254 = _T_2252 | _T_2238; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41470.4]
assign _T_2256 = _T_2254 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41472.4]
assign _T_2257 = _T_2256 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41473.4]
assign _T_2258 = _T_2243 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41478.4]
assign _T_2259 = _T_2238 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41479.4]
assign _T_2260 = _T_2258 | _T_2259; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41480.4]
assign _T_2262 = _T_2260 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41482.4]
assign _T_2263 = _T_2262 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41483.4]
assign _T_2274 = _T_1437 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41500.4]
assign _T_2275 = _T_1569 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41501.4]
assign _T_2277 = _T_2275 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41503.4]
assign _T_2279 = _T_2269 + _T_2274; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41505.4]
assign _T_2280 = _T_2279 - _T_2277; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41506.4]
assign _T_2281 = $unsigned(_T_2280); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41507.4]
assign _T_2282 = _T_2281[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41508.4]
assign _T_2283 = _T_2277 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41510.4]
assign _T_2285 = _T_2283 | _T_2269; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41512.4]
assign _T_2287 = _T_2285 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41514.4]
assign _T_2288 = _T_2287 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41515.4]
assign _T_2289 = _T_2274 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41520.4]
assign _T_2290 = _T_2269 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41521.4]
assign _T_2291 = _T_2289 | _T_2290; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41522.4]
assign _T_2293 = _T_2291 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41524.4]
assign _T_2294 = _T_2293 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41525.4]
assign _T_2305 = _T_1438 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41542.4]
assign _T_2306 = _T_1570 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41543.4]
assign _T_2308 = _T_2306 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41545.4]
assign _T_2310 = _T_2300 + _T_2305; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41547.4]
assign _T_2311 = _T_2310 - _T_2308; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41548.4]
assign _T_2312 = $unsigned(_T_2311); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41549.4]
assign _T_2313 = _T_2312[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41550.4]
assign _T_2314 = _T_2308 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41552.4]
assign _T_2316 = _T_2314 | _T_2300; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41554.4]
assign _T_2318 = _T_2316 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41556.4]
assign _T_2319 = _T_2318 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41557.4]
assign _T_2320 = _T_2305 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41562.4]
assign _T_2321 = _T_2300 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41563.4]
assign _T_2322 = _T_2320 | _T_2321; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41564.4]
assign _T_2324 = _T_2322 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41566.4]
assign _T_2325 = _T_2324 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41567.4]
assign _T_2336 = _T_1439 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41584.4]
assign _T_2337 = _T_1571 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41585.4]
assign _T_2339 = _T_2337 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41587.4]
assign _T_2341 = _T_2331 + _T_2336; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41589.4]
assign _T_2342 = _T_2341 - _T_2339; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41590.4]
assign _T_2343 = $unsigned(_T_2342); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41591.4]
assign _T_2344 = _T_2343[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41592.4]
assign _T_2345 = _T_2339 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41594.4]
assign _T_2347 = _T_2345 | _T_2331; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41596.4]
assign _T_2349 = _T_2347 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41598.4]
assign _T_2350 = _T_2349 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41599.4]
assign _T_2351 = _T_2336 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41604.4]
assign _T_2352 = _T_2331 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41605.4]
assign _T_2353 = _T_2351 | _T_2352; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41606.4]
assign _T_2355 = _T_2353 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41608.4]
assign _T_2356 = _T_2355 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41609.4]
assign _T_2367 = _T_1440 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41626.4]
assign _T_2368 = _T_1572 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41627.4]
assign _T_2370 = _T_2368 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41629.4]
assign _T_2372 = _T_2362 + _T_2367; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41631.4]
assign _T_2373 = _T_2372 - _T_2370; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41632.4]
assign _T_2374 = $unsigned(_T_2373); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41633.4]
assign _T_2375 = _T_2374[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41634.4]
assign _T_2376 = _T_2370 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41636.4]
assign _T_2378 = _T_2376 | _T_2362; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41638.4]
assign _T_2380 = _T_2378 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41640.4]
assign _T_2381 = _T_2380 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41641.4]
assign _T_2382 = _T_2367 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41646.4]
assign _T_2383 = _T_2362 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41647.4]
assign _T_2384 = _T_2382 | _T_2383; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41648.4]
assign _T_2386 = _T_2384 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41650.4]
assign _T_2387 = _T_2386 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41651.4]
assign _T_2398 = _T_1441 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41668.4]
assign _T_2399 = _T_1573 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41669.4]
assign _T_2401 = _T_2399 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41671.4]
assign _T_2403 = _T_2393 + _T_2398; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41673.4]
assign _T_2404 = _T_2403 - _T_2401; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41674.4]
assign _T_2405 = $unsigned(_T_2404); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41675.4]
assign _T_2406 = _T_2405[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41676.4]
assign _T_2407 = _T_2401 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41678.4]
assign _T_2409 = _T_2407 | _T_2393; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41680.4]
assign _T_2411 = _T_2409 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41682.4]
assign _T_2412 = _T_2411 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41683.4]
assign _T_2413 = _T_2398 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41688.4]
assign _T_2414 = _T_2393 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41689.4]
assign _T_2415 = _T_2413 | _T_2414; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41690.4]
assign _T_2417 = _T_2415 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41692.4]
assign _T_2418 = _T_2417 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41693.4]
assign _T_2429 = _T_1442 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41710.4]
assign _T_2430 = _T_1574 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41711.4]
assign _T_2432 = _T_2430 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41713.4]
assign _T_2434 = _T_2424 + _T_2429; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41715.4]
assign _T_2435 = _T_2434 - _T_2432; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41716.4]
assign _T_2436 = $unsigned(_T_2435); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41717.4]
assign _T_2437 = _T_2436[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41718.4]
assign _T_2438 = _T_2432 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41720.4]
assign _T_2440 = _T_2438 | _T_2424; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41722.4]
assign _T_2442 = _T_2440 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41724.4]
assign _T_2443 = _T_2442 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41725.4]
assign _T_2444 = _T_2429 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41730.4]
assign _T_2445 = _T_2424 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41731.4]
assign _T_2446 = _T_2444 | _T_2445; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41732.4]
assign _T_2448 = _T_2446 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41734.4]
assign _T_2449 = _T_2448 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41735.4]
assign _T_2460 = _T_1443 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41752.4]
assign _T_2461 = _T_1575 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41753.4]
assign _T_2463 = _T_2461 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41755.4]
assign _T_2465 = _T_2455 + _T_2460; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41757.4]
assign _T_2466 = _T_2465 - _T_2463; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41758.4]
assign _T_2467 = $unsigned(_T_2466); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41759.4]
assign _T_2468 = _T_2467[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41760.4]
assign _T_2469 = _T_2463 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41762.4]
assign _T_2471 = _T_2469 | _T_2455; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41764.4]
assign _T_2473 = _T_2471 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41766.4]
assign _T_2474 = _T_2473 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41767.4]
assign _T_2475 = _T_2460 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41772.4]
assign _T_2476 = _T_2455 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41773.4]
assign _T_2477 = _T_2475 | _T_2476; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41774.4]
assign _T_2479 = _T_2477 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41776.4]
assign _T_2480 = _T_2479 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41777.4]
assign _T_2491 = _T_1444 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41794.4]
assign _T_2492 = _T_1576 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41795.4]
assign _T_2494 = _T_2492 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41797.4]
assign _T_2496 = _T_2486 + _T_2491; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41799.4]
assign _T_2497 = _T_2496 - _T_2494; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41800.4]
assign _T_2498 = $unsigned(_T_2497); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41801.4]
assign _T_2499 = _T_2498[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41802.4]
assign _T_2500 = _T_2494 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41804.4]
assign _T_2502 = _T_2500 | _T_2486; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41806.4]
assign _T_2504 = _T_2502 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41808.4]
assign _T_2505 = _T_2504 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41809.4]
assign _T_2506 = _T_2491 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41814.4]
assign _T_2507 = _T_2486 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41815.4]
assign _T_2508 = _T_2506 | _T_2507; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41816.4]
assign _T_2510 = _T_2508 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41818.4]
assign _T_2511 = _T_2510 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41819.4]
assign _T_2522 = _T_1445 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41836.4]
assign _T_2523 = _T_1577 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41837.4]
assign _T_2525 = _T_2523 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41839.4]
assign _T_2527 = _T_2517 + _T_2522; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41841.4]
assign _T_2528 = _T_2527 - _T_2525; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41842.4]
assign _T_2529 = $unsigned(_T_2528); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41843.4]
assign _T_2530 = _T_2529[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41844.4]
assign _T_2531 = _T_2525 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41846.4]
assign _T_2533 = _T_2531 | _T_2517; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41848.4]
assign _T_2535 = _T_2533 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41850.4]
assign _T_2536 = _T_2535 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41851.4]
assign _T_2537 = _T_2522 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41856.4]
assign _T_2538 = _T_2517 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41857.4]
assign _T_2539 = _T_2537 | _T_2538; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41858.4]
assign _T_2541 = _T_2539 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41860.4]
assign _T_2542 = _T_2541 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41861.4]
assign _T_2553 = _T_1446 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41878.4]
assign _T_2554 = _T_1578 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41879.4]
assign _T_2556 = _T_2554 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41881.4]
assign _T_2558 = _T_2548 + _T_2553; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41883.4]
assign _T_2559 = _T_2558 - _T_2556; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41884.4]
assign _T_2560 = $unsigned(_T_2559); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41885.4]
assign _T_2561 = _T_2560[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41886.4]
assign _T_2562 = _T_2556 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41888.4]
assign _T_2564 = _T_2562 | _T_2548; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41890.4]
assign _T_2566 = _T_2564 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41892.4]
assign _T_2567 = _T_2566 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41893.4]
assign _T_2568 = _T_2553 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41898.4]
assign _T_2569 = _T_2548 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41899.4]
assign _T_2570 = _T_2568 | _T_2569; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41900.4]
assign _T_2572 = _T_2570 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41902.4]
assign _T_2573 = _T_2572 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41903.4]
assign _T_2584 = _T_1447 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41920.4]
assign _T_2585 = _T_1579 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41921.4]
assign _T_2587 = _T_2585 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41923.4]
assign _T_2589 = _T_2579 + _T_2584; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41925.4]
assign _T_2590 = _T_2589 - _T_2587; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41926.4]
assign _T_2591 = $unsigned(_T_2590); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41927.4]
assign _T_2592 = _T_2591[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41928.4]
assign _T_2593 = _T_2587 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41930.4]
assign _T_2595 = _T_2593 | _T_2579; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41932.4]
assign _T_2597 = _T_2595 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41934.4]
assign _T_2598 = _T_2597 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41935.4]
assign _T_2599 = _T_2584 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41940.4]
assign _T_2600 = _T_2579 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41941.4]
assign _T_2601 = _T_2599 | _T_2600; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41942.4]
assign _T_2603 = _T_2601 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41944.4]
assign _T_2604 = _T_2603 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41945.4]
assign _T_2615 = _T_1448 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@41962.4]
assign _T_2616 = _T_1580 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@41963.4]
assign _T_2618 = _T_2616 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@41965.4]
assign _T_2620 = _T_2610 + _T_2615; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@41967.4]
assign _T_2621 = _T_2620 - _T_2618; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41968.4]
assign _T_2622 = $unsigned(_T_2621); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41969.4]
assign _T_2623 = _T_2622[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@41970.4]
assign _T_2624 = _T_2618 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@41972.4]
assign _T_2626 = _T_2624 | _T_2610; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@41974.4]
assign _T_2628 = _T_2626 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41976.4]
assign _T_2629 = _T_2628 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41977.4]
assign _T_2630 = _T_2615 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@41982.4]
assign _T_2631 = _T_2610 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@41983.4]
assign _T_2632 = _T_2630 | _T_2631; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@41984.4]
assign _T_2634 = _T_2632 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41986.4]
assign _T_2635 = _T_2634 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41987.4]
assign _T_2646 = _T_1449 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42004.4]
assign _T_2647 = _T_1581 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42005.4]
assign _T_2649 = _T_2647 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42007.4]
assign _T_2651 = _T_2641 + _T_2646; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42009.4]
assign _T_2652 = _T_2651 - _T_2649; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42010.4]
assign _T_2653 = $unsigned(_T_2652); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42011.4]
assign _T_2654 = _T_2653[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42012.4]
assign _T_2655 = _T_2649 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42014.4]
assign _T_2657 = _T_2655 | _T_2641; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42016.4]
assign _T_2659 = _T_2657 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42018.4]
assign _T_2660 = _T_2659 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42019.4]
assign _T_2661 = _T_2646 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42024.4]
assign _T_2662 = _T_2641 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42025.4]
assign _T_2663 = _T_2661 | _T_2662; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42026.4]
assign _T_2665 = _T_2663 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42028.4]
assign _T_2666 = _T_2665 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42029.4]
assign _T_2677 = _T_1450 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42046.4]
assign _T_2678 = _T_1582 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42047.4]
assign _T_2680 = _T_2678 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42049.4]
assign _T_2682 = _T_2672 + _T_2677; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42051.4]
assign _T_2683 = _T_2682 - _T_2680; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42052.4]
assign _T_2684 = $unsigned(_T_2683); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42053.4]
assign _T_2685 = _T_2684[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42054.4]
assign _T_2686 = _T_2680 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42056.4]
assign _T_2688 = _T_2686 | _T_2672; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42058.4]
assign _T_2690 = _T_2688 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42060.4]
assign _T_2691 = _T_2690 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42061.4]
assign _T_2692 = _T_2677 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42066.4]
assign _T_2693 = _T_2672 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42067.4]
assign _T_2694 = _T_2692 | _T_2693; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42068.4]
assign _T_2696 = _T_2694 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42070.4]
assign _T_2697 = _T_2696 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42071.4]
assign _T_2708 = _T_1451 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42088.4]
assign _T_2709 = _T_1583 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42089.4]
assign _T_2711 = _T_2709 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42091.4]
assign _T_2713 = _T_2703 + _T_2708; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42093.4]
assign _T_2714 = _T_2713 - _T_2711; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42094.4]
assign _T_2715 = $unsigned(_T_2714); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42095.4]
assign _T_2716 = _T_2715[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42096.4]
assign _T_2717 = _T_2711 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42098.4]
assign _T_2719 = _T_2717 | _T_2703; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42100.4]
assign _T_2721 = _T_2719 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42102.4]
assign _T_2722 = _T_2721 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42103.4]
assign _T_2723 = _T_2708 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42108.4]
assign _T_2724 = _T_2703 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42109.4]
assign _T_2725 = _T_2723 | _T_2724; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42110.4]
assign _T_2727 = _T_2725 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42112.4]
assign _T_2728 = _T_2727 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42113.4]
assign _T_2739 = _T_1452 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42130.4]
assign _T_2740 = _T_1584 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42131.4]
assign _T_2742 = _T_2740 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42133.4]
assign _T_2744 = _T_2734 + _T_2739; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42135.4]
assign _T_2745 = _T_2744 - _T_2742; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42136.4]
assign _T_2746 = $unsigned(_T_2745); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42137.4]
assign _T_2747 = _T_2746[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42138.4]
assign _T_2748 = _T_2742 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42140.4]
assign _T_2750 = _T_2748 | _T_2734; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42142.4]
assign _T_2752 = _T_2750 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42144.4]
assign _T_2753 = _T_2752 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42145.4]
assign _T_2754 = _T_2739 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42150.4]
assign _T_2755 = _T_2734 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42151.4]
assign _T_2756 = _T_2754 | _T_2755; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42152.4]
assign _T_2758 = _T_2756 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42154.4]
assign _T_2759 = _T_2758 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42155.4]
assign _T_2770 = _T_1453 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42172.4]
assign _T_2771 = _T_1585 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42173.4]
assign _T_2773 = _T_2771 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42175.4]
assign _T_2775 = _T_2765 + _T_2770; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42177.4]
assign _T_2776 = _T_2775 - _T_2773; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42178.4]
assign _T_2777 = $unsigned(_T_2776); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42179.4]
assign _T_2778 = _T_2777[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42180.4]
assign _T_2779 = _T_2773 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42182.4]
assign _T_2781 = _T_2779 | _T_2765; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42184.4]
assign _T_2783 = _T_2781 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42186.4]
assign _T_2784 = _T_2783 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42187.4]
assign _T_2785 = _T_2770 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42192.4]
assign _T_2786 = _T_2765 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42193.4]
assign _T_2787 = _T_2785 | _T_2786; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42194.4]
assign _T_2789 = _T_2787 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42196.4]
assign _T_2790 = _T_2789 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42197.4]
assign _T_2801 = _T_1454 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42214.4]
assign _T_2802 = _T_1586 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42215.4]
assign _T_2804 = _T_2802 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42217.4]
assign _T_2806 = _T_2796 + _T_2801; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42219.4]
assign _T_2807 = _T_2806 - _T_2804; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42220.4]
assign _T_2808 = $unsigned(_T_2807); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42221.4]
assign _T_2809 = _T_2808[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42222.4]
assign _T_2810 = _T_2804 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42224.4]
assign _T_2812 = _T_2810 | _T_2796; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42226.4]
assign _T_2814 = _T_2812 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42228.4]
assign _T_2815 = _T_2814 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42229.4]
assign _T_2816 = _T_2801 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42234.4]
assign _T_2817 = _T_2796 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42235.4]
assign _T_2818 = _T_2816 | _T_2817; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42236.4]
assign _T_2820 = _T_2818 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42238.4]
assign _T_2821 = _T_2820 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42239.4]
assign _T_2832 = _T_1455 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42256.4]
assign _T_2833 = _T_1587 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42257.4]
assign _T_2835 = _T_2833 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42259.4]
assign _T_2837 = _T_2827 + _T_2832; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42261.4]
assign _T_2838 = _T_2837 - _T_2835; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42262.4]
assign _T_2839 = $unsigned(_T_2838); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42263.4]
assign _T_2840 = _T_2839[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42264.4]
assign _T_2841 = _T_2835 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42266.4]
assign _T_2843 = _T_2841 | _T_2827; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42268.4]
assign _T_2845 = _T_2843 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42270.4]
assign _T_2846 = _T_2845 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42271.4]
assign _T_2847 = _T_2832 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42276.4]
assign _T_2848 = _T_2827 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42277.4]
assign _T_2849 = _T_2847 | _T_2848; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42278.4]
assign _T_2851 = _T_2849 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42280.4]
assign _T_2852 = _T_2851 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42281.4]
assign _T_2863 = _T_1456 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42298.4]
assign _T_2864 = _T_1588 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42299.4]
assign _T_2866 = _T_2864 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42301.4]
assign _T_2868 = _T_2858 + _T_2863; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42303.4]
assign _T_2869 = _T_2868 - _T_2866; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42304.4]
assign _T_2870 = $unsigned(_T_2869); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42305.4]
assign _T_2871 = _T_2870[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42306.4]
assign _T_2872 = _T_2866 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42308.4]
assign _T_2874 = _T_2872 | _T_2858; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42310.4]
assign _T_2876 = _T_2874 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42312.4]
assign _T_2877 = _T_2876 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42313.4]
assign _T_2878 = _T_2863 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42318.4]
assign _T_2879 = _T_2858 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42319.4]
assign _T_2880 = _T_2878 | _T_2879; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42320.4]
assign _T_2882 = _T_2880 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42322.4]
assign _T_2883 = _T_2882 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42323.4]
assign _T_2894 = _T_1457 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42340.4]
assign _T_2895 = _T_1589 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42341.4]
assign _T_2897 = _T_2895 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42343.4]
assign _T_2899 = _T_2889 + _T_2894; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42345.4]
assign _T_2900 = _T_2899 - _T_2897; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42346.4]
assign _T_2901 = $unsigned(_T_2900); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42347.4]
assign _T_2902 = _T_2901[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42348.4]
assign _T_2903 = _T_2897 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42350.4]
assign _T_2905 = _T_2903 | _T_2889; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42352.4]
assign _T_2907 = _T_2905 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42354.4]
assign _T_2908 = _T_2907 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42355.4]
assign _T_2909 = _T_2894 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42360.4]
assign _T_2910 = _T_2889 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42361.4]
assign _T_2911 = _T_2909 | _T_2910; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42362.4]
assign _T_2913 = _T_2911 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42364.4]
assign _T_2914 = _T_2913 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42365.4]
assign _T_2925 = _T_1458 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42382.4]
assign _T_2926 = _T_1590 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42383.4]
assign _T_2928 = _T_2926 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42385.4]
assign _T_2930 = _T_2920 + _T_2925; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42387.4]
assign _T_2931 = _T_2930 - _T_2928; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42388.4]
assign _T_2932 = $unsigned(_T_2931); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42389.4]
assign _T_2933 = _T_2932[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42390.4]
assign _T_2934 = _T_2928 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42392.4]
assign _T_2936 = _T_2934 | _T_2920; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42394.4]
assign _T_2938 = _T_2936 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42396.4]
assign _T_2939 = _T_2938 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42397.4]
assign _T_2940 = _T_2925 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42402.4]
assign _T_2941 = _T_2920 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42403.4]
assign _T_2942 = _T_2940 | _T_2941; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42404.4]
assign _T_2944 = _T_2942 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42406.4]
assign _T_2945 = _T_2944 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42407.4]
assign _T_2956 = _T_1459 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42424.4]
assign _T_2957 = _T_1591 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42425.4]
assign _T_2959 = _T_2957 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42427.4]
assign _T_2961 = _T_2951 + _T_2956; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42429.4]
assign _T_2962 = _T_2961 - _T_2959; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42430.4]
assign _T_2963 = $unsigned(_T_2962); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42431.4]
assign _T_2964 = _T_2963[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42432.4]
assign _T_2965 = _T_2959 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42434.4]
assign _T_2967 = _T_2965 | _T_2951; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42436.4]
assign _T_2969 = _T_2967 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42438.4]
assign _T_2970 = _T_2969 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42439.4]
assign _T_2971 = _T_2956 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42444.4]
assign _T_2972 = _T_2951 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42445.4]
assign _T_2973 = _T_2971 | _T_2972; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42446.4]
assign _T_2975 = _T_2973 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42448.4]
assign _T_2976 = _T_2975 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42449.4]
assign _T_2987 = _T_1460 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42466.4]
assign _T_2988 = _T_1592 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42467.4]
assign _T_2990 = _T_2988 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42469.4]
assign _T_2992 = _T_2982 + _T_2987; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42471.4]
assign _T_2993 = _T_2992 - _T_2990; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42472.4]
assign _T_2994 = $unsigned(_T_2993); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42473.4]
assign _T_2995 = _T_2994[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42474.4]
assign _T_2996 = _T_2990 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42476.4]
assign _T_2998 = _T_2996 | _T_2982; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42478.4]
assign _T_3000 = _T_2998 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42480.4]
assign _T_3001 = _T_3000 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42481.4]
assign _T_3002 = _T_2987 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42486.4]
assign _T_3003 = _T_2982 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42487.4]
assign _T_3004 = _T_3002 | _T_3003; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42488.4]
assign _T_3006 = _T_3004 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42490.4]
assign _T_3007 = _T_3006 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42491.4]
assign _T_3018 = _T_1461 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42508.4]
assign _T_3019 = _T_1593 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42509.4]
assign _T_3021 = _T_3019 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42511.4]
assign _T_3023 = _T_3013 + _T_3018; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42513.4]
assign _T_3024 = _T_3023 - _T_3021; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42514.4]
assign _T_3025 = $unsigned(_T_3024); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42515.4]
assign _T_3026 = _T_3025[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42516.4]
assign _T_3027 = _T_3021 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42518.4]
assign _T_3029 = _T_3027 | _T_3013; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42520.4]
assign _T_3031 = _T_3029 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42522.4]
assign _T_3032 = _T_3031 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42523.4]
assign _T_3033 = _T_3018 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42528.4]
assign _T_3034 = _T_3013 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42529.4]
assign _T_3035 = _T_3033 | _T_3034; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42530.4]
assign _T_3037 = _T_3035 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42532.4]
assign _T_3038 = _T_3037 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42533.4]
assign _T_3049 = _T_1462 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42550.4]
assign _T_3050 = _T_1594 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42551.4]
assign _T_3052 = _T_3050 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42553.4]
assign _T_3054 = _T_3044 + _T_3049; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42555.4]
assign _T_3055 = _T_3054 - _T_3052; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42556.4]
assign _T_3056 = $unsigned(_T_3055); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42557.4]
assign _T_3057 = _T_3056[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42558.4]
assign _T_3058 = _T_3052 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42560.4]
assign _T_3060 = _T_3058 | _T_3044; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42562.4]
assign _T_3062 = _T_3060 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42564.4]
assign _T_3063 = _T_3062 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42565.4]
assign _T_3064 = _T_3049 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42570.4]
assign _T_3065 = _T_3044 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42571.4]
assign _T_3066 = _T_3064 | _T_3065; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42572.4]
assign _T_3068 = _T_3066 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42574.4]
assign _T_3069 = _T_3068 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42575.4]
assign _T_3080 = _T_1463 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42592.4]
assign _T_3081 = _T_1595 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42593.4]
assign _T_3083 = _T_3081 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42595.4]
assign _T_3085 = _T_3075 + _T_3080; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42597.4]
assign _T_3086 = _T_3085 - _T_3083; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42598.4]
assign _T_3087 = $unsigned(_T_3086); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42599.4]
assign _T_3088 = _T_3087[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42600.4]
assign _T_3089 = _T_3083 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42602.4]
assign _T_3091 = _T_3089 | _T_3075; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42604.4]
assign _T_3093 = _T_3091 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42606.4]
assign _T_3094 = _T_3093 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42607.4]
assign _T_3095 = _T_3080 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42612.4]
assign _T_3096 = _T_3075 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42613.4]
assign _T_3097 = _T_3095 | _T_3096; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42614.4]
assign _T_3099 = _T_3097 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42616.4]
assign _T_3100 = _T_3099 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42617.4]
assign _T_3111 = _T_1464 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42634.4]
assign _T_3112 = _T_1596 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42635.4]
assign _T_3114 = _T_3112 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42637.4]
assign _T_3116 = _T_3106 + _T_3111; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42639.4]
assign _T_3117 = _T_3116 - _T_3114; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42640.4]
assign _T_3118 = $unsigned(_T_3117); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42641.4]
assign _T_3119 = _T_3118[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42642.4]
assign _T_3120 = _T_3114 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42644.4]
assign _T_3122 = _T_3120 | _T_3106; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42646.4]
assign _T_3124 = _T_3122 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42648.4]
assign _T_3125 = _T_3124 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42649.4]
assign _T_3126 = _T_3111 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42654.4]
assign _T_3127 = _T_3106 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42655.4]
assign _T_3128 = _T_3126 | _T_3127; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42656.4]
assign _T_3130 = _T_3128 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42658.4]
assign _T_3131 = _T_3130 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42659.4]
assign _T_3142 = _T_1465 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42676.4]
assign _T_3143 = _T_1597 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42677.4]
assign _T_3145 = _T_3143 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42679.4]
assign _T_3147 = _T_3137 + _T_3142; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42681.4]
assign _T_3148 = _T_3147 - _T_3145; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42682.4]
assign _T_3149 = $unsigned(_T_3148); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42683.4]
assign _T_3150 = _T_3149[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42684.4]
assign _T_3151 = _T_3145 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42686.4]
assign _T_3153 = _T_3151 | _T_3137; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42688.4]
assign _T_3155 = _T_3153 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42690.4]
assign _T_3156 = _T_3155 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42691.4]
assign _T_3157 = _T_3142 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42696.4]
assign _T_3158 = _T_3137 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42697.4]
assign _T_3159 = _T_3157 | _T_3158; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42698.4]
assign _T_3161 = _T_3159 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42700.4]
assign _T_3162 = _T_3161 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42701.4]
assign _T_3173 = _T_1466 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42718.4]
assign _T_3174 = _T_1598 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42719.4]
assign _T_3176 = _T_3174 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42721.4]
assign _T_3178 = _T_3168 + _T_3173; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42723.4]
assign _T_3179 = _T_3178 - _T_3176; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42724.4]
assign _T_3180 = $unsigned(_T_3179); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42725.4]
assign _T_3181 = _T_3180[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42726.4]
assign _T_3182 = _T_3176 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42728.4]
assign _T_3184 = _T_3182 | _T_3168; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42730.4]
assign _T_3186 = _T_3184 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42732.4]
assign _T_3187 = _T_3186 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42733.4]
assign _T_3188 = _T_3173 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42738.4]
assign _T_3189 = _T_3168 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42739.4]
assign _T_3190 = _T_3188 | _T_3189; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42740.4]
assign _T_3192 = _T_3190 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42742.4]
assign _T_3193 = _T_3192 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42743.4]
assign _T_3204 = _T_1467 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42760.4]
assign _T_3205 = _T_1599 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42761.4]
assign _T_3207 = _T_3205 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42763.4]
assign _T_3209 = _T_3199 + _T_3204; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42765.4]
assign _T_3210 = _T_3209 - _T_3207; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42766.4]
assign _T_3211 = $unsigned(_T_3210); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42767.4]
assign _T_3212 = _T_3211[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42768.4]
assign _T_3213 = _T_3207 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42770.4]
assign _T_3215 = _T_3213 | _T_3199; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42772.4]
assign _T_3217 = _T_3215 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42774.4]
assign _T_3218 = _T_3217 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42775.4]
assign _T_3219 = _T_3204 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42780.4]
assign _T_3220 = _T_3199 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42781.4]
assign _T_3221 = _T_3219 | _T_3220; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42782.4]
assign _T_3223 = _T_3221 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42784.4]
assign _T_3224 = _T_3223 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42785.4]
assign _T_3235 = _T_1468 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42802.4]
assign _T_3236 = _T_1600 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42803.4]
assign _T_3238 = _T_3236 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42805.4]
assign _T_3240 = _T_3230 + _T_3235; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42807.4]
assign _T_3241 = _T_3240 - _T_3238; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42808.4]
assign _T_3242 = $unsigned(_T_3241); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42809.4]
assign _T_3243 = _T_3242[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42810.4]
assign _T_3244 = _T_3238 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42812.4]
assign _T_3246 = _T_3244 | _T_3230; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42814.4]
assign _T_3248 = _T_3246 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42816.4]
assign _T_3249 = _T_3248 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42817.4]
assign _T_3250 = _T_3235 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42822.4]
assign _T_3251 = _T_3230 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42823.4]
assign _T_3252 = _T_3250 | _T_3251; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42824.4]
assign _T_3254 = _T_3252 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42826.4]
assign _T_3255 = _T_3254 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42827.4]
assign _T_3266 = _T_1469 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42844.4]
assign _T_3267 = _T_1601 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42845.4]
assign _T_3269 = _T_3267 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42847.4]
assign _T_3271 = _T_3261 + _T_3266; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42849.4]
assign _T_3272 = _T_3271 - _T_3269; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42850.4]
assign _T_3273 = $unsigned(_T_3272); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42851.4]
assign _T_3274 = _T_3273[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42852.4]
assign _T_3275 = _T_3269 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42854.4]
assign _T_3277 = _T_3275 | _T_3261; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42856.4]
assign _T_3279 = _T_3277 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42858.4]
assign _T_3280 = _T_3279 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42859.4]
assign _T_3281 = _T_3266 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42864.4]
assign _T_3282 = _T_3261 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42865.4]
assign _T_3283 = _T_3281 | _T_3282; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42866.4]
assign _T_3285 = _T_3283 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42868.4]
assign _T_3286 = _T_3285 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42869.4]
assign _T_3297 = _T_1470 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42886.4]
assign _T_3298 = _T_1602 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42887.4]
assign _T_3300 = _T_3298 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42889.4]
assign _T_3302 = _T_3292 + _T_3297; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42891.4]
assign _T_3303 = _T_3302 - _T_3300; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42892.4]
assign _T_3304 = $unsigned(_T_3303); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42893.4]
assign _T_3305 = _T_3304[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42894.4]
assign _T_3306 = _T_3300 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42896.4]
assign _T_3308 = _T_3306 | _T_3292; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42898.4]
assign _T_3310 = _T_3308 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42900.4]
assign _T_3311 = _T_3310 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42901.4]
assign _T_3312 = _T_3297 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42906.4]
assign _T_3313 = _T_3292 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42907.4]
assign _T_3314 = _T_3312 | _T_3313; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42908.4]
assign _T_3316 = _T_3314 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42910.4]
assign _T_3317 = _T_3316 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42911.4]
assign _T_3328 = _T_1471 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42928.4]
assign _T_3329 = _T_1603 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42929.4]
assign _T_3331 = _T_3329 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42931.4]
assign _T_3333 = _T_3323 + _T_3328; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42933.4]
assign _T_3334 = _T_3333 - _T_3331; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42934.4]
assign _T_3335 = $unsigned(_T_3334); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42935.4]
assign _T_3336 = _T_3335[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42936.4]
assign _T_3337 = _T_3331 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42938.4]
assign _T_3339 = _T_3337 | _T_3323; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42940.4]
assign _T_3341 = _T_3339 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42942.4]
assign _T_3342 = _T_3341 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42943.4]
assign _T_3343 = _T_3328 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42948.4]
assign _T_3344 = _T_3323 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42949.4]
assign _T_3345 = _T_3343 | _T_3344; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42950.4]
assign _T_3347 = _T_3345 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42952.4]
assign _T_3348 = _T_3347 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42953.4]
assign _T_3359 = _T_1472 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@42970.4]
assign _T_3360 = _T_1604 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@42971.4]
assign _T_3362 = _T_3360 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@42973.4]
assign _T_3364 = _T_3354 + _T_3359; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@42975.4]
assign _T_3365 = _T_3364 - _T_3362; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42976.4]
assign _T_3366 = $unsigned(_T_3365); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42977.4]
assign _T_3367 = _T_3366[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@42978.4]
assign _T_3368 = _T_3362 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@42980.4]
assign _T_3370 = _T_3368 | _T_3354; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@42982.4]
assign _T_3372 = _T_3370 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42984.4]
assign _T_3373 = _T_3372 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42985.4]
assign _T_3374 = _T_3359 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@42990.4]
assign _T_3375 = _T_3354 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@42991.4]
assign _T_3376 = _T_3374 | _T_3375; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@42992.4]
assign _T_3378 = _T_3376 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42994.4]
assign _T_3379 = _T_3378 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42995.4]
assign _T_3390 = _T_1473 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43012.4]
assign _T_3391 = _T_1605 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43013.4]
assign _T_3393 = _T_3391 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43015.4]
assign _T_3395 = _T_3385 + _T_3390; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43017.4]
assign _T_3396 = _T_3395 - _T_3393; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43018.4]
assign _T_3397 = $unsigned(_T_3396); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43019.4]
assign _T_3398 = _T_3397[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43020.4]
assign _T_3399 = _T_3393 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43022.4]
assign _T_3401 = _T_3399 | _T_3385; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43024.4]
assign _T_3403 = _T_3401 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43026.4]
assign _T_3404 = _T_3403 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43027.4]
assign _T_3405 = _T_3390 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43032.4]
assign _T_3406 = _T_3385 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43033.4]
assign _T_3407 = _T_3405 | _T_3406; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43034.4]
assign _T_3409 = _T_3407 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43036.4]
assign _T_3410 = _T_3409 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43037.4]
assign _T_3421 = _T_1474 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43054.4]
assign _T_3422 = _T_1606 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43055.4]
assign _T_3424 = _T_3422 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43057.4]
assign _T_3426 = _T_3416 + _T_3421; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43059.4]
assign _T_3427 = _T_3426 - _T_3424; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43060.4]
assign _T_3428 = $unsigned(_T_3427); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43061.4]
assign _T_3429 = _T_3428[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43062.4]
assign _T_3430 = _T_3424 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43064.4]
assign _T_3432 = _T_3430 | _T_3416; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43066.4]
assign _T_3434 = _T_3432 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43068.4]
assign _T_3435 = _T_3434 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43069.4]
assign _T_3436 = _T_3421 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43074.4]
assign _T_3437 = _T_3416 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43075.4]
assign _T_3438 = _T_3436 | _T_3437; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43076.4]
assign _T_3440 = _T_3438 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43078.4]
assign _T_3441 = _T_3440 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43079.4]
assign _T_3452 = _T_1475 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43096.4]
assign _T_3453 = _T_1607 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43097.4]
assign _T_3455 = _T_3453 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43099.4]
assign _T_3457 = _T_3447 + _T_3452; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43101.4]
assign _T_3458 = _T_3457 - _T_3455; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43102.4]
assign _T_3459 = $unsigned(_T_3458); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43103.4]
assign _T_3460 = _T_3459[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43104.4]
assign _T_3461 = _T_3455 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43106.4]
assign _T_3463 = _T_3461 | _T_3447; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43108.4]
assign _T_3465 = _T_3463 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43110.4]
assign _T_3466 = _T_3465 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43111.4]
assign _T_3467 = _T_3452 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43116.4]
assign _T_3468 = _T_3447 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43117.4]
assign _T_3469 = _T_3467 | _T_3468; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43118.4]
assign _T_3471 = _T_3469 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43120.4]
assign _T_3472 = _T_3471 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43121.4]
assign _T_3483 = _T_1476 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43138.4]
assign _T_3484 = _T_1608 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43139.4]
assign _T_3486 = _T_3484 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43141.4]
assign _T_3488 = _T_3478 + _T_3483; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43143.4]
assign _T_3489 = _T_3488 - _T_3486; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43144.4]
assign _T_3490 = $unsigned(_T_3489); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43145.4]
assign _T_3491 = _T_3490[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43146.4]
assign _T_3492 = _T_3486 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43148.4]
assign _T_3494 = _T_3492 | _T_3478; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43150.4]
assign _T_3496 = _T_3494 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43152.4]
assign _T_3497 = _T_3496 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43153.4]
assign _T_3498 = _T_3483 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43158.4]
assign _T_3499 = _T_3478 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43159.4]
assign _T_3500 = _T_3498 | _T_3499; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43160.4]
assign _T_3502 = _T_3500 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43162.4]
assign _T_3503 = _T_3502 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43163.4]
assign _T_3514 = _T_1477 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43180.4]
assign _T_3515 = _T_1609 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43181.4]
assign _T_3517 = _T_3515 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43183.4]
assign _T_3519 = _T_3509 + _T_3514; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43185.4]
assign _T_3520 = _T_3519 - _T_3517; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43186.4]
assign _T_3521 = $unsigned(_T_3520); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43187.4]
assign _T_3522 = _T_3521[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43188.4]
assign _T_3523 = _T_3517 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43190.4]
assign _T_3525 = _T_3523 | _T_3509; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43192.4]
assign _T_3527 = _T_3525 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43194.4]
assign _T_3528 = _T_3527 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43195.4]
assign _T_3529 = _T_3514 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43200.4]
assign _T_3530 = _T_3509 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43201.4]
assign _T_3531 = _T_3529 | _T_3530; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43202.4]
assign _T_3533 = _T_3531 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43204.4]
assign _T_3534 = _T_3533 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43205.4]
assign _T_3545 = _T_1478 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43222.4]
assign _T_3546 = _T_1610 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43223.4]
assign _T_3548 = _T_3546 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43225.4]
assign _T_3550 = _T_3540 + _T_3545; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43227.4]
assign _T_3551 = _T_3550 - _T_3548; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43228.4]
assign _T_3552 = $unsigned(_T_3551); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43229.4]
assign _T_3553 = _T_3552[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43230.4]
assign _T_3554 = _T_3548 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43232.4]
assign _T_3556 = _T_3554 | _T_3540; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43234.4]
assign _T_3558 = _T_3556 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43236.4]
assign _T_3559 = _T_3558 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43237.4]
assign _T_3560 = _T_3545 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43242.4]
assign _T_3561 = _T_3540 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43243.4]
assign _T_3562 = _T_3560 | _T_3561; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43244.4]
assign _T_3564 = _T_3562 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43246.4]
assign _T_3565 = _T_3564 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43247.4]
assign _T_3576 = _T_1479 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43264.4]
assign _T_3577 = _T_1611 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43265.4]
assign _T_3579 = _T_3577 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43267.4]
assign _T_3581 = _T_3571 + _T_3576; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43269.4]
assign _T_3582 = _T_3581 - _T_3579; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43270.4]
assign _T_3583 = $unsigned(_T_3582); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43271.4]
assign _T_3584 = _T_3583[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43272.4]
assign _T_3585 = _T_3579 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43274.4]
assign _T_3587 = _T_3585 | _T_3571; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43276.4]
assign _T_3589 = _T_3587 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43278.4]
assign _T_3590 = _T_3589 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43279.4]
assign _T_3591 = _T_3576 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43284.4]
assign _T_3592 = _T_3571 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43285.4]
assign _T_3593 = _T_3591 | _T_3592; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43286.4]
assign _T_3595 = _T_3593 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43288.4]
assign _T_3596 = _T_3595 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43289.4]
assign _T_3607 = _T_1480 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43306.4]
assign _T_3608 = _T_1612 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43307.4]
assign _T_3610 = _T_3608 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43309.4]
assign _T_3612 = _T_3602 + _T_3607; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43311.4]
assign _T_3613 = _T_3612 - _T_3610; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43312.4]
assign _T_3614 = $unsigned(_T_3613); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43313.4]
assign _T_3615 = _T_3614[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43314.4]
assign _T_3616 = _T_3610 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43316.4]
assign _T_3618 = _T_3616 | _T_3602; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43318.4]
assign _T_3620 = _T_3618 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43320.4]
assign _T_3621 = _T_3620 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43321.4]
assign _T_3622 = _T_3607 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43326.4]
assign _T_3623 = _T_3602 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43327.4]
assign _T_3624 = _T_3622 | _T_3623; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43328.4]
assign _T_3626 = _T_3624 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43330.4]
assign _T_3627 = _T_3626 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43331.4]
assign _T_3638 = _T_1481 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43348.4]
assign _T_3639 = _T_1613 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43349.4]
assign _T_3641 = _T_3639 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43351.4]
assign _T_3643 = _T_3633 + _T_3638; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43353.4]
assign _T_3644 = _T_3643 - _T_3641; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43354.4]
assign _T_3645 = $unsigned(_T_3644); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43355.4]
assign _T_3646 = _T_3645[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43356.4]
assign _T_3647 = _T_3641 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43358.4]
assign _T_3649 = _T_3647 | _T_3633; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43360.4]
assign _T_3651 = _T_3649 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43362.4]
assign _T_3652 = _T_3651 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43363.4]
assign _T_3653 = _T_3638 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43368.4]
assign _T_3654 = _T_3633 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43369.4]
assign _T_3655 = _T_3653 | _T_3654; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43370.4]
assign _T_3657 = _T_3655 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43372.4]
assign _T_3658 = _T_3657 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43373.4]
assign _T_3669 = _T_1482 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43390.4]
assign _T_3670 = _T_1614 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43391.4]
assign _T_3672 = _T_3670 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43393.4]
assign _T_3674 = _T_3664 + _T_3669; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43395.4]
assign _T_3675 = _T_3674 - _T_3672; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43396.4]
assign _T_3676 = $unsigned(_T_3675); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43397.4]
assign _T_3677 = _T_3676[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43398.4]
assign _T_3678 = _T_3672 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43400.4]
assign _T_3680 = _T_3678 | _T_3664; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43402.4]
assign _T_3682 = _T_3680 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43404.4]
assign _T_3683 = _T_3682 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43405.4]
assign _T_3684 = _T_3669 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43410.4]
assign _T_3685 = _T_3664 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43411.4]
assign _T_3686 = _T_3684 | _T_3685; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43412.4]
assign _T_3688 = _T_3686 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43414.4]
assign _T_3689 = _T_3688 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43415.4]
assign _T_3700 = _T_1483 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43432.4]
assign _T_3701 = _T_1615 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43433.4]
assign _T_3703 = _T_3701 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43435.4]
assign _T_3705 = _T_3695 + _T_3700; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43437.4]
assign _T_3706 = _T_3705 - _T_3703; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43438.4]
assign _T_3707 = $unsigned(_T_3706); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43439.4]
assign _T_3708 = _T_3707[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43440.4]
assign _T_3709 = _T_3703 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43442.4]
assign _T_3711 = _T_3709 | _T_3695; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43444.4]
assign _T_3713 = _T_3711 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43446.4]
assign _T_3714 = _T_3713 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43447.4]
assign _T_3715 = _T_3700 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43452.4]
assign _T_3716 = _T_3695 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43453.4]
assign _T_3717 = _T_3715 | _T_3716; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43454.4]
assign _T_3719 = _T_3717 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43456.4]
assign _T_3720 = _T_3719 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43457.4]
assign _T_3731 = _T_1484 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43474.4]
assign _T_3732 = _T_1616 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43475.4]
assign _T_3734 = _T_3732 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43477.4]
assign _T_3736 = _T_3726 + _T_3731; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43479.4]
assign _T_3737 = _T_3736 - _T_3734; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43480.4]
assign _T_3738 = $unsigned(_T_3737); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43481.4]
assign _T_3739 = _T_3738[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43482.4]
assign _T_3740 = _T_3734 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43484.4]
assign _T_3742 = _T_3740 | _T_3726; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43486.4]
assign _T_3744 = _T_3742 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43488.4]
assign _T_3745 = _T_3744 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43489.4]
assign _T_3746 = _T_3731 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43494.4]
assign _T_3747 = _T_3726 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43495.4]
assign _T_3748 = _T_3746 | _T_3747; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43496.4]
assign _T_3750 = _T_3748 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43498.4]
assign _T_3751 = _T_3750 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43499.4]
assign _T_3762 = _T_1485 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43516.4]
assign _T_3763 = _T_1617 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43517.4]
assign _T_3765 = _T_3763 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43519.4]
assign _T_3767 = _T_3757 + _T_3762; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43521.4]
assign _T_3768 = _T_3767 - _T_3765; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43522.4]
assign _T_3769 = $unsigned(_T_3768); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43523.4]
assign _T_3770 = _T_3769[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43524.4]
assign _T_3771 = _T_3765 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43526.4]
assign _T_3773 = _T_3771 | _T_3757; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43528.4]
assign _T_3775 = _T_3773 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43530.4]
assign _T_3776 = _T_3775 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43531.4]
assign _T_3777 = _T_3762 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43536.4]
assign _T_3778 = _T_3757 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43537.4]
assign _T_3779 = _T_3777 | _T_3778; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43538.4]
assign _T_3781 = _T_3779 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43540.4]
assign _T_3782 = _T_3781 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43541.4]
assign _T_3793 = _T_1486 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43558.4]
assign _T_3794 = _T_1618 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43559.4]
assign _T_3796 = _T_3794 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43561.4]
assign _T_3798 = _T_3788 + _T_3793; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43563.4]
assign _T_3799 = _T_3798 - _T_3796; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43564.4]
assign _T_3800 = $unsigned(_T_3799); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43565.4]
assign _T_3801 = _T_3800[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43566.4]
assign _T_3802 = _T_3796 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43568.4]
assign _T_3804 = _T_3802 | _T_3788; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43570.4]
assign _T_3806 = _T_3804 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43572.4]
assign _T_3807 = _T_3806 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43573.4]
assign _T_3808 = _T_3793 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43578.4]
assign _T_3809 = _T_3788 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43579.4]
assign _T_3810 = _T_3808 | _T_3809; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43580.4]
assign _T_3812 = _T_3810 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43582.4]
assign _T_3813 = _T_3812 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43583.4]
assign _T_3824 = _T_1487 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43600.4]
assign _T_3825 = _T_1619 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43601.4]
assign _T_3827 = _T_3825 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43603.4]
assign _T_3829 = _T_3819 + _T_3824; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43605.4]
assign _T_3830 = _T_3829 - _T_3827; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43606.4]
assign _T_3831 = $unsigned(_T_3830); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43607.4]
assign _T_3832 = _T_3831[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43608.4]
assign _T_3833 = _T_3827 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43610.4]
assign _T_3835 = _T_3833 | _T_3819; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43612.4]
assign _T_3837 = _T_3835 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43614.4]
assign _T_3838 = _T_3837 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43615.4]
assign _T_3839 = _T_3824 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43620.4]
assign _T_3840 = _T_3819 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43621.4]
assign _T_3841 = _T_3839 | _T_3840; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43622.4]
assign _T_3843 = _T_3841 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43624.4]
assign _T_3844 = _T_3843 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43625.4]
assign _T_3855 = _T_1488 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43642.4]
assign _T_3856 = _T_1620 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43643.4]
assign _T_3858 = _T_3856 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43645.4]
assign _T_3860 = _T_3850 + _T_3855; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43647.4]
assign _T_3861 = _T_3860 - _T_3858; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43648.4]
assign _T_3862 = $unsigned(_T_3861); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43649.4]
assign _T_3863 = _T_3862[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43650.4]
assign _T_3864 = _T_3858 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43652.4]
assign _T_3866 = _T_3864 | _T_3850; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43654.4]
assign _T_3868 = _T_3866 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43656.4]
assign _T_3869 = _T_3868 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43657.4]
assign _T_3870 = _T_3855 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43662.4]
assign _T_3871 = _T_3850 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43663.4]
assign _T_3872 = _T_3870 | _T_3871; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43664.4]
assign _T_3874 = _T_3872 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43666.4]
assign _T_3875 = _T_3874 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43667.4]
assign _T_3886 = _T_1489 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43684.4]
assign _T_3887 = _T_1621 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43685.4]
assign _T_3889 = _T_3887 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43687.4]
assign _T_3891 = _T_3881 + _T_3886; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43689.4]
assign _T_3892 = _T_3891 - _T_3889; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43690.4]
assign _T_3893 = $unsigned(_T_3892); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43691.4]
assign _T_3894 = _T_3893[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43692.4]
assign _T_3895 = _T_3889 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43694.4]
assign _T_3897 = _T_3895 | _T_3881; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43696.4]
assign _T_3899 = _T_3897 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43698.4]
assign _T_3900 = _T_3899 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43699.4]
assign _T_3901 = _T_3886 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43704.4]
assign _T_3902 = _T_3881 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43705.4]
assign _T_3903 = _T_3901 | _T_3902; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43706.4]
assign _T_3905 = _T_3903 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43708.4]
assign _T_3906 = _T_3905 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43709.4]
assign _T_3917 = _T_1490 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43726.4]
assign _T_3918 = _T_1622 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43727.4]
assign _T_3920 = _T_3918 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43729.4]
assign _T_3922 = _T_3912 + _T_3917; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43731.4]
assign _T_3923 = _T_3922 - _T_3920; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43732.4]
assign _T_3924 = $unsigned(_T_3923); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43733.4]
assign _T_3925 = _T_3924[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43734.4]
assign _T_3926 = _T_3920 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43736.4]
assign _T_3928 = _T_3926 | _T_3912; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43738.4]
assign _T_3930 = _T_3928 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43740.4]
assign _T_3931 = _T_3930 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43741.4]
assign _T_3932 = _T_3917 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43746.4]
assign _T_3933 = _T_3912 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43747.4]
assign _T_3934 = _T_3932 | _T_3933; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43748.4]
assign _T_3936 = _T_3934 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43750.4]
assign _T_3937 = _T_3936 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43751.4]
assign _T_3948 = _T_1491 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43768.4]
assign _T_3949 = _T_1623 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43769.4]
assign _T_3951 = _T_3949 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43771.4]
assign _T_3953 = _T_3943 + _T_3948; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43773.4]
assign _T_3954 = _T_3953 - _T_3951; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43774.4]
assign _T_3955 = $unsigned(_T_3954); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43775.4]
assign _T_3956 = _T_3955[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43776.4]
assign _T_3957 = _T_3951 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43778.4]
assign _T_3959 = _T_3957 | _T_3943; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43780.4]
assign _T_3961 = _T_3959 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43782.4]
assign _T_3962 = _T_3961 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43783.4]
assign _T_3963 = _T_3948 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43788.4]
assign _T_3964 = _T_3943 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43789.4]
assign _T_3965 = _T_3963 | _T_3964; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43790.4]
assign _T_3967 = _T_3965 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43792.4]
assign _T_3968 = _T_3967 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43793.4]
assign _T_3979 = _T_1492 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43810.4]
assign _T_3980 = _T_1624 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43811.4]
assign _T_3982 = _T_3980 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43813.4]
assign _T_3984 = _T_3974 + _T_3979; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43815.4]
assign _T_3985 = _T_3984 - _T_3982; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43816.4]
assign _T_3986 = $unsigned(_T_3985); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43817.4]
assign _T_3987 = _T_3986[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43818.4]
assign _T_3988 = _T_3982 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43820.4]
assign _T_3990 = _T_3988 | _T_3974; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43822.4]
assign _T_3992 = _T_3990 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43824.4]
assign _T_3993 = _T_3992 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43825.4]
assign _T_3994 = _T_3979 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43830.4]
assign _T_3995 = _T_3974 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43831.4]
assign _T_3996 = _T_3994 | _T_3995; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43832.4]
assign _T_3998 = _T_3996 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43834.4]
assign _T_3999 = _T_3998 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43835.4]
assign _T_4010 = _T_1493 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43852.4]
assign _T_4011 = _T_1625 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43853.4]
assign _T_4013 = _T_4011 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43855.4]
assign _T_4015 = _T_4005 + _T_4010; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43857.4]
assign _T_4016 = _T_4015 - _T_4013; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43858.4]
assign _T_4017 = $unsigned(_T_4016); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43859.4]
assign _T_4018 = _T_4017[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43860.4]
assign _T_4019 = _T_4013 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43862.4]
assign _T_4021 = _T_4019 | _T_4005; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43864.4]
assign _T_4023 = _T_4021 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43866.4]
assign _T_4024 = _T_4023 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43867.4]
assign _T_4025 = _T_4010 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43872.4]
assign _T_4026 = _T_4005 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43873.4]
assign _T_4027 = _T_4025 | _T_4026; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43874.4]
assign _T_4029 = _T_4027 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43876.4]
assign _T_4030 = _T_4029 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43877.4]
assign _T_4041 = _T_1494 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43894.4]
assign _T_4042 = _T_1626 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43895.4]
assign _T_4044 = _T_4042 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43897.4]
assign _T_4046 = _T_4036 + _T_4041; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43899.4]
assign _T_4047 = _T_4046 - _T_4044; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43900.4]
assign _T_4048 = $unsigned(_T_4047); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43901.4]
assign _T_4049 = _T_4048[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43902.4]
assign _T_4050 = _T_4044 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43904.4]
assign _T_4052 = _T_4050 | _T_4036; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43906.4]
assign _T_4054 = _T_4052 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43908.4]
assign _T_4055 = _T_4054 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43909.4]
assign _T_4056 = _T_4041 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43914.4]
assign _T_4057 = _T_4036 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43915.4]
assign _T_4058 = _T_4056 | _T_4057; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43916.4]
assign _T_4060 = _T_4058 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43918.4]
assign _T_4061 = _T_4060 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43919.4]
assign _T_4072 = _T_1495 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43936.4]
assign _T_4073 = _T_1627 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43937.4]
assign _T_4075 = _T_4073 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43939.4]
assign _T_4077 = _T_4067 + _T_4072; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43941.4]
assign _T_4078 = _T_4077 - _T_4075; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43942.4]
assign _T_4079 = $unsigned(_T_4078); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43943.4]
assign _T_4080 = _T_4079[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43944.4]
assign _T_4081 = _T_4075 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43946.4]
assign _T_4083 = _T_4081 | _T_4067; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43948.4]
assign _T_4085 = _T_4083 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43950.4]
assign _T_4086 = _T_4085 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43951.4]
assign _T_4087 = _T_4072 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43956.4]
assign _T_4088 = _T_4067 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43957.4]
assign _T_4089 = _T_4087 | _T_4088; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@43958.4]
assign _T_4091 = _T_4089 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43960.4]
assign _T_4092 = _T_4091 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43961.4]
assign _T_4103 = _T_1496 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@43978.4]
assign _T_4104 = _T_1628 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@43979.4]
assign _T_4106 = _T_4104 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@43981.4]
assign _T_4108 = _T_4098 + _T_4103; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@43983.4]
assign _T_4109 = _T_4108 - _T_4106; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43984.4]
assign _T_4110 = $unsigned(_T_4109); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43985.4]
assign _T_4111 = _T_4110[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@43986.4]
assign _T_4112 = _T_4106 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@43988.4]
assign _T_4114 = _T_4112 | _T_4098; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@43990.4]
assign _T_4116 = _T_4114 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43992.4]
assign _T_4117 = _T_4116 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43993.4]
assign _T_4118 = _T_4103 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@43998.4]
assign _T_4119 = _T_4098 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@43999.4]
assign _T_4120 = _T_4118 | _T_4119; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44000.4]
assign _T_4122 = _T_4120 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44002.4]
assign _T_4123 = _T_4122 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44003.4]
assign _T_4134 = _T_1497 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44020.4]
assign _T_4135 = _T_1629 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44021.4]
assign _T_4137 = _T_4135 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44023.4]
assign _T_4139 = _T_4129 + _T_4134; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44025.4]
assign _T_4140 = _T_4139 - _T_4137; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44026.4]
assign _T_4141 = $unsigned(_T_4140); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44027.4]
assign _T_4142 = _T_4141[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44028.4]
assign _T_4143 = _T_4137 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44030.4]
assign _T_4145 = _T_4143 | _T_4129; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44032.4]
assign _T_4147 = _T_4145 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44034.4]
assign _T_4148 = _T_4147 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44035.4]
assign _T_4149 = _T_4134 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44040.4]
assign _T_4150 = _T_4129 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44041.4]
assign _T_4151 = _T_4149 | _T_4150; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44042.4]
assign _T_4153 = _T_4151 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44044.4]
assign _T_4154 = _T_4153 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44045.4]
assign _T_4165 = _T_1498 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44062.4]
assign _T_4166 = _T_1630 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44063.4]
assign _T_4168 = _T_4166 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44065.4]
assign _T_4170 = _T_4160 + _T_4165; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44067.4]
assign _T_4171 = _T_4170 - _T_4168; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44068.4]
assign _T_4172 = $unsigned(_T_4171); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44069.4]
assign _T_4173 = _T_4172[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44070.4]
assign _T_4174 = _T_4168 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44072.4]
assign _T_4176 = _T_4174 | _T_4160; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44074.4]
assign _T_4178 = _T_4176 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44076.4]
assign _T_4179 = _T_4178 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44077.4]
assign _T_4180 = _T_4165 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44082.4]
assign _T_4181 = _T_4160 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44083.4]
assign _T_4182 = _T_4180 | _T_4181; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44084.4]
assign _T_4184 = _T_4182 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44086.4]
assign _T_4185 = _T_4184 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44087.4]
assign _T_4196 = _T_1499 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44104.4]
assign _T_4197 = _T_1631 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44105.4]
assign _T_4199 = _T_4197 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44107.4]
assign _T_4201 = _T_4191 + _T_4196; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44109.4]
assign _T_4202 = _T_4201 - _T_4199; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44110.4]
assign _T_4203 = $unsigned(_T_4202); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44111.4]
assign _T_4204 = _T_4203[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44112.4]
assign _T_4205 = _T_4199 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44114.4]
assign _T_4207 = _T_4205 | _T_4191; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44116.4]
assign _T_4209 = _T_4207 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44118.4]
assign _T_4210 = _T_4209 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44119.4]
assign _T_4211 = _T_4196 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44124.4]
assign _T_4212 = _T_4191 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44125.4]
assign _T_4213 = _T_4211 | _T_4212; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44126.4]
assign _T_4215 = _T_4213 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44128.4]
assign _T_4216 = _T_4215 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44129.4]
assign _T_4227 = _T_1500 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44146.4]
assign _T_4228 = _T_1632 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44147.4]
assign _T_4230 = _T_4228 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44149.4]
assign _T_4232 = _T_4222 + _T_4227; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44151.4]
assign _T_4233 = _T_4232 - _T_4230; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44152.4]
assign _T_4234 = $unsigned(_T_4233); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44153.4]
assign _T_4235 = _T_4234[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44154.4]
assign _T_4236 = _T_4230 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44156.4]
assign _T_4238 = _T_4236 | _T_4222; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44158.4]
assign _T_4240 = _T_4238 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44160.4]
assign _T_4241 = _T_4240 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44161.4]
assign _T_4242 = _T_4227 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44166.4]
assign _T_4243 = _T_4222 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44167.4]
assign _T_4244 = _T_4242 | _T_4243; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44168.4]
assign _T_4246 = _T_4244 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44170.4]
assign _T_4247 = _T_4246 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44171.4]
assign _T_4258 = _T_1501 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44188.4]
assign _T_4259 = _T_1633 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44189.4]
assign _T_4261 = _T_4259 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44191.4]
assign _T_4263 = _T_4253 + _T_4258; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44193.4]
assign _T_4264 = _T_4263 - _T_4261; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44194.4]
assign _T_4265 = $unsigned(_T_4264); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44195.4]
assign _T_4266 = _T_4265[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44196.4]
assign _T_4267 = _T_4261 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44198.4]
assign _T_4269 = _T_4267 | _T_4253; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44200.4]
assign _T_4271 = _T_4269 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44202.4]
assign _T_4272 = _T_4271 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44203.4]
assign _T_4273 = _T_4258 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44208.4]
assign _T_4274 = _T_4253 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44209.4]
assign _T_4275 = _T_4273 | _T_4274; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44210.4]
assign _T_4277 = _T_4275 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44212.4]
assign _T_4278 = _T_4277 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44213.4]
assign _T_4289 = _T_1502 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44230.4]
assign _T_4290 = _T_1634 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44231.4]
assign _T_4292 = _T_4290 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44233.4]
assign _T_4294 = _T_4284 + _T_4289; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44235.4]
assign _T_4295 = _T_4294 - _T_4292; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44236.4]
assign _T_4296 = $unsigned(_T_4295); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44237.4]
assign _T_4297 = _T_4296[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44238.4]
assign _T_4298 = _T_4292 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44240.4]
assign _T_4300 = _T_4298 | _T_4284; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44242.4]
assign _T_4302 = _T_4300 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44244.4]
assign _T_4303 = _T_4302 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44245.4]
assign _T_4304 = _T_4289 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44250.4]
assign _T_4305 = _T_4284 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44251.4]
assign _T_4306 = _T_4304 | _T_4305; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44252.4]
assign _T_4308 = _T_4306 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44254.4]
assign _T_4309 = _T_4308 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44255.4]
assign _T_4320 = _T_1503 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44272.4]
assign _T_4321 = _T_1635 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44273.4]
assign _T_4323 = _T_4321 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44275.4]
assign _T_4325 = _T_4315 + _T_4320; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44277.4]
assign _T_4326 = _T_4325 - _T_4323; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44278.4]
assign _T_4327 = $unsigned(_T_4326); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44279.4]
assign _T_4328 = _T_4327[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44280.4]
assign _T_4329 = _T_4323 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44282.4]
assign _T_4331 = _T_4329 | _T_4315; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44284.4]
assign _T_4333 = _T_4331 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44286.4]
assign _T_4334 = _T_4333 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44287.4]
assign _T_4335 = _T_4320 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44292.4]
assign _T_4336 = _T_4315 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44293.4]
assign _T_4337 = _T_4335 | _T_4336; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44294.4]
assign _T_4339 = _T_4337 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44296.4]
assign _T_4340 = _T_4339 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44297.4]
assign _T_4351 = _T_1504 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44314.4]
assign _T_4352 = _T_1636 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44315.4]
assign _T_4354 = _T_4352 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44317.4]
assign _T_4356 = _T_4346 + _T_4351; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44319.4]
assign _T_4357 = _T_4356 - _T_4354; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44320.4]
assign _T_4358 = $unsigned(_T_4357); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44321.4]
assign _T_4359 = _T_4358[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44322.4]
assign _T_4360 = _T_4354 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44324.4]
assign _T_4362 = _T_4360 | _T_4346; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44326.4]
assign _T_4364 = _T_4362 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44328.4]
assign _T_4365 = _T_4364 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44329.4]
assign _T_4366 = _T_4351 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44334.4]
assign _T_4367 = _T_4346 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44335.4]
assign _T_4368 = _T_4366 | _T_4367; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44336.4]
assign _T_4370 = _T_4368 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44338.4]
assign _T_4371 = _T_4370 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44339.4]
assign _T_4382 = _T_1505 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44356.4]
assign _T_4383 = _T_1637 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44357.4]
assign _T_4385 = _T_4383 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44359.4]
assign _T_4387 = _T_4377 + _T_4382; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44361.4]
assign _T_4388 = _T_4387 - _T_4385; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44362.4]
assign _T_4389 = $unsigned(_T_4388); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44363.4]
assign _T_4390 = _T_4389[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44364.4]
assign _T_4391 = _T_4385 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44366.4]
assign _T_4393 = _T_4391 | _T_4377; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44368.4]
assign _T_4395 = _T_4393 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44370.4]
assign _T_4396 = _T_4395 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44371.4]
assign _T_4397 = _T_4382 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44376.4]
assign _T_4398 = _T_4377 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44377.4]
assign _T_4399 = _T_4397 | _T_4398; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44378.4]
assign _T_4401 = _T_4399 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44380.4]
assign _T_4402 = _T_4401 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44381.4]
assign _T_4413 = _T_1506 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44398.4]
assign _T_4414 = _T_1638 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44399.4]
assign _T_4416 = _T_4414 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44401.4]
assign _T_4418 = _T_4408 + _T_4413; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44403.4]
assign _T_4419 = _T_4418 - _T_4416; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44404.4]
assign _T_4420 = $unsigned(_T_4419); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44405.4]
assign _T_4421 = _T_4420[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44406.4]
assign _T_4422 = _T_4416 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44408.4]
assign _T_4424 = _T_4422 | _T_4408; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44410.4]
assign _T_4426 = _T_4424 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44412.4]
assign _T_4427 = _T_4426 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44413.4]
assign _T_4428 = _T_4413 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44418.4]
assign _T_4429 = _T_4408 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44419.4]
assign _T_4430 = _T_4428 | _T_4429; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44420.4]
assign _T_4432 = _T_4430 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44422.4]
assign _T_4433 = _T_4432 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44423.4]
assign _T_4444 = _T_1507 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44440.4]
assign _T_4445 = _T_1639 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44441.4]
assign _T_4447 = _T_4445 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44443.4]
assign _T_4449 = _T_4439 + _T_4444; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44445.4]
assign _T_4450 = _T_4449 - _T_4447; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44446.4]
assign _T_4451 = $unsigned(_T_4450); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44447.4]
assign _T_4452 = _T_4451[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44448.4]
assign _T_4453 = _T_4447 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44450.4]
assign _T_4455 = _T_4453 | _T_4439; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44452.4]
assign _T_4457 = _T_4455 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44454.4]
assign _T_4458 = _T_4457 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44455.4]
assign _T_4459 = _T_4444 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44460.4]
assign _T_4460 = _T_4439 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44461.4]
assign _T_4461 = _T_4459 | _T_4460; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44462.4]
assign _T_4463 = _T_4461 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44464.4]
assign _T_4464 = _T_4463 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44465.4]
assign _T_4475 = _T_1508 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44482.4]
assign _T_4476 = _T_1640 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44483.4]
assign _T_4478 = _T_4476 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44485.4]
assign _T_4480 = _T_4470 + _T_4475; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44487.4]
assign _T_4481 = _T_4480 - _T_4478; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44488.4]
assign _T_4482 = $unsigned(_T_4481); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44489.4]
assign _T_4483 = _T_4482[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44490.4]
assign _T_4484 = _T_4478 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44492.4]
assign _T_4486 = _T_4484 | _T_4470; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44494.4]
assign _T_4488 = _T_4486 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44496.4]
assign _T_4489 = _T_4488 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44497.4]
assign _T_4490 = _T_4475 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44502.4]
assign _T_4491 = _T_4470 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44503.4]
assign _T_4492 = _T_4490 | _T_4491; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44504.4]
assign _T_4494 = _T_4492 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44506.4]
assign _T_4495 = _T_4494 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44507.4]
assign _T_4506 = _T_1509 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44524.4]
assign _T_4507 = _T_1641 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44525.4]
assign _T_4509 = _T_4507 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44527.4]
assign _T_4511 = _T_4501 + _T_4506; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44529.4]
assign _T_4512 = _T_4511 - _T_4509; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44530.4]
assign _T_4513 = $unsigned(_T_4512); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44531.4]
assign _T_4514 = _T_4513[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44532.4]
assign _T_4515 = _T_4509 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44534.4]
assign _T_4517 = _T_4515 | _T_4501; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44536.4]
assign _T_4519 = _T_4517 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44538.4]
assign _T_4520 = _T_4519 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44539.4]
assign _T_4521 = _T_4506 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44544.4]
assign _T_4522 = _T_4501 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44545.4]
assign _T_4523 = _T_4521 | _T_4522; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44546.4]
assign _T_4525 = _T_4523 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44548.4]
assign _T_4526 = _T_4525 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44549.4]
assign _T_4537 = _T_1510 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44566.4]
assign _T_4538 = _T_1642 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44567.4]
assign _T_4540 = _T_4538 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44569.4]
assign _T_4542 = _T_4532 + _T_4537; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44571.4]
assign _T_4543 = _T_4542 - _T_4540; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44572.4]
assign _T_4544 = $unsigned(_T_4543); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44573.4]
assign _T_4545 = _T_4544[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44574.4]
assign _T_4546 = _T_4540 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44576.4]
assign _T_4548 = _T_4546 | _T_4532; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44578.4]
assign _T_4550 = _T_4548 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44580.4]
assign _T_4551 = _T_4550 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44581.4]
assign _T_4552 = _T_4537 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44586.4]
assign _T_4553 = _T_4532 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44587.4]
assign _T_4554 = _T_4552 | _T_4553; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44588.4]
assign _T_4556 = _T_4554 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44590.4]
assign _T_4557 = _T_4556 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44591.4]
assign _T_4568 = _T_1511 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44608.4]
assign _T_4569 = _T_1643 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44609.4]
assign _T_4571 = _T_4569 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44611.4]
assign _T_4573 = _T_4563 + _T_4568; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44613.4]
assign _T_4574 = _T_4573 - _T_4571; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44614.4]
assign _T_4575 = $unsigned(_T_4574); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44615.4]
assign _T_4576 = _T_4575[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44616.4]
assign _T_4577 = _T_4571 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44618.4]
assign _T_4579 = _T_4577 | _T_4563; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44620.4]
assign _T_4581 = _T_4579 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44622.4]
assign _T_4582 = _T_4581 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44623.4]
assign _T_4583 = _T_4568 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44628.4]
assign _T_4584 = _T_4563 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44629.4]
assign _T_4585 = _T_4583 | _T_4584; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44630.4]
assign _T_4587 = _T_4585 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44632.4]
assign _T_4588 = _T_4587 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44633.4]
assign _T_4599 = _T_1512 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44650.4]
assign _T_4600 = _T_1644 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44651.4]
assign _T_4602 = _T_4600 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44653.4]
assign _T_4604 = _T_4594 + _T_4599; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44655.4]
assign _T_4605 = _T_4604 - _T_4602; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44656.4]
assign _T_4606 = $unsigned(_T_4605); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44657.4]
assign _T_4607 = _T_4606[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44658.4]
assign _T_4608 = _T_4602 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44660.4]
assign _T_4610 = _T_4608 | _T_4594; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44662.4]
assign _T_4612 = _T_4610 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44664.4]
assign _T_4613 = _T_4612 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44665.4]
assign _T_4614 = _T_4599 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44670.4]
assign _T_4615 = _T_4594 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44671.4]
assign _T_4616 = _T_4614 | _T_4615; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44672.4]
assign _T_4618 = _T_4616 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44674.4]
assign _T_4619 = _T_4618 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44675.4]
assign _T_4630 = _T_1513 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44692.4]
assign _T_4631 = _T_1645 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44693.4]
assign _T_4633 = _T_4631 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44695.4]
assign _T_4635 = _T_4625 + _T_4630; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44697.4]
assign _T_4636 = _T_4635 - _T_4633; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44698.4]
assign _T_4637 = $unsigned(_T_4636); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44699.4]
assign _T_4638 = _T_4637[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44700.4]
assign _T_4639 = _T_4633 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44702.4]
assign _T_4641 = _T_4639 | _T_4625; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44704.4]
assign _T_4643 = _T_4641 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44706.4]
assign _T_4644 = _T_4643 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44707.4]
assign _T_4645 = _T_4630 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44712.4]
assign _T_4646 = _T_4625 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44713.4]
assign _T_4647 = _T_4645 | _T_4646; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44714.4]
assign _T_4649 = _T_4647 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44716.4]
assign _T_4650 = _T_4649 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44717.4]
assign _T_4661 = _T_1514 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44734.4]
assign _T_4662 = _T_1646 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44735.4]
assign _T_4664 = _T_4662 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44737.4]
assign _T_4666 = _T_4656 + _T_4661; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44739.4]
assign _T_4667 = _T_4666 - _T_4664; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44740.4]
assign _T_4668 = $unsigned(_T_4667); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44741.4]
assign _T_4669 = _T_4668[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44742.4]
assign _T_4670 = _T_4664 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44744.4]
assign _T_4672 = _T_4670 | _T_4656; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44746.4]
assign _T_4674 = _T_4672 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44748.4]
assign _T_4675 = _T_4674 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44749.4]
assign _T_4676 = _T_4661 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44754.4]
assign _T_4677 = _T_4656 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44755.4]
assign _T_4678 = _T_4676 | _T_4677; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44756.4]
assign _T_4680 = _T_4678 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44758.4]
assign _T_4681 = _T_4680 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44759.4]
assign _T_4692 = _T_1515 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44776.4]
assign _T_4693 = _T_1647 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44777.4]
assign _T_4695 = _T_4693 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44779.4]
assign _T_4697 = _T_4687 + _T_4692; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44781.4]
assign _T_4698 = _T_4697 - _T_4695; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44782.4]
assign _T_4699 = $unsigned(_T_4698); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44783.4]
assign _T_4700 = _T_4699[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44784.4]
assign _T_4701 = _T_4695 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44786.4]
assign _T_4703 = _T_4701 | _T_4687; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44788.4]
assign _T_4705 = _T_4703 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44790.4]
assign _T_4706 = _T_4705 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44791.4]
assign _T_4707 = _T_4692 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44796.4]
assign _T_4708 = _T_4687 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44797.4]
assign _T_4709 = _T_4707 | _T_4708; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44798.4]
assign _T_4711 = _T_4709 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44800.4]
assign _T_4712 = _T_4711 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44801.4]
assign _T_4723 = _T_1516 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44818.4]
assign _T_4724 = _T_1648 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44819.4]
assign _T_4726 = _T_4724 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44821.4]
assign _T_4728 = _T_4718 + _T_4723; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44823.4]
assign _T_4729 = _T_4728 - _T_4726; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44824.4]
assign _T_4730 = $unsigned(_T_4729); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44825.4]
assign _T_4731 = _T_4730[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44826.4]
assign _T_4732 = _T_4726 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44828.4]
assign _T_4734 = _T_4732 | _T_4718; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44830.4]
assign _T_4736 = _T_4734 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44832.4]
assign _T_4737 = _T_4736 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44833.4]
assign _T_4738 = _T_4723 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44838.4]
assign _T_4739 = _T_4718 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44839.4]
assign _T_4740 = _T_4738 | _T_4739; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44840.4]
assign _T_4742 = _T_4740 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44842.4]
assign _T_4743 = _T_4742 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44843.4]
assign _T_4754 = _T_1517 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44860.4]
assign _T_4755 = _T_1649 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44861.4]
assign _T_4757 = _T_4755 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44863.4]
assign _T_4759 = _T_4749 + _T_4754; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44865.4]
assign _T_4760 = _T_4759 - _T_4757; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44866.4]
assign _T_4761 = $unsigned(_T_4760); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44867.4]
assign _T_4762 = _T_4761[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44868.4]
assign _T_4763 = _T_4757 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44870.4]
assign _T_4765 = _T_4763 | _T_4749; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44872.4]
assign _T_4767 = _T_4765 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44874.4]
assign _T_4768 = _T_4767 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44875.4]
assign _T_4769 = _T_4754 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44880.4]
assign _T_4770 = _T_4749 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44881.4]
assign _T_4771 = _T_4769 | _T_4770; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44882.4]
assign _T_4773 = _T_4771 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44884.4]
assign _T_4774 = _T_4773 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44885.4]
assign _T_4785 = _T_1518 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44902.4]
assign _T_4786 = _T_1650 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44903.4]
assign _T_4788 = _T_4786 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44905.4]
assign _T_4790 = _T_4780 + _T_4785; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44907.4]
assign _T_4791 = _T_4790 - _T_4788; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44908.4]
assign _T_4792 = $unsigned(_T_4791); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44909.4]
assign _T_4793 = _T_4792[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44910.4]
assign _T_4794 = _T_4788 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44912.4]
assign _T_4796 = _T_4794 | _T_4780; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44914.4]
assign _T_4798 = _T_4796 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44916.4]
assign _T_4799 = _T_4798 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44917.4]
assign _T_4800 = _T_4785 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44922.4]
assign _T_4801 = _T_4780 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44923.4]
assign _T_4802 = _T_4800 | _T_4801; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44924.4]
assign _T_4804 = _T_4802 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44926.4]
assign _T_4805 = _T_4804 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44927.4]
assign _T_4816 = _T_1519 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44944.4]
assign _T_4817 = _T_1651 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44945.4]
assign _T_4819 = _T_4817 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44947.4]
assign _T_4821 = _T_4811 + _T_4816; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44949.4]
assign _T_4822 = _T_4821 - _T_4819; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44950.4]
assign _T_4823 = $unsigned(_T_4822); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44951.4]
assign _T_4824 = _T_4823[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44952.4]
assign _T_4825 = _T_4819 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44954.4]
assign _T_4827 = _T_4825 | _T_4811; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44956.4]
assign _T_4829 = _T_4827 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44958.4]
assign _T_4830 = _T_4829 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44959.4]
assign _T_4831 = _T_4816 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@44964.4]
assign _T_4832 = _T_4811 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@44965.4]
assign _T_4833 = _T_4831 | _T_4832; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@44966.4]
assign _T_4835 = _T_4833 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44968.4]
assign _T_4836 = _T_4835 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44969.4]
assign _T_4847 = _T_1520 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@44986.4]
assign _T_4848 = _T_1652 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@44987.4]
assign _T_4850 = _T_4848 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@44989.4]
assign _T_4852 = _T_4842 + _T_4847; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@44991.4]
assign _T_4853 = _T_4852 - _T_4850; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44992.4]
assign _T_4854 = $unsigned(_T_4853); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44993.4]
assign _T_4855 = _T_4854[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@44994.4]
assign _T_4856 = _T_4850 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@44996.4]
assign _T_4858 = _T_4856 | _T_4842; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@44998.4]
assign _T_4860 = _T_4858 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45000.4]
assign _T_4861 = _T_4860 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45001.4]
assign _T_4862 = _T_4847 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45006.4]
assign _T_4863 = _T_4842 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45007.4]
assign _T_4864 = _T_4862 | _T_4863; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45008.4]
assign _T_4866 = _T_4864 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45010.4]
assign _T_4867 = _T_4866 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45011.4]
assign _T_4878 = _T_1521 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45028.4]
assign _T_4879 = _T_1653 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45029.4]
assign _T_4881 = _T_4879 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45031.4]
assign _T_4883 = _T_4873 + _T_4878; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45033.4]
assign _T_4884 = _T_4883 - _T_4881; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45034.4]
assign _T_4885 = $unsigned(_T_4884); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45035.4]
assign _T_4886 = _T_4885[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45036.4]
assign _T_4887 = _T_4881 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45038.4]
assign _T_4889 = _T_4887 | _T_4873; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45040.4]
assign _T_4891 = _T_4889 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45042.4]
assign _T_4892 = _T_4891 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45043.4]
assign _T_4893 = _T_4878 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45048.4]
assign _T_4894 = _T_4873 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45049.4]
assign _T_4895 = _T_4893 | _T_4894; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45050.4]
assign _T_4897 = _T_4895 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45052.4]
assign _T_4898 = _T_4897 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45053.4]
assign _T_4909 = _T_1522 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45070.4]
assign _T_4910 = _T_1654 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45071.4]
assign _T_4912 = _T_4910 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45073.4]
assign _T_4914 = _T_4904 + _T_4909; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45075.4]
assign _T_4915 = _T_4914 - _T_4912; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45076.4]
assign _T_4916 = $unsigned(_T_4915); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45077.4]
assign _T_4917 = _T_4916[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45078.4]
assign _T_4918 = _T_4912 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45080.4]
assign _T_4920 = _T_4918 | _T_4904; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45082.4]
assign _T_4922 = _T_4920 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45084.4]
assign _T_4923 = _T_4922 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45085.4]
assign _T_4924 = _T_4909 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45090.4]
assign _T_4925 = _T_4904 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45091.4]
assign _T_4926 = _T_4924 | _T_4925; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45092.4]
assign _T_4928 = _T_4926 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45094.4]
assign _T_4929 = _T_4928 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45095.4]
assign _T_4940 = _T_1523 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45112.4]
assign _T_4941 = _T_1655 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45113.4]
assign _T_4943 = _T_4941 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45115.4]
assign _T_4945 = _T_4935 + _T_4940; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45117.4]
assign _T_4946 = _T_4945 - _T_4943; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45118.4]
assign _T_4947 = $unsigned(_T_4946); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45119.4]
assign _T_4948 = _T_4947[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45120.4]
assign _T_4949 = _T_4943 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45122.4]
assign _T_4951 = _T_4949 | _T_4935; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45124.4]
assign _T_4953 = _T_4951 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45126.4]
assign _T_4954 = _T_4953 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45127.4]
assign _T_4955 = _T_4940 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45132.4]
assign _T_4956 = _T_4935 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45133.4]
assign _T_4957 = _T_4955 | _T_4956; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45134.4]
assign _T_4959 = _T_4957 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45136.4]
assign _T_4960 = _T_4959 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45137.4]
assign _T_4971 = _T_1524 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45154.4]
assign _T_4972 = _T_1656 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45155.4]
assign _T_4974 = _T_4972 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45157.4]
assign _T_4976 = _T_4966 + _T_4971; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45159.4]
assign _T_4977 = _T_4976 - _T_4974; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45160.4]
assign _T_4978 = $unsigned(_T_4977); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45161.4]
assign _T_4979 = _T_4978[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45162.4]
assign _T_4980 = _T_4974 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45164.4]
assign _T_4982 = _T_4980 | _T_4966; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45166.4]
assign _T_4984 = _T_4982 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45168.4]
assign _T_4985 = _T_4984 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45169.4]
assign _T_4986 = _T_4971 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45174.4]
assign _T_4987 = _T_4966 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45175.4]
assign _T_4988 = _T_4986 | _T_4987; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45176.4]
assign _T_4990 = _T_4988 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45178.4]
assign _T_4991 = _T_4990 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45179.4]
assign _T_5002 = _T_1525 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45196.4]
assign _T_5003 = _T_1657 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45197.4]
assign _T_5005 = _T_5003 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45199.4]
assign _T_5007 = _T_4997 + _T_5002; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45201.4]
assign _T_5008 = _T_5007 - _T_5005; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45202.4]
assign _T_5009 = $unsigned(_T_5008); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45203.4]
assign _T_5010 = _T_5009[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45204.4]
assign _T_5011 = _T_5005 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45206.4]
assign _T_5013 = _T_5011 | _T_4997; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45208.4]
assign _T_5015 = _T_5013 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45210.4]
assign _T_5016 = _T_5015 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45211.4]
assign _T_5017 = _T_5002 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45216.4]
assign _T_5018 = _T_4997 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45217.4]
assign _T_5019 = _T_5017 | _T_5018; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45218.4]
assign _T_5021 = _T_5019 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45220.4]
assign _T_5022 = _T_5021 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45221.4]
assign _T_5033 = _T_1526 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45238.4]
assign _T_5034 = _T_1658 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45239.4]
assign _T_5036 = _T_5034 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45241.4]
assign _T_5038 = _T_5028 + _T_5033; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45243.4]
assign _T_5039 = _T_5038 - _T_5036; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45244.4]
assign _T_5040 = $unsigned(_T_5039); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45245.4]
assign _T_5041 = _T_5040[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45246.4]
assign _T_5042 = _T_5036 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45248.4]
assign _T_5044 = _T_5042 | _T_5028; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45250.4]
assign _T_5046 = _T_5044 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45252.4]
assign _T_5047 = _T_5046 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45253.4]
assign _T_5048 = _T_5033 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45258.4]
assign _T_5049 = _T_5028 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45259.4]
assign _T_5050 = _T_5048 | _T_5049; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45260.4]
assign _T_5052 = _T_5050 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45262.4]
assign _T_5053 = _T_5052 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45263.4]
assign _T_5064 = _T_1527 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45280.4]
assign _T_5065 = _T_1659 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45281.4]
assign _T_5067 = _T_5065 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45283.4]
assign _T_5069 = _T_5059 + _T_5064; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45285.4]
assign _T_5070 = _T_5069 - _T_5067; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45286.4]
assign _T_5071 = $unsigned(_T_5070); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45287.4]
assign _T_5072 = _T_5071[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45288.4]
assign _T_5073 = _T_5067 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45290.4]
assign _T_5075 = _T_5073 | _T_5059; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45292.4]
assign _T_5077 = _T_5075 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45294.4]
assign _T_5078 = _T_5077 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45295.4]
assign _T_5079 = _T_5064 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45300.4]
assign _T_5080 = _T_5059 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45301.4]
assign _T_5081 = _T_5079 | _T_5080; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45302.4]
assign _T_5083 = _T_5081 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45304.4]
assign _T_5084 = _T_5083 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45305.4]
assign _T_5095 = _T_1528 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45322.4]
assign _T_5096 = _T_1660 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45323.4]
assign _T_5098 = _T_5096 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45325.4]
assign _T_5100 = _T_5090 + _T_5095; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45327.4]
assign _T_5101 = _T_5100 - _T_5098; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45328.4]
assign _T_5102 = $unsigned(_T_5101); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45329.4]
assign _T_5103 = _T_5102[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45330.4]
assign _T_5104 = _T_5098 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45332.4]
assign _T_5106 = _T_5104 | _T_5090; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45334.4]
assign _T_5108 = _T_5106 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45336.4]
assign _T_5109 = _T_5108 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45337.4]
assign _T_5110 = _T_5095 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45342.4]
assign _T_5111 = _T_5090 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45343.4]
assign _T_5112 = _T_5110 | _T_5111; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45344.4]
assign _T_5114 = _T_5112 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45346.4]
assign _T_5115 = _T_5114 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45347.4]
assign _T_5126 = _T_1529 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45364.4]
assign _T_5127 = _T_1661 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45365.4]
assign _T_5129 = _T_5127 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45367.4]
assign _T_5131 = _T_5121 + _T_5126; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45369.4]
assign _T_5132 = _T_5131 - _T_5129; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45370.4]
assign _T_5133 = $unsigned(_T_5132); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45371.4]
assign _T_5134 = _T_5133[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45372.4]
assign _T_5135 = _T_5129 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45374.4]
assign _T_5137 = _T_5135 | _T_5121; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45376.4]
assign _T_5139 = _T_5137 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45378.4]
assign _T_5140 = _T_5139 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45379.4]
assign _T_5141 = _T_5126 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45384.4]
assign _T_5142 = _T_5121 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45385.4]
assign _T_5143 = _T_5141 | _T_5142; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45386.4]
assign _T_5145 = _T_5143 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45388.4]
assign _T_5146 = _T_5145 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45389.4]
assign _T_5157 = _T_1530 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45406.4]
assign _T_5158 = _T_1662 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45407.4]
assign _T_5160 = _T_5158 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45409.4]
assign _T_5162 = _T_5152 + _T_5157; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45411.4]
assign _T_5163 = _T_5162 - _T_5160; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45412.4]
assign _T_5164 = $unsigned(_T_5163); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45413.4]
assign _T_5165 = _T_5164[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45414.4]
assign _T_5166 = _T_5160 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45416.4]
assign _T_5168 = _T_5166 | _T_5152; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45418.4]
assign _T_5170 = _T_5168 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45420.4]
assign _T_5171 = _T_5170 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45421.4]
assign _T_5172 = _T_5157 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45426.4]
assign _T_5173 = _T_5152 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45427.4]
assign _T_5174 = _T_5172 | _T_5173; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45428.4]
assign _T_5176 = _T_5174 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45430.4]
assign _T_5177 = _T_5176 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45431.4]
assign _T_5188 = _T_1531 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45448.4]
assign _T_5189 = _T_1663 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45449.4]
assign _T_5191 = _T_5189 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45451.4]
assign _T_5193 = _T_5183 + _T_5188; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45453.4]
assign _T_5194 = _T_5193 - _T_5191; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45454.4]
assign _T_5195 = $unsigned(_T_5194); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45455.4]
assign _T_5196 = _T_5195[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45456.4]
assign _T_5197 = _T_5191 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45458.4]
assign _T_5199 = _T_5197 | _T_5183; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45460.4]
assign _T_5201 = _T_5199 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45462.4]
assign _T_5202 = _T_5201 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45463.4]
assign _T_5203 = _T_5188 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45468.4]
assign _T_5204 = _T_5183 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45469.4]
assign _T_5205 = _T_5203 | _T_5204; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45470.4]
assign _T_5207 = _T_5205 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45472.4]
assign _T_5208 = _T_5207 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45473.4]
assign _T_5219 = _T_1532 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45490.4]
assign _T_5220 = _T_1664 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45491.4]
assign _T_5222 = _T_5220 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45493.4]
assign _T_5224 = _T_5214 + _T_5219; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45495.4]
assign _T_5225 = _T_5224 - _T_5222; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45496.4]
assign _T_5226 = $unsigned(_T_5225); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45497.4]
assign _T_5227 = _T_5226[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45498.4]
assign _T_5228 = _T_5222 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45500.4]
assign _T_5230 = _T_5228 | _T_5214; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45502.4]
assign _T_5232 = _T_5230 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45504.4]
assign _T_5233 = _T_5232 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45505.4]
assign _T_5234 = _T_5219 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45510.4]
assign _T_5235 = _T_5214 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45511.4]
assign _T_5236 = _T_5234 | _T_5235; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45512.4]
assign _T_5238 = _T_5236 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45514.4]
assign _T_5239 = _T_5238 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45515.4]
assign _T_5250 = _T_1533 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45532.4]
assign _T_5251 = _T_1665 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45533.4]
assign _T_5253 = _T_5251 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45535.4]
assign _T_5255 = _T_5245 + _T_5250; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45537.4]
assign _T_5256 = _T_5255 - _T_5253; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45538.4]
assign _T_5257 = $unsigned(_T_5256); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45539.4]
assign _T_5258 = _T_5257[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45540.4]
assign _T_5259 = _T_5253 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45542.4]
assign _T_5261 = _T_5259 | _T_5245; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45544.4]
assign _T_5263 = _T_5261 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45546.4]
assign _T_5264 = _T_5263 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45547.4]
assign _T_5265 = _T_5250 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45552.4]
assign _T_5266 = _T_5245 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45553.4]
assign _T_5267 = _T_5265 | _T_5266; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45554.4]
assign _T_5269 = _T_5267 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45556.4]
assign _T_5270 = _T_5269 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45557.4]
assign _T_5281 = _T_1534 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45574.4]
assign _T_5282 = _T_1666 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45575.4]
assign _T_5284 = _T_5282 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45577.4]
assign _T_5286 = _T_5276 + _T_5281; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45579.4]
assign _T_5287 = _T_5286 - _T_5284; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45580.4]
assign _T_5288 = $unsigned(_T_5287); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45581.4]
assign _T_5289 = _T_5288[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45582.4]
assign _T_5290 = _T_5284 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45584.4]
assign _T_5292 = _T_5290 | _T_5276; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45586.4]
assign _T_5294 = _T_5292 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45588.4]
assign _T_5295 = _T_5294 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45589.4]
assign _T_5296 = _T_5281 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45594.4]
assign _T_5297 = _T_5276 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45595.4]
assign _T_5298 = _T_5296 | _T_5297; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45596.4]
assign _T_5300 = _T_5298 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45598.4]
assign _T_5301 = _T_5300 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45599.4]
assign _T_5312 = _T_1535 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45616.4]
assign _T_5313 = _T_1667 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45617.4]
assign _T_5315 = _T_5313 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45619.4]
assign _T_5317 = _T_5307 + _T_5312; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45621.4]
assign _T_5318 = _T_5317 - _T_5315; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45622.4]
assign _T_5319 = $unsigned(_T_5318); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45623.4]
assign _T_5320 = _T_5319[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45624.4]
assign _T_5321 = _T_5315 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45626.4]
assign _T_5323 = _T_5321 | _T_5307; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45628.4]
assign _T_5325 = _T_5323 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45630.4]
assign _T_5326 = _T_5325 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45631.4]
assign _T_5327 = _T_5312 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45636.4]
assign _T_5328 = _T_5307 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45637.4]
assign _T_5329 = _T_5327 | _T_5328; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45638.4]
assign _T_5331 = _T_5329 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45640.4]
assign _T_5332 = _T_5331 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45641.4]
assign _T_5343 = _T_1536 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45658.4]
assign _T_5344 = _T_1668 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45659.4]
assign _T_5346 = _T_5344 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45661.4]
assign _T_5348 = _T_5338 + _T_5343; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45663.4]
assign _T_5349 = _T_5348 - _T_5346; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45664.4]
assign _T_5350 = $unsigned(_T_5349); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45665.4]
assign _T_5351 = _T_5350[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45666.4]
assign _T_5352 = _T_5346 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45668.4]
assign _T_5354 = _T_5352 | _T_5338; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45670.4]
assign _T_5356 = _T_5354 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45672.4]
assign _T_5357 = _T_5356 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45673.4]
assign _T_5358 = _T_5343 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45678.4]
assign _T_5359 = _T_5338 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45679.4]
assign _T_5360 = _T_5358 | _T_5359; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45680.4]
assign _T_5362 = _T_5360 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45682.4]
assign _T_5363 = _T_5362 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45683.4]
assign _T_5374 = _T_1537 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45700.4]
assign _T_5375 = _T_1669 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45701.4]
assign _T_5377 = _T_5375 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45703.4]
assign _T_5379 = _T_5369 + _T_5374; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45705.4]
assign _T_5380 = _T_5379 - _T_5377; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45706.4]
assign _T_5381 = $unsigned(_T_5380); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45707.4]
assign _T_5382 = _T_5381[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45708.4]
assign _T_5383 = _T_5377 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45710.4]
assign _T_5385 = _T_5383 | _T_5369; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45712.4]
assign _T_5387 = _T_5385 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45714.4]
assign _T_5388 = _T_5387 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45715.4]
assign _T_5389 = _T_5374 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45720.4]
assign _T_5390 = _T_5369 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45721.4]
assign _T_5391 = _T_5389 | _T_5390; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45722.4]
assign _T_5393 = _T_5391 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45724.4]
assign _T_5394 = _T_5393 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45725.4]
assign _T_5405 = _T_1538 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45742.4]
assign _T_5406 = _T_1670 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45743.4]
assign _T_5408 = _T_5406 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45745.4]
assign _T_5410 = _T_5400 + _T_5405; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45747.4]
assign _T_5411 = _T_5410 - _T_5408; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45748.4]
assign _T_5412 = $unsigned(_T_5411); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45749.4]
assign _T_5413 = _T_5412[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45750.4]
assign _T_5414 = _T_5408 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45752.4]
assign _T_5416 = _T_5414 | _T_5400; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45754.4]
assign _T_5418 = _T_5416 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45756.4]
assign _T_5419 = _T_5418 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45757.4]
assign _T_5420 = _T_5405 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45762.4]
assign _T_5421 = _T_5400 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45763.4]
assign _T_5422 = _T_5420 | _T_5421; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45764.4]
assign _T_5424 = _T_5422 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45766.4]
assign _T_5425 = _T_5424 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45767.4]
assign _T_5436 = _T_1539 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45784.4]
assign _T_5437 = _T_1671 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45785.4]
assign _T_5439 = _T_5437 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45787.4]
assign _T_5441 = _T_5431 + _T_5436; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45789.4]
assign _T_5442 = _T_5441 - _T_5439; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45790.4]
assign _T_5443 = $unsigned(_T_5442); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45791.4]
assign _T_5444 = _T_5443[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45792.4]
assign _T_5445 = _T_5439 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45794.4]
assign _T_5447 = _T_5445 | _T_5431; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45796.4]
assign _T_5449 = _T_5447 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45798.4]
assign _T_5450 = _T_5449 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45799.4]
assign _T_5451 = _T_5436 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45804.4]
assign _T_5452 = _T_5431 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45805.4]
assign _T_5453 = _T_5451 | _T_5452; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45806.4]
assign _T_5455 = _T_5453 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45808.4]
assign _T_5456 = _T_5455 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45809.4]
assign _T_5467 = _T_1540 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45826.4]
assign _T_5468 = _T_1672 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45827.4]
assign _T_5470 = _T_5468 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45829.4]
assign _T_5472 = _T_5462 + _T_5467; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45831.4]
assign _T_5473 = _T_5472 - _T_5470; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45832.4]
assign _T_5474 = $unsigned(_T_5473); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45833.4]
assign _T_5475 = _T_5474[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45834.4]
assign _T_5476 = _T_5470 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45836.4]
assign _T_5478 = _T_5476 | _T_5462; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45838.4]
assign _T_5480 = _T_5478 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45840.4]
assign _T_5481 = _T_5480 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45841.4]
assign _T_5482 = _T_5467 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45846.4]
assign _T_5483 = _T_5462 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45847.4]
assign _T_5484 = _T_5482 | _T_5483; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45848.4]
assign _T_5486 = _T_5484 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45850.4]
assign _T_5487 = _T_5486 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45851.4]
assign _T_5498 = _T_1541 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45868.4]
assign _T_5499 = _T_1673 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45869.4]
assign _T_5501 = _T_5499 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45871.4]
assign _T_5503 = _T_5493 + _T_5498; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45873.4]
assign _T_5504 = _T_5503 - _T_5501; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45874.4]
assign _T_5505 = $unsigned(_T_5504); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45875.4]
assign _T_5506 = _T_5505[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45876.4]
assign _T_5507 = _T_5501 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45878.4]
assign _T_5509 = _T_5507 | _T_5493; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45880.4]
assign _T_5511 = _T_5509 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45882.4]
assign _T_5512 = _T_5511 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45883.4]
assign _T_5513 = _T_5498 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45888.4]
assign _T_5514 = _T_5493 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45889.4]
assign _T_5515 = _T_5513 | _T_5514; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45890.4]
assign _T_5517 = _T_5515 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45892.4]
assign _T_5518 = _T_5517 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45893.4]
assign _T_5529 = _T_1542 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45910.4]
assign _T_5530 = _T_1674 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45911.4]
assign _T_5532 = _T_5530 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45913.4]
assign _T_5534 = _T_5524 + _T_5529; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45915.4]
assign _T_5535 = _T_5534 - _T_5532; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45916.4]
assign _T_5536 = $unsigned(_T_5535); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45917.4]
assign _T_5537 = _T_5536[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45918.4]
assign _T_5538 = _T_5532 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45920.4]
assign _T_5540 = _T_5538 | _T_5524; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45922.4]
assign _T_5542 = _T_5540 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45924.4]
assign _T_5543 = _T_5542 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45925.4]
assign _T_5544 = _T_5529 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45930.4]
assign _T_5545 = _T_5524 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45931.4]
assign _T_5546 = _T_5544 | _T_5545; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45932.4]
assign _T_5548 = _T_5546 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45934.4]
assign _T_5549 = _T_5548 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45935.4]
assign _T_5560 = _T_1543 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45952.4]
assign _T_5561 = _T_1675 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45953.4]
assign _T_5563 = _T_5561 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45955.4]
assign _T_5565 = _T_5555 + _T_5560; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45957.4]
assign _T_5566 = _T_5565 - _T_5563; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45958.4]
assign _T_5567 = $unsigned(_T_5566); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45959.4]
assign _T_5568 = _T_5567[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@45960.4]
assign _T_5569 = _T_5563 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@45962.4]
assign _T_5571 = _T_5569 | _T_5555; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@45964.4]
assign _T_5573 = _T_5571 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45966.4]
assign _T_5574 = _T_5573 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45967.4]
assign _T_5575 = _T_5560 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@45972.4]
assign _T_5576 = _T_5555 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@45973.4]
assign _T_5577 = _T_5575 | _T_5576; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@45974.4]
assign _T_5579 = _T_5577 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45976.4]
assign _T_5580 = _T_5579 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45977.4]
assign _T_5591 = _T_1544 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@45994.4]
assign _T_5592 = _T_1676 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@45995.4]
assign _T_5594 = _T_5592 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@45997.4]
assign _T_5596 = _T_5586 + _T_5591; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@45999.4]
assign _T_5597 = _T_5596 - _T_5594; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46000.4]
assign _T_5598 = $unsigned(_T_5597); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46001.4]
assign _T_5599 = _T_5598[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46002.4]
assign _T_5600 = _T_5594 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@46004.4]
assign _T_5602 = _T_5600 | _T_5586; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@46006.4]
assign _T_5604 = _T_5602 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46008.4]
assign _T_5605 = _T_5604 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46009.4]
assign _T_5606 = _T_5591 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@46014.4]
assign _T_5607 = _T_5586 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@46015.4]
assign _T_5608 = _T_5606 | _T_5607; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@46016.4]
assign _T_5610 = _T_5608 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46018.4]
assign _T_5611 = _T_5610 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46019.4]
assign _T_5622 = _T_1545 & _T_1684; // @[ToAXI4.scala 229:22:freechips.rocketchip.system.LowRiscConfig.fir@46036.4]
assign _T_5623 = _T_1677 & _T_1678; // @[ToAXI4.scala 230:22:freechips.rocketchip.system.LowRiscConfig.fir@46037.4]
assign _T_5625 = _T_5623 & _T_1687; // @[ToAXI4.scala 230:32:freechips.rocketchip.system.LowRiscConfig.fir@46039.4]
assign _T_5627 = _T_5617 + _T_5622; // @[ToAXI4.scala 231:24:freechips.rocketchip.system.LowRiscConfig.fir@46041.4]
assign _T_5628 = _T_5627 - _T_5625; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46042.4]
assign _T_5629 = $unsigned(_T_5628); // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46043.4]
assign _T_5630 = _T_5629[0:0]; // @[ToAXI4.scala 231:37:freechips.rocketchip.system.LowRiscConfig.fir@46044.4]
assign _T_5631 = _T_5625 == 1'h0; // @[ToAXI4.scala 233:17:freechips.rocketchip.system.LowRiscConfig.fir@46046.4]
assign _T_5633 = _T_5631 | _T_5617; // @[ToAXI4.scala 233:22:freechips.rocketchip.system.LowRiscConfig.fir@46048.4]
assign _T_5635 = _T_5633 | reset; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46050.4]
assign _T_5636 = _T_5635 == 1'h0; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46051.4]
assign _T_5637 = _T_5622 == 1'h0; // @[ToAXI4.scala 234:17:freechips.rocketchip.system.LowRiscConfig.fir@46056.4]
assign _T_5638 = _T_5617 != 1'h1; // @[ToAXI4.scala 234:31:freechips.rocketchip.system.LowRiscConfig.fir@46057.4]
assign _T_5639 = _T_5637 | _T_5638; // @[ToAXI4.scala 234:22:freechips.rocketchip.system.LowRiscConfig.fir@46058.4]
assign _T_5641 = _T_5639 | reset; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46060.4]
assign _T_5642 = _T_5641 == 1'h0; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46061.4]
assign auto_in_a_ready = _T_1376 & _T_1379; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_valid = _T_1396 ? auto_out_r_valid : auto_out_b_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_bits_opcode = _T_1396 ? 3'h1 : 3'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_bits_size = _T_1396 ? _T_1329 : _T_1331; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_bits_source = _T_1396 ? _T_1328 : _T_1330; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_bits_denied = _T_1396 ? _GEN_260 : _T_1408; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_bits_data = auto_out_r_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_in_d_bits_corrupt = _T_1396 ? _T_1409 : 1'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@39836.4]
assign auto_out_aw_valid = _T_1354_valid & _T_1354_bits_wen; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_addr = Queue_1_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_len = Queue_1_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_burst = Queue_1_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_lock = Queue_1_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_cache = Queue_1_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_prot = Queue_1_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_qos = Queue_1_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_aw_bits_user = Queue_1_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_w_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_w_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_w_bits_strb = Queue_io_deq_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_w_bits_last = Queue_io_deq_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_b_ready = auto_in_d_ready & _T_1397; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_valid = _T_1354_valid & _T_1358; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_id = Queue_1_io_deq_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_addr = Queue_1_io_deq_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_len = Queue_1_io_deq_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_burst = Queue_1_io_deq_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_lock = Queue_1_io_deq_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_cache = Queue_1_io_deq_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_prot = Queue_1_io_deq_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_qos = Queue_1_io_deq_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_ar_bits_user = Queue_1_io_deq_bits_user; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign auto_out_r_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@39835.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@39798.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@39799.4]
assign TLMonitor_io_in_a_ready = _T_1376 & _T_1379; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_valid = _T_1396 ? auto_out_r_valid : auto_out_b_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_bits_opcode = _T_1396 ? 3'h1 : 3'h0; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_bits_size = _T_1396 ? _T_1329 : _T_1331; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_bits_source = _T_1396 ? _T_1328 : _T_1330; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_bits_denied = _T_1396 ? _GEN_260 : _T_1408; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign TLMonitor_io_in_d_bits_corrupt = _T_1396 ? _T_1409 : 1'h0; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@39832.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@40284.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@40285.4]
assign Queue_io_enq_valid = _T_1389 & _T_1377; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@40286.4]
assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40289.4]
assign Queue_io_enq_bits_strb = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40288.4]
assign Queue_io_enq_bits_last = _T_1310 | _T_1311; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40287.4]
assign Queue_io_deq_ready = auto_out_w_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@40296.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@40299.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@40300.4]
assign Queue_1_io_enq_valid = _T_1382 & _T_1385; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@40301.4]
assign Queue_1_io_enq_bits_id = 7'h7f == auto_in_a_bits_source ? 7'h7f : _GEN_128; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40312.4]
assign Queue_1_io_enq_bits_addr = auto_in_a_bits_address; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40311.4]
assign Queue_1_io_enq_bits_len = _T_1370[10:3]; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40310.4]
assign Queue_1_io_enq_bits_size = _T_1372 ? 3'h3 : auto_in_a_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40309.4]
assign Queue_1_io_enq_bits_user = {{1'd0}, _T_1327}; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40303.4]
assign Queue_1_io_enq_bits_wen = _T_1293 == 1'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@40302.4]
assign Queue_1_io_deq_ready = _T_1354_bits_wen ? auto_out_aw_ready : auto_out_ar_ready; // @[Decoupled.scala 317:15:freechips.rocketchip.system.LowRiscConfig.fir@40327.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_5617 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_5586 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_5555 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_5524 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_5493 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_5462 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_5431 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_5400 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_5369 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_5338 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_5307 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_5276 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_5245 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_5214 = _RAND_13[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_5183 = _RAND_14[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_5152 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_5121 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_5090 = _RAND_17[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_5059 = _RAND_18[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_5028 = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_4997 = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_4966 = _RAND_21[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_22 = {1{`RANDOM}};
_T_4935 = _RAND_22[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_23 = {1{`RANDOM}};
_T_4904 = _RAND_23[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_24 = {1{`RANDOM}};
_T_4873 = _RAND_24[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_25 = {1{`RANDOM}};
_T_4842 = _RAND_25[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_26 = {1{`RANDOM}};
_T_4811 = _RAND_26[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_27 = {1{`RANDOM}};
_T_4780 = _RAND_27[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_28 = {1{`RANDOM}};
_T_4749 = _RAND_28[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_29 = {1{`RANDOM}};
_T_4718 = _RAND_29[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_30 = {1{`RANDOM}};
_T_4687 = _RAND_30[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_31 = {1{`RANDOM}};
_T_4656 = _RAND_31[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_32 = {1{`RANDOM}};
_T_4625 = _RAND_32[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_33 = {1{`RANDOM}};
_T_4594 = _RAND_33[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_34 = {1{`RANDOM}};
_T_4563 = _RAND_34[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_35 = {1{`RANDOM}};
_T_4532 = _RAND_35[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_36 = {1{`RANDOM}};
_T_4501 = _RAND_36[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_37 = {1{`RANDOM}};
_T_4470 = _RAND_37[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_38 = {1{`RANDOM}};
_T_4439 = _RAND_38[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_39 = {1{`RANDOM}};
_T_4408 = _RAND_39[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_40 = {1{`RANDOM}};
_T_4377 = _RAND_40[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_41 = {1{`RANDOM}};
_T_4346 = _RAND_41[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_42 = {1{`RANDOM}};
_T_4315 = _RAND_42[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_43 = {1{`RANDOM}};
_T_4284 = _RAND_43[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_44 = {1{`RANDOM}};
_T_4253 = _RAND_44[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_45 = {1{`RANDOM}};
_T_4222 = _RAND_45[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_46 = {1{`RANDOM}};
_T_4191 = _RAND_46[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_47 = {1{`RANDOM}};
_T_4160 = _RAND_47[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_48 = {1{`RANDOM}};
_T_4129 = _RAND_48[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_49 = {1{`RANDOM}};
_T_4098 = _RAND_49[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_50 = {1{`RANDOM}};
_T_4067 = _RAND_50[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_51 = {1{`RANDOM}};
_T_4036 = _RAND_51[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_52 = {1{`RANDOM}};
_T_4005 = _RAND_52[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_53 = {1{`RANDOM}};
_T_3974 = _RAND_53[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_54 = {1{`RANDOM}};
_T_3943 = _RAND_54[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_55 = {1{`RANDOM}};
_T_3912 = _RAND_55[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_56 = {1{`RANDOM}};
_T_3881 = _RAND_56[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_57 = {1{`RANDOM}};
_T_3850 = _RAND_57[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_58 = {1{`RANDOM}};
_T_3819 = _RAND_58[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_59 = {1{`RANDOM}};
_T_3788 = _RAND_59[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_60 = {1{`RANDOM}};
_T_3757 = _RAND_60[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_61 = {1{`RANDOM}};
_T_3726 = _RAND_61[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_62 = {1{`RANDOM}};
_T_3695 = _RAND_62[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_63 = {1{`RANDOM}};
_T_3664 = _RAND_63[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_64 = {1{`RANDOM}};
_T_3633 = _RAND_64[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_65 = {1{`RANDOM}};
_T_3602 = _RAND_65[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_66 = {1{`RANDOM}};
_T_3571 = _RAND_66[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_67 = {1{`RANDOM}};
_T_3540 = _RAND_67[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_68 = {1{`RANDOM}};
_T_3509 = _RAND_68[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_69 = {1{`RANDOM}};
_T_3478 = _RAND_69[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_70 = {1{`RANDOM}};
_T_3447 = _RAND_70[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_71 = {1{`RANDOM}};
_T_3416 = _RAND_71[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_72 = {1{`RANDOM}};
_T_3385 = _RAND_72[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_73 = {1{`RANDOM}};
_T_3354 = _RAND_73[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_74 = {1{`RANDOM}};
_T_3323 = _RAND_74[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_75 = {1{`RANDOM}};
_T_3292 = _RAND_75[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_76 = {1{`RANDOM}};
_T_3261 = _RAND_76[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_77 = {1{`RANDOM}};
_T_3230 = _RAND_77[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_78 = {1{`RANDOM}};
_T_3199 = _RAND_78[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_79 = {1{`RANDOM}};
_T_3168 = _RAND_79[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_80 = {1{`RANDOM}};
_T_3137 = _RAND_80[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_81 = {1{`RANDOM}};
_T_3106 = _RAND_81[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_82 = {1{`RANDOM}};
_T_3075 = _RAND_82[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_83 = {1{`RANDOM}};
_T_3044 = _RAND_83[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_84 = {1{`RANDOM}};
_T_3013 = _RAND_84[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_85 = {1{`RANDOM}};
_T_2982 = _RAND_85[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_86 = {1{`RANDOM}};
_T_2951 = _RAND_86[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_87 = {1{`RANDOM}};
_T_2920 = _RAND_87[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_88 = {1{`RANDOM}};
_T_2889 = _RAND_88[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_89 = {1{`RANDOM}};
_T_2858 = _RAND_89[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_90 = {1{`RANDOM}};
_T_2827 = _RAND_90[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_91 = {1{`RANDOM}};
_T_2796 = _RAND_91[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_92 = {1{`RANDOM}};
_T_2765 = _RAND_92[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_93 = {1{`RANDOM}};
_T_2734 = _RAND_93[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_94 = {1{`RANDOM}};
_T_2703 = _RAND_94[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_95 = {1{`RANDOM}};
_T_2672 = _RAND_95[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_96 = {1{`RANDOM}};
_T_2641 = _RAND_96[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_97 = {1{`RANDOM}};
_T_2610 = _RAND_97[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_98 = {1{`RANDOM}};
_T_2579 = _RAND_98[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_99 = {1{`RANDOM}};
_T_2548 = _RAND_99[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_100 = {1{`RANDOM}};
_T_2517 = _RAND_100[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_101 = {1{`RANDOM}};
_T_2486 = _RAND_101[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_102 = {1{`RANDOM}};
_T_2455 = _RAND_102[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_103 = {1{`RANDOM}};
_T_2424 = _RAND_103[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_104 = {1{`RANDOM}};
_T_2393 = _RAND_104[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_105 = {1{`RANDOM}};
_T_2362 = _RAND_105[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_106 = {1{`RANDOM}};
_T_2331 = _RAND_106[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_107 = {1{`RANDOM}};
_T_2300 = _RAND_107[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_108 = {1{`RANDOM}};
_T_2269 = _RAND_108[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_109 = {1{`RANDOM}};
_T_2238 = _RAND_109[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_110 = {1{`RANDOM}};
_T_2207 = _RAND_110[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_111 = {1{`RANDOM}};
_T_2176 = _RAND_111[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_112 = {1{`RANDOM}};
_T_2145 = _RAND_112[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_113 = {1{`RANDOM}};
_T_2114 = _RAND_113[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_114 = {1{`RANDOM}};
_T_2083 = _RAND_114[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_115 = {1{`RANDOM}};
_T_2052 = _RAND_115[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_116 = {1{`RANDOM}};
_T_2021 = _RAND_116[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_117 = {1{`RANDOM}};
_T_1990 = _RAND_117[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_118 = {1{`RANDOM}};
_T_1959 = _RAND_118[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_119 = {1{`RANDOM}};
_T_1928 = _RAND_119[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_120 = {1{`RANDOM}};
_T_1897 = _RAND_120[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_121 = {1{`RANDOM}};
_T_1866 = _RAND_121[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_122 = {1{`RANDOM}};
_T_1835 = _RAND_122[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_123 = {1{`RANDOM}};
_T_1804 = _RAND_123[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_124 = {1{`RANDOM}};
_T_1773 = _RAND_124[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_125 = {1{`RANDOM}};
_T_1742 = _RAND_125[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_126 = {1{`RANDOM}};
_T_1711 = _RAND_126[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_127 = {1{`RANDOM}};
_T_1680 = _RAND_127[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_128 = {1{`RANDOM}};
_T_1305 = _RAND_128[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_129 = {1{`RANDOM}};
_T_1363 = _RAND_129[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_130 = {1{`RANDOM}};
_T_1393 = _RAND_130[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_131 = {1{`RANDOM}};
_T_1401 = _RAND_131[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_132 = {1{`RANDOM}};
_T_1405 = _RAND_132[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_5617 <= 1'h0;
end else begin
_T_5617 <= _T_5630;
end
if (reset) begin
_T_5586 <= 1'h0;
end else begin
_T_5586 <= _T_5599;
end
if (reset) begin
_T_5555 <= 1'h0;
end else begin
_T_5555 <= _T_5568;
end
if (reset) begin
_T_5524 <= 1'h0;
end else begin
_T_5524 <= _T_5537;
end
if (reset) begin
_T_5493 <= 1'h0;
end else begin
_T_5493 <= _T_5506;
end
if (reset) begin
_T_5462 <= 1'h0;
end else begin
_T_5462 <= _T_5475;
end
if (reset) begin
_T_5431 <= 1'h0;
end else begin
_T_5431 <= _T_5444;
end
if (reset) begin
_T_5400 <= 1'h0;
end else begin
_T_5400 <= _T_5413;
end
if (reset) begin
_T_5369 <= 1'h0;
end else begin
_T_5369 <= _T_5382;
end
if (reset) begin
_T_5338 <= 1'h0;
end else begin
_T_5338 <= _T_5351;
end
if (reset) begin
_T_5307 <= 1'h0;
end else begin
_T_5307 <= _T_5320;
end
if (reset) begin
_T_5276 <= 1'h0;
end else begin
_T_5276 <= _T_5289;
end
if (reset) begin
_T_5245 <= 1'h0;
end else begin
_T_5245 <= _T_5258;
end
if (reset) begin
_T_5214 <= 1'h0;
end else begin
_T_5214 <= _T_5227;
end
if (reset) begin
_T_5183 <= 1'h0;
end else begin
_T_5183 <= _T_5196;
end
if (reset) begin
_T_5152 <= 1'h0;
end else begin
_T_5152 <= _T_5165;
end
if (reset) begin
_T_5121 <= 1'h0;
end else begin
_T_5121 <= _T_5134;
end
if (reset) begin
_T_5090 <= 1'h0;
end else begin
_T_5090 <= _T_5103;
end
if (reset) begin
_T_5059 <= 1'h0;
end else begin
_T_5059 <= _T_5072;
end
if (reset) begin
_T_5028 <= 1'h0;
end else begin
_T_5028 <= _T_5041;
end
if (reset) begin
_T_4997 <= 1'h0;
end else begin
_T_4997 <= _T_5010;
end
if (reset) begin
_T_4966 <= 1'h0;
end else begin
_T_4966 <= _T_4979;
end
if (reset) begin
_T_4935 <= 1'h0;
end else begin
_T_4935 <= _T_4948;
end
if (reset) begin
_T_4904 <= 1'h0;
end else begin
_T_4904 <= _T_4917;
end
if (reset) begin
_T_4873 <= 1'h0;
end else begin
_T_4873 <= _T_4886;
end
if (reset) begin
_T_4842 <= 1'h0;
end else begin
_T_4842 <= _T_4855;
end
if (reset) begin
_T_4811 <= 1'h0;
end else begin
_T_4811 <= _T_4824;
end
if (reset) begin
_T_4780 <= 1'h0;
end else begin
_T_4780 <= _T_4793;
end
if (reset) begin
_T_4749 <= 1'h0;
end else begin
_T_4749 <= _T_4762;
end
if (reset) begin
_T_4718 <= 1'h0;
end else begin
_T_4718 <= _T_4731;
end
if (reset) begin
_T_4687 <= 1'h0;
end else begin
_T_4687 <= _T_4700;
end
if (reset) begin
_T_4656 <= 1'h0;
end else begin
_T_4656 <= _T_4669;
end
if (reset) begin
_T_4625 <= 1'h0;
end else begin
_T_4625 <= _T_4638;
end
if (reset) begin
_T_4594 <= 1'h0;
end else begin
_T_4594 <= _T_4607;
end
if (reset) begin
_T_4563 <= 1'h0;
end else begin
_T_4563 <= _T_4576;
end
if (reset) begin
_T_4532 <= 1'h0;
end else begin
_T_4532 <= _T_4545;
end
if (reset) begin
_T_4501 <= 1'h0;
end else begin
_T_4501 <= _T_4514;
end
if (reset) begin
_T_4470 <= 1'h0;
end else begin
_T_4470 <= _T_4483;
end
if (reset) begin
_T_4439 <= 1'h0;
end else begin
_T_4439 <= _T_4452;
end
if (reset) begin
_T_4408 <= 1'h0;
end else begin
_T_4408 <= _T_4421;
end
if (reset) begin
_T_4377 <= 1'h0;
end else begin
_T_4377 <= _T_4390;
end
if (reset) begin
_T_4346 <= 1'h0;
end else begin
_T_4346 <= _T_4359;
end
if (reset) begin
_T_4315 <= 1'h0;
end else begin
_T_4315 <= _T_4328;
end
if (reset) begin
_T_4284 <= 1'h0;
end else begin
_T_4284 <= _T_4297;
end
if (reset) begin
_T_4253 <= 1'h0;
end else begin
_T_4253 <= _T_4266;
end
if (reset) begin
_T_4222 <= 1'h0;
end else begin
_T_4222 <= _T_4235;
end
if (reset) begin
_T_4191 <= 1'h0;
end else begin
_T_4191 <= _T_4204;
end
if (reset) begin
_T_4160 <= 1'h0;
end else begin
_T_4160 <= _T_4173;
end
if (reset) begin
_T_4129 <= 1'h0;
end else begin
_T_4129 <= _T_4142;
end
if (reset) begin
_T_4098 <= 1'h0;
end else begin
_T_4098 <= _T_4111;
end
if (reset) begin
_T_4067 <= 1'h0;
end else begin
_T_4067 <= _T_4080;
end
if (reset) begin
_T_4036 <= 1'h0;
end else begin
_T_4036 <= _T_4049;
end
if (reset) begin
_T_4005 <= 1'h0;
end else begin
_T_4005 <= _T_4018;
end
if (reset) begin
_T_3974 <= 1'h0;
end else begin
_T_3974 <= _T_3987;
end
if (reset) begin
_T_3943 <= 1'h0;
end else begin
_T_3943 <= _T_3956;
end
if (reset) begin
_T_3912 <= 1'h0;
end else begin
_T_3912 <= _T_3925;
end
if (reset) begin
_T_3881 <= 1'h0;
end else begin
_T_3881 <= _T_3894;
end
if (reset) begin
_T_3850 <= 1'h0;
end else begin
_T_3850 <= _T_3863;
end
if (reset) begin
_T_3819 <= 1'h0;
end else begin
_T_3819 <= _T_3832;
end
if (reset) begin
_T_3788 <= 1'h0;
end else begin
_T_3788 <= _T_3801;
end
if (reset) begin
_T_3757 <= 1'h0;
end else begin
_T_3757 <= _T_3770;
end
if (reset) begin
_T_3726 <= 1'h0;
end else begin
_T_3726 <= _T_3739;
end
if (reset) begin
_T_3695 <= 1'h0;
end else begin
_T_3695 <= _T_3708;
end
if (reset) begin
_T_3664 <= 1'h0;
end else begin
_T_3664 <= _T_3677;
end
if (reset) begin
_T_3633 <= 1'h0;
end else begin
_T_3633 <= _T_3646;
end
if (reset) begin
_T_3602 <= 1'h0;
end else begin
_T_3602 <= _T_3615;
end
if (reset) begin
_T_3571 <= 1'h0;
end else begin
_T_3571 <= _T_3584;
end
if (reset) begin
_T_3540 <= 1'h0;
end else begin
_T_3540 <= _T_3553;
end
if (reset) begin
_T_3509 <= 1'h0;
end else begin
_T_3509 <= _T_3522;
end
if (reset) begin
_T_3478 <= 1'h0;
end else begin
_T_3478 <= _T_3491;
end
if (reset) begin
_T_3447 <= 1'h0;
end else begin
_T_3447 <= _T_3460;
end
if (reset) begin
_T_3416 <= 1'h0;
end else begin
_T_3416 <= _T_3429;
end
if (reset) begin
_T_3385 <= 1'h0;
end else begin
_T_3385 <= _T_3398;
end
if (reset) begin
_T_3354 <= 1'h0;
end else begin
_T_3354 <= _T_3367;
end
if (reset) begin
_T_3323 <= 1'h0;
end else begin
_T_3323 <= _T_3336;
end
if (reset) begin
_T_3292 <= 1'h0;
end else begin
_T_3292 <= _T_3305;
end
if (reset) begin
_T_3261 <= 1'h0;
end else begin
_T_3261 <= _T_3274;
end
if (reset) begin
_T_3230 <= 1'h0;
end else begin
_T_3230 <= _T_3243;
end
if (reset) begin
_T_3199 <= 1'h0;
end else begin
_T_3199 <= _T_3212;
end
if (reset) begin
_T_3168 <= 1'h0;
end else begin
_T_3168 <= _T_3181;
end
if (reset) begin
_T_3137 <= 1'h0;
end else begin
_T_3137 <= _T_3150;
end
if (reset) begin
_T_3106 <= 1'h0;
end else begin
_T_3106 <= _T_3119;
end
if (reset) begin
_T_3075 <= 1'h0;
end else begin
_T_3075 <= _T_3088;
end
if (reset) begin
_T_3044 <= 1'h0;
end else begin
_T_3044 <= _T_3057;
end
if (reset) begin
_T_3013 <= 1'h0;
end else begin
_T_3013 <= _T_3026;
end
if (reset) begin
_T_2982 <= 1'h0;
end else begin
_T_2982 <= _T_2995;
end
if (reset) begin
_T_2951 <= 1'h0;
end else begin
_T_2951 <= _T_2964;
end
if (reset) begin
_T_2920 <= 1'h0;
end else begin
_T_2920 <= _T_2933;
end
if (reset) begin
_T_2889 <= 1'h0;
end else begin
_T_2889 <= _T_2902;
end
if (reset) begin
_T_2858 <= 1'h0;
end else begin
_T_2858 <= _T_2871;
end
if (reset) begin
_T_2827 <= 1'h0;
end else begin
_T_2827 <= _T_2840;
end
if (reset) begin
_T_2796 <= 1'h0;
end else begin
_T_2796 <= _T_2809;
end
if (reset) begin
_T_2765 <= 1'h0;
end else begin
_T_2765 <= _T_2778;
end
if (reset) begin
_T_2734 <= 1'h0;
end else begin
_T_2734 <= _T_2747;
end
if (reset) begin
_T_2703 <= 1'h0;
end else begin
_T_2703 <= _T_2716;
end
if (reset) begin
_T_2672 <= 1'h0;
end else begin
_T_2672 <= _T_2685;
end
if (reset) begin
_T_2641 <= 1'h0;
end else begin
_T_2641 <= _T_2654;
end
if (reset) begin
_T_2610 <= 1'h0;
end else begin
_T_2610 <= _T_2623;
end
if (reset) begin
_T_2579 <= 1'h0;
end else begin
_T_2579 <= _T_2592;
end
if (reset) begin
_T_2548 <= 1'h0;
end else begin
_T_2548 <= _T_2561;
end
if (reset) begin
_T_2517 <= 1'h0;
end else begin
_T_2517 <= _T_2530;
end
if (reset) begin
_T_2486 <= 1'h0;
end else begin
_T_2486 <= _T_2499;
end
if (reset) begin
_T_2455 <= 1'h0;
end else begin
_T_2455 <= _T_2468;
end
if (reset) begin
_T_2424 <= 1'h0;
end else begin
_T_2424 <= _T_2437;
end
if (reset) begin
_T_2393 <= 1'h0;
end else begin
_T_2393 <= _T_2406;
end
if (reset) begin
_T_2362 <= 1'h0;
end else begin
_T_2362 <= _T_2375;
end
if (reset) begin
_T_2331 <= 1'h0;
end else begin
_T_2331 <= _T_2344;
end
if (reset) begin
_T_2300 <= 1'h0;
end else begin
_T_2300 <= _T_2313;
end
if (reset) begin
_T_2269 <= 1'h0;
end else begin
_T_2269 <= _T_2282;
end
if (reset) begin
_T_2238 <= 1'h0;
end else begin
_T_2238 <= _T_2251;
end
if (reset) begin
_T_2207 <= 1'h0;
end else begin
_T_2207 <= _T_2220;
end
if (reset) begin
_T_2176 <= 1'h0;
end else begin
_T_2176 <= _T_2189;
end
if (reset) begin
_T_2145 <= 1'h0;
end else begin
_T_2145 <= _T_2158;
end
if (reset) begin
_T_2114 <= 1'h0;
end else begin
_T_2114 <= _T_2127;
end
if (reset) begin
_T_2083 <= 1'h0;
end else begin
_T_2083 <= _T_2096;
end
if (reset) begin
_T_2052 <= 1'h0;
end else begin
_T_2052 <= _T_2065;
end
if (reset) begin
_T_2021 <= 1'h0;
end else begin
_T_2021 <= _T_2034;
end
if (reset) begin
_T_1990 <= 1'h0;
end else begin
_T_1990 <= _T_2003;
end
if (reset) begin
_T_1959 <= 1'h0;
end else begin
_T_1959 <= _T_1972;
end
if (reset) begin
_T_1928 <= 1'h0;
end else begin
_T_1928 <= _T_1941;
end
if (reset) begin
_T_1897 <= 1'h0;
end else begin
_T_1897 <= _T_1910;
end
if (reset) begin
_T_1866 <= 1'h0;
end else begin
_T_1866 <= _T_1879;
end
if (reset) begin
_T_1835 <= 1'h0;
end else begin
_T_1835 <= _T_1848;
end
if (reset) begin
_T_1804 <= 1'h0;
end else begin
_T_1804 <= _T_1817;
end
if (reset) begin
_T_1773 <= 1'h0;
end else begin
_T_1773 <= _T_1786;
end
if (reset) begin
_T_1742 <= 1'h0;
end else begin
_T_1742 <= _T_1755;
end
if (reset) begin
_T_1711 <= 1'h0;
end else begin
_T_1711 <= _T_1724;
end
if (reset) begin
_T_1680 <= 1'h0;
end else begin
_T_1680 <= _T_1693;
end
if (reset) begin
_T_1305 <= 3'h0;
end else begin
if (_T_1295) begin
if (_T_1309) begin
if (_T_1294) begin
_T_1305 <= _T_1300;
end else begin
_T_1305 <= 3'h0;
end
end else begin
_T_1305 <= _T_1308;
end
end
end
if (reset) begin
_T_1363 <= 1'h0;
end else begin
if (_T_1295) begin
_T_1363 <= _T_1365;
end
end
if (reset) begin
_T_1393 <= 1'h0;
end else begin
if (_T_1394) begin
_T_1393 <= _T_1395;
end
end
if (reset) begin
_T_1401 <= 1'h1;
end else begin
if (_T_1394) begin
_T_1401 <= auto_out_r_bits_last;
end
end
if (_T_1401) begin
_T_1405 <= _T_1403;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:125 assert (a_source < UInt(BigInt(1) << sourceBits))\n"); // @[ToAXI4.scala 125:14:freechips.rocketchip.system.LowRiscConfig.fir@40261.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[ToAXI4.scala 125:14:freechips.rocketchip.system.LowRiscConfig.fir@40262.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:126 assert (a_size < UInt(BigInt(1) << sizeBits))\n"); // @[ToAXI4.scala 126:14:freechips.rocketchip.system.LowRiscConfig.fir@40269.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[ToAXI4.scala 126:14:freechips.rocketchip.system.LowRiscConfig.fir@40270.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1699) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40719.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1699) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40720.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1705) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40729.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1705) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40730.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1730) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40761.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1730) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40762.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1736) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40771.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1736) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40772.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1761) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40803.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1761) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40804.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1767) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40813.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1767) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40814.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1792) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40845.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1792) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40846.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1798) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40855.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1798) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40856.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1823) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40887.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1823) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40888.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1829) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40897.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1829) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40898.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1854) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40929.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1854) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40930.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1860) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40939.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1860) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40940.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1885) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40971.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1885) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@40972.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1891) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40981.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1891) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@40982.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1916) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41013.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1916) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41014.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1922) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41023.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1922) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41024.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1947) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41055.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1947) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41056.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1953) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41065.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1953) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41066.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1978) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41097.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1978) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41098.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1984) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41107.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1984) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41108.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2009) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41139.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2009) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41140.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2015) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41149.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2015) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41150.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2040) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41181.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2040) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41182.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2046) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41191.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2046) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41192.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2071) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41223.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2071) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41224.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2077) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41233.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2077) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41234.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2102) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41265.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2102) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41266.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2108) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41275.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2108) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41276.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2133) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41307.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2133) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41308.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2139) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41317.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2139) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41318.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2164) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41349.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2164) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41350.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2170) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41359.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2170) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41360.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2195) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41391.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2195) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41392.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2201) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41401.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2201) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41402.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2226) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41433.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2226) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41434.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2232) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41443.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2232) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41444.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2257) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41475.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2257) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41476.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2263) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41485.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2263) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41486.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2288) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41517.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2288) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41518.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2294) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41527.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2294) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41528.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2319) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41559.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2319) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41560.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2325) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41569.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2325) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41570.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2350) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41601.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2350) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41602.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2356) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41611.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2356) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41612.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2381) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41643.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2381) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41644.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2387) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41653.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2387) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41654.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2412) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41685.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2412) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41686.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2418) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41695.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2418) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41696.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2443) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41727.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2443) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41728.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2449) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41737.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2449) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41738.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2474) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41769.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2474) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41770.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2480) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41779.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2480) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41780.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2505) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41811.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2505) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41812.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2511) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41821.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2511) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41822.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2536) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41853.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2536) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41854.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2542) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41863.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2542) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41864.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2567) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41895.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2567) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41896.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2573) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41905.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2573) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41906.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2598) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41937.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2598) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41938.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2604) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41947.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2604) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41948.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2629) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41979.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2629) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@41980.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2635) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41989.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2635) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@41990.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2660) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42021.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2660) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42022.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2666) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42031.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2666) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42032.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2691) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42063.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2691) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42064.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2697) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42073.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2697) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42074.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2722) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42105.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2722) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42106.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2728) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42115.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2728) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42116.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2753) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42147.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2753) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42148.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2759) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42157.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2759) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42158.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2784) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42189.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2784) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42190.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2790) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42199.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2790) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42200.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2815) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42231.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2815) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42232.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2821) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42241.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2821) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42242.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2846) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42273.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2846) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42274.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2852) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42283.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2852) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42284.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2877) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42315.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2877) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42316.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2883) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42325.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2883) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42326.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2908) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42357.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2908) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42358.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2914) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42367.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2914) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42368.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2939) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42399.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2939) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42400.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2945) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42409.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2945) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42410.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2970) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42441.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2970) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42442.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_2976) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42451.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_2976) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42452.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3001) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42483.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3001) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42484.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3007) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42493.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3007) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42494.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3032) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42525.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3032) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42526.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3038) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42535.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3038) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42536.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3063) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42567.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3063) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42568.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3069) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42577.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3069) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42578.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3094) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42609.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3094) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42610.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3100) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42619.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3100) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42620.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3125) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42651.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3125) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42652.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3131) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42661.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3131) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42662.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3156) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42693.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3156) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42694.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3162) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42703.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3162) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42704.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3187) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42735.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3187) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42736.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3193) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42745.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3193) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42746.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3218) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42777.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3218) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42778.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3224) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42787.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3224) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42788.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3249) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42819.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3249) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42820.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3255) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42829.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3255) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42830.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3280) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42861.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3280) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42862.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3286) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42871.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3286) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42872.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3311) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42903.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3311) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42904.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3317) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42913.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3317) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42914.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3342) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42945.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3342) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42946.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3348) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42955.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3348) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42956.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3373) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42987.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3373) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@42988.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3379) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42997.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3379) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@42998.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3404) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43029.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3404) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43030.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3410) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43039.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3410) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43040.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3435) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43071.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3435) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43072.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3441) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43081.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3441) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43082.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3466) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43113.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3466) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43114.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3472) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43123.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3472) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43124.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3497) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43155.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3497) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43156.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3503) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43165.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3503) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43166.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3528) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43197.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3528) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43198.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3534) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43207.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3534) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43208.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3559) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43239.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3559) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43240.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3565) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43249.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3565) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43250.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3590) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43281.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3590) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43282.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3596) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43291.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3596) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43292.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3621) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43323.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3621) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43324.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3627) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43333.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3627) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43334.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3652) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43365.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3652) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43366.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3658) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43375.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3658) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43376.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3683) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43407.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3683) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43408.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3689) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43417.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3689) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43418.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3714) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43449.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3714) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43450.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3720) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43459.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3720) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43460.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3745) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43491.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3745) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43492.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3751) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43501.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3751) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43502.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3776) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43533.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3776) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43534.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3782) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43543.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3782) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43544.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3807) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43575.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3807) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43576.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3813) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43585.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3813) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43586.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3838) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43617.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3838) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43618.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3844) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43627.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3844) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43628.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3869) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43659.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3869) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43660.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3875) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43669.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3875) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43670.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3900) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43701.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3900) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43702.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3906) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43711.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3906) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43712.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3931) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43743.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3931) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43744.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3937) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43753.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3937) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43754.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3962) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43785.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3962) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43786.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3968) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43795.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3968) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43796.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3993) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43827.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3993) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43828.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_3999) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43837.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_3999) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43838.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4024) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43869.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4024) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43870.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4030) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43879.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4030) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43880.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4055) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43911.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4055) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43912.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4061) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43921.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4061) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43922.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4086) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43953.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4086) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43954.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4092) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43963.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4092) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@43964.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4117) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43995.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4117) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@43996.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4123) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44005.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4123) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44006.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4148) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44037.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4148) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44038.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4154) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44047.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4154) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44048.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4179) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44079.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4179) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44080.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4185) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44089.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4185) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44090.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4210) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44121.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4210) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44122.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4216) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44131.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4216) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44132.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4241) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44163.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4241) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44164.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4247) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44173.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4247) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44174.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4272) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44205.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4272) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44206.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4278) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44215.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4278) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44216.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4303) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44247.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4303) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44248.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4309) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44257.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4309) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44258.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4334) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44289.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4334) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44290.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4340) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44299.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4340) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44300.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4365) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44331.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4365) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44332.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4371) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44341.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4371) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44342.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4396) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44373.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4396) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44374.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4402) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44383.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4402) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44384.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4427) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44415.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4427) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44416.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4433) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44425.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4433) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44426.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4458) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44457.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4458) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44458.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4464) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44467.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4464) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44468.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4489) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44499.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4489) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44500.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4495) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44509.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4495) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44510.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4520) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44541.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4520) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44542.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4526) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44551.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4526) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44552.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4551) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44583.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4551) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44584.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4557) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44593.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4557) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44594.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4582) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44625.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4582) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44626.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4588) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44635.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4588) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44636.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4613) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44667.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4613) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44668.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4619) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44677.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4619) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44678.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4644) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44709.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4644) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44710.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4650) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44719.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4650) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44720.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4675) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44751.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4675) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44752.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4681) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44761.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4681) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44762.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4706) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44793.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4706) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44794.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4712) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44803.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4712) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44804.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4737) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44835.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4737) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44836.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4743) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44845.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4743) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44846.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4768) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44877.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4768) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44878.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4774) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44887.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4774) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44888.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4799) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44919.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4799) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44920.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4805) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44929.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4805) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44930.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4830) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44961.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4830) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@44962.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4836) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44971.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4836) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@44972.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4861) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45003.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4861) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45004.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4867) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45013.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4867) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45014.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4892) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45045.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4892) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45046.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4898) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45055.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4898) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45056.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4923) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45087.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4923) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45088.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4929) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45097.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4929) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45098.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4954) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45129.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4954) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45130.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4960) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45139.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4960) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45140.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4985) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45171.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4985) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45172.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_4991) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45181.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_4991) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45182.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5016) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45213.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5016) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45214.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5022) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45223.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5022) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45224.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5047) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45255.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5047) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45256.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5053) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45265.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5053) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45266.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5078) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45297.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5078) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45298.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5084) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45307.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5084) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45308.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5109) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45339.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5109) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45340.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5115) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45349.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5115) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45350.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5140) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45381.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5140) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45382.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5146) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45391.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5146) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45392.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5171) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45423.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5171) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45424.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5177) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45433.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5177) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45434.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5202) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45465.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5202) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45466.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5208) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45475.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5208) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45476.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5233) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45507.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5233) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45508.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5239) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45517.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5239) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45518.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5264) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45549.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5264) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45550.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5270) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45559.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5270) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45560.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5295) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45591.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5295) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45592.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5301) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45601.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5301) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45602.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5326) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45633.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5326) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45634.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5332) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45643.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5332) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45644.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5357) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45675.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5357) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45676.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5363) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45685.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5363) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45686.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5388) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45717.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5388) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45718.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5394) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45727.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5394) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45728.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5419) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45759.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5419) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45760.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5425) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45769.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5425) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45770.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5450) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45801.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5450) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45802.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5456) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45811.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5456) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45812.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5481) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45843.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5481) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45844.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5487) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45853.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5487) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45854.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5512) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45885.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5512) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45886.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5518) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45895.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5518) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45896.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5543) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45927.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5543) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45928.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5549) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45937.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5549) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45938.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5574) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45969.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5574) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@45970.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5580) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45979.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5580) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@45980.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5605) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46011.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5605) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46012.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5611) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46021.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5611) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46022.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5636) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:233 assert (!dec || count =/= UInt(0)) // underflow\n"); // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46053.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5636) begin
$fatal; // @[ToAXI4.scala 233:16:freechips.rocketchip.system.LowRiscConfig.fir@46054.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_5642) begin
$fwrite(32'h80000002,"Assertion failed\n at ToAXI4.scala:234 assert (!inc || count =/= UInt(maxCount)) // overflow\n"); // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46063.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_5642) begin
$fatal; // @[ToAXI4.scala 234:16:freechips.rocketchip.system.LowRiscConfig.fir@46064.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_16( // @[:freechips.rocketchip.system.LowRiscConfig.fir@46085.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46086.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46087.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [6:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input [6:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@46088.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@47257.4]
wire [12:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@46115.6]
wire [5:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@46116.6]
wire [5:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@46117.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@46118.6]
wire [31:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@46118.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@46119.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@46121.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@46122.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@46123.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@46124.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@46125.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@46126.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@46127.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@46128.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46130.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46131.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46133.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46134.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@46135.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@46136.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@46137.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46138.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46139.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46140.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46141.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46142.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46143.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46144.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46145.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46146.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46147.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46148.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46149.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@46150.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@46151.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@46152.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46153.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46154.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46155.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46156.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46157.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46158.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46159.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46160.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46161.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46162.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46163.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46164.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46165.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46166.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46167.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46168.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46169.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46170.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46171.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46172.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46173.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46174.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46175.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46176.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@46183.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@46206.6]
wire [31:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@46209.8]
wire [32:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@46210.8]
wire [32:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@46211.8]
wire [32:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@46212.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@46213.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@46218.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@46239.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@46240.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@46246.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@46247.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@46252.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@46254.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@46255.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@46260.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@46261.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@46263.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@46264.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@46269.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@46271.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@46272.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@46278.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@46332.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@46334.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@46335.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@46358.6]
wire _T_205; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@46361.8]
wire _T_213; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@46369.8]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46372.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46373.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@46392.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@46394.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@46395.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@46400.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@46402.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@46403.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@46417.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@46468.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@46510.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@46511.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@46512.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@46514.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@46515.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@46521.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@46552.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@46554.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@46555.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@46569.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@46600.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@46602.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@46603.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@46617.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@46667.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@46669.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@46670.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@46687.6]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@46696.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46698.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46699.8]
wire _T_406; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@46712.8]
wire _T_408; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@46714.8]
wire _T_409; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@46715.8]
wire _T_410; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@46720.8]
wire _T_412; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@46722.8]
wire _T_413; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@46723.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@46729.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@46787.6]
wire _T_462; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@46828.8]
wire _T_464; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@46830.8]
wire _T_465; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@46831.8]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@46846.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@46881.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@46917.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@46977.4]
wire [2:0] _T_540; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@46982.4]
wire _T_541; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@46983.4]
wire _T_542; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@46984.4]
reg [2:0] _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@46986.4]
reg [31:0] _RAND_0;
wire [3:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@46987.4]
wire [3:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@46988.4]
wire [2:0] _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@46989.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@46990.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@47001.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@47002.4]
reg [31:0] _RAND_2;
reg [2:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@47003.4]
reg [31:0] _RAND_3;
reg [6:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@47004.4]
reg [31:0] _RAND_4;
reg [31:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@47005.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@47006.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@47007.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@47009.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@47011.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@47012.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@47017.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@47019.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@47020.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@47025.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@47027.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@47028.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@47033.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@47035.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@47036.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@47041.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@47043.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@47044.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@47051.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@47059.4]
wire [12:0] _T_593; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@47061.4]
wire [5:0] _T_594; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@47062.4]
wire [5:0] _T_595; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@47063.4]
wire [2:0] _T_596; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@47064.4]
wire _T_597; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@47065.4]
reg [2:0] _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@47067.4]
reg [31:0] _RAND_6;
wire [3:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47068.4]
wire [3:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47069.4]
wire [2:0] _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47070.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@47071.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@47082.4]
reg [31:0] _RAND_7;
reg [2:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@47084.4]
reg [31:0] _RAND_8;
reg [6:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@47085.4]
reg [31:0] _RAND_9;
reg _T_623; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@47087.4]
reg [31:0] _RAND_10;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@47088.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@47089.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@47091.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@47093.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@47094.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@47107.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@47109.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@47110.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@47115.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@47117.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@47118.6]
wire _T_646; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@47131.6]
wire _T_648; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@47133.6]
wire _T_649; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@47134.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@47141.4]
reg [127:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@47150.4]
reg [127:0] _RAND_11;
reg [2:0] _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@47160.4]
reg [31:0] _RAND_12;
wire [3:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47161.4]
wire [3:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47162.4]
wire [2:0] _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47163.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@47164.4]
reg [2:0] _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@47183.4]
reg [31:0] _RAND_13;
wire [3:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47184.4]
wire [3:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47185.4]
wire [2:0] _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47186.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@47187.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@47202.4]
wire [127:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@47205.6]
wire [127:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@47207.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@47208.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@47209.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@47211.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@47212.6]
wire [127:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@47204.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@47223.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@47225.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@47226.4]
wire [127:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@47228.6]
wire [127:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@47230.6]
wire [127:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@47231.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@47232.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@47234.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@47235.6]
wire [127:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@47227.4]
wire _T_724; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@47241.4]
wire _T_725; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@47242.4]
wire _T_726; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@47243.4]
wire _T_727; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@47244.4]
wire _T_729; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@47246.4]
wire _T_730; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@47247.4]
wire [127:0] _T_731; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@47252.4]
wire [127:0] _T_732; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@47253.4]
wire [127:0] _T_733; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@47254.4]
reg [31:0] _T_735; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@47256.4]
reg [31:0] _RAND_14;
wire _T_736; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@47259.4]
wire _T_737; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@47260.4]
wire _T_738; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@47261.4]
wire _T_739; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@47262.4]
wire _T_740; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@47263.4]
wire _T_741; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@47264.4]
wire _T_743; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@47266.4]
wire _T_744; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@47267.4]
wire [31:0] _T_746; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@47273.4]
wire _T_749; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@47277.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@46220.10]
wire _GEN_33; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@46292.10]
wire _GEN_49; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46375.10]
wire _GEN_59; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@46434.10]
wire _GEN_67; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@46485.10]
wire _GEN_75; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@46535.10]
wire _GEN_83; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@46583.10]
wire _GEN_91; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@46631.10]
wire _GEN_99; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46701.10]
wire _GEN_105; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@46742.10]
wire _GEN_111; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@46800.10]
wire _GEN_117; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@46868.10]
wire _GEN_119; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@46904.10]
wire _GEN_121; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@46939.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@47257.4]
.out(plusarg_reader_out)
);
assign _T_36 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@46115.6]
assign _T_37 = _T_36[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@46116.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@46117.6]
assign _GEN_18 = {{26'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@46118.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@46118.6]
assign _T_40 = _T_39 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@46119.6]
assign _T_42 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@46121.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@46122.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@46123.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@46124.6]
assign _T_46 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@46125.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@46126.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@46127.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@46128.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46130.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46131.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46133.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46134.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@46135.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@46136.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@46137.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46138.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46139.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46140.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46141.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46142.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46143.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46144.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46145.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46146.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46147.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46148.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46149.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@46150.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@46151.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@46152.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46153.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46154.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46155.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46156.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46157.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46158.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46159.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46160.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46161.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46162.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46163.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46164.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46165.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46166.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46167.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46168.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46169.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46170.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46171.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46172.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46173.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@46174.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@46175.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@46176.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@46183.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@46206.6]
assign _T_125 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@46209.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@46210.8]
assign _T_127 = $signed(_T_126) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@46211.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@46212.8]
assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@46213.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@46218.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@46239.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@46240.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@46246.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@46247.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@46252.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@46254.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@46255.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@46260.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@46261.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@46263.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@46264.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@46269.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@46271.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@46272.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@46278.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@46332.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@46334.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@46335.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@46358.6]
assign _T_205 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@46361.8]
assign _T_213 = _T_205 & _T_129; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@46369.8]
assign _T_216 = _T_213 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46372.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46373.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@46392.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@46394.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@46395.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@46400.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@46402.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@46403.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@46417.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@46468.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@46510.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@46511.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@46512.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@46514.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@46515.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@46521.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@46552.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@46554.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@46555.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@46569.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@46600.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@46602.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@46603.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@46617.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@46667.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@46669.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@46670.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@46687.6]
assign _T_398 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@46696.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46698.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46699.8]
assign _T_406 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@46712.8]
assign _T_408 = _T_406 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@46714.8]
assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@46715.8]
assign _T_410 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@46720.8]
assign _T_412 = _T_410 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@46722.8]
assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@46723.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@46729.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@46787.6]
assign _T_462 = _T_410 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@46828.8]
assign _T_464 = _T_462 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@46830.8]
assign _T_465 = _T_464 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@46831.8]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@46846.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@46881.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@46917.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@46977.4]
assign _T_540 = _T_38[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@46982.4]
assign _T_541 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@46983.4]
assign _T_542 = _T_541 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@46984.4]
assign _T_546 = _T_545 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@46987.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@46988.4]
assign _T_548 = _T_547[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@46989.4]
assign _T_549 = _T_545 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@46990.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@47006.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@47007.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@47009.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@47011.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@47012.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@47017.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@47019.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@47020.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@47025.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@47027.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@47028.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@47033.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@47035.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@47036.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@47041.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@47043.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@47044.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@47051.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@47059.4]
assign _T_593 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@47061.4]
assign _T_594 = _T_593[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@47062.4]
assign _T_595 = ~ _T_594; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@47063.4]
assign _T_596 = _T_595[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@47064.4]
assign _T_597 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@47065.4]
assign _T_601 = _T_600 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47068.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47069.4]
assign _T_603 = _T_602[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47070.4]
assign _T_604 = _T_600 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@47071.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@47088.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@47089.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@47091.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@47093.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@47094.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@47107.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@47109.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@47110.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@47115.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@47117.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@47118.6]
assign _T_646 = io_in_d_bits_denied == _T_623; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@47131.6]
assign _T_648 = _T_646 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@47133.6]
assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@47134.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@47141.4]
assign _T_665 = _T_664 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47161.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47162.4]
assign _T_667 = _T_666[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47163.4]
assign _T_668 = _T_664 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@47164.4]
assign _T_686 = _T_685 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47184.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47185.4]
assign _T_688 = _T_687[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@47186.4]
assign _T_689 = _T_685 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@47187.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@47202.4]
assign _T_702 = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@47205.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@47207.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@47208.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@47209.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@47211.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@47212.6]
assign _GEN_15 = _T_700 ? _T_702 : 128'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@47204.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@47223.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@47225.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@47226.4]
assign _T_717 = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@47228.6]
assign _T_718 = _GEN_15 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@47230.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@47231.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@47232.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@47234.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@47235.6]
assign _GEN_16 = _T_716 ? _T_717 : 128'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@47227.4]
assign _T_724 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@47241.4]
assign _T_725 = _GEN_15 != 128'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@47242.4]
assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@47243.4]
assign _T_727 = _T_724 | _T_726; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@47244.4]
assign _T_729 = _T_727 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@47246.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@47247.4]
assign _T_731 = _T_653 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@47252.4]
assign _T_732 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@47253.4]
assign _T_733 = _T_731 & _T_732; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@47254.4]
assign _T_736 = _T_653 != 128'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@47259.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@47260.4]
assign _T_738 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@47261.4]
assign _T_739 = _T_737 | _T_738; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@47262.4]
assign _T_740 = _T_735 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@47263.4]
assign _T_741 = _T_739 | _T_740; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@47264.4]
assign _T_743 = _T_741 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@47266.4]
assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@47267.4]
assign _T_746 = _T_735 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@47273.4]
assign _T_749 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@47277.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@46220.10]
assign _GEN_33 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@46292.10]
assign _GEN_49 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46375.10]
assign _GEN_59 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@46434.10]
assign _GEN_67 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@46485.10]
assign _GEN_75 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@46535.10]
assign _GEN_83 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@46583.10]
assign _GEN_91 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@46631.10]
assign _GEN_99 = io_in_d_valid & _T_394; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46701.10]
assign _GEN_105 = io_in_d_valid & _T_414; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@46742.10]
assign _GEN_111 = io_in_d_valid & _T_442; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@46800.10]
assign _GEN_117 = io_in_d_valid & _T_471; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@46868.10]
assign _GEN_119 = io_in_d_valid & _T_488; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@46904.10]
assign _GEN_121 = io_in_d_valid & _T_506; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@46939.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_623 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {4{`RANDOM}};
_T_653 = _RAND_11[127:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_664 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_685 = _RAND_13[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_735 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
if (_T_542) begin
_T_545 <= _T_540;
end else begin
_T_545 <= 3'h0;
end
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
if (_T_597) begin
_T_600 <= _T_596;
end else begin
_T_600 <= 3'h0;
end
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (_T_651) begin
_T_623 <= io_in_d_bits_denied;
end
if (reset) begin
_T_653 <= 128'h0;
end else begin
_T_653 <= _T_733;
end
if (reset) begin
_T_664 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
if (_T_542) begin
_T_664 <= _T_540;
end else begin
_T_664 <= 3'h0;
end
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
if (_T_597) begin
_T_685 <= _T_596;
end else begin
_T_685 <= 3'h0;
end
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_735 <= 32'h0;
end else begin
if (_T_749) begin
_T_735 <= 32'h0;
end else begin
_T_735 <= _T_746;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at MemoryBus.scala:65:66)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@46100.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@46101.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@46203.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@46204.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@46220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@46221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MemoryBus.scala:65:66)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@46227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@46228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@46234.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@46235.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MemoryBus.scala:65:66)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@46242.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@46243.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@46249.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@46250.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@46257.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@46258.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@46266.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@46267.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@46274.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@46275.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@46292.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@46293.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MemoryBus.scala:65:66)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@46299.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@46300.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@46306.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@46307.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MemoryBus.scala:65:66)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@46314.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@46315.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@46321.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@46322.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@46329.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@46330.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MemoryBus.scala:65:66)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@46337.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@46338.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@46346.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@46347.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@46354.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@46355.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46375.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@46376.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@46382.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@46383.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@46389.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@46390.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@46397.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@46398.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@46405.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@46406.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@46413.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@46414.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@46434.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@46435.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@46441.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@46442.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@46448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@46449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@46456.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@46457.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@46464.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@46465.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@46485.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@46486.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@46492.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@46493.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@46499.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@46500.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@46507.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@46508.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@46517.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@46518.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@46535.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@46536.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@46542.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@46543.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@46549.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@46550.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@46557.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@46558.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@46565.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@46566.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@46583.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@46584.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@46590.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@46591.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@46597.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@46598.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@46605.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@46606.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@46613.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@46614.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at MemoryBus.scala:65:66)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@46631.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@46632.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@46638.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@46639.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at MemoryBus.scala:65:66)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@46645.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@46646.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at MemoryBus.scala:65:66)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@46653.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@46654.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@46661.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@46662.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at MemoryBus.scala:65:66)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@46672.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@46673.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@46693.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@46694.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MemoryBus.scala:65:66)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46701.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@46702.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@46709.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@46710.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@46717.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@46718.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at MemoryBus.scala:65:66)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@46725.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@46726.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@46735.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@46736.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@46742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@46743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at MemoryBus.scala:65:66)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@46750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@46751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@46758.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@46759.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@46766.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@46767.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@46774.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@46775.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at MemoryBus.scala:65:66)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@46783.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@46784.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@46793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@46794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@46800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@46801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at MemoryBus.scala:65:66)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@46808.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@46809.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@46816.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@46817.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@46824.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@46825.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@46833.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@46834.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at MemoryBus.scala:65:66)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@46842.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@46843.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@46852.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@46853.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@46860.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@46861.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@46868.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@46869.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at MemoryBus.scala:65:66)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@46877.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@46878.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@46887.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@46888.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@46895.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@46896.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@46904.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@46905.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at MemoryBus.scala:65:66)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@46913.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@46914.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@46923.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@46924.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at MemoryBus.scala:65:66)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@46931.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@46932.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at MemoryBus.scala:65:66)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@46939.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@46940.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at MemoryBus.scala:65:66)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@46948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@46949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at MemoryBus.scala:65:66)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@46958.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@46959.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at MemoryBus.scala:65:66)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@46966.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@46967.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at MemoryBus.scala:65:66)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@46974.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@46975.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@47014.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@47015.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@47022.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@47023.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@47030.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@47031.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@47038.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@47039.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@47046.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@47047.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@47096.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@47097.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@47104.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@47105.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@47112.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@47113.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@47120.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@47121.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@47128.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@47129.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_649) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at MemoryBus.scala:65:66)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@47136.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_649) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@47137.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at MemoryBus.scala:65:66)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@47214.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@47215.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MemoryBus.scala:65:66)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@47237.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@47238.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_730) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at MemoryBus.scala:65:66)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@47249.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_730) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@47250.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_744) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at MemoryBus.scala:65:66)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@47269.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_744) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@47270.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLBuffer_6( // @[:freechips.rocketchip.system.LowRiscConfig.fir@47282.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47283.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47284.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [6:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [6:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [6:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [6:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@47285.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [6:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire [6:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
TLMonitor_16 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@47292.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@47332.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@47331.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@47294.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@47295.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@47328.4]
endmodule
module TLMonitor_17( // @[:freechips.rocketchip.system.LowRiscConfig.fir@47349.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47350.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47351.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [6:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input [6:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@47352.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@48521.4]
wire [12:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@47379.6]
wire [5:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@47380.6]
wire [5:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@47381.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@47382.6]
wire [31:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@47382.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@47383.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@47385.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@47386.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@47387.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@47388.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@47389.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@47390.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@47391.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@47392.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47394.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47395.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47397.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47398.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@47399.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@47400.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@47401.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47402.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47403.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47404.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47405.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47406.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47407.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47408.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47409.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47410.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47411.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47412.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47413.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@47414.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@47415.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@47416.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47417.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47418.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47419.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47420.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47421.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47422.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47423.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47424.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47425.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47426.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47427.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47428.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47429.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47430.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47431.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47432.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47433.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47434.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47435.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47436.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47437.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47438.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47439.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47440.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@47447.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@47470.6]
wire [31:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@47473.8]
wire [32:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@47474.8]
wire [32:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@47475.8]
wire [32:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@47476.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@47477.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@47482.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@47503.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@47504.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@47510.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@47511.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@47516.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@47518.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@47519.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@47524.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@47525.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@47527.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@47528.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@47533.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@47535.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@47536.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@47542.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@47596.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@47598.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@47599.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@47622.6]
wire _T_205; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@47625.8]
wire _T_213; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@47633.8]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47636.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47637.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@47656.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@47658.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@47659.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@47664.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@47666.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@47667.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@47681.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@47732.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@47774.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@47775.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@47776.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@47778.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@47779.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@47785.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@47816.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@47818.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@47819.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@47833.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@47864.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@47866.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@47867.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@47881.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@47931.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@47933.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@47934.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@47951.6]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@47960.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47962.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47963.8]
wire _T_406; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@47976.8]
wire _T_408; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@47978.8]
wire _T_409; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@47979.8]
wire _T_410; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@47984.8]
wire _T_412; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@47986.8]
wire _T_413; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@47987.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@47993.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@48051.6]
wire _T_462; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@48092.8]
wire _T_464; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@48094.8]
wire _T_465; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@48095.8]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@48110.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@48145.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@48181.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@48241.4]
wire [2:0] _T_540; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@48246.4]
wire _T_541; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@48247.4]
wire _T_542; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@48248.4]
reg [2:0] _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@48250.4]
reg [31:0] _RAND_0;
wire [3:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48251.4]
wire [3:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48252.4]
wire [2:0] _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48253.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48254.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@48265.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@48266.4]
reg [31:0] _RAND_2;
reg [2:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@48267.4]
reg [31:0] _RAND_3;
reg [6:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@48268.4]
reg [31:0] _RAND_4;
reg [31:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@48269.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@48270.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@48271.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@48273.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@48275.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@48276.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@48281.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@48283.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@48284.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@48289.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@48291.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@48292.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@48297.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@48299.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@48300.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@48305.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@48307.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@48308.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@48315.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@48323.4]
wire [12:0] _T_593; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@48325.4]
wire [5:0] _T_594; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@48326.4]
wire [5:0] _T_595; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@48327.4]
wire [2:0] _T_596; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@48328.4]
wire _T_597; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@48329.4]
reg [2:0] _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@48331.4]
reg [31:0] _RAND_6;
wire [3:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48332.4]
wire [3:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48333.4]
wire [2:0] _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48334.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48335.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@48346.4]
reg [31:0] _RAND_7;
reg [2:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@48348.4]
reg [31:0] _RAND_8;
reg [6:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@48349.4]
reg [31:0] _RAND_9;
reg _T_623; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@48351.4]
reg [31:0] _RAND_10;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@48352.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@48353.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@48355.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@48357.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@48358.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@48371.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@48373.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@48374.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@48379.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@48381.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@48382.6]
wire _T_646; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@48395.6]
wire _T_648; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@48397.6]
wire _T_649; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@48398.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@48405.4]
reg [127:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@48414.4]
reg [127:0] _RAND_11;
reg [2:0] _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@48424.4]
reg [31:0] _RAND_12;
wire [3:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48425.4]
wire [3:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48426.4]
wire [2:0] _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48427.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48428.4]
reg [2:0] _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@48447.4]
reg [31:0] _RAND_13;
wire [3:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48448.4]
wire [3:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48449.4]
wire [2:0] _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48450.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48451.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@48466.4]
wire [127:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@48469.6]
wire [127:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@48471.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@48472.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@48473.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@48475.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@48476.6]
wire [127:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@48468.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@48487.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@48489.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@48490.4]
wire [127:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@48492.6]
wire [127:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@48494.6]
wire [127:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@48495.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@48496.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@48498.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@48499.6]
wire [127:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@48491.4]
wire _T_724; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@48505.4]
wire _T_725; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@48506.4]
wire _T_726; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@48507.4]
wire _T_727; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@48508.4]
wire _T_729; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@48510.4]
wire _T_730; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@48511.4]
wire [127:0] _T_731; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@48516.4]
wire [127:0] _T_732; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@48517.4]
wire [127:0] _T_733; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@48518.4]
reg [31:0] _T_735; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@48520.4]
reg [31:0] _RAND_14;
wire _T_736; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@48523.4]
wire _T_737; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@48524.4]
wire _T_738; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@48525.4]
wire _T_739; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@48526.4]
wire _T_740; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@48527.4]
wire _T_741; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@48528.4]
wire _T_743; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@48530.4]
wire _T_744; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@48531.4]
wire [31:0] _T_746; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@48537.4]
wire _T_749; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@48541.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@47484.10]
wire _GEN_33; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@47556.10]
wire _GEN_49; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47639.10]
wire _GEN_59; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@47698.10]
wire _GEN_67; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@47749.10]
wire _GEN_75; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@47799.10]
wire _GEN_83; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@47847.10]
wire _GEN_91; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@47895.10]
wire _GEN_99; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47965.10]
wire _GEN_105; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@48006.10]
wire _GEN_111; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@48064.10]
wire _GEN_117; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@48132.10]
wire _GEN_119; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@48168.10]
wire _GEN_121; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@48203.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@48521.4]
.out(plusarg_reader_out)
);
assign _T_36 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@47379.6]
assign _T_37 = _T_36[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@47380.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@47381.6]
assign _GEN_18 = {{26'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@47382.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@47382.6]
assign _T_40 = _T_39 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@47383.6]
assign _T_42 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@47385.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@47386.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@47387.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@47388.6]
assign _T_46 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@47389.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@47390.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@47391.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@47392.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47394.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47395.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47397.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47398.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@47399.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@47400.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@47401.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47402.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47403.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47404.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47405.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47406.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47407.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47408.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47409.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47410.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47411.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47412.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47413.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@47414.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@47415.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@47416.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47417.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47418.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47419.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47420.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47421.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47422.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47423.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47424.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47425.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47426.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47427.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47428.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47429.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47430.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47431.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47432.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47433.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47434.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47435.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47436.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47437.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@47438.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@47439.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@47440.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@47447.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@47470.6]
assign _T_125 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@47473.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@47474.8]
assign _T_127 = $signed(_T_126) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@47475.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@47476.8]
assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@47477.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@47482.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@47503.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@47504.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@47510.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@47511.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@47516.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@47518.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@47519.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@47524.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@47525.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@47527.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@47528.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@47533.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@47535.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@47536.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@47542.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@47596.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@47598.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@47599.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@47622.6]
assign _T_205 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@47625.8]
assign _T_213 = _T_205 & _T_129; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@47633.8]
assign _T_216 = _T_213 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47636.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47637.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@47656.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@47658.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@47659.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@47664.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@47666.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@47667.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@47681.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@47732.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@47774.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@47775.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@47776.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@47778.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@47779.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@47785.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@47816.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@47818.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@47819.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@47833.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@47864.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@47866.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@47867.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@47881.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@47931.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@47933.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@47934.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@47951.6]
assign _T_398 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@47960.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47962.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47963.8]
assign _T_406 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@47976.8]
assign _T_408 = _T_406 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@47978.8]
assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@47979.8]
assign _T_410 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@47984.8]
assign _T_412 = _T_410 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@47986.8]
assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@47987.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@47993.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@48051.6]
assign _T_462 = _T_410 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@48092.8]
assign _T_464 = _T_462 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@48094.8]
assign _T_465 = _T_464 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@48095.8]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@48110.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@48145.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@48181.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@48241.4]
assign _T_540 = _T_38[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@48246.4]
assign _T_541 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@48247.4]
assign _T_542 = _T_541 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@48248.4]
assign _T_546 = _T_545 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48251.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48252.4]
assign _T_548 = _T_547[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48253.4]
assign _T_549 = _T_545 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48254.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@48270.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@48271.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@48273.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@48275.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@48276.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@48281.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@48283.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@48284.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@48289.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@48291.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@48292.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@48297.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@48299.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@48300.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@48305.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@48307.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@48308.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@48315.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@48323.4]
assign _T_593 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@48325.4]
assign _T_594 = _T_593[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@48326.4]
assign _T_595 = ~ _T_594; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@48327.4]
assign _T_596 = _T_595[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@48328.4]
assign _T_597 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@48329.4]
assign _T_601 = _T_600 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48332.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48333.4]
assign _T_603 = _T_602[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48334.4]
assign _T_604 = _T_600 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48335.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@48352.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@48353.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@48355.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@48357.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@48358.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@48371.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@48373.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@48374.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@48379.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@48381.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@48382.6]
assign _T_646 = io_in_d_bits_denied == _T_623; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@48395.6]
assign _T_648 = _T_646 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@48397.6]
assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@48398.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@48405.4]
assign _T_665 = _T_664 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48425.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48426.4]
assign _T_667 = _T_666[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48427.4]
assign _T_668 = _T_664 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48428.4]
assign _T_686 = _T_685 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48448.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48449.4]
assign _T_688 = _T_687[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@48450.4]
assign _T_689 = _T_685 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@48451.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@48466.4]
assign _T_702 = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@48469.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@48471.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@48472.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@48473.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@48475.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@48476.6]
assign _GEN_15 = _T_700 ? _T_702 : 128'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@48468.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@48487.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@48489.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@48490.4]
assign _T_717 = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@48492.6]
assign _T_718 = _GEN_15 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@48494.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@48495.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@48496.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@48498.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@48499.6]
assign _GEN_16 = _T_716 ? _T_717 : 128'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@48491.4]
assign _T_724 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@48505.4]
assign _T_725 = _GEN_15 != 128'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@48506.4]
assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@48507.4]
assign _T_727 = _T_724 | _T_726; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@48508.4]
assign _T_729 = _T_727 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@48510.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@48511.4]
assign _T_731 = _T_653 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@48516.4]
assign _T_732 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@48517.4]
assign _T_733 = _T_731 & _T_732; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@48518.4]
assign _T_736 = _T_653 != 128'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@48523.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@48524.4]
assign _T_738 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@48525.4]
assign _T_739 = _T_737 | _T_738; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@48526.4]
assign _T_740 = _T_735 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@48527.4]
assign _T_741 = _T_739 | _T_740; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@48528.4]
assign _T_743 = _T_741 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@48530.4]
assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@48531.4]
assign _T_746 = _T_735 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@48537.4]
assign _T_749 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@48541.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@47484.10]
assign _GEN_33 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@47556.10]
assign _GEN_49 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47639.10]
assign _GEN_59 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@47698.10]
assign _GEN_67 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@47749.10]
assign _GEN_75 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@47799.10]
assign _GEN_83 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@47847.10]
assign _GEN_91 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@47895.10]
assign _GEN_99 = io_in_d_valid & _T_394; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47965.10]
assign _GEN_105 = io_in_d_valid & _T_414; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@48006.10]
assign _GEN_111 = io_in_d_valid & _T_442; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@48064.10]
assign _GEN_117 = io_in_d_valid & _T_471; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@48132.10]
assign _GEN_119 = io_in_d_valid & _T_488; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@48168.10]
assign _GEN_121 = io_in_d_valid & _T_506; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@48203.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_623 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {4{`RANDOM}};
_T_653 = _RAND_11[127:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_664 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_685 = _RAND_13[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_735 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
if (_T_542) begin
_T_545 <= _T_540;
end else begin
_T_545 <= 3'h0;
end
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
if (_T_597) begin
_T_600 <= _T_596;
end else begin
_T_600 <= 3'h0;
end
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (_T_651) begin
_T_623 <= io_in_d_bits_denied;
end
if (reset) begin
_T_653 <= 128'h0;
end else begin
_T_653 <= _T_733;
end
if (reset) begin
_T_664 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
if (_T_542) begin
_T_664 <= _T_540;
end else begin
_T_664 <= 3'h0;
end
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
if (_T_597) begin
_T_685 <= _T_596;
end else begin
_T_685 <= 3'h0;
end
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_735 <= 32'h0;
end else begin
if (_T_749) begin
_T_735 <= 32'h0;
end else begin
_T_735 <= _T_746;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at MemoryBus.scala:57:50)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@47364.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@47365.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@47467.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@47468.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@47484.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@47485.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at MemoryBus.scala:57:50)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@47491.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@47492.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@47498.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@47499.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at MemoryBus.scala:57:50)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@47506.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@47507.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@47513.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@47514.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@47521.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@47522.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@47530.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@47531.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@47538.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@47539.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@47556.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@47557.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at MemoryBus.scala:57:50)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@47563.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@47564.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@47570.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@47571.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at MemoryBus.scala:57:50)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@47578.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@47579.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@47585.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@47586.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@47593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@47594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at MemoryBus.scala:57:50)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@47601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@47602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@47610.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@47611.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@47618.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@47619.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47639.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@47640.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@47646.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@47647.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@47653.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@47654.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@47661.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@47662.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@47669.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@47670.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@47677.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@47678.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@47698.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@47699.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@47705.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@47706.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@47712.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@47713.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@47720.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@47721.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@47728.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@47729.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@47749.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@47750.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@47756.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@47757.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@47763.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@47764.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@47771.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@47772.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@47781.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@47782.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@47799.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@47800.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@47806.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@47807.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@47813.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@47814.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@47821.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@47822.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@47829.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@47830.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@47847.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@47848.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@47854.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@47855.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@47861.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@47862.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@47869.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@47870.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@47877.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@47878.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at MemoryBus.scala:57:50)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@47895.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@47896.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@47902.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@47903.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at MemoryBus.scala:57:50)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@47909.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@47910.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at MemoryBus.scala:57:50)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@47917.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@47918.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@47925.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@47926.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at MemoryBus.scala:57:50)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@47936.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@47937.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@47957.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@47958.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at MemoryBus.scala:57:50)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47965.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@47966.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@47973.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@47974.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@47981.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@47982.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at MemoryBus.scala:57:50)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@47989.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@47990.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@47999.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@48000.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@48006.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@48007.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at MemoryBus.scala:57:50)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@48014.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@48015.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@48022.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@48023.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@48030.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@48031.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@48038.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@48039.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at MemoryBus.scala:57:50)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@48047.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@48048.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@48057.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@48058.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@48064.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@48065.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at MemoryBus.scala:57:50)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@48072.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@48073.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@48080.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@48081.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@48088.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@48089.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@48097.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@48098.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at MemoryBus.scala:57:50)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@48106.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@48107.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@48116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@48117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@48124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@48125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@48132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@48133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at MemoryBus.scala:57:50)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@48141.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@48142.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@48151.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@48152.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@48159.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@48160.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@48168.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@48169.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at MemoryBus.scala:57:50)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@48177.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@48178.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@48187.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@48188.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at MemoryBus.scala:57:50)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@48195.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@48196.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at MemoryBus.scala:57:50)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@48203.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@48204.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at MemoryBus.scala:57:50)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@48212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@48213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at MemoryBus.scala:57:50)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@48222.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@48223.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at MemoryBus.scala:57:50)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@48230.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@48231.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at MemoryBus.scala:57:50)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@48238.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@48239.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@48278.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@48279.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@48286.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@48287.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@48294.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@48295.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@48302.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@48303.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@48310.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@48311.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@48360.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@48361.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@48368.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@48369.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@48376.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@48377.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@48384.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@48385.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@48392.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@48393.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_649) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at MemoryBus.scala:57:50)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@48400.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_649) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@48401.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at MemoryBus.scala:57:50)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@48478.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@48479.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at MemoryBus.scala:57:50)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@48501.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@48502.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_730) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at MemoryBus.scala:57:50)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@48513.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_730) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@48514.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_744) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at MemoryBus.scala:57:50)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@48533.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_744) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@48534.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module ProbePicker( // @[:freechips.rocketchip.system.LowRiscConfig.fir@48546.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48547.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48548.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [6:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [6:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [6:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [6:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@48549.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [6:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire [6:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
TLMonitor_17 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@48556.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48596.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48595.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48558.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48559.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@48592.4]
endmodule
module SimpleLazyModule_6( // @[:freechips.rocketchip.system.LowRiscConfig.fir@48599.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48600.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48601.4]
output auto_picker_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_picker_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [2:0] auto_picker_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [2:0] auto_picker_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [2:0] auto_picker_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [6:0] auto_picker_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [31:0] auto_picker_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [7:0] auto_picker_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [63:0] auto_picker_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_picker_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_picker_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_picker_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [2:0] auto_picker_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [2:0] auto_picker_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [6:0] auto_picker_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_picker_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [63:0] auto_picker_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_picker_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_axi4yank_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [3:0] auto_axi4yank_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [31:0] auto_axi4yank_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [7:0] auto_axi4yank_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [2:0] auto_axi4yank_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [1:0] auto_axi4yank_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [3:0] auto_axi4yank_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [2:0] auto_axi4yank_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [3:0] auto_axi4yank_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_axi4yank_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [63:0] auto_axi4yank_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [7:0] auto_axi4yank_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_axi4yank_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [3:0] auto_axi4yank_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [1:0] auto_axi4yank_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_axi4yank_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [3:0] auto_axi4yank_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [31:0] auto_axi4yank_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [7:0] auto_axi4yank_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [2:0] auto_axi4yank_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [1:0] auto_axi4yank_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [3:0] auto_axi4yank_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [2:0] auto_axi4yank_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output [3:0] auto_axi4yank_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
output auto_axi4yank_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_axi4yank_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [3:0] auto_axi4yank_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [63:0] auto_axi4yank_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input [1:0] auto_axi4yank_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
input auto_axi4yank_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@48602.4]
);
wire axi4yank_clock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_reset; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [31:0] axi4yank_auto_in_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [7:0] axi4yank_auto_in_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_in_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_in_aw_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_aw_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_aw_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_in_aw_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_aw_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [13:0] axi4yank_auto_in_aw_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [63:0] axi4yank_auto_in_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [7:0] axi4yank_auto_in_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_in_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [13:0] axi4yank_auto_in_b_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [31:0] axi4yank_auto_in_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [7:0] axi4yank_auto_in_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_in_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_in_ar_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_ar_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_ar_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_in_ar_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_ar_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [13:0] axi4yank_auto_in_ar_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_in_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [63:0] axi4yank_auto_in_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_in_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [13:0] axi4yank_auto_in_r_bits_user; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_in_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_aw_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_aw_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_aw_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [31:0] axi4yank_auto_out_aw_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [7:0] axi4yank_auto_out_aw_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_out_aw_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_out_aw_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_aw_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_aw_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_out_aw_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_aw_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_w_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_w_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [63:0] axi4yank_auto_out_w_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [7:0] axi4yank_auto_out_w_bits_strb; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_w_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_b_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_b_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_b_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_out_b_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_ar_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_ar_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_ar_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [31:0] axi4yank_auto_out_ar_bits_addr; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [7:0] axi4yank_auto_out_ar_bits_len; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_out_ar_bits_size; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_out_ar_bits_burst; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_ar_bits_lock; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_ar_bits_cache; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [2:0] axi4yank_auto_out_ar_bits_prot; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_ar_bits_qos; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_r_ready; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_r_valid; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [3:0] axi4yank_auto_out_r_bits_id; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [63:0] axi4yank_auto_out_r_bits_data; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire [1:0] axi4yank_auto_out_r_bits_resp; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4yank_auto_out_r_bits_last; // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
wire axi4index_auto_in_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [6:0] axi4index_auto_in_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [31:0] axi4index_auto_in_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [7:0] axi4index_auto_in_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_in_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_in_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_aw_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_in_aw_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_in_aw_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_in_aw_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [10:0] axi4index_auto_in_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [63:0] axi4index_auto_in_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [7:0] axi4index_auto_in_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [6:0] axi4index_auto_in_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_in_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [10:0] axi4index_auto_in_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [6:0] axi4index_auto_in_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [31:0] axi4index_auto_in_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [7:0] axi4index_auto_in_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_in_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_in_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_ar_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_in_ar_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_in_ar_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_in_ar_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [10:0] axi4index_auto_in_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [6:0] axi4index_auto_in_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [63:0] axi4index_auto_in_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_in_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [10:0] axi4index_auto_in_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_in_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_aw_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_aw_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_aw_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [31:0] axi4index_auto_out_aw_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [7:0] axi4index_auto_out_aw_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_out_aw_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_out_aw_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_aw_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_aw_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_out_aw_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_aw_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [13:0] axi4index_auto_out_aw_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_w_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_w_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [63:0] axi4index_auto_out_w_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [7:0] axi4index_auto_out_w_bits_strb; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_w_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_b_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_b_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_b_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_out_b_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [13:0] axi4index_auto_out_b_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_ar_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_ar_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_ar_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [31:0] axi4index_auto_out_ar_bits_addr; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [7:0] axi4index_auto_out_ar_bits_len; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_out_ar_bits_size; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_out_ar_bits_burst; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_ar_bits_lock; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_ar_bits_cache; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [2:0] axi4index_auto_out_ar_bits_prot; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_ar_bits_qos; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [13:0] axi4index_auto_out_ar_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_r_ready; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_r_valid; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [3:0] axi4index_auto_out_r_bits_id; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [63:0] axi4index_auto_out_r_bits_data; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [1:0] axi4index_auto_out_r_bits_resp; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire [13:0] axi4index_auto_out_r_bits_user; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire axi4index_auto_out_r_bits_last; // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
wire tl2axi4_clock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_reset; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_a_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_a_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_in_a_bits_opcode; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_in_a_bits_param; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_in_a_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [6:0] tl2axi4_auto_in_a_bits_source; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [31:0] tl2axi4_auto_in_a_bits_address; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [7:0] tl2axi4_auto_in_a_bits_mask; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [63:0] tl2axi4_auto_in_a_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_a_bits_corrupt; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_d_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_d_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_in_d_bits_opcode; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_in_d_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [6:0] tl2axi4_auto_in_d_bits_source; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_d_bits_denied; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [63:0] tl2axi4_auto_in_d_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_in_d_bits_corrupt; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_aw_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_aw_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [6:0] tl2axi4_auto_out_aw_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [31:0] tl2axi4_auto_out_aw_bits_addr; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [7:0] tl2axi4_auto_out_aw_bits_len; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_out_aw_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [1:0] tl2axi4_auto_out_aw_bits_burst; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_aw_bits_lock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [3:0] tl2axi4_auto_out_aw_bits_cache; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_out_aw_bits_prot; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [3:0] tl2axi4_auto_out_aw_bits_qos; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [10:0] tl2axi4_auto_out_aw_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_w_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_w_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [63:0] tl2axi4_auto_out_w_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [7:0] tl2axi4_auto_out_w_bits_strb; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_w_bits_last; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_b_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_b_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [6:0] tl2axi4_auto_out_b_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [1:0] tl2axi4_auto_out_b_bits_resp; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [10:0] tl2axi4_auto_out_b_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_ar_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_ar_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [6:0] tl2axi4_auto_out_ar_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [31:0] tl2axi4_auto_out_ar_bits_addr; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [7:0] tl2axi4_auto_out_ar_bits_len; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_out_ar_bits_size; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [1:0] tl2axi4_auto_out_ar_bits_burst; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_ar_bits_lock; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [3:0] tl2axi4_auto_out_ar_bits_cache; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [2:0] tl2axi4_auto_out_ar_bits_prot; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [3:0] tl2axi4_auto_out_ar_bits_qos; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [10:0] tl2axi4_auto_out_ar_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_r_ready; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_r_valid; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [6:0] tl2axi4_auto_out_r_bits_id; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [63:0] tl2axi4_auto_out_r_bits_data; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [1:0] tl2axi4_auto_out_r_bits_resp; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire [10:0] tl2axi4_auto_out_r_bits_user; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire tl2axi4_auto_out_r_bits_last; // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [6:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [6:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [6:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [2:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [6:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
wire picker_clock; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_reset; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_a_ready; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_a_valid; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_in_a_bits_opcode; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_in_a_bits_param; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_in_a_bits_size; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [6:0] picker_auto_in_a_bits_source; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [31:0] picker_auto_in_a_bits_address; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [7:0] picker_auto_in_a_bits_mask; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [63:0] picker_auto_in_a_bits_data; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_a_bits_corrupt; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_d_ready; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_d_valid; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_in_d_bits_opcode; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_in_d_bits_size; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [6:0] picker_auto_in_d_bits_source; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_d_bits_denied; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [63:0] picker_auto_in_d_bits_data; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_in_d_bits_corrupt; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_a_ready; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_a_valid; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_out_a_bits_opcode; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_out_a_bits_param; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_out_a_bits_size; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [6:0] picker_auto_out_a_bits_source; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [31:0] picker_auto_out_a_bits_address; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [7:0] picker_auto_out_a_bits_mask; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [63:0] picker_auto_out_a_bits_data; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_a_bits_corrupt; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_d_ready; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_d_valid; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_out_d_bits_opcode; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [2:0] picker_auto_out_d_bits_size; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [6:0] picker_auto_out_d_bits_source; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_d_bits_denied; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire [63:0] picker_auto_out_d_bits_data; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
wire picker_auto_out_d_bits_corrupt; // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
AXI4UserYanker_2 axi4yank ( // @[UserYanker.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@48607.4]
.clock(axi4yank_clock),
.reset(axi4yank_reset),
.auto_in_aw_ready(axi4yank_auto_in_aw_ready),
.auto_in_aw_valid(axi4yank_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4yank_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4yank_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4yank_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4yank_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4yank_auto_in_aw_bits_burst),
.auto_in_aw_bits_lock(axi4yank_auto_in_aw_bits_lock),
.auto_in_aw_bits_cache(axi4yank_auto_in_aw_bits_cache),
.auto_in_aw_bits_prot(axi4yank_auto_in_aw_bits_prot),
.auto_in_aw_bits_qos(axi4yank_auto_in_aw_bits_qos),
.auto_in_aw_bits_user(axi4yank_auto_in_aw_bits_user),
.auto_in_w_ready(axi4yank_auto_in_w_ready),
.auto_in_w_valid(axi4yank_auto_in_w_valid),
.auto_in_w_bits_data(axi4yank_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4yank_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4yank_auto_in_w_bits_last),
.auto_in_b_ready(axi4yank_auto_in_b_ready),
.auto_in_b_valid(axi4yank_auto_in_b_valid),
.auto_in_b_bits_id(axi4yank_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4yank_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4yank_auto_in_b_bits_user),
.auto_in_ar_ready(axi4yank_auto_in_ar_ready),
.auto_in_ar_valid(axi4yank_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4yank_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4yank_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4yank_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4yank_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4yank_auto_in_ar_bits_burst),
.auto_in_ar_bits_lock(axi4yank_auto_in_ar_bits_lock),
.auto_in_ar_bits_cache(axi4yank_auto_in_ar_bits_cache),
.auto_in_ar_bits_prot(axi4yank_auto_in_ar_bits_prot),
.auto_in_ar_bits_qos(axi4yank_auto_in_ar_bits_qos),
.auto_in_ar_bits_user(axi4yank_auto_in_ar_bits_user),
.auto_in_r_ready(axi4yank_auto_in_r_ready),
.auto_in_r_valid(axi4yank_auto_in_r_valid),
.auto_in_r_bits_id(axi4yank_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4yank_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4yank_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4yank_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4yank_auto_in_r_bits_last),
.auto_out_aw_ready(axi4yank_auto_out_aw_ready),
.auto_out_aw_valid(axi4yank_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4yank_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4yank_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4yank_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4yank_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4yank_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(axi4yank_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(axi4yank_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(axi4yank_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(axi4yank_auto_out_aw_bits_qos),
.auto_out_w_ready(axi4yank_auto_out_w_ready),
.auto_out_w_valid(axi4yank_auto_out_w_valid),
.auto_out_w_bits_data(axi4yank_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4yank_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4yank_auto_out_w_bits_last),
.auto_out_b_ready(axi4yank_auto_out_b_ready),
.auto_out_b_valid(axi4yank_auto_out_b_valid),
.auto_out_b_bits_id(axi4yank_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4yank_auto_out_b_bits_resp),
.auto_out_ar_ready(axi4yank_auto_out_ar_ready),
.auto_out_ar_valid(axi4yank_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4yank_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4yank_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4yank_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4yank_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4yank_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(axi4yank_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(axi4yank_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(axi4yank_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(axi4yank_auto_out_ar_bits_qos),
.auto_out_r_ready(axi4yank_auto_out_r_ready),
.auto_out_r_valid(axi4yank_auto_out_r_valid),
.auto_out_r_bits_id(axi4yank_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4yank_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4yank_auto_out_r_bits_resp),
.auto_out_r_bits_last(axi4yank_auto_out_r_bits_last)
);
AXI4IdIndexer_2 axi4index ( // @[IdIndexer.scala 80:31:freechips.rocketchip.system.LowRiscConfig.fir@48613.4]
.auto_in_aw_ready(axi4index_auto_in_aw_ready),
.auto_in_aw_valid(axi4index_auto_in_aw_valid),
.auto_in_aw_bits_id(axi4index_auto_in_aw_bits_id),
.auto_in_aw_bits_addr(axi4index_auto_in_aw_bits_addr),
.auto_in_aw_bits_len(axi4index_auto_in_aw_bits_len),
.auto_in_aw_bits_size(axi4index_auto_in_aw_bits_size),
.auto_in_aw_bits_burst(axi4index_auto_in_aw_bits_burst),
.auto_in_aw_bits_lock(axi4index_auto_in_aw_bits_lock),
.auto_in_aw_bits_cache(axi4index_auto_in_aw_bits_cache),
.auto_in_aw_bits_prot(axi4index_auto_in_aw_bits_prot),
.auto_in_aw_bits_qos(axi4index_auto_in_aw_bits_qos),
.auto_in_aw_bits_user(axi4index_auto_in_aw_bits_user),
.auto_in_w_ready(axi4index_auto_in_w_ready),
.auto_in_w_valid(axi4index_auto_in_w_valid),
.auto_in_w_bits_data(axi4index_auto_in_w_bits_data),
.auto_in_w_bits_strb(axi4index_auto_in_w_bits_strb),
.auto_in_w_bits_last(axi4index_auto_in_w_bits_last),
.auto_in_b_ready(axi4index_auto_in_b_ready),
.auto_in_b_valid(axi4index_auto_in_b_valid),
.auto_in_b_bits_id(axi4index_auto_in_b_bits_id),
.auto_in_b_bits_resp(axi4index_auto_in_b_bits_resp),
.auto_in_b_bits_user(axi4index_auto_in_b_bits_user),
.auto_in_ar_ready(axi4index_auto_in_ar_ready),
.auto_in_ar_valid(axi4index_auto_in_ar_valid),
.auto_in_ar_bits_id(axi4index_auto_in_ar_bits_id),
.auto_in_ar_bits_addr(axi4index_auto_in_ar_bits_addr),
.auto_in_ar_bits_len(axi4index_auto_in_ar_bits_len),
.auto_in_ar_bits_size(axi4index_auto_in_ar_bits_size),
.auto_in_ar_bits_burst(axi4index_auto_in_ar_bits_burst),
.auto_in_ar_bits_lock(axi4index_auto_in_ar_bits_lock),
.auto_in_ar_bits_cache(axi4index_auto_in_ar_bits_cache),
.auto_in_ar_bits_prot(axi4index_auto_in_ar_bits_prot),
.auto_in_ar_bits_qos(axi4index_auto_in_ar_bits_qos),
.auto_in_ar_bits_user(axi4index_auto_in_ar_bits_user),
.auto_in_r_ready(axi4index_auto_in_r_ready),
.auto_in_r_valid(axi4index_auto_in_r_valid),
.auto_in_r_bits_id(axi4index_auto_in_r_bits_id),
.auto_in_r_bits_data(axi4index_auto_in_r_bits_data),
.auto_in_r_bits_resp(axi4index_auto_in_r_bits_resp),
.auto_in_r_bits_user(axi4index_auto_in_r_bits_user),
.auto_in_r_bits_last(axi4index_auto_in_r_bits_last),
.auto_out_aw_ready(axi4index_auto_out_aw_ready),
.auto_out_aw_valid(axi4index_auto_out_aw_valid),
.auto_out_aw_bits_id(axi4index_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(axi4index_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(axi4index_auto_out_aw_bits_len),
.auto_out_aw_bits_size(axi4index_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(axi4index_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(axi4index_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(axi4index_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(axi4index_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(axi4index_auto_out_aw_bits_qos),
.auto_out_aw_bits_user(axi4index_auto_out_aw_bits_user),
.auto_out_w_ready(axi4index_auto_out_w_ready),
.auto_out_w_valid(axi4index_auto_out_w_valid),
.auto_out_w_bits_data(axi4index_auto_out_w_bits_data),
.auto_out_w_bits_strb(axi4index_auto_out_w_bits_strb),
.auto_out_w_bits_last(axi4index_auto_out_w_bits_last),
.auto_out_b_ready(axi4index_auto_out_b_ready),
.auto_out_b_valid(axi4index_auto_out_b_valid),
.auto_out_b_bits_id(axi4index_auto_out_b_bits_id),
.auto_out_b_bits_resp(axi4index_auto_out_b_bits_resp),
.auto_out_b_bits_user(axi4index_auto_out_b_bits_user),
.auto_out_ar_ready(axi4index_auto_out_ar_ready),
.auto_out_ar_valid(axi4index_auto_out_ar_valid),
.auto_out_ar_bits_id(axi4index_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(axi4index_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(axi4index_auto_out_ar_bits_len),
.auto_out_ar_bits_size(axi4index_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(axi4index_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(axi4index_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(axi4index_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(axi4index_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(axi4index_auto_out_ar_bits_qos),
.auto_out_ar_bits_user(axi4index_auto_out_ar_bits_user),
.auto_out_r_ready(axi4index_auto_out_r_ready),
.auto_out_r_valid(axi4index_auto_out_r_valid),
.auto_out_r_bits_id(axi4index_auto_out_r_bits_id),
.auto_out_r_bits_data(axi4index_auto_out_r_bits_data),
.auto_out_r_bits_resp(axi4index_auto_out_r_bits_resp),
.auto_out_r_bits_user(axi4index_auto_out_r_bits_user),
.auto_out_r_bits_last(axi4index_auto_out_r_bits_last)
);
TLToAXI4_1 tl2axi4 ( // @[ToAXI4.scala 254:29:freechips.rocketchip.system.LowRiscConfig.fir@48619.4]
.clock(tl2axi4_clock),
.reset(tl2axi4_reset),
.auto_in_a_ready(tl2axi4_auto_in_a_ready),
.auto_in_a_valid(tl2axi4_auto_in_a_valid),
.auto_in_a_bits_opcode(tl2axi4_auto_in_a_bits_opcode),
.auto_in_a_bits_param(tl2axi4_auto_in_a_bits_param),
.auto_in_a_bits_size(tl2axi4_auto_in_a_bits_size),
.auto_in_a_bits_source(tl2axi4_auto_in_a_bits_source),
.auto_in_a_bits_address(tl2axi4_auto_in_a_bits_address),
.auto_in_a_bits_mask(tl2axi4_auto_in_a_bits_mask),
.auto_in_a_bits_data(tl2axi4_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(tl2axi4_auto_in_a_bits_corrupt),
.auto_in_d_ready(tl2axi4_auto_in_d_ready),
.auto_in_d_valid(tl2axi4_auto_in_d_valid),
.auto_in_d_bits_opcode(tl2axi4_auto_in_d_bits_opcode),
.auto_in_d_bits_size(tl2axi4_auto_in_d_bits_size),
.auto_in_d_bits_source(tl2axi4_auto_in_d_bits_source),
.auto_in_d_bits_denied(tl2axi4_auto_in_d_bits_denied),
.auto_in_d_bits_data(tl2axi4_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(tl2axi4_auto_in_d_bits_corrupt),
.auto_out_aw_ready(tl2axi4_auto_out_aw_ready),
.auto_out_aw_valid(tl2axi4_auto_out_aw_valid),
.auto_out_aw_bits_id(tl2axi4_auto_out_aw_bits_id),
.auto_out_aw_bits_addr(tl2axi4_auto_out_aw_bits_addr),
.auto_out_aw_bits_len(tl2axi4_auto_out_aw_bits_len),
.auto_out_aw_bits_size(tl2axi4_auto_out_aw_bits_size),
.auto_out_aw_bits_burst(tl2axi4_auto_out_aw_bits_burst),
.auto_out_aw_bits_lock(tl2axi4_auto_out_aw_bits_lock),
.auto_out_aw_bits_cache(tl2axi4_auto_out_aw_bits_cache),
.auto_out_aw_bits_prot(tl2axi4_auto_out_aw_bits_prot),
.auto_out_aw_bits_qos(tl2axi4_auto_out_aw_bits_qos),
.auto_out_aw_bits_user(tl2axi4_auto_out_aw_bits_user),
.auto_out_w_ready(tl2axi4_auto_out_w_ready),
.auto_out_w_valid(tl2axi4_auto_out_w_valid),
.auto_out_w_bits_data(tl2axi4_auto_out_w_bits_data),
.auto_out_w_bits_strb(tl2axi4_auto_out_w_bits_strb),
.auto_out_w_bits_last(tl2axi4_auto_out_w_bits_last),
.auto_out_b_ready(tl2axi4_auto_out_b_ready),
.auto_out_b_valid(tl2axi4_auto_out_b_valid),
.auto_out_b_bits_id(tl2axi4_auto_out_b_bits_id),
.auto_out_b_bits_resp(tl2axi4_auto_out_b_bits_resp),
.auto_out_b_bits_user(tl2axi4_auto_out_b_bits_user),
.auto_out_ar_ready(tl2axi4_auto_out_ar_ready),
.auto_out_ar_valid(tl2axi4_auto_out_ar_valid),
.auto_out_ar_bits_id(tl2axi4_auto_out_ar_bits_id),
.auto_out_ar_bits_addr(tl2axi4_auto_out_ar_bits_addr),
.auto_out_ar_bits_len(tl2axi4_auto_out_ar_bits_len),
.auto_out_ar_bits_size(tl2axi4_auto_out_ar_bits_size),
.auto_out_ar_bits_burst(tl2axi4_auto_out_ar_bits_burst),
.auto_out_ar_bits_lock(tl2axi4_auto_out_ar_bits_lock),
.auto_out_ar_bits_cache(tl2axi4_auto_out_ar_bits_cache),
.auto_out_ar_bits_prot(tl2axi4_auto_out_ar_bits_prot),
.auto_out_ar_bits_qos(tl2axi4_auto_out_ar_bits_qos),
.auto_out_ar_bits_user(tl2axi4_auto_out_ar_bits_user),
.auto_out_r_ready(tl2axi4_auto_out_r_ready),
.auto_out_r_valid(tl2axi4_auto_out_r_valid),
.auto_out_r_bits_id(tl2axi4_auto_out_r_bits_id),
.auto_out_r_bits_data(tl2axi4_auto_out_r_bits_data),
.auto_out_r_bits_resp(tl2axi4_auto_out_r_bits_resp),
.auto_out_r_bits_user(tl2axi4_auto_out_r_bits_user),
.auto_out_r_bits_last(tl2axi4_auto_out_r_bits_last)
);
TLBuffer_6 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@48625.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
);
ProbePicker picker ( // @[ProbePicker.scala 65:28:freechips.rocketchip.system.LowRiscConfig.fir@48631.4]
.clock(picker_clock),
.reset(picker_reset),
.auto_in_a_ready(picker_auto_in_a_ready),
.auto_in_a_valid(picker_auto_in_a_valid),
.auto_in_a_bits_opcode(picker_auto_in_a_bits_opcode),
.auto_in_a_bits_param(picker_auto_in_a_bits_param),
.auto_in_a_bits_size(picker_auto_in_a_bits_size),
.auto_in_a_bits_source(picker_auto_in_a_bits_source),
.auto_in_a_bits_address(picker_auto_in_a_bits_address),
.auto_in_a_bits_mask(picker_auto_in_a_bits_mask),
.auto_in_a_bits_data(picker_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(picker_auto_in_a_bits_corrupt),
.auto_in_d_ready(picker_auto_in_d_ready),
.auto_in_d_valid(picker_auto_in_d_valid),
.auto_in_d_bits_opcode(picker_auto_in_d_bits_opcode),
.auto_in_d_bits_size(picker_auto_in_d_bits_size),
.auto_in_d_bits_source(picker_auto_in_d_bits_source),
.auto_in_d_bits_denied(picker_auto_in_d_bits_denied),
.auto_in_d_bits_data(picker_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(picker_auto_in_d_bits_corrupt),
.auto_out_a_ready(picker_auto_out_a_ready),
.auto_out_a_valid(picker_auto_out_a_valid),
.auto_out_a_bits_opcode(picker_auto_out_a_bits_opcode),
.auto_out_a_bits_param(picker_auto_out_a_bits_param),
.auto_out_a_bits_size(picker_auto_out_a_bits_size),
.auto_out_a_bits_source(picker_auto_out_a_bits_source),
.auto_out_a_bits_address(picker_auto_out_a_bits_address),
.auto_out_a_bits_mask(picker_auto_out_a_bits_mask),
.auto_out_a_bits_data(picker_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(picker_auto_out_a_bits_corrupt),
.auto_out_d_ready(picker_auto_out_d_ready),
.auto_out_d_valid(picker_auto_out_d_valid),
.auto_out_d_bits_opcode(picker_auto_out_d_bits_opcode),
.auto_out_d_bits_size(picker_auto_out_d_bits_size),
.auto_out_d_bits_source(picker_auto_out_d_bits_source),
.auto_out_d_bits_denied(picker_auto_out_d_bits_denied),
.auto_out_d_bits_data(picker_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(picker_auto_out_d_bits_corrupt)
);
assign auto_picker_in_a_ready = picker_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_valid = picker_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_bits_opcode = picker_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_bits_size = picker_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_bits_source = picker_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_bits_denied = picker_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_bits_data = picker_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_picker_in_d_bits_corrupt = picker_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign auto_axi4yank_out_aw_valid = axi4yank_auto_out_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_id = axi4yank_auto_out_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_addr = axi4yank_auto_out_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_len = axi4yank_auto_out_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_size = axi4yank_auto_out_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_burst = axi4yank_auto_out_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_lock = axi4yank_auto_out_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_cache = axi4yank_auto_out_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_prot = axi4yank_auto_out_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_aw_bits_qos = axi4yank_auto_out_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_w_valid = axi4yank_auto_out_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_w_bits_data = axi4yank_auto_out_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_w_bits_strb = axi4yank_auto_out_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_w_bits_last = axi4yank_auto_out_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_b_ready = axi4yank_auto_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_valid = axi4yank_auto_out_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_id = axi4yank_auto_out_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_addr = axi4yank_auto_out_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_len = axi4yank_auto_out_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_size = axi4yank_auto_out_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_burst = axi4yank_auto_out_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_lock = axi4yank_auto_out_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_cache = axi4yank_auto_out_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_prot = axi4yank_auto_out_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_ar_bits_qos = axi4yank_auto_out_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign auto_axi4yank_out_r_ready = axi4yank_auto_out_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48611.4]
assign axi4yank_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48612.4]
assign axi4yank_auto_in_aw_valid = axi4index_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_id = axi4index_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_addr = axi4index_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_len = axi4index_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_size = axi4index_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_burst = axi4index_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_lock = axi4index_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_cache = axi4index_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_prot = axi4index_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_qos = axi4index_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_aw_bits_user = axi4index_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_w_valid = axi4index_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_w_bits_data = axi4index_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_w_bits_strb = axi4index_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_w_bits_last = axi4index_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_b_ready = axi4index_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_valid = axi4index_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_id = axi4index_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_addr = axi4index_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_len = axi4index_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_size = axi4index_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_burst = axi4index_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_lock = axi4index_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_cache = axi4index_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_prot = axi4index_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_qos = axi4index_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_ar_bits_user = axi4index_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_in_r_ready = axi4index_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4yank_auto_out_aw_ready = auto_axi4yank_out_aw_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_w_ready = auto_axi4yank_out_w_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_b_valid = auto_axi4yank_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_b_bits_id = auto_axi4yank_out_b_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_b_bits_resp = auto_axi4yank_out_b_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_ar_ready = auto_axi4yank_out_ar_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_r_valid = auto_axi4yank_out_r_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_r_bits_id = auto_axi4yank_out_r_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_r_bits_data = auto_axi4yank_out_r_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_r_bits_resp = auto_axi4yank_out_r_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4yank_auto_out_r_bits_last = auto_axi4yank_out_r_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@48641.4]
assign axi4index_auto_in_aw_valid = tl2axi4_auto_out_aw_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_id = tl2axi4_auto_out_aw_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_addr = tl2axi4_auto_out_aw_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_len = tl2axi4_auto_out_aw_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_size = tl2axi4_auto_out_aw_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_burst = tl2axi4_auto_out_aw_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_lock = tl2axi4_auto_out_aw_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_cache = tl2axi4_auto_out_aw_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_prot = tl2axi4_auto_out_aw_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_qos = tl2axi4_auto_out_aw_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_aw_bits_user = tl2axi4_auto_out_aw_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_w_valid = tl2axi4_auto_out_w_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_w_bits_data = tl2axi4_auto_out_w_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_w_bits_strb = tl2axi4_auto_out_w_bits_strb; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_w_bits_last = tl2axi4_auto_out_w_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_b_ready = tl2axi4_auto_out_b_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_valid = tl2axi4_auto_out_ar_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_id = tl2axi4_auto_out_ar_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_addr = tl2axi4_auto_out_ar_bits_addr; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_len = tl2axi4_auto_out_ar_bits_len; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_size = tl2axi4_auto_out_ar_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_burst = tl2axi4_auto_out_ar_bits_burst; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_lock = tl2axi4_auto_out_ar_bits_lock; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_cache = tl2axi4_auto_out_ar_bits_cache; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_prot = tl2axi4_auto_out_ar_bits_prot; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_qos = tl2axi4_auto_out_ar_bits_qos; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_ar_bits_user = tl2axi4_auto_out_ar_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_in_r_ready = tl2axi4_auto_out_r_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign axi4index_auto_out_aw_ready = axi4yank_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_w_ready = axi4yank_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_b_valid = axi4yank_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_b_bits_id = axi4yank_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_b_bits_resp = axi4yank_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_b_bits_user = axi4yank_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_ar_ready = axi4yank_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_r_valid = axi4yank_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_r_bits_id = axi4yank_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_r_bits_data = axi4yank_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_r_bits_resp = axi4yank_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_r_bits_user = axi4yank_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign axi4index_auto_out_r_bits_last = axi4yank_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48637.4]
assign tl2axi4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48623.4]
assign tl2axi4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48624.4]
assign tl2axi4_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign tl2axi4_auto_out_aw_ready = axi4index_auto_in_aw_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_w_ready = axi4index_auto_in_w_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_b_valid = axi4index_auto_in_b_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_b_bits_id = axi4index_auto_in_b_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_b_bits_resp = axi4index_auto_in_b_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_b_bits_user = axi4index_auto_in_b_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_ar_ready = axi4index_auto_in_ar_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_r_valid = axi4index_auto_in_r_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_r_bits_id = axi4index_auto_in_r_bits_id; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_r_bits_data = axi4index_auto_in_r_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_r_bits_resp = axi4index_auto_in_r_bits_resp; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_r_bits_user = axi4index_auto_in_r_bits_user; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign tl2axi4_auto_out_r_bits_last = axi4index_auto_in_r_bits_last; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48638.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48629.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48630.4]
assign buffer_auto_in_a_valid = picker_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_opcode = picker_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_param = picker_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_size = picker_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_source = picker_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_address = picker_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_mask = picker_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_data = picker_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_a_bits_corrupt = picker_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_in_d_ready = picker_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign buffer_auto_out_a_ready = tl2axi4_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_valid = tl2axi4_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_bits_opcode = tl2axi4_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_bits_size = tl2axi4_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_bits_source = tl2axi4_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_bits_denied = tl2axi4_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_bits_data = tl2axi4_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign buffer_auto_out_d_bits_corrupt = tl2axi4_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48639.4]
assign picker_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48635.4]
assign picker_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@48636.4]
assign picker_auto_in_a_valid = auto_picker_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_opcode = auto_picker_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_param = auto_picker_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_size = auto_picker_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_source = auto_picker_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_address = auto_picker_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_mask = auto_picker_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_data = auto_picker_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_a_bits_corrupt = auto_picker_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_in_d_ready = auto_picker_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@48642.4]
assign picker_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
assign picker_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@48640.4]
endmodule
module TLMonitor_18( // @[:freechips.rocketchip.system.LowRiscConfig.fir@48651.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48652.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48653.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [6:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [31:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input [6:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@48654.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@49823.4]
wire [12:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@48681.6]
wire [5:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@48682.6]
wire [5:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@48683.6]
wire [31:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@48684.6]
wire [31:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@48684.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@48685.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@48687.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@48688.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@48689.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@48690.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@48691.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@48692.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@48693.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@48694.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48696.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48697.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48699.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48700.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@48701.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@48702.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@48703.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48704.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48705.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48706.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48707.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48708.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48709.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48710.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48711.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48712.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48713.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48714.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48715.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@48716.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@48717.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@48718.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48719.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48720.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48721.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48722.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48723.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48724.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48725.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48726.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48727.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48728.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48729.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48730.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48731.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48732.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48733.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48734.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48735.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48736.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48737.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48738.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48739.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48740.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48741.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48742.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@48749.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@48772.6]
wire [31:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@48775.8]
wire [32:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@48776.8]
wire [32:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@48777.8]
wire [32:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@48778.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@48779.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@48784.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@48805.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@48806.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@48812.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@48813.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@48818.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@48820.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@48821.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@48826.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@48827.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@48829.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@48830.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@48835.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@48837.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@48838.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@48844.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@48898.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@48900.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@48901.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@48924.6]
wire _T_205; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@48927.8]
wire _T_213; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@48935.8]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48938.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48939.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@48958.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@48960.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@48961.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@48966.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@48968.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@48969.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@48983.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@49034.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@49076.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@49077.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@49078.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@49080.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@49081.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@49087.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@49118.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@49120.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@49121.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@49135.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@49166.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@49168.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@49169.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@49183.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@49233.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@49235.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@49236.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@49253.6]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@49262.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49264.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49265.8]
wire _T_406; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@49278.8]
wire _T_408; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@49280.8]
wire _T_409; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@49281.8]
wire _T_410; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@49286.8]
wire _T_412; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@49288.8]
wire _T_413; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@49289.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@49295.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@49353.6]
wire _T_462; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@49394.8]
wire _T_464; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@49396.8]
wire _T_465; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@49397.8]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@49412.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@49447.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@49483.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@49543.4]
wire [2:0] _T_540; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@49548.4]
wire _T_541; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@49549.4]
wire _T_542; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@49550.4]
reg [2:0] _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@49552.4]
reg [31:0] _RAND_0;
wire [3:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49553.4]
wire [3:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49554.4]
wire [2:0] _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49555.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49556.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@49567.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@49568.4]
reg [31:0] _RAND_2;
reg [2:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@49569.4]
reg [31:0] _RAND_3;
reg [6:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@49570.4]
reg [31:0] _RAND_4;
reg [31:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@49571.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@49572.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@49573.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@49575.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@49577.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@49578.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@49583.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@49585.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@49586.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@49591.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@49593.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@49594.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@49599.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@49601.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@49602.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@49607.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@49609.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@49610.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@49617.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@49625.4]
wire [12:0] _T_593; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@49627.4]
wire [5:0] _T_594; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@49628.4]
wire [5:0] _T_595; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@49629.4]
wire [2:0] _T_596; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@49630.4]
wire _T_597; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@49631.4]
reg [2:0] _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@49633.4]
reg [31:0] _RAND_6;
wire [3:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49634.4]
wire [3:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49635.4]
wire [2:0] _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49636.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49637.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@49648.4]
reg [31:0] _RAND_7;
reg [2:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@49650.4]
reg [31:0] _RAND_8;
reg [6:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@49651.4]
reg [31:0] _RAND_9;
reg _T_623; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@49653.4]
reg [31:0] _RAND_10;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@49654.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@49655.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@49657.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@49659.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@49660.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@49673.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@49675.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@49676.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@49681.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@49683.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@49684.6]
wire _T_646; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@49697.6]
wire _T_648; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@49699.6]
wire _T_649; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@49700.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@49707.4]
reg [127:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@49716.4]
reg [127:0] _RAND_11;
reg [2:0] _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@49726.4]
reg [31:0] _RAND_12;
wire [3:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49727.4]
wire [3:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49728.4]
wire [2:0] _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49729.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49730.4]
reg [2:0] _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@49749.4]
reg [31:0] _RAND_13;
wire [3:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49750.4]
wire [3:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49751.4]
wire [2:0] _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49752.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49753.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@49768.4]
wire [127:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@49771.6]
wire [127:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@49773.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@49774.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@49775.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@49777.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@49778.6]
wire [127:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@49770.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@49789.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@49791.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@49792.4]
wire [127:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@49794.6]
wire [127:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@49796.6]
wire [127:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@49797.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@49798.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@49800.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@49801.6]
wire [127:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@49793.4]
wire _T_724; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@49807.4]
wire _T_725; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@49808.4]
wire _T_726; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@49809.4]
wire _T_727; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@49810.4]
wire _T_729; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@49812.4]
wire _T_730; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@49813.4]
wire [127:0] _T_731; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@49818.4]
wire [127:0] _T_732; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@49819.4]
wire [127:0] _T_733; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@49820.4]
reg [31:0] _T_735; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@49822.4]
reg [31:0] _RAND_14;
wire _T_736; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@49825.4]
wire _T_737; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@49826.4]
wire _T_738; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@49827.4]
wire _T_739; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@49828.4]
wire _T_740; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@49829.4]
wire _T_741; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@49830.4]
wire _T_743; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@49832.4]
wire _T_744; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@49833.4]
wire [31:0] _T_746; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@49839.4]
wire _T_749; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@49843.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@48786.10]
wire _GEN_33; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@48858.10]
wire _GEN_49; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48941.10]
wire _GEN_59; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@49000.10]
wire _GEN_67; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@49051.10]
wire _GEN_75; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@49101.10]
wire _GEN_83; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@49149.10]
wire _GEN_91; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@49197.10]
wire _GEN_99; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49267.10]
wire _GEN_105; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@49308.10]
wire _GEN_111; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@49366.10]
wire _GEN_117; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@49434.10]
wire _GEN_119; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@49470.10]
wire _GEN_121; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@49505.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@49823.4]
.out(plusarg_reader_out)
);
assign _T_36 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@48681.6]
assign _T_37 = _T_36[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@48682.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@48683.6]
assign _GEN_18 = {{26'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@48684.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@48684.6]
assign _T_40 = _T_39 == 32'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@48685.6]
assign _T_42 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@48687.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@48688.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@48689.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@48690.6]
assign _T_46 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@48691.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@48692.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@48693.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@48694.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48696.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48697.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48699.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48700.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@48701.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@48702.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@48703.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48704.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48705.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48706.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48707.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48708.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48709.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48710.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48711.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48712.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48713.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48714.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48715.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@48716.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@48717.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@48718.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48719.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48720.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48721.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48722.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48723.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48724.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48725.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48726.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48727.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48728.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48729.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48730.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48731.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48732.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48733.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48734.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48735.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48736.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48737.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48738.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48739.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@48740.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@48741.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@48742.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@48749.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@48772.6]
assign _T_125 = io_in_a_bits_address ^ 32'h80000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@48775.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@48776.8]
assign _T_127 = $signed(_T_126) & $signed(-33'sh40000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@48777.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@48778.8]
assign _T_129 = $signed(_T_128) == $signed(33'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@48779.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@48784.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@48805.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@48806.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@48812.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@48813.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@48818.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@48820.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@48821.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@48826.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@48827.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@48829.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@48830.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@48835.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@48837.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@48838.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@48844.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@48898.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@48900.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@48901.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@48924.6]
assign _T_205 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@48927.8]
assign _T_213 = _T_205 & _T_129; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@48935.8]
assign _T_216 = _T_213 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48938.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48939.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@48958.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@48960.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@48961.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@48966.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@48968.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@48969.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@48983.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@49034.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@49076.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@49077.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@49078.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@49080.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@49081.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@49087.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@49118.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@49120.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@49121.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@49135.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@49166.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@49168.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@49169.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@49183.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@49233.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@49235.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@49236.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@49253.6]
assign _T_398 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@49262.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49264.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49265.8]
assign _T_406 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@49278.8]
assign _T_408 = _T_406 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@49280.8]
assign _T_409 = _T_408 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@49281.8]
assign _T_410 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@49286.8]
assign _T_412 = _T_410 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@49288.8]
assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@49289.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@49295.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@49353.6]
assign _T_462 = _T_410 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@49394.8]
assign _T_464 = _T_462 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@49396.8]
assign _T_465 = _T_464 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@49397.8]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@49412.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@49447.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@49483.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@49543.4]
assign _T_540 = _T_38[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@49548.4]
assign _T_541 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@49549.4]
assign _T_542 = _T_541 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@49550.4]
assign _T_546 = _T_545 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49553.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49554.4]
assign _T_548 = _T_547[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49555.4]
assign _T_549 = _T_545 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49556.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@49572.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@49573.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@49575.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@49577.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@49578.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@49583.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@49585.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@49586.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@49591.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@49593.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@49594.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@49599.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@49601.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@49602.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@49607.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@49609.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@49610.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@49617.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@49625.4]
assign _T_593 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@49627.4]
assign _T_594 = _T_593[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@49628.4]
assign _T_595 = ~ _T_594; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@49629.4]
assign _T_596 = _T_595[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@49630.4]
assign _T_597 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@49631.4]
assign _T_601 = _T_600 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49634.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49635.4]
assign _T_603 = _T_602[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49636.4]
assign _T_604 = _T_600 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49637.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@49654.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@49655.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@49657.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@49659.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@49660.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@49673.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@49675.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@49676.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@49681.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@49683.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@49684.6]
assign _T_646 = io_in_d_bits_denied == _T_623; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@49697.6]
assign _T_648 = _T_646 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@49699.6]
assign _T_649 = _T_648 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@49700.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@49707.4]
assign _T_665 = _T_664 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49727.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49728.4]
assign _T_667 = _T_666[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49729.4]
assign _T_668 = _T_664 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49730.4]
assign _T_686 = _T_685 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49750.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49751.4]
assign _T_688 = _T_687[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@49752.4]
assign _T_689 = _T_685 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@49753.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@49768.4]
assign _T_702 = 128'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@49771.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@49773.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@49774.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@49775.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@49777.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@49778.6]
assign _GEN_15 = _T_700 ? _T_702 : 128'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@49770.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@49789.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@49791.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@49792.4]
assign _T_717 = 128'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@49794.6]
assign _T_718 = _GEN_15 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@49796.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@49797.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@49798.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@49800.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@49801.6]
assign _GEN_16 = _T_716 ? _T_717 : 128'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@49793.4]
assign _T_724 = _GEN_15 != _GEN_16; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@49807.4]
assign _T_725 = _GEN_15 != 128'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@49808.4]
assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@49809.4]
assign _T_727 = _T_724 | _T_726; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@49810.4]
assign _T_729 = _T_727 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@49812.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@49813.4]
assign _T_731 = _T_653 | _GEN_15; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@49818.4]
assign _T_732 = ~ _GEN_16; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@49819.4]
assign _T_733 = _T_731 & _T_732; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@49820.4]
assign _T_736 = _T_653 != 128'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@49825.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@49826.4]
assign _T_738 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@49827.4]
assign _T_739 = _T_737 | _T_738; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@49828.4]
assign _T_740 = _T_735 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@49829.4]
assign _T_741 = _T_739 | _T_740; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@49830.4]
assign _T_743 = _T_741 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@49832.4]
assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@49833.4]
assign _T_746 = _T_735 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@49839.4]
assign _T_749 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@49843.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@48786.10]
assign _GEN_33 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@48858.10]
assign _GEN_49 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48941.10]
assign _GEN_59 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@49000.10]
assign _GEN_67 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@49051.10]
assign _GEN_75 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@49101.10]
assign _GEN_83 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@49149.10]
assign _GEN_91 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@49197.10]
assign _GEN_99 = io_in_d_valid & _T_394; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49267.10]
assign _GEN_105 = io_in_d_valid & _T_414; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@49308.10]
assign _GEN_111 = io_in_d_valid & _T_442; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@49366.10]
assign _GEN_117 = io_in_d_valid & _T_471; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@49434.10]
assign _GEN_119 = io_in_d_valid & _T_488; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@49470.10]
assign _GEN_121 = io_in_d_valid & _T_506; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@49505.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_623 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {4{`RANDOM}};
_T_653 = _RAND_11[127:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_664 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_685 = _RAND_13[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_735 = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
if (_T_542) begin
_T_545 <= _T_540;
end else begin
_T_545 <= 3'h0;
end
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
if (_T_597) begin
_T_600 <= _T_596;
end else begin
_T_600 <= 3'h0;
end
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (_T_651) begin
_T_623 <= io_in_d_bits_denied;
end
if (reset) begin
_T_653 <= 128'h0;
end else begin
_T_653 <= _T_733;
end
if (reset) begin
_T_664 <= 3'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
if (_T_542) begin
_T_664 <= _T_540;
end else begin
_T_664 <= 3'h0;
end
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 3'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
if (_T_597) begin
_T_685 <= _T_596;
end else begin
_T_685 <= 3'h0;
end
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_735 <= 32'h0;
end else begin
if (_T_749) begin
_T_735 <= 32'h0;
end else begin
_T_735 <= _T_746;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@48666.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@48667.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@48769.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@48770.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@48786.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@48787.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@48793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@48794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@48800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@48801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@48808.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@48809.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@48815.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@48816.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@48823.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@48824.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@48832.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@48833.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@48840.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@48841.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@48858.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@48859.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@48865.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@48866.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@48872.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@48873.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@48880.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@48881.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@48887.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@48888.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@48895.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@48896.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@48903.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@48904.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@48912.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@48913.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@48920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_33 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@48921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48941.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@48942.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@48948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@48949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@48955.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@48956.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@48963.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@48964.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@48971.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@48972.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@48979.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@48980.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@49000.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@49001.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@49007.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@49008.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@49014.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@49015.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@49022.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@49023.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@49030.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@49031.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@49051.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@49052.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@49058.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@49059.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@49065.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@49066.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@49073.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@49074.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@49083.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_67 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@49084.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@49101.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@49102.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@49108.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@49109.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@49115.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@49116.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@49123.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@49124.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@49131.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@49132.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@49149.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@49150.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@49156.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@49157.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@49163.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@49164.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@49171.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@49172.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@49179.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_83 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@49180.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@49197.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@49198.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@49204.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@49205.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@49211.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@49212.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@49219.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@49220.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@49227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@49228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@49238.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@49239.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@49259.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@49260.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49267.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@49268.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@49275.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@49276.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@49283.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_409) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@49284.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@49291.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_99 & _T_413) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@49292.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@49301.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@49302.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@49308.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@49309.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@49316.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@49317.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@49324.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@49325.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@49332.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@49333.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@49340.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_409) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@49341.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@49349.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@49350.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@49359.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@49360.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@49366.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@49367.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@49374.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@49375.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@49382.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@49383.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@49390.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@49391.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@49399.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_111 & _T_465) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@49400.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@49408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@49409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@49418.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@49419.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@49426.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@49427.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@49434.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_409) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@49435.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@49443.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@49444.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@49453.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@49454.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@49461.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@49462.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@49470.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_465) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@49471.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@49479.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@49480.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@49489.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@49490.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@49497.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@49498.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@49505.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_121 & _T_409) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@49506.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@49514.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@49515.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@49524.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@49525.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@49532.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@49533.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@49540.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@49541.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@49580.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@49581.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@49588.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@49589.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@49596.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@49597.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@49604.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@49605.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@49612.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@49613.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@49662.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@49663.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@49670.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@49671.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@49678.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@49679.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@49686.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@49687.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@49694.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@49695.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_649) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@49702.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_649) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@49703.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@49780.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@49781.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@49803.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@49804.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_730) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@49815.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_730) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@49816.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_744) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at ExampleRocketSystem.scala:40:91)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@49835.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_744) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@49836.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module BankBinder( // @[:freechips.rocketchip.system.LowRiscConfig.fir@49848.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49849.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49850.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [6:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [31:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [6:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [2:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [6:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [31:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [2:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [6:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@49851.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [6:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [31:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire [6:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
TLMonitor_18 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@49858.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49898.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49897.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49860.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49861.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@49894.4]
endmodule
module SimpleLazyModule_7( // @[:freechips.rocketchip.system.LowRiscConfig.fir@49901.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49902.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49903.4]
output auto_binder_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [2:0] auto_binder_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [2:0] auto_binder_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [2:0] auto_binder_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [6:0] auto_binder_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [31:0] auto_binder_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [7:0] auto_binder_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [63:0] auto_binder_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output auto_binder_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [2:0] auto_binder_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [2:0] auto_binder_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [6:0] auto_binder_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output auto_binder_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [63:0] auto_binder_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output auto_binder_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output auto_binder_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [2:0] auto_binder_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [2:0] auto_binder_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [2:0] auto_binder_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [6:0] auto_binder_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [31:0] auto_binder_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [7:0] auto_binder_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output [63:0] auto_binder_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output auto_binder_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
output auto_binder_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [2:0] auto_binder_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [2:0] auto_binder_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [6:0] auto_binder_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input [63:0] auto_binder_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
input auto_binder_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@49904.4]
);
wire binder_clock; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_reset; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_a_ready; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_a_valid; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_in_a_bits_opcode; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_in_a_bits_param; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_in_a_bits_size; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [6:0] binder_auto_in_a_bits_source; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [31:0] binder_auto_in_a_bits_address; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [7:0] binder_auto_in_a_bits_mask; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [63:0] binder_auto_in_a_bits_data; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_a_bits_corrupt; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_d_ready; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_d_valid; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_in_d_bits_opcode; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_in_d_bits_size; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [6:0] binder_auto_in_d_bits_source; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_d_bits_denied; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [63:0] binder_auto_in_d_bits_data; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_in_d_bits_corrupt; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_a_ready; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_a_valid; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_out_a_bits_opcode; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_out_a_bits_param; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_out_a_bits_size; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [6:0] binder_auto_out_a_bits_source; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [31:0] binder_auto_out_a_bits_address; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [7:0] binder_auto_out_a_bits_mask; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [63:0] binder_auto_out_a_bits_data; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_a_bits_corrupt; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_d_ready; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_d_valid; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_out_d_bits_opcode; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [2:0] binder_auto_out_d_bits_size; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [6:0] binder_auto_out_d_bits_source; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_d_bits_denied; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire [63:0] binder_auto_out_d_bits_data; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
wire binder_auto_out_d_bits_corrupt; // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
BankBinder binder ( // @[BankBinder.scala 63:28:freechips.rocketchip.system.LowRiscConfig.fir@49909.4]
.clock(binder_clock),
.reset(binder_reset),
.auto_in_a_ready(binder_auto_in_a_ready),
.auto_in_a_valid(binder_auto_in_a_valid),
.auto_in_a_bits_opcode(binder_auto_in_a_bits_opcode),
.auto_in_a_bits_param(binder_auto_in_a_bits_param),
.auto_in_a_bits_size(binder_auto_in_a_bits_size),
.auto_in_a_bits_source(binder_auto_in_a_bits_source),
.auto_in_a_bits_address(binder_auto_in_a_bits_address),
.auto_in_a_bits_mask(binder_auto_in_a_bits_mask),
.auto_in_a_bits_data(binder_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(binder_auto_in_a_bits_corrupt),
.auto_in_d_ready(binder_auto_in_d_ready),
.auto_in_d_valid(binder_auto_in_d_valid),
.auto_in_d_bits_opcode(binder_auto_in_d_bits_opcode),
.auto_in_d_bits_size(binder_auto_in_d_bits_size),
.auto_in_d_bits_source(binder_auto_in_d_bits_source),
.auto_in_d_bits_denied(binder_auto_in_d_bits_denied),
.auto_in_d_bits_data(binder_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(binder_auto_in_d_bits_corrupt),
.auto_out_a_ready(binder_auto_out_a_ready),
.auto_out_a_valid(binder_auto_out_a_valid),
.auto_out_a_bits_opcode(binder_auto_out_a_bits_opcode),
.auto_out_a_bits_param(binder_auto_out_a_bits_param),
.auto_out_a_bits_size(binder_auto_out_a_bits_size),
.auto_out_a_bits_source(binder_auto_out_a_bits_source),
.auto_out_a_bits_address(binder_auto_out_a_bits_address),
.auto_out_a_bits_mask(binder_auto_out_a_bits_mask),
.auto_out_a_bits_data(binder_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(binder_auto_out_a_bits_corrupt),
.auto_out_d_ready(binder_auto_out_d_ready),
.auto_out_d_valid(binder_auto_out_d_valid),
.auto_out_d_bits_opcode(binder_auto_out_d_bits_opcode),
.auto_out_d_bits_size(binder_auto_out_d_bits_size),
.auto_out_d_bits_source(binder_auto_out_d_bits_source),
.auto_out_d_bits_denied(binder_auto_out_d_bits_denied),
.auto_out_d_bits_data(binder_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(binder_auto_out_d_bits_corrupt)
);
assign auto_binder_in_a_ready = binder_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_valid = binder_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_bits_opcode = binder_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_bits_size = binder_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_bits_source = binder_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_bits_denied = binder_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_bits_data = binder_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_in_d_bits_corrupt = binder_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign auto_binder_out_a_valid = binder_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_opcode = binder_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_param = binder_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_size = binder_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_source = binder_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_address = binder_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_mask = binder_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_data = binder_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_a_bits_corrupt = binder_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign auto_binder_out_d_ready = binder_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49913.4]
assign binder_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49914.4]
assign binder_auto_in_a_valid = auto_binder_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_opcode = auto_binder_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_param = auto_binder_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_size = auto_binder_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_source = auto_binder_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_address = auto_binder_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_mask = auto_binder_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_data = auto_binder_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_a_bits_corrupt = auto_binder_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_in_d_ready = auto_binder_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49916.4]
assign binder_auto_out_a_ready = auto_binder_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_valid = auto_binder_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_bits_opcode = auto_binder_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_bits_size = auto_binder_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_bits_source = auto_binder_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_bits_denied = auto_binder_out_d_bits_denied; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_bits_data = auto_binder_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
assign binder_auto_out_d_bits_corrupt = auto_binder_out_d_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49915.4]
endmodule
module MemoryBus( // @[:freechips.rocketchip.system.LowRiscConfig.fir@49918.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49919.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49920.4]
output auto_coupler_from_coherence_manager_binder_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_from_coherence_manager_binder_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [2:0] auto_coupler_from_coherence_manager_binder_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [2:0] auto_coupler_from_coherence_manager_binder_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [2:0] auto_coupler_from_coherence_manager_binder_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [6:0] auto_coupler_from_coherence_manager_binder_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [31:0] auto_coupler_from_coherence_manager_binder_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [7:0] auto_coupler_from_coherence_manager_binder_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [63:0] auto_coupler_from_coherence_manager_binder_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_from_coherence_manager_binder_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_from_coherence_manager_binder_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_from_coherence_manager_binder_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [2:0] auto_coupler_from_coherence_manager_binder_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [2:0] auto_coupler_from_coherence_manager_binder_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [6:0] auto_coupler_from_coherence_manager_binder_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_from_coherence_manager_binder_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [63:0] auto_coupler_from_coherence_manager_binder_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_from_coherence_manager_binder_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [31:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [7:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [2:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [1:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [2:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [63:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [7:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_bits_strb, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_bits_last, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [1:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [31:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [7:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_len, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [2:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [1:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_burst, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_lock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_cache, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [2:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_prot, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_qos, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
output auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [3:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_id, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [63:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input [1:0] auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_resp, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
input auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_last // @[:freechips.rocketchip.system.LowRiscConfig.fir@49921.4]
);
wire memory_bus_xbar_clock; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_reset; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_a_ready; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_a_valid; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_in_a_bits_opcode; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_in_a_bits_param; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_in_a_bits_size; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [6:0] memory_bus_xbar_auto_in_a_bits_source; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [31:0] memory_bus_xbar_auto_in_a_bits_address; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [7:0] memory_bus_xbar_auto_in_a_bits_mask; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [63:0] memory_bus_xbar_auto_in_a_bits_data; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_a_bits_corrupt; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_d_ready; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_d_valid; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_in_d_bits_opcode; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_in_d_bits_size; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [6:0] memory_bus_xbar_auto_in_d_bits_source; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_d_bits_denied; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [63:0] memory_bus_xbar_auto_in_d_bits_data; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_in_d_bits_corrupt; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_a_ready; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_a_valid; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_out_a_bits_opcode; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_out_a_bits_param; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_out_a_bits_size; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [6:0] memory_bus_xbar_auto_out_a_bits_source; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [31:0] memory_bus_xbar_auto_out_a_bits_address; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [7:0] memory_bus_xbar_auto_out_a_bits_mask; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [63:0] memory_bus_xbar_auto_out_a_bits_data; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_a_bits_corrupt; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_d_ready; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_d_valid; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_out_d_bits_opcode; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [2:0] memory_bus_xbar_auto_out_d_bits_size; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [6:0] memory_bus_xbar_auto_out_d_bits_source; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_d_bits_denied; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire [63:0] memory_bus_xbar_auto_out_d_bits_data; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire memory_bus_xbar_auto_out_d_bits_corrupt; // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
wire coupler_to_memory_controller_named_axi4_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [6:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [31:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [7:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [63:0] coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [6:0] coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [63:0] coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [31:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [7:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [1:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_lock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_cache; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_prot; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_qos; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [63:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [7:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_strb; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [1:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [31:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_addr; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [7:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_len; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [1:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_burst; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_lock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_cache; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [2:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_prot; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_qos; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [3:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_id; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [63:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire [1:0] coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_resp; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_last; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
wire coupler_from_coherence_manager_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [6:0] coupler_from_coherence_manager_auto_binder_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [31:0] coupler_from_coherence_manager_auto_binder_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [7:0] coupler_from_coherence_manager_auto_binder_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [63:0] coupler_from_coherence_manager_auto_binder_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [6:0] coupler_from_coherence_manager_auto_binder_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [63:0] coupler_from_coherence_manager_auto_binder_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [6:0] coupler_from_coherence_manager_auto_binder_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [31:0] coupler_from_coherence_manager_auto_binder_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [7:0] coupler_from_coherence_manager_auto_binder_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [63:0] coupler_from_coherence_manager_auto_binder_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [2:0] coupler_from_coherence_manager_auto_binder_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [6:0] coupler_from_coherence_manager_auto_binder_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire [63:0] coupler_from_coherence_manager_auto_binder_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
wire coupler_from_coherence_manager_auto_binder_out_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
TLXbar_4 memory_bus_xbar ( // @[MemoryBus.scala 54:32:freechips.rocketchip.system.LowRiscConfig.fir@49926.4]
.clock(memory_bus_xbar_clock),
.reset(memory_bus_xbar_reset),
.auto_in_a_ready(memory_bus_xbar_auto_in_a_ready),
.auto_in_a_valid(memory_bus_xbar_auto_in_a_valid),
.auto_in_a_bits_opcode(memory_bus_xbar_auto_in_a_bits_opcode),
.auto_in_a_bits_param(memory_bus_xbar_auto_in_a_bits_param),
.auto_in_a_bits_size(memory_bus_xbar_auto_in_a_bits_size),
.auto_in_a_bits_source(memory_bus_xbar_auto_in_a_bits_source),
.auto_in_a_bits_address(memory_bus_xbar_auto_in_a_bits_address),
.auto_in_a_bits_mask(memory_bus_xbar_auto_in_a_bits_mask),
.auto_in_a_bits_data(memory_bus_xbar_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(memory_bus_xbar_auto_in_a_bits_corrupt),
.auto_in_d_ready(memory_bus_xbar_auto_in_d_ready),
.auto_in_d_valid(memory_bus_xbar_auto_in_d_valid),
.auto_in_d_bits_opcode(memory_bus_xbar_auto_in_d_bits_opcode),
.auto_in_d_bits_size(memory_bus_xbar_auto_in_d_bits_size),
.auto_in_d_bits_source(memory_bus_xbar_auto_in_d_bits_source),
.auto_in_d_bits_denied(memory_bus_xbar_auto_in_d_bits_denied),
.auto_in_d_bits_data(memory_bus_xbar_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(memory_bus_xbar_auto_in_d_bits_corrupt),
.auto_out_a_ready(memory_bus_xbar_auto_out_a_ready),
.auto_out_a_valid(memory_bus_xbar_auto_out_a_valid),
.auto_out_a_bits_opcode(memory_bus_xbar_auto_out_a_bits_opcode),
.auto_out_a_bits_param(memory_bus_xbar_auto_out_a_bits_param),
.auto_out_a_bits_size(memory_bus_xbar_auto_out_a_bits_size),
.auto_out_a_bits_source(memory_bus_xbar_auto_out_a_bits_source),
.auto_out_a_bits_address(memory_bus_xbar_auto_out_a_bits_address),
.auto_out_a_bits_mask(memory_bus_xbar_auto_out_a_bits_mask),
.auto_out_a_bits_data(memory_bus_xbar_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(memory_bus_xbar_auto_out_a_bits_corrupt),
.auto_out_d_ready(memory_bus_xbar_auto_out_d_ready),
.auto_out_d_valid(memory_bus_xbar_auto_out_d_valid),
.auto_out_d_bits_opcode(memory_bus_xbar_auto_out_d_bits_opcode),
.auto_out_d_bits_size(memory_bus_xbar_auto_out_d_bits_size),
.auto_out_d_bits_source(memory_bus_xbar_auto_out_d_bits_source),
.auto_out_d_bits_denied(memory_bus_xbar_auto_out_d_bits_denied),
.auto_out_d_bits_data(memory_bus_xbar_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(memory_bus_xbar_auto_out_d_bits_corrupt)
);
SimpleLazyModule_6 coupler_to_memory_controller_named_axi4 ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49932.4]
.clock(coupler_to_memory_controller_named_axi4_clock),
.reset(coupler_to_memory_controller_named_axi4_reset),
.auto_picker_in_a_ready(coupler_to_memory_controller_named_axi4_auto_picker_in_a_ready),
.auto_picker_in_a_valid(coupler_to_memory_controller_named_axi4_auto_picker_in_a_valid),
.auto_picker_in_a_bits_opcode(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_opcode),
.auto_picker_in_a_bits_param(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_param),
.auto_picker_in_a_bits_size(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_size),
.auto_picker_in_a_bits_source(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_source),
.auto_picker_in_a_bits_address(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_address),
.auto_picker_in_a_bits_mask(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_mask),
.auto_picker_in_a_bits_data(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_data),
.auto_picker_in_a_bits_corrupt(coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_corrupt),
.auto_picker_in_d_ready(coupler_to_memory_controller_named_axi4_auto_picker_in_d_ready),
.auto_picker_in_d_valid(coupler_to_memory_controller_named_axi4_auto_picker_in_d_valid),
.auto_picker_in_d_bits_opcode(coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_opcode),
.auto_picker_in_d_bits_size(coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_size),
.auto_picker_in_d_bits_source(coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_source),
.auto_picker_in_d_bits_denied(coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_denied),
.auto_picker_in_d_bits_data(coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_data),
.auto_picker_in_d_bits_corrupt(coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_corrupt),
.auto_axi4yank_out_aw_ready(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_ready),
.auto_axi4yank_out_aw_valid(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_valid),
.auto_axi4yank_out_aw_bits_id(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_id),
.auto_axi4yank_out_aw_bits_addr(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_addr),
.auto_axi4yank_out_aw_bits_len(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_len),
.auto_axi4yank_out_aw_bits_size(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_size),
.auto_axi4yank_out_aw_bits_burst(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_burst),
.auto_axi4yank_out_aw_bits_lock(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_lock),
.auto_axi4yank_out_aw_bits_cache(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_cache),
.auto_axi4yank_out_aw_bits_prot(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_prot),
.auto_axi4yank_out_aw_bits_qos(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_qos),
.auto_axi4yank_out_w_ready(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_ready),
.auto_axi4yank_out_w_valid(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_valid),
.auto_axi4yank_out_w_bits_data(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_data),
.auto_axi4yank_out_w_bits_strb(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_strb),
.auto_axi4yank_out_w_bits_last(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_last),
.auto_axi4yank_out_b_ready(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_ready),
.auto_axi4yank_out_b_valid(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_valid),
.auto_axi4yank_out_b_bits_id(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_bits_id),
.auto_axi4yank_out_b_bits_resp(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_bits_resp),
.auto_axi4yank_out_ar_ready(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_ready),
.auto_axi4yank_out_ar_valid(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_valid),
.auto_axi4yank_out_ar_bits_id(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_id),
.auto_axi4yank_out_ar_bits_addr(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_addr),
.auto_axi4yank_out_ar_bits_len(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_len),
.auto_axi4yank_out_ar_bits_size(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_size),
.auto_axi4yank_out_ar_bits_burst(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_burst),
.auto_axi4yank_out_ar_bits_lock(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_lock),
.auto_axi4yank_out_ar_bits_cache(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_cache),
.auto_axi4yank_out_ar_bits_prot(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_prot),
.auto_axi4yank_out_ar_bits_qos(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_qos),
.auto_axi4yank_out_r_ready(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_ready),
.auto_axi4yank_out_r_valid(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_valid),
.auto_axi4yank_out_r_bits_id(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_id),
.auto_axi4yank_out_r_bits_data(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_data),
.auto_axi4yank_out_r_bits_resp(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_resp),
.auto_axi4yank_out_r_bits_last(coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_last)
);
SimpleLazyModule_7 coupler_from_coherence_manager ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@49938.4]
.clock(coupler_from_coherence_manager_clock),
.reset(coupler_from_coherence_manager_reset),
.auto_binder_in_a_ready(coupler_from_coherence_manager_auto_binder_in_a_ready),
.auto_binder_in_a_valid(coupler_from_coherence_manager_auto_binder_in_a_valid),
.auto_binder_in_a_bits_opcode(coupler_from_coherence_manager_auto_binder_in_a_bits_opcode),
.auto_binder_in_a_bits_param(coupler_from_coherence_manager_auto_binder_in_a_bits_param),
.auto_binder_in_a_bits_size(coupler_from_coherence_manager_auto_binder_in_a_bits_size),
.auto_binder_in_a_bits_source(coupler_from_coherence_manager_auto_binder_in_a_bits_source),
.auto_binder_in_a_bits_address(coupler_from_coherence_manager_auto_binder_in_a_bits_address),
.auto_binder_in_a_bits_mask(coupler_from_coherence_manager_auto_binder_in_a_bits_mask),
.auto_binder_in_a_bits_data(coupler_from_coherence_manager_auto_binder_in_a_bits_data),
.auto_binder_in_a_bits_corrupt(coupler_from_coherence_manager_auto_binder_in_a_bits_corrupt),
.auto_binder_in_d_ready(coupler_from_coherence_manager_auto_binder_in_d_ready),
.auto_binder_in_d_valid(coupler_from_coherence_manager_auto_binder_in_d_valid),
.auto_binder_in_d_bits_opcode(coupler_from_coherence_manager_auto_binder_in_d_bits_opcode),
.auto_binder_in_d_bits_size(coupler_from_coherence_manager_auto_binder_in_d_bits_size),
.auto_binder_in_d_bits_source(coupler_from_coherence_manager_auto_binder_in_d_bits_source),
.auto_binder_in_d_bits_denied(coupler_from_coherence_manager_auto_binder_in_d_bits_denied),
.auto_binder_in_d_bits_data(coupler_from_coherence_manager_auto_binder_in_d_bits_data),
.auto_binder_in_d_bits_corrupt(coupler_from_coherence_manager_auto_binder_in_d_bits_corrupt),
.auto_binder_out_a_ready(coupler_from_coherence_manager_auto_binder_out_a_ready),
.auto_binder_out_a_valid(coupler_from_coherence_manager_auto_binder_out_a_valid),
.auto_binder_out_a_bits_opcode(coupler_from_coherence_manager_auto_binder_out_a_bits_opcode),
.auto_binder_out_a_bits_param(coupler_from_coherence_manager_auto_binder_out_a_bits_param),
.auto_binder_out_a_bits_size(coupler_from_coherence_manager_auto_binder_out_a_bits_size),
.auto_binder_out_a_bits_source(coupler_from_coherence_manager_auto_binder_out_a_bits_source),
.auto_binder_out_a_bits_address(coupler_from_coherence_manager_auto_binder_out_a_bits_address),
.auto_binder_out_a_bits_mask(coupler_from_coherence_manager_auto_binder_out_a_bits_mask),
.auto_binder_out_a_bits_data(coupler_from_coherence_manager_auto_binder_out_a_bits_data),
.auto_binder_out_a_bits_corrupt(coupler_from_coherence_manager_auto_binder_out_a_bits_corrupt),
.auto_binder_out_d_ready(coupler_from_coherence_manager_auto_binder_out_d_ready),
.auto_binder_out_d_valid(coupler_from_coherence_manager_auto_binder_out_d_valid),
.auto_binder_out_d_bits_opcode(coupler_from_coherence_manager_auto_binder_out_d_bits_opcode),
.auto_binder_out_d_bits_size(coupler_from_coherence_manager_auto_binder_out_d_bits_size),
.auto_binder_out_d_bits_source(coupler_from_coherence_manager_auto_binder_out_d_bits_source),
.auto_binder_out_d_bits_denied(coupler_from_coherence_manager_auto_binder_out_d_bits_denied),
.auto_binder_out_d_bits_data(coupler_from_coherence_manager_auto_binder_out_d_bits_data),
.auto_binder_out_d_bits_corrupt(coupler_from_coherence_manager_auto_binder_out_d_bits_corrupt)
);
assign auto_coupler_from_coherence_manager_binder_in_a_ready = coupler_from_coherence_manager_auto_binder_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_valid = coupler_from_coherence_manager_auto_binder_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_bits_opcode = coupler_from_coherence_manager_auto_binder_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_bits_size = coupler_from_coherence_manager_auto_binder_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_bits_source = coupler_from_coherence_manager_auto_binder_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_bits_denied = coupler_from_coherence_manager_auto_binder_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_bits_data = coupler_from_coherence_manager_auto_binder_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_from_coherence_manager_binder_in_d_bits_corrupt = coupler_from_coherence_manager_auto_binder_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_valid = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_id = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_addr = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_len = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_size = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_burst = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_lock = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_cache = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_prot = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_bits_qos = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_valid = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_bits_data = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_bits_strb = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_strb; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_bits_last = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_ready = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_valid = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_id = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_addr = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_addr; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_len = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_len; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_size = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_burst = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_burst; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_lock = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_lock; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_cache = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_cache; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_prot = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_prot; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_bits_qos = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_bits_qos; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_ready = coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign memory_bus_xbar_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49930.4]
assign memory_bus_xbar_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49931.4]
assign memory_bus_xbar_auto_in_a_valid = coupler_from_coherence_manager_auto_binder_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_opcode = coupler_from_coherence_manager_auto_binder_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_param = coupler_from_coherence_manager_auto_binder_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_size = coupler_from_coherence_manager_auto_binder_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_source = coupler_from_coherence_manager_auto_binder_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_address = coupler_from_coherence_manager_auto_binder_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_mask = coupler_from_coherence_manager_auto_binder_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_data = coupler_from_coherence_manager_auto_binder_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_a_bits_corrupt = coupler_from_coherence_manager_auto_binder_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_in_d_ready = coupler_from_coherence_manager_auto_binder_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign memory_bus_xbar_auto_out_a_ready = coupler_to_memory_controller_named_axi4_auto_picker_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_valid = coupler_to_memory_controller_named_axi4_auto_picker_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_bits_opcode = coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_bits_size = coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_bits_source = coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_bits_denied = coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_bits_data = coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign memory_bus_xbar_auto_out_d_bits_corrupt = coupler_to_memory_controller_named_axi4_auto_picker_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49936.4]
assign coupler_to_memory_controller_named_axi4_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49937.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_valid = memory_bus_xbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_opcode = memory_bus_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_param = memory_bus_xbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_size = memory_bus_xbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_source = memory_bus_xbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_address = memory_bus_xbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_mask = memory_bus_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_data = memory_bus_xbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_a_bits_corrupt = memory_bus_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_picker_in_d_ready = memory_bus_xbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@49944.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_aw_ready = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_aw_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_w_ready = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_w_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_valid = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_bits_id = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_b_bits_resp = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_b_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_ar_ready = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_ar_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_valid = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_id = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_id; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_data = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_resp = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_resp; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_to_memory_controller_named_axi4_auto_axi4yank_out_r_bits_last = auto_coupler_to_memory_controller_named_axi4_axi4yank_out_r_bits_last; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@49946.4]
assign coupler_from_coherence_manager_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49942.4]
assign coupler_from_coherence_manager_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@49943.4]
assign coupler_from_coherence_manager_auto_binder_in_a_valid = auto_coupler_from_coherence_manager_binder_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_opcode = auto_coupler_from_coherence_manager_binder_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_param = auto_coupler_from_coherence_manager_binder_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_size = auto_coupler_from_coherence_manager_binder_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_source = auto_coupler_from_coherence_manager_binder_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_address = auto_coupler_from_coherence_manager_binder_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_mask = auto_coupler_from_coherence_manager_binder_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_data = auto_coupler_from_coherence_manager_binder_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_a_bits_corrupt = auto_coupler_from_coherence_manager_binder_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_in_d_ready = auto_coupler_from_coherence_manager_binder_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@49947.4]
assign coupler_from_coherence_manager_auto_binder_out_a_ready = memory_bus_xbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_valid = memory_bus_xbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_bits_opcode = memory_bus_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_bits_size = memory_bus_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_bits_source = memory_bus_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_bits_denied = memory_bus_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_bits_data = memory_bus_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
assign coupler_from_coherence_manager_auto_binder_out_d_bits_corrupt = memory_bus_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@49945.4]
endmodule
module TLMonitor_19( // @[:freechips.rocketchip.system.LowRiscConfig.fir@49956.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49957.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49958.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@49959.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@51535.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@49976.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@49977.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@49982.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@49983.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@49986.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@49987.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@49995.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50007.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50008.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50009.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50010.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@50012.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@50013.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@50014.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@50015.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@50015.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@50016.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@50018.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@50019.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@50020.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@50021.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@50022.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@50023.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@50024.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@50025.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50027.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50028.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50030.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50031.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@50032.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@50033.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@50034.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50035.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50036.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50037.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50038.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50039.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50040.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50041.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50042.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50043.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50044.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50045.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50046.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@50047.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@50048.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@50049.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50050.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50051.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50052.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50053.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50054.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50055.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50056.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50057.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50058.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50059.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50060.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50061.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50062.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50063.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50064.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50065.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50066.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50067.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50068.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50069.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50070.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50071.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50072.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50073.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@50080.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50091.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@50153.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50156.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50157.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50158.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50159.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50160.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50161.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50162.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50163.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50164.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50165.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50166.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50167.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50168.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50169.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50170.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50173.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50174.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50175.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50176.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50177.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50178.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50179.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50180.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@50189.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@50227.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@50228.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@50240.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@50241.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@50247.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@50248.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@50255.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@50256.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@50262.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@50263.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@50268.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@50270.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@50271.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@50276.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@50277.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@50279.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@50280.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@50285.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@50287.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@50288.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@50294.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@50417.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@50419.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@50420.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@50443.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@50446.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@50469.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@50470.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@50471.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50472.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@50474.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50482.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@50484.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50486.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50487.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@50506.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@50508.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@50509.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@50514.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@50516.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@50517.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@50531.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50561.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@50574.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50576.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50577.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@50613.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@50686.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@50687.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@50688.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@50690.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@50691.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@50697.6]
wire _T_638; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@50725.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50733.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50737.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50738.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@50757.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@50759.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@50760.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@50774.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@50834.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@50836.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@50837.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@50851.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50891.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50892.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@50930.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@50932.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@50933.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@50940.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50941.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@50946.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@50947.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@50950.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50951.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50959.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50971.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50972.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50973.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50974.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@50976.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50979.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50980.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@50985.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@50987.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@50988.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@50993.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@50995.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@50996.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@51001.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@51003.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@51004.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@51009.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@51011.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@51012.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@51018.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@51042.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@51044.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@51045.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@51050.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@51052.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@51053.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@51076.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@51117.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@51119.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@51120.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@51135.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@51170.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@51206.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@51266.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51271.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@51272.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@51273.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@51275.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51276.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51277.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51278.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51279.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@51290.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@51291.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@51292.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@51293.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@51294.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@51295.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@51296.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@51298.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@51300.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@51301.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@51306.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@51308.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@51309.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@51314.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@51316.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@51317.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@51322.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@51324.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@51325.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@51330.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@51332.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@51333.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@51340.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@51348.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51350.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51351.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51352.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51353.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@51354.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@51356.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51357.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51358.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51359.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51360.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@51371.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@51372.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@51373.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@51374.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@51375.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@51376.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@51377.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@51378.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@51380.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@51382.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@51383.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@51388.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@51390.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@51391.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@51396.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@51398.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@51399.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@51404.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@51406.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@51407.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@51412.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@51414.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@51415.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@51420.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@51422.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@51423.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@51430.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@51439.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@51449.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51450.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51451.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51452.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51453.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@51472.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51473.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51474.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51475.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51476.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@51491.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@51494.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@51496.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@51497.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@51498.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@51500.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@51501.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@51493.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@51512.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@51514.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@51515.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@51517.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@51487.4 :freechips.rocketchip.system.LowRiscConfig.fir@51489.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@51495.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@51519.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@51520.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@51521.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@51523.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@51524.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@51516.4]
wire [24:0] _T_1152; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@51530.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@51507.4 :freechips.rocketchip.system.LowRiscConfig.fir@51509.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@51518.6]
wire [24:0] _T_1153; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@51531.4]
wire [24:0] _T_1154; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@51532.4]
reg [31:0] _T_1156; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@51534.4]
reg [31:0] _RAND_16;
wire _T_1157; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@51537.4]
wire _T_1158; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@51538.4]
wire _T_1159; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@51539.4]
wire _T_1160; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@51540.4]
wire _T_1161; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@51541.4]
wire _T_1162; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@51542.4]
wire _T_1164; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@51544.4]
wire _T_1165; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@51545.4]
wire [31:0] _T_1167; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@51551.4]
wire _T_1170; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@51555.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@50191.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@50332.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50489.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50579.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@50661.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50740.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@50817.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50894.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50982.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@51024.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@51082.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@51141.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@51176.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@51212.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@51535.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@49976.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@49977.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@49982.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@49983.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@49986.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@49987.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@49995.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50007.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50008.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50009.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50010.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@50012.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@50013.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@50014.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@50015.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@50015.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@50016.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@50018.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@50019.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@50020.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@50021.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@50022.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@50023.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@50024.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@50025.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50027.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50028.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50030.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50031.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@50032.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@50033.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@50034.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50035.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50036.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50037.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50038.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50039.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50040.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50041.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50042.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50043.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50044.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50045.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50046.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@50047.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@50048.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@50049.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50050.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50051.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50052.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50053.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50054.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50055.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50056.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50057.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50058.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50059.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50060.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50061.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50062.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50063.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50064.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50065.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50066.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50067.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50068.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50069.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50070.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@50071.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@50072.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@50073.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@50080.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50091.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@50153.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50156.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50157.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50158.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50159.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50160.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50161.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50162.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50163.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50164.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50165.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50166.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50167.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50168.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50169.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50170.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50173.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50174.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50175.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@50176.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@50177.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50178.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@50179.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@50180.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@50189.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@50227.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@50228.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@50240.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@50241.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@50247.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@50248.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@50255.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@50256.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@50262.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@50263.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@50268.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@50270.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@50271.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@50276.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@50277.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@50279.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@50280.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@50285.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@50287.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@50288.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@50294.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@50417.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@50419.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@50420.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@50443.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@50446.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@50469.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@50470.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@50471.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50472.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@50474.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50482.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@50484.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50486.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50487.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@50506.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@50508.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@50509.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@50514.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@50516.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@50517.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@50531.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50561.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@50574.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50576.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50577.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@50613.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@50686.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@50687.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@50688.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@50690.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@50691.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@50697.6]
assign _T_638 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@50725.8]
assign _T_646 = _T_638 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@50733.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50737.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50738.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@50757.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@50759.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@50760.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@50774.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@50834.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@50836.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@50837.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@50851.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50891.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50892.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@50930.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@50932.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@50933.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@50940.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50941.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@50946.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@50947.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@50950.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50951.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@50959.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50971.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50972.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50973.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@50974.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@50976.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50979.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50980.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@50985.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@50987.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@50988.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@50993.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@50995.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@50996.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@51001.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@51003.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@51004.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@51009.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@51011.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@51012.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@51018.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@51042.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@51044.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@51045.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@51050.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@51052.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@51053.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@51076.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@51117.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@51119.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@51120.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@51135.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@51170.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@51206.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@51266.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51271.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@51272.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@51273.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51276.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51277.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51278.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51279.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@51295.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@51296.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@51298.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@51300.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@51301.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@51306.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@51308.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@51309.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@51314.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@51316.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@51317.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@51322.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@51324.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@51325.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@51330.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@51332.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@51333.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@51340.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@51348.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51350.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51351.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51352.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51353.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@51354.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51357.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51358.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51359.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51360.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@51377.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@51378.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@51380.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@51382.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@51383.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@51388.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@51390.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@51391.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@51396.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@51398.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@51399.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@51404.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@51406.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@51407.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@51412.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@51414.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@51415.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@51420.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@51422.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@51423.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@51430.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51450.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51451.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51452.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51453.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51473.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51474.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51475.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51476.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@51491.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@51494.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@51496.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@51497.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@51498.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@51500.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@51501.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@51493.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@51512.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@51514.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@51515.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@51517.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@51487.4 :freechips.rocketchip.system.LowRiscConfig.fir@51489.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@51495.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@51519.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@51520.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@51521.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@51523.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@51524.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@51516.4]
assign _T_1152 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@51530.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@51507.4 :freechips.rocketchip.system.LowRiscConfig.fir@51509.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@51518.6]
assign _T_1153 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@51531.4]
assign _T_1154 = _T_1152 & _T_1153; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@51532.4]
assign _T_1157 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@51537.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@51538.4]
assign _T_1159 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@51539.4]
assign _T_1160 = _T_1158 | _T_1159; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@51540.4]
assign _T_1161 = _T_1156 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@51541.4]
assign _T_1162 = _T_1160 | _T_1161; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@51542.4]
assign _T_1164 = _T_1162 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@51544.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@51545.4]
assign _T_1167 = _T_1156 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@51551.4]
assign _T_1170 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@51555.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@50191.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@50332.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50489.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50579.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@50661.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50740.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@50817.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50894.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50982.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@51024.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@51082.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@51141.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@51176.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@51212.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1156 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1154;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1156 <= 32'h0;
end else begin
if (_T_1170) begin
_T_1156 <= 32'h0;
end else begin
_T_1156 <= _T_1167;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@49971.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@49972.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@50150.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@50151.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@50191.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@50192.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@50243.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@50244.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@50250.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@50251.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@50258.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@50259.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@50265.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@50266.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@50273.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@50274.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@50282.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@50283.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@50290.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@50291.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@50332.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@50333.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@50384.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@50385.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@50391.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@50392.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@50399.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@50400.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@50406.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@50407.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@50414.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@50415.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@50422.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@50423.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@50431.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@50432.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@50439.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@50440.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50489.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@50490.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@50496.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@50497.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@50503.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@50504.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@50511.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@50512.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@50519.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@50520.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@50527.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@50528.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50579.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@50580.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@50586.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@50587.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@50593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@50594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@50601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@50602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@50609.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@50610.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@50661.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@50662.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@50668.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@50669.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@50675.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@50676.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@50683.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@50684.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@50693.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@50694.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50740.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@50741.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@50747.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@50748.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@50754.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@50755.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@50762.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@50763.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@50770.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@50771.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@50817.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@50818.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@50824.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@50825.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@50831.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@50832.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@50839.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@50840.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@50847.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@50848.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50894.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@50895.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@50901.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@50902.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@50908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@50909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@50916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@50917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@50924.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@50925.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@50935.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@50936.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50982.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@50983.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@50990.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@50991.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@50998.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@50999.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@51006.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@51007.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@51014.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@51015.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@51024.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@51025.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@51031.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@51032.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@51039.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@51040.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@51047.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@51048.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@51055.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@51056.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@51063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@51064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@51072.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@51073.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@51082.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@51083.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@51089.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@51090.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@51097.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@51098.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@51105.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@51106.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@51113.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@51114.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@51122.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@51123.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@51131.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@51132.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@51141.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@51142.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@51149.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@51150.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@51157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@51158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@51166.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@51167.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@51176.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@51177.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@51184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@51185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@51193.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@51194.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@51202.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@51203.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@51212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@51213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@51220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@51221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@51228.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@51229.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@51237.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@51238.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@51247.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@51248.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@51255.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@51256.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@51263.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@51264.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@51303.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@51304.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@51311.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@51312.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@51319.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@51320.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@51327.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@51328.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@51335.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@51336.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@51385.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@51386.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@51393.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@51394.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@51401.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@51402.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@51409.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@51410.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@51417.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@51418.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@51425.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@51426.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@51503.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@51504.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@51526.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@51527.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1165) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:42:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@51547.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1165) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@51548.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLFIFOFixer_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@51560.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51561.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51562.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@51563.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
wire [28:0] _T_244; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51612.4]
wire [27:0] _T_248; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51616.4]
wire [28:0] _T_249; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51617.4]
wire [28:0] _T_250; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51618.4]
wire [28:0] _T_251; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51619.4]
wire _T_252; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51620.4]
wire [27:0] _T_253; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51621.4]
wire [28:0] _T_254; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51622.4]
wire [28:0] _T_255; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51623.4]
wire [28:0] _T_256; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51624.4]
wire _T_257; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51625.4]
wire [27:0] _T_258; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51626.4]
wire [28:0] _T_259; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51627.4]
wire [28:0] _T_260; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51628.4]
wire [28:0] _T_261; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51629.4]
wire _T_262; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51630.4]
wire [27:0] _T_263; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51631.4]
wire [28:0] _T_264; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51632.4]
wire [28:0] _T_265; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51633.4]
wire [28:0] _T_266; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51634.4]
wire _T_267; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51635.4]
wire [28:0] _T_270; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51638.4]
wire [28:0] _T_271; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51639.4]
wire _T_272; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51640.4]
wire [1:0] _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51641.4]
wire [2:0] _T_275; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51642.4]
wire [2:0] _T_276; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51643.4]
wire [1:0] _T_277; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51644.4]
wire [2:0] _GEN_106; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51646.4]
wire [2:0] _T_279; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51646.4]
wire [2:0] _T_280; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51647.4]
wire [2:0] _GEN_107; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51648.4]
wire [2:0] _T_281; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51648.4]
wire [2:0] _GEN_108; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51649.4]
wire [2:0] _T_282; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51649.4]
wire _T_285; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.LowRiscConfig.fir@51652.4]
wire [1:0] _T_509; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@51743.4]
wire _T_510; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51744.4]
reg [8:0] _T_296; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@51662.4]
reg [31:0] _RAND_0;
wire _T_300; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51666.4]
wire _T_521; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@51757.4]
reg _T_416_0; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_1;
reg _T_416_1; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_2;
wire _T_522; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51758.4]
reg _T_416_2; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_3;
wire _T_523; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51759.4]
reg _T_416_3; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_4;
wire _T_524; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51760.4]
reg _T_416_4; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_5;
wire _T_525; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51761.4]
reg _T_416_5; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_6;
wire _T_526; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51762.4]
reg _T_416_6; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_7;
wire _T_527; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51763.4]
reg _T_416_7; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_8;
wire _T_528; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51764.4]
wire _T_529; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@51765.4]
reg [2:0] _T_520; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@51753.4]
reg [31:0] _RAND_9;
wire _T_530; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@51766.4]
wire _T_531; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@51767.4]
wire _T_532; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@51768.4]
wire _T_536; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51772.4]
wire _T_547; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@51785.4]
reg _T_416_8; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_10;
reg _T_416_9; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_11;
wire _T_548; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51786.4]
reg _T_416_10; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_12;
wire _T_549; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51787.4]
reg _T_416_11; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_13;
wire _T_550; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51788.4]
reg _T_416_12; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_14;
wire _T_551; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51789.4]
reg _T_416_13; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_15;
wire _T_552; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51790.4]
reg _T_416_14; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_16;
wire _T_553; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51791.4]
reg _T_416_15; // @[FIFOFixer.scala 73:27:freechips.rocketchip.system.LowRiscConfig.fir@51729.4]
reg [31:0] _RAND_17;
wire _T_554; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51792.4]
wire _T_555; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@51793.4]
reg [2:0] _T_546; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@51781.4]
reg [31:0] _RAND_18;
wire _T_556; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@51794.4]
wire _T_557; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@51795.4]
wire _T_558; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@51796.4]
wire _T_560; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.LowRiscConfig.fir@51798.4]
wire _T_564; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.LowRiscConfig.fir@51805.4]
wire _T_566; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.LowRiscConfig.fir@51807.4]
wire _T_286; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@51653.4]
wire [26:0] _T_288; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51655.4]
wire [11:0] _T_289; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51656.4]
wire [11:0] _T_290; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51657.4]
wire [8:0] _T_291; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51658.4]
wire _T_292; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@51659.4]
wire _T_293; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@51660.4]
wire [9:0] _T_297; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51663.4]
wire [9:0] _T_298; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51664.4]
wire [8:0] _T_299; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51665.4]
wire _T_308; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@51677.4]
wire [26:0] _T_310; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51679.4]
wire [11:0] _T_311; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51680.4]
wire [11:0] _T_312; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51681.4]
wire [8:0] _T_313; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51682.4]
wire _T_314; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@51683.4]
reg [8:0] _T_317; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@51685.4]
reg [31:0] _RAND_19;
wire [9:0] _T_318; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51686.4]
wire [9:0] _T_319; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51687.4]
wire [8:0] _T_320; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51688.4]
wire _T_321; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51689.4]
wire _T_329; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.LowRiscConfig.fir@51700.4]
wire _T_330; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.LowRiscConfig.fir@51701.4]
wire _T_497; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.LowRiscConfig.fir@51731.4]
wire _T_503; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.LowRiscConfig.fir@51737.4]
wire _T_516; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@51750.4]
wire _T_542; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@51778.4]
TLMonitor_19 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@51570.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign _T_244 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51612.4]
assign _T_248 = auto_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51616.4]
assign _T_249 = {1'b0,$signed(_T_248)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51617.4]
assign _T_250 = $signed(_T_249) & $signed(29'sha010000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51618.4]
assign _T_251 = $signed(_T_250); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51619.4]
assign _T_252 = $signed(_T_251) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51620.4]
assign _T_253 = auto_in_a_bits_address ^ 28'h2000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51621.4]
assign _T_254 = {1'b0,$signed(_T_253)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51622.4]
assign _T_255 = $signed(_T_254) & $signed(29'sha012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51623.4]
assign _T_256 = $signed(_T_255); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51624.4]
assign _T_257 = $signed(_T_256) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51625.4]
assign _T_258 = auto_in_a_bits_address ^ 28'h8000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51626.4]
assign _T_259 = {1'b0,$signed(_T_258)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51627.4]
assign _T_260 = $signed(_T_259) & $signed(29'sh8000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51628.4]
assign _T_261 = $signed(_T_260); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51629.4]
assign _T_262 = $signed(_T_261) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51630.4]
assign _T_263 = auto_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@51631.4]
assign _T_264 = {1'b0,$signed(_T_263)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@51632.4]
assign _T_265 = $signed(_T_264) & $signed(29'sha010000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51633.4]
assign _T_266 = $signed(_T_265); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51634.4]
assign _T_267 = $signed(_T_266) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51635.4]
assign _T_270 = $signed(_T_244) & $signed(29'sha012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51638.4]
assign _T_271 = $signed(_T_270); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@51639.4]
assign _T_272 = $signed(_T_271) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@51640.4]
assign _T_274 = _T_262 ? 2'h2 : 2'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51641.4]
assign _T_275 = _T_272 ? 3'h4 : 3'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51642.4]
assign _T_276 = _T_252 ? 3'h5 : 3'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51643.4]
assign _T_277 = _T_267 ? 2'h3 : 2'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51644.4]
assign _GEN_106 = {{1'd0}, _T_274}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51646.4]
assign _T_279 = _GEN_106 | _T_275; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51646.4]
assign _T_280 = _T_279 | _T_276; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51647.4]
assign _GEN_107 = {{1'd0}, _T_277}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51648.4]
assign _T_281 = _T_280 | _GEN_107; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51648.4]
assign _GEN_108 = {{2'd0}, _T_257}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51649.4]
assign _T_282 = _T_281 | _GEN_108; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@51649.4]
assign _T_285 = _T_282 == 3'h0; // @[FIFOFixer.scala 57:29:freechips.rocketchip.system.LowRiscConfig.fir@51652.4]
assign _T_509 = auto_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@51743.4]
assign _T_510 = _T_509 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51744.4]
assign _T_300 = _T_296 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51666.4]
assign _T_521 = _T_510 & _T_300; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@51757.4]
assign _T_522 = _T_416_0 | _T_416_1; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51758.4]
assign _T_523 = _T_522 | _T_416_2; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51759.4]
assign _T_524 = _T_523 | _T_416_3; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51760.4]
assign _T_525 = _T_524 | _T_416_4; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51761.4]
assign _T_526 = _T_525 | _T_416_5; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51762.4]
assign _T_527 = _T_526 | _T_416_6; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51763.4]
assign _T_528 = _T_527 | _T_416_7; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51764.4]
assign _T_529 = _T_521 & _T_528; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@51765.4]
assign _T_530 = _T_520 != _T_282; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@51766.4]
assign _T_531 = _T_285 | _T_530; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@51767.4]
assign _T_532 = _T_529 & _T_531; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@51768.4]
assign _T_536 = _T_509 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51772.4]
assign _T_547 = _T_536 & _T_300; // @[FIFOFixer.scala 82:15:freechips.rocketchip.system.LowRiscConfig.fir@51785.4]
assign _T_548 = _T_416_8 | _T_416_9; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51786.4]
assign _T_549 = _T_548 | _T_416_10; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51787.4]
assign _T_550 = _T_549 | _T_416_11; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51788.4]
assign _T_551 = _T_550 | _T_416_12; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51789.4]
assign _T_552 = _T_551 | _T_416_13; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51790.4]
assign _T_553 = _T_552 | _T_416_14; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51791.4]
assign _T_554 = _T_553 | _T_416_15; // @[FIFOFixer.scala 82:44:freechips.rocketchip.system.LowRiscConfig.fir@51792.4]
assign _T_555 = _T_547 & _T_554; // @[FIFOFixer.scala 82:26:freechips.rocketchip.system.LowRiscConfig.fir@51793.4]
assign _T_556 = _T_546 != _T_282; // @[FIFOFixer.scala 82:71:freechips.rocketchip.system.LowRiscConfig.fir@51794.4]
assign _T_557 = _T_285 | _T_556; // @[FIFOFixer.scala 82:65:freechips.rocketchip.system.LowRiscConfig.fir@51795.4]
assign _T_558 = _T_555 & _T_557; // @[FIFOFixer.scala 82:50:freechips.rocketchip.system.LowRiscConfig.fir@51796.4]
assign _T_560 = _T_532 | _T_558; // @[FIFOFixer.scala 85:49:freechips.rocketchip.system.LowRiscConfig.fir@51798.4]
assign _T_564 = _T_560 == 1'h0; // @[FIFOFixer.scala 90:50:freechips.rocketchip.system.LowRiscConfig.fir@51805.4]
assign _T_566 = auto_out_a_ready & _T_564; // @[FIFOFixer.scala 90:33:freechips.rocketchip.system.LowRiscConfig.fir@51807.4]
assign _T_286 = _T_566 & auto_in_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@51653.4]
assign _T_288 = 27'hfff << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51655.4]
assign _T_289 = _T_288[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51656.4]
assign _T_290 = ~ _T_289; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51657.4]
assign _T_291 = _T_290[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51658.4]
assign _T_292 = auto_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@51659.4]
assign _T_293 = _T_292 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@51660.4]
assign _T_297 = _T_296 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51663.4]
assign _T_298 = $unsigned(_T_297); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51664.4]
assign _T_299 = _T_298[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51665.4]
assign _T_308 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@51677.4]
assign _T_310 = 27'hfff << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51679.4]
assign _T_311 = _T_310[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51680.4]
assign _T_312 = ~ _T_311; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51681.4]
assign _T_313 = _T_312[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@51682.4]
assign _T_314 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@51683.4]
assign _T_318 = _T_317 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51686.4]
assign _T_319 = $unsigned(_T_318); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51687.4]
assign _T_320 = _T_319[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@51688.4]
assign _T_321 = _T_317 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@51689.4]
assign _T_329 = auto_out_d_bits_opcode != 3'h6; // @[FIFOFixer.scala 69:63:freechips.rocketchip.system.LowRiscConfig.fir@51700.4]
assign _T_330 = _T_321 & _T_329; // @[FIFOFixer.scala 69:42:freechips.rocketchip.system.LowRiscConfig.fir@51701.4]
assign _T_497 = _T_300 & _T_286; // @[FIFOFixer.scala 74:21:freechips.rocketchip.system.LowRiscConfig.fir@51731.4]
assign _T_503 = _T_330 & _T_308; // @[FIFOFixer.scala 75:21:freechips.rocketchip.system.LowRiscConfig.fir@51737.4]
assign _T_516 = _T_286 & _T_510; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@51750.4]
assign _T_542 = _T_286 & _T_536; // @[FIFOFixer.scala 79:49:freechips.rocketchip.system.LowRiscConfig.fir@51778.4]
assign auto_in_a_ready = auto_out_a_ready & _T_564; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@51610.4]
assign auto_out_a_valid = auto_in_a_valid & _T_564; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@51609.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@51572.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@51573.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready & _T_564; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@51606.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_296 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_416_0 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_416_1 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_416_2 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_416_3 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_416_4 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_416_5 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_416_6 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_416_7 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_520 = _RAND_9[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_416_8 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_416_9 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_416_10 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_416_11 = _RAND_13[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_416_12 = _RAND_14[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_416_13 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_416_14 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_416_15 = _RAND_17[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_546 = _RAND_18[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_317 = _RAND_19[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_296 <= 9'h0;
end else begin
if (_T_286) begin
if (_T_300) begin
if (_T_293) begin
_T_296 <= _T_291;
end else begin
_T_296 <= 9'h0;
end
end else begin
_T_296 <= _T_299;
end
end
end
if (reset) begin
_T_416_0 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h0 == auto_out_d_bits_source) begin
_T_416_0 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h0 == auto_in_a_bits_source) begin
_T_416_0 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h0 == auto_in_a_bits_source) begin
_T_416_0 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_1 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h1 == auto_out_d_bits_source) begin
_T_416_1 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h1 == auto_in_a_bits_source) begin
_T_416_1 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h1 == auto_in_a_bits_source) begin
_T_416_1 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_2 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h2 == auto_out_d_bits_source) begin
_T_416_2 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h2 == auto_in_a_bits_source) begin
_T_416_2 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h2 == auto_in_a_bits_source) begin
_T_416_2 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_3 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h3 == auto_out_d_bits_source) begin
_T_416_3 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h3 == auto_in_a_bits_source) begin
_T_416_3 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h3 == auto_in_a_bits_source) begin
_T_416_3 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_4 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h4 == auto_out_d_bits_source) begin
_T_416_4 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h4 == auto_in_a_bits_source) begin
_T_416_4 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h4 == auto_in_a_bits_source) begin
_T_416_4 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_5 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h5 == auto_out_d_bits_source) begin
_T_416_5 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h5 == auto_in_a_bits_source) begin
_T_416_5 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h5 == auto_in_a_bits_source) begin
_T_416_5 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_6 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h6 == auto_out_d_bits_source) begin
_T_416_6 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h6 == auto_in_a_bits_source) begin
_T_416_6 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h6 == auto_in_a_bits_source) begin
_T_416_6 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_7 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h7 == auto_out_d_bits_source) begin
_T_416_7 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h7 == auto_in_a_bits_source) begin
_T_416_7 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h7 == auto_in_a_bits_source) begin
_T_416_7 <= 1'h1;
end
end
end
end
if (_T_516) begin
_T_520 <= _T_282;
end
if (reset) begin
_T_416_8 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h8 == auto_out_d_bits_source) begin
_T_416_8 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h8 == auto_in_a_bits_source) begin
_T_416_8 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h8 == auto_in_a_bits_source) begin
_T_416_8 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_9 <= 1'h0;
end else begin
if (_T_503) begin
if (5'h9 == auto_out_d_bits_source) begin
_T_416_9 <= 1'h0;
end else begin
if (_T_497) begin
if (5'h9 == auto_in_a_bits_source) begin
_T_416_9 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'h9 == auto_in_a_bits_source) begin
_T_416_9 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_10 <= 1'h0;
end else begin
if (_T_503) begin
if (5'ha == auto_out_d_bits_source) begin
_T_416_10 <= 1'h0;
end else begin
if (_T_497) begin
if (5'ha == auto_in_a_bits_source) begin
_T_416_10 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'ha == auto_in_a_bits_source) begin
_T_416_10 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_11 <= 1'h0;
end else begin
if (_T_503) begin
if (5'hb == auto_out_d_bits_source) begin
_T_416_11 <= 1'h0;
end else begin
if (_T_497) begin
if (5'hb == auto_in_a_bits_source) begin
_T_416_11 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'hb == auto_in_a_bits_source) begin
_T_416_11 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_12 <= 1'h0;
end else begin
if (_T_503) begin
if (5'hc == auto_out_d_bits_source) begin
_T_416_12 <= 1'h0;
end else begin
if (_T_497) begin
if (5'hc == auto_in_a_bits_source) begin
_T_416_12 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'hc == auto_in_a_bits_source) begin
_T_416_12 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_13 <= 1'h0;
end else begin
if (_T_503) begin
if (5'hd == auto_out_d_bits_source) begin
_T_416_13 <= 1'h0;
end else begin
if (_T_497) begin
if (5'hd == auto_in_a_bits_source) begin
_T_416_13 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'hd == auto_in_a_bits_source) begin
_T_416_13 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_14 <= 1'h0;
end else begin
if (_T_503) begin
if (5'he == auto_out_d_bits_source) begin
_T_416_14 <= 1'h0;
end else begin
if (_T_497) begin
if (5'he == auto_in_a_bits_source) begin
_T_416_14 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'he == auto_in_a_bits_source) begin
_T_416_14 <= 1'h1;
end
end
end
end
if (reset) begin
_T_416_15 <= 1'h0;
end else begin
if (_T_503) begin
if (5'hf == auto_out_d_bits_source) begin
_T_416_15 <= 1'h0;
end else begin
if (_T_497) begin
if (5'hf == auto_in_a_bits_source) begin
_T_416_15 <= 1'h1;
end
end
end
end else begin
if (_T_497) begin
if (5'hf == auto_in_a_bits_source) begin
_T_416_15 <= 1'h1;
end
end
end
end
if (_T_542) begin
_T_546 <= _T_282;
end
if (reset) begin
_T_317 <= 9'h0;
end else begin
if (_T_308) begin
if (_T_321) begin
if (_T_314) begin
_T_317 <= _T_313;
end else begin
_T_317 <= 9'h0;
end
end else begin
_T_317 <= _T_320;
end
end
end
end
endmodule
module TLMonitor_20( // @[:freechips.rocketchip.system.LowRiscConfig.fir@51876.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51877.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51878.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@51879.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@53466.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@51896.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51897.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@51902.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@51903.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@51906.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51907.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51915.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51927.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51928.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51929.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51930.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51932.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51933.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51934.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@51935.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@51935.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@51936.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@51938.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@51939.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@51940.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@51941.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@51942.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@51943.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@51944.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@51945.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51947.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51948.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51950.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51951.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@51952.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@51953.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@51954.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51955.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51956.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51957.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51958.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51959.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51960.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51961.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51962.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51963.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51964.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51965.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51966.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@51967.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@51968.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@51969.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51970.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51971.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51972.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51973.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51974.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51975.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51976.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51977.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51978.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51979.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51980.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51981.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51982.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51983.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51984.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51985.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51986.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51987.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51988.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51989.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51990.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51991.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51992.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51993.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@52000.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52011.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@52073.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52076.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52077.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52078.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52079.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52080.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52081.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52082.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52083.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52084.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52085.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52086.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52087.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52088.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52089.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52090.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52093.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52094.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52095.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52096.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52097.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52098.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52099.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52100.8]
wire _T_226; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52101.8]
wire _T_227; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52102.8]
wire _T_228; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52103.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@52109.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@52147.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@52148.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@52160.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@52161.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@52167.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@52168.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@52175.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@52176.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@52182.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@52183.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@52188.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@52190.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@52191.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@52196.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@52197.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@52199.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@52200.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@52205.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@52207.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@52208.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@52214.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@52337.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@52339.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@52340.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@52363.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@52366.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52389.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52390.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52391.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52392.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@52394.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52402.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@52404.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52406.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52407.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@52426.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@52428.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@52429.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@52434.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@52436.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@52437.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@52451.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52481.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@52494.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52496.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52497.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@52533.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@52606.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@52607.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@52608.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@52610.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@52611.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@52617.6]
wire _T_620; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@52627.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52653.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52657.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52658.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@52677.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@52679.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@52680.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@52694.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@52754.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@52756.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@52757.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@52771.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52811.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52812.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@52850.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@52852.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@52853.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@52860.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@52861.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@52866.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@52867.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@52870.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@52871.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@52879.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52891.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52892.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52893.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52894.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@52896.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52899.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52900.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@52905.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@52907.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@52908.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@52913.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@52915.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@52916.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@52921.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@52923.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@52924.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@52929.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@52931.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@52932.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@52938.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@52962.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@52964.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@52965.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@52970.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@52972.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@52973.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@52996.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@53037.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@53039.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@53040.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@53055.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@53090.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@53126.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@53186.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@53191.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@53192.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@53193.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@53195.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53196.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53197.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53198.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53199.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@53210.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@53211.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@53212.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@53213.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@53214.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@53215.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@53216.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@53218.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@53220.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@53221.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@53226.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@53228.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@53229.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@53234.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@53236.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@53237.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@53242.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@53244.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@53245.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@53250.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@53252.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@53253.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@53260.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@53268.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@53270.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@53271.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@53272.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@53273.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@53274.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@53276.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53277.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53278.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53279.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53280.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@53291.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@53292.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@53293.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@53294.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@53295.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@53296.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@53297.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@53298.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@53300.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@53302.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@53303.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@53308.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@53310.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@53311.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@53316.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@53318.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@53319.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@53324.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@53326.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@53327.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@53332.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@53334.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@53335.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@53340.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@53342.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@53343.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@53350.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@53359.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@53369.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53370.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53371.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53372.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53373.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@53392.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53393.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53394.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53395.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53396.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@53411.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@53414.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@53416.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@53417.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@53418.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@53420.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@53421.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@53413.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@53432.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@53434.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@53435.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@53437.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@53407.4 :freechips.rocketchip.system.LowRiscConfig.fir@53409.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@53415.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@53439.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@53440.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@53441.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@53443.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@53444.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@53436.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@53427.4 :freechips.rocketchip.system.LowRiscConfig.fir@53429.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@53438.6]
wire _T_1152; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@53450.4]
wire _T_1153; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@53451.4]
wire _T_1154; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@53452.4]
wire _T_1155; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@53453.4]
wire _T_1157; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@53455.4]
wire _T_1158; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@53456.4]
wire [24:0] _T_1159; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@53461.4]
wire [24:0] _T_1160; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@53462.4]
wire [24:0] _T_1161; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@53463.4]
reg [31:0] _T_1163; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@53465.4]
reg [31:0] _RAND_16;
wire _T_1164; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@53468.4]
wire _T_1165; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@53469.4]
wire _T_1166; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@53470.4]
wire _T_1167; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@53471.4]
wire _T_1168; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@53472.4]
wire _T_1169; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@53473.4]
wire _T_1171; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@53475.4]
wire _T_1172; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@53476.4]
wire [31:0] _T_1174; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@53482.4]
wire _T_1177; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@53486.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@52111.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@52252.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52409.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52499.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@52581.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52660.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@52737.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52814.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52902.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@52944.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@53002.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@53061.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@53096.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@53132.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@53466.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@51896.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51897.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@51902.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@51903.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@51906.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51907.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@51915.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51927.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51928.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51929.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@51930.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@51932.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@51933.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@51934.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@51935.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@51935.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@51936.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@51938.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@51939.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@51940.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@51941.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@51942.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@51943.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@51944.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@51945.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51947.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51948.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51950.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51951.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@51952.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@51953.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@51954.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51955.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51956.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51957.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51958.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51959.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51960.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51961.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51962.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51963.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51964.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51965.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51966.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@51967.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@51968.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@51969.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51970.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51971.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51972.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51973.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51974.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51975.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51976.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51977.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51978.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51979.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51980.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51981.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51982.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51983.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51984.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51985.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51986.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51987.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51988.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51989.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51990.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@51991.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@51992.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@51993.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@52000.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52011.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@52073.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52076.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52077.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52078.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52079.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52080.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52081.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52082.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52083.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52084.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52085.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52086.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52087.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52088.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52089.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52090.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52093.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52094.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52095.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@52096.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@52097.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52098.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@52099.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@52100.8]
assign _T_226 = _T_205 | _T_210; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52101.8]
assign _T_227 = _T_226 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52102.8]
assign _T_228 = _T_227 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52103.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@52109.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@52147.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@52148.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@52160.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@52161.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@52167.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@52168.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@52175.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@52176.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@52182.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@52183.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@52188.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@52190.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@52191.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@52196.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@52197.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@52199.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@52200.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@52205.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@52207.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@52208.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@52214.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@52337.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@52339.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@52340.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@52363.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@52366.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52389.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52390.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@52391.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52392.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@52394.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52402.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@52404.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52406.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52407.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@52426.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@52428.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@52429.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@52434.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@52436.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@52437.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@52451.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52481.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@52494.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52496.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52497.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@52533.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@52606.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@52607.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@52608.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@52610.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@52611.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@52617.6]
assign _T_620 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@52627.8]
assign _T_646 = _T_620 & _T_228; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@52653.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52657.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52658.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@52677.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@52679.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@52680.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@52694.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@52754.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@52756.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@52757.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@52771.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52811.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52812.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@52850.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@52852.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@52853.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@52860.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@52861.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@52866.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@52867.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@52870.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@52871.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@52879.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52891.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52892.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52893.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@52894.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@52896.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52899.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52900.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@52905.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@52907.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@52908.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@52913.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@52915.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@52916.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@52921.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@52923.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@52924.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@52929.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@52931.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@52932.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@52938.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@52962.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@52964.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@52965.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@52970.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@52972.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@52973.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@52996.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@53037.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@53039.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@53040.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@53055.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@53090.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@53126.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@53186.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@53191.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@53192.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@53193.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53196.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53197.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53198.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53199.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@53215.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@53216.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@53218.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@53220.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@53221.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@53226.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@53228.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@53229.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@53234.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@53236.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@53237.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@53242.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@53244.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@53245.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@53250.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@53252.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@53253.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@53260.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@53268.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@53270.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@53271.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@53272.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@53273.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@53274.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53277.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53278.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53279.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53280.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@53297.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@53298.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@53300.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@53302.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@53303.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@53308.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@53310.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@53311.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@53316.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@53318.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@53319.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@53324.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@53326.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@53327.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@53332.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@53334.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@53335.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@53340.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@53342.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@53343.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@53350.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53370.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53371.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53372.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53373.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53393.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53394.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@53395.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@53396.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@53411.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@53414.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@53416.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@53417.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@53418.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@53420.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@53421.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@53413.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@53432.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@53434.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@53435.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@53437.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@53407.4 :freechips.rocketchip.system.LowRiscConfig.fir@53409.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@53415.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@53439.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@53440.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@53441.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@53443.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@53444.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@53436.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@53427.4 :freechips.rocketchip.system.LowRiscConfig.fir@53429.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@53438.6]
assign _T_1152 = _T_1126 != _T_1138; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@53450.4]
assign _T_1153 = _T_1126 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@53451.4]
assign _T_1154 = _T_1153 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@53452.4]
assign _T_1155 = _T_1152 | _T_1154; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@53453.4]
assign _T_1157 = _T_1155 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@53455.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@53456.4]
assign _T_1159 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@53461.4]
assign _T_1160 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@53462.4]
assign _T_1161 = _T_1159 & _T_1160; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@53463.4]
assign _T_1164 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@53468.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@53469.4]
assign _T_1166 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@53470.4]
assign _T_1167 = _T_1165 | _T_1166; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@53471.4]
assign _T_1168 = _T_1163 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@53472.4]
assign _T_1169 = _T_1167 | _T_1168; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@53473.4]
assign _T_1171 = _T_1169 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@53475.4]
assign _T_1172 = _T_1171 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@53476.4]
assign _T_1174 = _T_1163 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@53482.4]
assign _T_1177 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@53486.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@52111.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@52252.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52409.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52499.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@52581.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52660.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@52737.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52814.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52902.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@52944.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@53002.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@53061.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@53096.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@53132.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1163 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1161;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1163 <= 32'h0;
end else begin
if (_T_1177) begin
_T_1163 <= 32'h0;
end else begin
_T_1163 <= _T_1174;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@51891.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@51892.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@52070.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@52071.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@52111.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@52112.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@52163.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@52164.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@52170.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@52171.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@52178.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@52179.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@52185.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@52186.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@52193.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@52194.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@52202.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@52203.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@52210.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@52211.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@52252.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@52253.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@52304.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@52305.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@52311.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@52312.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@52319.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@52320.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@52326.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@52327.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@52334.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@52335.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@52342.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@52343.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@52351.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@52352.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@52359.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@52360.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52409.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@52410.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@52416.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@52417.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@52423.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@52424.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@52431.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@52432.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@52439.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@52440.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@52447.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@52448.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52499.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@52500.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@52506.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@52507.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@52513.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@52514.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@52521.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@52522.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@52529.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@52530.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@52581.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@52582.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@52588.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@52589.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@52595.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@52596.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@52603.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@52604.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@52613.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@52614.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52660.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@52661.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@52667.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@52668.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@52674.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@52675.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@52682.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@52683.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@52690.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@52691.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@52737.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@52738.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@52744.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@52745.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@52751.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@52752.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@52759.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@52760.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@52767.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@52768.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52814.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@52815.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@52821.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@52822.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@52828.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@52829.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@52836.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@52837.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@52844.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@52845.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@52855.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@52856.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52902.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@52903.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@52910.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@52911.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@52918.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@52919.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@52926.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@52927.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@52934.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@52935.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@52944.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@52945.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@52951.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@52952.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@52959.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@52960.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@52967.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@52968.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@52975.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@52976.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@52983.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@52984.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@52992.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@52993.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@53002.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@53003.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@53009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@53010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@53017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@53018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@53025.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@53026.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@53033.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@53034.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@53042.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@53043.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@53051.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@53052.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@53061.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@53062.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@53069.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@53070.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@53077.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@53078.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@53086.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@53087.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@53096.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@53097.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@53104.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@53105.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@53113.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@53114.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@53122.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@53123.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@53132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@53133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@53140.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@53141.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@53148.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@53149.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@53157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@53158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@53167.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@53168.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@53175.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@53176.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@53183.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@53184.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@53223.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@53224.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@53231.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@53232.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@53239.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@53240.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@53247.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@53248.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@53255.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@53256.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@53305.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@53306.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@53313.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@53314.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@53321.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@53322.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@53329.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@53330.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@53337.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@53338.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@53345.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@53346.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@53423.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@53424.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@53446.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@53447.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1158) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@53458.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1158) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@53459.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1172) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:17:14)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@53478.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1172) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@53479.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLXbar_5( // @[:freechips.rocketchip.system.LowRiscConfig.fir@53491.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53492.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53493.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@53494.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
TLMonitor_20 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@53501.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@53541.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@53540.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@53503.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@53504.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@53537.4]
endmodule
module TLMonitor_21( // @[:freechips.rocketchip.system.LowRiscConfig.fir@53674.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53675.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53676.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@53677.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@55253.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@53694.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@53695.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@53700.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@53701.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@53704.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@53705.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@53713.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53725.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53726.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53727.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53728.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@53730.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@53731.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@53732.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@53733.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@53733.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@53734.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@53736.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@53737.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@53738.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@53739.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@53740.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@53741.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@53742.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@53743.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53745.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53746.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53748.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53749.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@53750.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@53751.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@53752.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53753.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53754.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53755.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53756.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53757.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53758.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53759.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53760.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53761.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53762.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53763.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53764.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@53765.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@53766.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@53767.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53768.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53769.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53770.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53771.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53772.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53773.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53774.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53775.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53776.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53777.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53778.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53779.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53780.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53781.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53782.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53783.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53784.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53785.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53786.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53787.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53788.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53789.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53790.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53791.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@53798.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53809.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@53871.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53874.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53875.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53876.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53877.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53878.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53879.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53880.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53881.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53882.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53883.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53884.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53885.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53886.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53887.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53888.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53891.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53892.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53893.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53894.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53895.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53896.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53897.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53898.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@53907.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@53945.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@53946.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@53958.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@53959.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@53965.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@53966.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@53973.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@53974.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@53980.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@53981.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@53986.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@53988.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@53989.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@53994.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@53995.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@53997.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@53998.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@54003.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@54005.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@54006.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@54012.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@54135.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@54137.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@54138.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@54161.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@54164.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@54187.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@54188.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@54189.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54190.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@54192.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54200.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@54202.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54204.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54205.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@54224.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@54226.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@54227.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@54232.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@54234.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@54235.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@54249.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54279.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@54292.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54294.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54295.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@54331.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@54404.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@54405.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@54406.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@54408.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@54409.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@54415.6]
wire _T_638; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@54443.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54451.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54455.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54456.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@54475.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@54477.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@54478.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@54492.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@54552.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@54554.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@54555.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@54569.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54609.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54610.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@54648.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@54650.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@54651.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@54658.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@54659.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@54664.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@54665.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@54668.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@54669.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@54677.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54689.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54690.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54691.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54692.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@54694.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54697.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54698.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@54703.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@54705.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@54706.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@54711.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@54713.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@54714.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@54719.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@54721.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@54722.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@54727.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@54729.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@54730.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@54736.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@54760.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@54762.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@54763.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@54768.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@54770.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@54771.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@54794.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@54835.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@54837.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@54838.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@54853.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@54888.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@54924.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@54984.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@54989.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@54990.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@54991.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@54993.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@54994.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@54995.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@54996.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@54997.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@55008.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@55009.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@55010.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@55011.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@55012.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@55013.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@55014.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@55016.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@55018.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@55019.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@55024.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@55026.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@55027.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@55032.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@55034.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@55035.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@55040.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@55042.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@55043.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@55048.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@55050.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@55051.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@55058.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@55066.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55068.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55069.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55070.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55071.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55072.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@55074.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55075.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55076.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55077.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@55078.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@55089.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@55090.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@55091.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@55092.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@55093.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@55094.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@55095.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@55096.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@55098.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@55100.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@55101.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@55106.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@55108.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@55109.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@55114.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@55116.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@55117.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@55122.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@55124.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@55125.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@55130.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@55132.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@55133.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@55138.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@55140.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@55141.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@55148.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@55157.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@55167.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55168.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55169.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55170.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@55171.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@55190.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55191.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55192.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55193.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@55194.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@55209.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@55212.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@55214.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@55215.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@55216.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@55218.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@55219.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@55211.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@55230.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@55232.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@55233.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@55235.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@55205.4 :freechips.rocketchip.system.LowRiscConfig.fir@55207.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@55213.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@55237.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@55238.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@55239.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@55241.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@55242.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@55234.4]
wire [24:0] _T_1152; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@55248.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@55225.4 :freechips.rocketchip.system.LowRiscConfig.fir@55227.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@55236.6]
wire [24:0] _T_1153; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@55249.4]
wire [24:0] _T_1154; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@55250.4]
reg [31:0] _T_1156; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@55252.4]
reg [31:0] _RAND_16;
wire _T_1157; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@55255.4]
wire _T_1158; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@55256.4]
wire _T_1159; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@55257.4]
wire _T_1160; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@55258.4]
wire _T_1161; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@55259.4]
wire _T_1162; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@55260.4]
wire _T_1164; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@55262.4]
wire _T_1165; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@55263.4]
wire [31:0] _T_1167; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@55269.4]
wire _T_1170; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@55273.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@53909.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@54050.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54207.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54297.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@54379.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54458.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@54535.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54612.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54700.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@54742.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@54800.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@54859.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@54894.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@54930.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@55253.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@53694.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@53695.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@53700.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@53701.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@53704.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@53705.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@53713.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53725.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53726.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53727.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@53728.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@53730.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@53731.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@53732.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@53733.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@53733.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@53734.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@53736.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@53737.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@53738.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@53739.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@53740.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@53741.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@53742.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@53743.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53745.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53746.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53748.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53749.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@53750.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@53751.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@53752.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53753.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53754.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53755.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53756.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53757.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53758.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53759.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53760.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53761.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53762.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53763.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53764.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@53765.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@53766.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@53767.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53768.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53769.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53770.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53771.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53772.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53773.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53774.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53775.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53776.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53777.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53778.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53779.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53780.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53781.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53782.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53783.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53784.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53785.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53786.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53787.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53788.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@53789.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@53790.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@53791.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@53798.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53809.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@53871.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53874.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53875.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53876.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53877.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53878.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53879.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53880.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53881.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53882.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53883.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53884.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53885.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53886.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53887.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53888.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53891.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53892.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53893.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@53894.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@53895.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53896.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@53897.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@53898.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@53907.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@53945.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@53946.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@53958.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@53959.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@53965.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@53966.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@53973.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@53974.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@53980.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@53981.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@53986.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@53988.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@53989.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@53994.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@53995.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@53997.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@53998.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@54003.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@54005.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@54006.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@54012.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@54135.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@54137.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@54138.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@54161.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@54164.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@54187.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@54188.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@54189.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54190.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@54192.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54200.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@54202.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54204.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54205.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@54224.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@54226.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@54227.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@54232.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@54234.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@54235.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@54249.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54279.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@54292.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54294.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54295.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@54331.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@54404.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@54405.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@54406.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@54408.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@54409.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@54415.6]
assign _T_638 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@54443.8]
assign _T_646 = _T_638 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@54451.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54455.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54456.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@54475.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@54477.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@54478.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@54492.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@54552.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@54554.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@54555.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@54569.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54609.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54610.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@54648.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@54650.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@54651.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@54658.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@54659.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@54664.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@54665.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@54668.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@54669.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@54677.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54689.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54690.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54691.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@54692.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@54694.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54697.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54698.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@54703.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@54705.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@54706.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@54711.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@54713.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@54714.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@54719.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@54721.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@54722.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@54727.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@54729.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@54730.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@54736.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@54760.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@54762.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@54763.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@54768.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@54770.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@54771.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@54794.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@54835.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@54837.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@54838.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@54853.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@54888.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@54924.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@54984.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@54989.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@54990.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@54991.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@54994.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@54995.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@54996.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@54997.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@55013.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@55014.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@55016.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@55018.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@55019.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@55024.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@55026.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@55027.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@55032.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@55034.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@55035.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@55040.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@55042.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@55043.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@55048.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@55050.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@55051.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@55058.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@55066.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55068.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55069.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55070.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55071.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55072.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55075.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55076.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55077.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@55078.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@55095.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@55096.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@55098.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@55100.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@55101.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@55106.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@55108.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@55109.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@55114.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@55116.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@55117.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@55122.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@55124.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@55125.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@55130.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@55132.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@55133.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@55138.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@55140.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@55141.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@55148.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55168.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55169.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55170.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@55171.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55191.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55192.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@55193.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@55194.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@55209.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@55212.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@55214.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@55215.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@55216.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@55218.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@55219.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@55211.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@55230.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@55232.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@55233.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@55235.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@55205.4 :freechips.rocketchip.system.LowRiscConfig.fir@55207.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@55213.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@55237.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@55238.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@55239.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@55241.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@55242.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@55234.4]
assign _T_1152 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@55248.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@55225.4 :freechips.rocketchip.system.LowRiscConfig.fir@55227.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@55236.6]
assign _T_1153 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@55249.4]
assign _T_1154 = _T_1152 & _T_1153; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@55250.4]
assign _T_1157 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@55255.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@55256.4]
assign _T_1159 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@55257.4]
assign _T_1160 = _T_1158 | _T_1159; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@55258.4]
assign _T_1161 = _T_1156 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@55259.4]
assign _T_1162 = _T_1160 | _T_1161; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@55260.4]
assign _T_1164 = _T_1162 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@55262.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@55263.4]
assign _T_1167 = _T_1156 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@55269.4]
assign _T_1170 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@55273.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@53909.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@54050.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54207.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54297.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@54379.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54458.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@54535.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54612.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54700.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@54742.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@54800.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@54859.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@54894.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@54930.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1156 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1154;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1156 <= 32'h0;
end else begin
if (_T_1170) begin
_T_1156 <= 32'h0;
end else begin
_T_1156 <= _T_1167;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@53689.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@53690.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@53868.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@53869.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@53909.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@53910.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@53961.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@53962.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@53968.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@53969.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@53976.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@53977.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@53983.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@53984.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@53991.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@53992.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@54000.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@54001.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@54008.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@54009.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@54050.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@54051.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@54102.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@54103.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@54109.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@54110.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@54117.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@54118.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@54124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@54125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@54132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@54133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@54140.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@54141.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@54149.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@54150.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@54157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@54158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@54208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@54214.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@54215.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@54221.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@54222.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@54229.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@54230.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@54237.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@54238.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@54245.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@54246.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54297.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@54298.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@54304.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@54305.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@54311.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@54312.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@54319.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@54320.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@54327.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@54328.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@54379.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@54380.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@54386.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@54387.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@54393.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@54394.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@54401.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@54402.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@54411.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@54412.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@54459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@54465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@54466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@54472.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@54473.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@54480.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@54481.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@54488.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@54489.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@54535.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@54536.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@54542.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@54543.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@54549.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@54550.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@54557.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@54558.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@54565.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@54566.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54612.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@54613.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@54619.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@54620.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@54626.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@54627.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@54634.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@54635.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@54642.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@54643.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@54653.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@54654.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54700.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@54701.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@54708.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@54709.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@54716.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@54717.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@54724.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@54725.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@54732.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@54733.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@54742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@54743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@54749.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@54750.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@54757.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@54758.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@54765.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@54766.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@54773.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@54774.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@54781.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@54782.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@54790.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@54791.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@54800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@54801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@54807.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@54808.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@54815.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@54816.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@54823.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@54824.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@54831.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@54832.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@54840.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@54841.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@54849.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@54850.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@54859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@54860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@54867.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@54868.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@54875.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@54876.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@54884.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@54885.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@54894.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@54895.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@54902.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@54903.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@54911.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@54912.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@54920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@54921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@54930.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@54931.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@54938.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@54939.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@54946.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@54947.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@54955.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@54956.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@54965.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@54966.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@54973.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@54974.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@54981.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@54982.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@55021.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@55022.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@55029.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@55030.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@55037.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@55038.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@55045.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@55046.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@55053.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@55054.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@55103.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@55104.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@55111.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@55112.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@55119.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@55120.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@55127.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@55128.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@55135.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@55136.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@55143.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@55144.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@55221.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@55222.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@55244.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@55245.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1165) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:41:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@55265.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1165) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@55266.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLXbar_6( // @[:freechips.rocketchip.system.LowRiscConfig.fir@55278.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55279.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55280.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_4_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_4_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_4_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_4_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_4_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [4:0] auto_out_4_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [16:0] auto_out_4_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [7:0] auto_out_4_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_4_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_4_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_4_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_4_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [4:0] auto_out_4_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [63:0] auto_out_4_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_3_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_3_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_3_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_3_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_3_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [4:0] auto_out_3_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [11:0] auto_out_3_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [7:0] auto_out_3_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [63:0] auto_out_3_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_3_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_3_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_3_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_3_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_3_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [4:0] auto_out_3_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [63:0] auto_out_3_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_2_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_2_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_2_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_2_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_2_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [4:0] auto_out_2_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [25:0] auto_out_2_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [7:0] auto_out_2_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [63:0] auto_out_2_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_2_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_2_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_2_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_2_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_2_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [4:0] auto_out_2_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [63:0] auto_out_2_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_1_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_1_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_1_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_1_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_1_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [4:0] auto_out_1_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [27:0] auto_out_1_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [7:0] auto_out_1_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [63:0] auto_out_1_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_1_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_1_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_1_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_1_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_1_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [4:0] auto_out_1_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [63:0] auto_out_1_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_0_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_0_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_0_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [2:0] auto_out_0_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [3:0] auto_out_0_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [4:0] auto_out_0_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [13:0] auto_out_0_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output [7:0] auto_out_0_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_0_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
output auto_out_0_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_0_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [2:0] auto_out_0_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [1:0] auto_out_0_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [3:0] auto_out_0_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [4:0] auto_out_0_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_0_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_0_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input [63:0] auto_out_0_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
input auto_out_0_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@55281.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
reg [8:0] _T_1753; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@55825.4]
reg [31:0] _RAND_0;
wire _T_1754; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@55826.4]
wire [4:0] _T_1759; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@55831.4]
reg [4:0] _T_1767; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@55842.4]
reg [31:0] _RAND_1;
wire [4:0] _T_1768; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@55843.4]
wire [4:0] _T_1769; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@55844.4]
wire [9:0] _T_1770; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@55845.4]
wire [8:0] _T_1771; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@55846.4]
wire [9:0] _GEN_1; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55847.4]
wire [9:0] _T_1772; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55847.4]
wire [7:0] _T_1773; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@55848.4]
wire [9:0] _GEN_2; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55849.4]
wire [9:0] _T_1774; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55849.4]
wire [5:0] _T_1775; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@55850.4]
wire [9:0] _GEN_3; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55851.4]
wire [9:0] _T_1776; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55851.4]
wire [8:0] _T_1778; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@55853.4]
wire [9:0] _GEN_4; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@55854.4]
wire [9:0] _T_1779; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@55854.4]
wire [9:0] _GEN_5; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@55855.4]
wire [9:0] _T_1780; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@55855.4]
wire [4:0] _T_1781; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@55856.4]
wire [4:0] _T_1782; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@55857.4]
wire [4:0] _T_1783; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@55858.4]
wire [4:0] _T_1784; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@55859.4]
wire _T_1799; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55877.4]
wire _T_1815; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55889.4]
reg _T_1910_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@55971.4]
reg [31:0] _RAND_2;
wire _T_1930_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
wire [80:0] _T_1987; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56008.4]
wire [80:0] _T_1988; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56009.4]
wire _T_1800; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55878.4]
wire _T_1816; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55890.4]
reg _T_1910_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@55971.4]
reg [31:0] _RAND_3;
wire _T_1930_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
wire [3:0] out_1_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55372.4]
wire [80:0] _T_1995; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56016.4]
wire [80:0] _T_1996; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56017.4]
wire [80:0] _T_2021; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56042.4]
wire _T_1801; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55879.4]
wire _T_1817; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55891.4]
reg _T_1910_2; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@55971.4]
reg [31:0] _RAND_4;
wire _T_1930_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
wire [3:0] out_2_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55382.4]
wire [80:0] _T_2003; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56024.4]
wire [80:0] _T_2004; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56025.4]
wire [80:0] _T_2022; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56043.4]
wire _T_1802; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55880.4]
wire _T_1818; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55892.4]
reg _T_1910_3; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@55971.4]
reg [31:0] _RAND_5;
wire _T_1930_3; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
wire [3:0] out_3_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55392.4]
wire [80:0] _T_2011; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56032.4]
wire [80:0] _T_2012; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56033.4]
wire [80:0] _T_2023; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56044.4]
wire _T_1803; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55881.4]
wire _T_1819; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55893.4]
reg _T_1910_4; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@55971.4]
reg [31:0] _RAND_6;
wire _T_1930_4; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
wire [3:0] out_4_d_bits_size; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55402.4]
wire [80:0] _T_2019; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56040.4]
wire [80:0] _T_2020; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56041.4]
wire [80:0] _T_2024; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56045.4]
wire [27:0] _T_1150; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55407.4]
wire [28:0] _T_1151; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55408.4]
wire [28:0] _T_1152; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55409.4]
wire [28:0] _T_1153; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55410.4]
wire requestAIO_0_0; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55411.4]
wire [27:0] _T_1155; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55413.4]
wire [28:0] _T_1156; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55414.4]
wire [28:0] _T_1157; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55415.4]
wire [28:0] _T_1158; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55416.4]
wire requestAIO_0_1; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55417.4]
wire [27:0] _T_1160; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55419.4]
wire [28:0] _T_1161; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55420.4]
wire [28:0] _T_1162; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55421.4]
wire [28:0] _T_1163; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55422.4]
wire requestAIO_0_2; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55423.4]
wire [28:0] _T_1166; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55426.4]
wire [28:0] _T_1167; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55427.4]
wire [28:0] _T_1168; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55428.4]
wire requestAIO_0_3; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55429.4]
wire [27:0] _T_1170; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55431.4]
wire [28:0] _T_1171; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55432.4]
wire [28:0] _T_1172; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55433.4]
wire [28:0] _T_1173; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55434.4]
wire requestAIO_0_4; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55435.4]
wire [26:0] _T_1319; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55603.4]
wire [11:0] _T_1320; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55604.4]
wire [11:0] _T_1321; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55605.4]
wire [8:0] _T_1322; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55606.4]
wire _T_1323; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55607.4]
wire [8:0] beatsDO_0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55608.4]
wire [20:0] _T_1325; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55610.4]
wire [5:0] _T_1326; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55611.4]
wire [5:0] _T_1327; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55612.4]
wire [2:0] _T_1328; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55613.4]
wire _T_1329; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55614.4]
wire [2:0] beatsDO_1; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55615.4]
wire [20:0] _T_1331; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55617.4]
wire [5:0] _T_1332; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55618.4]
wire [5:0] _T_1333; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55619.4]
wire [2:0] _T_1334; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55620.4]
wire _T_1335; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55621.4]
wire [2:0] beatsDO_2; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55622.4]
wire [20:0] _T_1337; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55624.4]
wire [5:0] _T_1338; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55625.4]
wire [5:0] _T_1339; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55626.4]
wire [2:0] _T_1340; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55627.4]
wire _T_1341; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55628.4]
wire [2:0] beatsDO_3; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55629.4]
wire [20:0] _T_1343; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55631.4]
wire [5:0] _T_1344; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55632.4]
wire [5:0] _T_1345; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55633.4]
wire [2:0] beatsDO_4; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55634.4]
wire _T_1405; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55659.4]
wire _T_1406; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55660.4]
wire _T_1407; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55661.4]
wire _T_1408; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55662.4]
wire _T_1409; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55663.4]
wire _T_1410; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55664.4]
wire _T_1411; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55665.4]
wire _T_1412; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55666.4]
wire _T_1755; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@55827.4]
wire _T_1761; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@55833.4]
wire _T_1763; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@55835.4]
wire _T_1764; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@55836.4]
wire _T_1785; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@55860.4]
wire _T_1786; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@55861.4]
wire [4:0] _T_1787; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@55863.6]
wire [5:0] _GEN_6; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55864.6]
wire [5:0] _T_1788; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55864.6]
wire [4:0] _T_1789; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@55865.6]
wire [4:0] _T_1790; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@55866.6]
wire [6:0] _GEN_7; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55867.6]
wire [6:0] _T_1791; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55867.6]
wire [4:0] _T_1792; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@55868.6]
wire [4:0] _T_1793; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@55869.6]
wire [8:0] _GEN_8; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55870.6]
wire [8:0] _T_1794; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55870.6]
wire [4:0] _T_1795; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@55871.6]
wire [4:0] _T_1796; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@55872.6]
wire _T_1832; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55902.4]
wire _T_1833; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55903.4]
wire _T_1834; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55904.4]
wire _T_1835; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55905.4]
wire _T_1837; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55907.4]
wire _T_1840; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55910.4]
wire _T_1841; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55911.4]
wire _T_1842; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@55912.4]
wire _T_1843; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55913.4]
wire _T_1844; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55914.4]
wire _T_1845; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@55915.4]
wire _T_1846; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55916.4]
wire _T_1847; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55917.4]
wire _T_1848; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@55918.4]
wire _T_1849; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55919.4]
wire _T_1850; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55920.4]
wire _T_1852; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@55922.4]
wire _T_1853; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@55923.4]
wire _T_1854; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@55924.4]
wire _T_1856; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@55926.4]
wire _T_1857; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@55927.4]
wire _T_1858; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55932.4]
wire _T_1859; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55933.4]
wire _T_1860; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55934.4]
wire _T_1861; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55935.4]
wire _T_1862; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@55936.4]
wire _T_1867; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@55941.4]
wire _T_1869; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@55943.4]
wire _T_1870; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@55944.4]
wire [8:0] _T_1871; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55949.4]
wire [2:0] _T_1872; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55950.4]
wire [2:0] _T_1873; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55951.4]
wire [2:0] _T_1874; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55952.4]
wire [2:0] _T_1875; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55953.4]
wire [8:0] _GEN_9; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55954.4]
wire [8:0] _T_1876; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55954.4]
wire [8:0] _GEN_10; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55955.4]
wire [8:0] _T_1877; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55955.4]
wire [8:0] _GEN_11; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55956.4]
wire [8:0] _T_1878; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55956.4]
wire [8:0] _GEN_12; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55957.4]
wire [8:0] _T_1879; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55957.4]
wire _T_1968; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55989.4]
wire _T_1969; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55990.4]
wire _T_1973; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55994.4]
wire _T_1970; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55991.4]
wire _T_1974; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55995.4]
wire _T_1971; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55992.4]
wire _T_1975; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55996.4]
wire _T_1972; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55993.4]
wire _T_1976; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55997.4]
wire in_0_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@56000.4]
wire _T_1880; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@55958.4]
wire [8:0] _GEN_13; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55959.4]
wire [9:0] _T_1881; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55959.4]
wire [9:0] _T_1882; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55960.4]
wire [8:0] _T_1883; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55961.4]
wire _T_1944_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
wire _T_1944_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
wire _T_1944_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
wire _T_1944_3; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
wire _T_1944_4; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
TLMonitor_21 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@55288.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign _T_1754 = _T_1753 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@55826.4]
assign _T_1759 = {auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@55831.4]
assign _T_1768 = ~ _T_1767; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@55843.4]
assign _T_1769 = _T_1759 & _T_1768; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@55844.4]
assign _T_1770 = {_T_1769,auto_out_4_d_valid,auto_out_3_d_valid,auto_out_2_d_valid,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@55845.4]
assign _T_1771 = _T_1770[9:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@55846.4]
assign _GEN_1 = {{1'd0}, _T_1771}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55847.4]
assign _T_1772 = _T_1770 | _GEN_1; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55847.4]
assign _T_1773 = _T_1772[9:2]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@55848.4]
assign _GEN_2 = {{2'd0}, _T_1773}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55849.4]
assign _T_1774 = _T_1772 | _GEN_2; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55849.4]
assign _T_1775 = _T_1774[9:4]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@55850.4]
assign _GEN_3 = {{4'd0}, _T_1775}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55851.4]
assign _T_1776 = _T_1774 | _GEN_3; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@55851.4]
assign _T_1778 = _T_1776[9:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@55853.4]
assign _GEN_4 = {{5'd0}, _T_1767}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@55854.4]
assign _T_1779 = _GEN_4 << 5; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@55854.4]
assign _GEN_5 = {{1'd0}, _T_1778}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@55855.4]
assign _T_1780 = _GEN_5 | _T_1779; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@55855.4]
assign _T_1781 = _T_1780[9:5]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@55856.4]
assign _T_1782 = _T_1780[4:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@55857.4]
assign _T_1783 = _T_1781 & _T_1782; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@55858.4]
assign _T_1784 = ~ _T_1783; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@55859.4]
assign _T_1799 = _T_1784[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55877.4]
assign _T_1815 = _T_1799 & auto_out_0_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55889.4]
assign _T_1930_0 = _T_1754 ? _T_1815 : _T_1910_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
assign _T_1987 = {auto_out_0_d_bits_opcode,auto_out_0_d_bits_param,auto_out_0_d_bits_size,auto_out_0_d_bits_source,auto_out_0_d_bits_sink,auto_out_0_d_bits_denied,auto_out_0_d_bits_data,auto_out_0_d_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56008.4]
assign _T_1988 = _T_1930_0 ? _T_1987 : 81'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56009.4]
assign _T_1800 = _T_1784[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55878.4]
assign _T_1816 = _T_1800 & auto_out_1_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55890.4]
assign _T_1930_1 = _T_1754 ? _T_1816 : _T_1910_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
assign out_1_d_bits_size = {{1'd0}, auto_out_1_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55372.4]
assign _T_1995 = {auto_out_1_d_bits_opcode,2'h0,out_1_d_bits_size,auto_out_1_d_bits_source,2'h0,auto_out_1_d_bits_data,1'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56016.4]
assign _T_1996 = _T_1930_1 ? _T_1995 : 81'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56017.4]
assign _T_2021 = _T_1988 | _T_1996; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56042.4]
assign _T_1801 = _T_1784[2]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55879.4]
assign _T_1817 = _T_1801 & auto_out_2_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55891.4]
assign _T_1930_2 = _T_1754 ? _T_1817 : _T_1910_2; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
assign out_2_d_bits_size = {{1'd0}, auto_out_2_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55382.4]
assign _T_2003 = {auto_out_2_d_bits_opcode,2'h0,out_2_d_bits_size,auto_out_2_d_bits_source,2'h0,auto_out_2_d_bits_data,1'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56024.4]
assign _T_2004 = _T_1930_2 ? _T_2003 : 81'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56025.4]
assign _T_2022 = _T_2021 | _T_2004; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56043.4]
assign _T_1802 = _T_1784[3]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55880.4]
assign _T_1818 = _T_1802 & auto_out_3_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55892.4]
assign _T_1930_3 = _T_1754 ? _T_1818 : _T_1910_3; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
assign out_3_d_bits_size = {{1'd0}, auto_out_3_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55392.4]
assign _T_2011 = {auto_out_3_d_bits_opcode,2'h0,out_3_d_bits_size,auto_out_3_d_bits_source,2'h0,auto_out_3_d_bits_data,1'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56032.4]
assign _T_2012 = _T_1930_3 ? _T_2011 : 81'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56033.4]
assign _T_2023 = _T_2022 | _T_2012; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56044.4]
assign _T_1803 = _T_1784[4]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@55881.4]
assign _T_1819 = _T_1803 & auto_out_4_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@55893.4]
assign _T_1930_4 = _T_1754 ? _T_1819 : _T_1910_4; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@55972.4]
assign out_4_d_bits_size = {{1'd0}, auto_out_4_d_bits_size}; // @[Xbar.scala 154:19:freechips.rocketchip.system.LowRiscConfig.fir@55355.4 Xbar.scala 180:18:freechips.rocketchip.system.LowRiscConfig.fir@55402.4]
assign _T_2019 = {5'h4,out_4_d_bits_size,auto_out_4_d_bits_source,2'h0,auto_out_4_d_bits_data,1'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56040.4]
assign _T_2020 = _T_1930_4 ? _T_2019 : 81'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56041.4]
assign _T_2024 = _T_2023 | _T_2020; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56045.4]
assign _T_1150 = auto_in_a_bits_address ^ 28'h2000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55407.4]
assign _T_1151 = {1'b0,$signed(_T_1150)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55408.4]
assign _T_1152 = $signed(_T_1151) & $signed(29'sha012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55409.4]
assign _T_1153 = $signed(_T_1152); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55410.4]
assign requestAIO_0_0 = $signed(_T_1153) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55411.4]
assign _T_1155 = auto_in_a_bits_address ^ 28'h8000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55413.4]
assign _T_1156 = {1'b0,$signed(_T_1155)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55414.4]
assign _T_1157 = $signed(_T_1156) & $signed(29'sh8000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55415.4]
assign _T_1158 = $signed(_T_1157); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55416.4]
assign requestAIO_0_1 = $signed(_T_1158) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55417.4]
assign _T_1160 = auto_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55419.4]
assign _T_1161 = {1'b0,$signed(_T_1160)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55420.4]
assign _T_1162 = $signed(_T_1161) & $signed(29'sha010000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55421.4]
assign _T_1163 = $signed(_T_1162); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55422.4]
assign requestAIO_0_2 = $signed(_T_1163) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55423.4]
assign _T_1166 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55426.4]
assign _T_1167 = $signed(_T_1166) & $signed(29'sha012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55427.4]
assign _T_1168 = $signed(_T_1167); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55428.4]
assign requestAIO_0_3 = $signed(_T_1168) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55429.4]
assign _T_1170 = auto_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@55431.4]
assign _T_1171 = {1'b0,$signed(_T_1170)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@55432.4]
assign _T_1172 = $signed(_T_1171) & $signed(29'sha010000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55433.4]
assign _T_1173 = $signed(_T_1172); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@55434.4]
assign requestAIO_0_4 = $signed(_T_1173) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@55435.4]
assign _T_1319 = 27'hfff << auto_out_0_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55603.4]
assign _T_1320 = _T_1319[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55604.4]
assign _T_1321 = ~ _T_1320; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55605.4]
assign _T_1322 = _T_1321[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55606.4]
assign _T_1323 = auto_out_0_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55607.4]
assign beatsDO_0 = _T_1323 ? _T_1322 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55608.4]
assign _T_1325 = 21'h3f << out_1_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55610.4]
assign _T_1326 = _T_1325[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55611.4]
assign _T_1327 = ~ _T_1326; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55612.4]
assign _T_1328 = _T_1327[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55613.4]
assign _T_1329 = auto_out_1_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55614.4]
assign beatsDO_1 = _T_1329 ? _T_1328 : 3'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55615.4]
assign _T_1331 = 21'h3f << out_2_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55617.4]
assign _T_1332 = _T_1331[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55618.4]
assign _T_1333 = ~ _T_1332; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55619.4]
assign _T_1334 = _T_1333[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55620.4]
assign _T_1335 = auto_out_2_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55621.4]
assign beatsDO_2 = _T_1335 ? _T_1334 : 3'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55622.4]
assign _T_1337 = 21'h3f << out_3_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55624.4]
assign _T_1338 = _T_1337[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55625.4]
assign _T_1339 = ~ _T_1338; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55626.4]
assign _T_1340 = _T_1339[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55627.4]
assign _T_1341 = auto_out_3_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@55628.4]
assign beatsDO_3 = _T_1341 ? _T_1340 : 3'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@55629.4]
assign _T_1343 = 21'h3f << out_4_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@55631.4]
assign _T_1344 = _T_1343[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@55632.4]
assign _T_1345 = ~ _T_1344; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@55633.4]
assign beatsDO_4 = _T_1345[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@55634.4]
assign _T_1405 = requestAIO_0_0 ? auto_out_0_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55659.4]
assign _T_1406 = requestAIO_0_1 ? auto_out_1_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55660.4]
assign _T_1407 = requestAIO_0_2 ? auto_out_2_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55661.4]
assign _T_1408 = requestAIO_0_3 ? auto_out_3_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55662.4]
assign _T_1409 = requestAIO_0_4 ? auto_out_4_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55663.4]
assign _T_1410 = _T_1405 | _T_1406; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55664.4]
assign _T_1411 = _T_1410 | _T_1407; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55665.4]
assign _T_1412 = _T_1411 | _T_1408; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55666.4]
assign _T_1755 = _T_1754 & auto_in_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@55827.4]
assign _T_1761 = _T_1759 == _T_1759; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@55833.4]
assign _T_1763 = _T_1761 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@55835.4]
assign _T_1764 = _T_1763 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@55836.4]
assign _T_1785 = _T_1759 != 5'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@55860.4]
assign _T_1786 = _T_1755 & _T_1785; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@55861.4]
assign _T_1787 = _T_1784 & _T_1759; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@55863.6]
assign _GEN_6 = {{1'd0}, _T_1787}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55864.6]
assign _T_1788 = _GEN_6 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55864.6]
assign _T_1789 = _T_1788[4:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@55865.6]
assign _T_1790 = _T_1787 | _T_1789; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@55866.6]
assign _GEN_7 = {{2'd0}, _T_1790}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55867.6]
assign _T_1791 = _GEN_7 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55867.6]
assign _T_1792 = _T_1791[4:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@55868.6]
assign _T_1793 = _T_1790 | _T_1792; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@55869.6]
assign _GEN_8 = {{4'd0}, _T_1793}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55870.6]
assign _T_1794 = _GEN_8 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@55870.6]
assign _T_1795 = _T_1794[4:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@55871.6]
assign _T_1796 = _T_1793 | _T_1795; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@55872.6]
assign _T_1832 = _T_1815 | _T_1816; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55902.4]
assign _T_1833 = _T_1832 | _T_1817; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55903.4]
assign _T_1834 = _T_1833 | _T_1818; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55904.4]
assign _T_1835 = _T_1834 | _T_1819; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@55905.4]
assign _T_1837 = _T_1815 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55907.4]
assign _T_1840 = _T_1816 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55910.4]
assign _T_1841 = _T_1837 | _T_1840; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55911.4]
assign _T_1842 = _T_1832 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@55912.4]
assign _T_1843 = _T_1817 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55913.4]
assign _T_1844 = _T_1842 | _T_1843; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55914.4]
assign _T_1845 = _T_1833 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@55915.4]
assign _T_1846 = _T_1818 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55916.4]
assign _T_1847 = _T_1845 | _T_1846; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55917.4]
assign _T_1848 = _T_1834 == 1'h0; // @[Arbiter.scala 68:56:freechips.rocketchip.system.LowRiscConfig.fir@55918.4]
assign _T_1849 = _T_1819 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@55919.4]
assign _T_1850 = _T_1848 | _T_1849; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@55920.4]
assign _T_1852 = _T_1841 & _T_1844; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@55922.4]
assign _T_1853 = _T_1852 & _T_1847; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@55923.4]
assign _T_1854 = _T_1853 & _T_1850; // @[Arbiter.scala 68:77:freechips.rocketchip.system.LowRiscConfig.fir@55924.4]
assign _T_1856 = _T_1854 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@55926.4]
assign _T_1857 = _T_1856 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@55927.4]
assign _T_1858 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55932.4]
assign _T_1859 = _T_1858 | auto_out_2_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55933.4]
assign _T_1860 = _T_1859 | auto_out_3_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55934.4]
assign _T_1861 = _T_1860 | auto_out_4_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@55935.4]
assign _T_1862 = _T_1861 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@55936.4]
assign _T_1867 = _T_1862 | _T_1835; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@55941.4]
assign _T_1869 = _T_1867 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@55943.4]
assign _T_1870 = _T_1869 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@55944.4]
assign _T_1871 = _T_1815 ? beatsDO_0 : 9'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55949.4]
assign _T_1872 = _T_1816 ? beatsDO_1 : 3'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55950.4]
assign _T_1873 = _T_1817 ? beatsDO_2 : 3'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55951.4]
assign _T_1874 = _T_1818 ? beatsDO_3 : 3'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55952.4]
assign _T_1875 = _T_1819 ? beatsDO_4 : 3'h0; // @[Arbiter.scala 73:69:freechips.rocketchip.system.LowRiscConfig.fir@55953.4]
assign _GEN_9 = {{6'd0}, _T_1872}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55954.4]
assign _T_1876 = _T_1871 | _GEN_9; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55954.4]
assign _GEN_10 = {{6'd0}, _T_1873}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55955.4]
assign _T_1877 = _T_1876 | _GEN_10; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55955.4]
assign _GEN_11 = {{6'd0}, _T_1874}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55956.4]
assign _T_1878 = _T_1877 | _GEN_11; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55956.4]
assign _GEN_12 = {{6'd0}, _T_1875}; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55957.4]
assign _T_1879 = _T_1878 | _GEN_12; // @[Arbiter.scala 74:44:freechips.rocketchip.system.LowRiscConfig.fir@55957.4]
assign _T_1968 = _T_1910_0 ? auto_out_0_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55989.4]
assign _T_1969 = _T_1910_1 ? auto_out_1_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55990.4]
assign _T_1973 = _T_1968 | _T_1969; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55994.4]
assign _T_1970 = _T_1910_2 ? auto_out_2_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55991.4]
assign _T_1974 = _T_1973 | _T_1970; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55995.4]
assign _T_1971 = _T_1910_3 ? auto_out_3_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55992.4]
assign _T_1975 = _T_1974 | _T_1971; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55996.4]
assign _T_1972 = _T_1910_4 ? auto_out_4_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55993.4]
assign _T_1976 = _T_1975 | _T_1972; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@55997.4]
assign in_0_d_valid = _T_1754 ? _T_1861 : _T_1976; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@56000.4]
assign _T_1880 = auto_in_d_ready & in_0_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@55958.4]
assign _GEN_13 = {{8'd0}, _T_1880}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55959.4]
assign _T_1881 = _T_1753 - _GEN_13; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55959.4]
assign _T_1882 = $unsigned(_T_1881); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55960.4]
assign _T_1883 = _T_1882[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@55961.4]
assign _T_1944_0 = _T_1754 ? _T_1799 : _T_1910_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
assign _T_1944_1 = _T_1754 ? _T_1800 : _T_1910_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
assign _T_1944_2 = _T_1754 ? _T_1801 : _T_1910_2; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
assign _T_1944_3 = _T_1754 ? _T_1802 : _T_1910_3; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
assign _T_1944_4 = _T_1754 ? _T_1803 : _T_1910_4; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@55974.4]
assign auto_in_a_ready = _T_1412 | _T_1409; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_valid = _T_1754 ? _T_1861 : _T_1976; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_opcode = _T_2024[80:78]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_param = _T_2024[77:76]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_size = _T_2024[75:72]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_source = _T_2024[71:67]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_sink = _T_2024[66]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_denied = _T_2024[65]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_data = _T_2024[64:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_in_d_bits_corrupt = _T_2024[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@55340.4]
assign auto_out_4_a_valid = auto_in_a_valid & requestAIO_0_4; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_address = auto_in_a_bits_address[16:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_4_d_ready = auto_in_d_ready & _T_1944_4; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55339.4]
assign auto_out_3_a_valid = auto_in_a_valid & requestAIO_0_3; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_address = auto_in_a_bits_address[11:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_3_d_ready = auto_in_d_ready & _T_1944_3; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55338.4]
assign auto_out_2_a_valid = auto_in_a_valid & requestAIO_0_2; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_address = auto_in_a_bits_address[25:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_2_d_ready = auto_in_d_ready & _T_1944_2; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55337.4]
assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_size = auto_in_a_bits_size[2:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_1_d_ready = auto_in_d_ready & _T_1944_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55336.4]
assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_address = auto_in_a_bits_address[13:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign auto_out_0_d_ready = auto_in_d_ready & _T_1944_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@55335.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@55290.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@55291.4]
assign TLMonitor_io_in_a_ready = _T_1412 | _T_1409; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_valid = _T_1754 ? _T_1861 : _T_1976; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_opcode = _T_2024[80:78]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_param = _T_2024[77:76]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_size = _T_2024[75:72]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_source = _T_2024[71:67]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_sink = _T_2024[66]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_denied = _T_2024[65]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
assign TLMonitor_io_in_d_bits_corrupt = _T_2024[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@55324.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1753 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1767 = _RAND_1[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1910_0 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1910_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_1910_2 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_1910_3 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1910_4 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_1753 <= 9'h0;
end else begin
if (_T_1755) begin
_T_1753 <= _T_1879;
end else begin
_T_1753 <= _T_1883;
end
end
if (reset) begin
_T_1767 <= 5'h1f;
end else begin
if (_T_1786) begin
_T_1767 <= _T_1796;
end
end
if (reset) begin
_T_1910_0 <= 1'h0;
end else begin
if (_T_1754) begin
_T_1910_0 <= _T_1815;
end
end
if (reset) begin
_T_1910_1 <= 1'h0;
end else begin
if (_T_1754) begin
_T_1910_1 <= _T_1816;
end
end
if (reset) begin
_T_1910_2 <= 1'h0;
end else begin
if (_T_1754) begin
_T_1910_2 <= _T_1817;
end
end
if (reset) begin
_T_1910_3 <= 1'h0;
end else begin
if (_T_1754) begin
_T_1910_3 <= _T_1818;
end
end
if (reset) begin
_T_1910_4 <= 1'h0;
end else begin
if (_T_1754) begin
_T_1910_4 <= _T_1819;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1764) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@55838.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1764) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@55839.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1857) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@55929.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1857) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@55930.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1870) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@55946.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1870) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@55947.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_22( // @[:freechips.rocketchip.system.LowRiscConfig.fir@56074.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56075.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56076.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@56077.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@57664.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@56094.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@56095.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@56100.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@56101.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@56104.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@56105.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@56113.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56125.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56126.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56127.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56128.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@56130.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@56131.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@56132.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@56133.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@56133.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@56134.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@56136.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@56137.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@56138.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@56139.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@56140.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@56141.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@56142.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@56143.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56145.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56146.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56148.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56149.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@56150.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@56151.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@56152.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56153.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56154.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56155.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56156.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56157.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56158.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56159.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56160.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56161.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56162.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56163.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56164.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@56165.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@56166.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@56167.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56168.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56169.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56170.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56171.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56172.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56173.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56174.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56175.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56176.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56177.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56178.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56179.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56180.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56181.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56182.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56183.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56184.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56185.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56186.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56187.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56188.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56189.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56190.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56191.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@56198.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56209.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@56271.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56274.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56275.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56276.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56277.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56278.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56279.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56280.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56281.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56282.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56283.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56284.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56285.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56286.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56287.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56288.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56291.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56292.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56293.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56294.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56295.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56296.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56297.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56298.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@56307.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@56345.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56346.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@56358.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@56359.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@56365.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@56366.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@56373.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@56374.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@56380.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@56381.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@56386.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@56388.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@56389.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@56394.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@56395.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@56397.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@56398.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@56403.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@56405.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@56406.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@56412.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@56535.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@56537.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@56538.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@56561.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@56564.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@56587.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@56588.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@56589.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56590.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@56592.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56600.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@56602.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56604.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56605.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@56624.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@56626.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@56627.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@56632.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@56634.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@56635.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@56649.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56679.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@56692.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56694.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56695.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@56731.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@56804.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@56805.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@56806.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@56808.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@56809.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@56815.6]
wire _T_638; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@56843.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56851.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56855.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56856.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@56875.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@56877.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@56878.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@56892.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@56952.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@56954.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@56955.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@56969.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57009.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57010.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@57048.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@57050.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@57051.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57058.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57059.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57064.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57065.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57068.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57069.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57077.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57089.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57090.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57091.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57092.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@57094.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57097.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57098.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@57103.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@57105.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@57106.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@57111.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@57113.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@57114.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@57119.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@57121.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@57122.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@57127.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@57129.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@57130.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@57136.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@57160.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@57162.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@57163.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@57168.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@57170.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@57171.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@57194.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@57235.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@57237.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@57238.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@57253.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@57288.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@57324.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@57384.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@57389.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@57390.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@57391.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@57393.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57394.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57395.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57396.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57397.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@57408.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@57409.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@57410.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@57411.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@57412.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@57413.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@57414.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@57416.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@57418.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@57419.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@57424.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@57426.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@57427.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@57432.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@57434.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@57435.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@57440.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@57442.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@57443.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@57448.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@57450.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@57451.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@57458.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@57466.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@57468.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@57469.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@57470.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@57471.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@57472.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@57474.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57475.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57476.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57477.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57478.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@57489.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@57490.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@57491.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@57492.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@57493.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@57494.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@57495.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@57496.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@57498.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@57500.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@57501.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@57506.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@57508.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@57509.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@57514.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@57516.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@57517.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@57522.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@57524.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@57525.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@57530.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@57532.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@57533.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@57538.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@57540.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@57541.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@57548.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@57557.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@57567.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57568.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57569.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57570.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57571.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@57590.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57591.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57592.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57593.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57594.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@57609.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@57612.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@57614.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@57615.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@57616.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@57618.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@57619.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@57611.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@57630.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@57632.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@57633.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@57635.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57605.4 :freechips.rocketchip.system.LowRiscConfig.fir@57607.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@57613.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@57637.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@57638.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@57639.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@57641.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@57642.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@57634.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57625.4 :freechips.rocketchip.system.LowRiscConfig.fir@57627.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@57636.6]
wire _T_1152; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@57648.4]
wire _T_1153; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@57649.4]
wire _T_1154; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@57650.4]
wire _T_1155; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@57651.4]
wire _T_1157; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@57653.4]
wire _T_1158; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@57654.4]
wire [24:0] _T_1159; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@57659.4]
wire [24:0] _T_1160; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@57660.4]
wire [24:0] _T_1161; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@57661.4]
reg [31:0] _T_1163; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@57663.4]
reg [31:0] _RAND_16;
wire _T_1164; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@57666.4]
wire _T_1165; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@57667.4]
wire _T_1166; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@57668.4]
wire _T_1167; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@57669.4]
wire _T_1168; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@57670.4]
wire _T_1169; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@57671.4]
wire _T_1171; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@57673.4]
wire _T_1172; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@57674.4]
wire [31:0] _T_1174; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@57680.4]
wire _T_1177; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@57684.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@56309.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@56450.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56607.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56697.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@56779.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56858.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@56935.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57012.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57100.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@57142.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@57200.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@57259.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@57294.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@57330.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@57664.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@56094.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@56095.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@56100.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@56101.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@56104.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@56105.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@56113.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56125.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56126.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56127.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@56128.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@56130.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@56131.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@56132.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@56133.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@56133.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@56134.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@56136.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@56137.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@56138.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@56139.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@56140.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@56141.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@56142.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@56143.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56145.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56146.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56148.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56149.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@56150.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@56151.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@56152.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56153.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56154.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56155.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56156.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56157.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56158.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56159.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56160.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56161.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56162.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56163.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56164.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@56165.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@56166.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@56167.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56168.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56169.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56170.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56171.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56172.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56173.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56174.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56175.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56176.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56177.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56178.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56179.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56180.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56181.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56182.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56183.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56184.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56185.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56186.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56187.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56188.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@56189.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@56190.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@56191.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@56198.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56209.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@56271.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56274.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56275.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56276.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56277.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56278.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56279.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56280.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56281.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56282.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56283.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56284.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56285.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56286.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56287.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56288.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56291.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56292.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56293.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@56294.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@56295.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56296.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@56297.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@56298.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@56307.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@56345.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@56346.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@56358.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@56359.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@56365.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@56366.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@56373.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@56374.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@56380.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@56381.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@56386.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@56388.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@56389.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@56394.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@56395.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@56397.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@56398.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@56403.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@56405.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@56406.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@56412.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@56535.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@56537.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@56538.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@56561.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@56564.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@56587.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@56588.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@56589.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56590.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@56592.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56600.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@56602.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56604.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56605.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@56624.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@56626.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@56627.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@56632.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@56634.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@56635.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@56649.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56679.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@56692.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56694.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56695.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@56731.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@56804.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@56805.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@56806.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@56808.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@56809.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@56815.6]
assign _T_638 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@56843.8]
assign _T_646 = _T_638 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@56851.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56855.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56856.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@56875.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@56877.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@56878.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@56892.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@56952.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@56954.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@56955.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@56969.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57009.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57010.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@57048.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@57050.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@57051.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57058.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57059.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57064.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57065.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57068.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57069.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57077.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57089.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57090.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57091.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57092.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@57094.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57097.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57098.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@57103.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@57105.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@57106.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@57111.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@57113.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@57114.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@57119.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@57121.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@57122.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@57127.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@57129.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@57130.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@57136.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@57160.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@57162.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@57163.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@57168.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@57170.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@57171.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@57194.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@57235.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@57237.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@57238.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@57253.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@57288.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@57324.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@57384.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@57389.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@57390.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@57391.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57394.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57395.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57396.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57397.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@57413.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@57414.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@57416.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@57418.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@57419.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@57424.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@57426.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@57427.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@57432.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@57434.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@57435.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@57440.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@57442.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@57443.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@57448.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@57450.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@57451.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@57458.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@57466.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@57468.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@57469.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@57470.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@57471.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@57472.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57475.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57476.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57477.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57478.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@57495.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@57496.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@57498.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@57500.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@57501.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@57506.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@57508.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@57509.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@57514.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@57516.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@57517.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@57522.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@57524.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@57525.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@57530.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@57532.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@57533.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@57538.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@57540.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@57541.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@57548.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57568.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57569.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57570.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57571.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57591.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57592.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@57593.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@57594.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@57609.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@57612.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@57614.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@57615.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@57616.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@57618.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@57619.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@57611.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@57630.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@57632.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@57633.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@57635.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57605.4 :freechips.rocketchip.system.LowRiscConfig.fir@57607.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@57613.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@57637.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@57638.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@57639.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@57641.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@57642.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@57634.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57625.4 :freechips.rocketchip.system.LowRiscConfig.fir@57627.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@57636.6]
assign _T_1152 = _T_1126 != _T_1138; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@57648.4]
assign _T_1153 = _T_1126 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@57649.4]
assign _T_1154 = _T_1153 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@57650.4]
assign _T_1155 = _T_1152 | _T_1154; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@57651.4]
assign _T_1157 = _T_1155 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@57653.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@57654.4]
assign _T_1159 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@57659.4]
assign _T_1160 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@57660.4]
assign _T_1161 = _T_1159 & _T_1160; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@57661.4]
assign _T_1164 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@57666.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@57667.4]
assign _T_1166 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@57668.4]
assign _T_1167 = _T_1165 | _T_1166; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@57669.4]
assign _T_1168 = _T_1163 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@57670.4]
assign _T_1169 = _T_1167 | _T_1168; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@57671.4]
assign _T_1171 = _T_1169 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@57673.4]
assign _T_1172 = _T_1171 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@57674.4]
assign _T_1174 = _T_1163 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@57680.4]
assign _T_1177 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@57684.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@56309.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@56450.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56607.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56697.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@56779.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56858.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@56935.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57012.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57100.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@57142.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@57200.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@57259.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@57294.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@57330.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1163 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1161;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1163 <= 32'h0;
end else begin
if (_T_1177) begin
_T_1163 <= 32'h0;
end else begin
_T_1163 <= _T_1174;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@56089.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@56090.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@56268.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@56269.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@56309.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@56310.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@56361.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@56362.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@56368.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@56369.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@56376.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@56377.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@56383.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@56384.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@56391.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@56392.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@56400.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@56401.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@56408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@56409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@56450.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@56451.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@56502.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@56503.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@56509.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@56510.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@56517.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@56518.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@56524.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@56525.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@56532.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@56533.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@56540.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@56541.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@56549.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@56550.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@56557.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@56558.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56607.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@56608.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@56614.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@56615.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@56621.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@56622.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@56629.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@56630.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@56637.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@56638.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@56645.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@56646.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56697.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@56698.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@56704.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@56705.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@56711.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@56712.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@56719.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@56720.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@56727.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@56728.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@56779.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@56780.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@56786.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@56787.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@56793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@56794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@56801.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@56802.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@56811.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@56812.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56858.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@56859.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@56865.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@56866.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@56872.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@56873.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@56880.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@56881.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@56888.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@56889.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@56935.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@56936.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@56942.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@56943.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@56949.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@56950.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@56957.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@56958.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@56965.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@56966.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57012.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@57013.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@57019.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@57020.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@57026.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@57027.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@57034.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@57035.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@57042.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@57043.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@57053.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@57054.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57100.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@57101.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@57108.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@57109.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@57116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@57117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@57124.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@57125.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@57132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@57133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@57142.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@57143.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@57149.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@57150.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@57157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@57158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@57165.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@57166.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@57173.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@57174.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@57181.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@57182.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@57190.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@57191.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@57200.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@57201.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@57207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@57208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@57215.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@57216.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@57223.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@57224.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@57231.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@57232.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@57240.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@57241.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@57249.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@57250.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@57259.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@57260.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@57267.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@57268.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@57275.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@57276.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@57284.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@57285.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@57294.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@57295.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@57302.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@57303.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@57311.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@57312.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@57320.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@57321.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@57330.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@57331.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@57338.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@57339.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@57346.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@57347.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@57355.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@57356.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@57365.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@57366.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@57373.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@57374.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@57381.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@57382.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@57421.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@57422.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@57429.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@57430.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@57437.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@57438.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@57445.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@57446.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@57453.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@57454.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@57503.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@57504.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@57511.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@57512.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@57519.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@57520.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@57527.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@57528.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@57535.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@57536.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@57543.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@57544.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@57621.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@57622.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@57644.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@57645.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1158) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@57656.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1158) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@57657.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1172) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:43:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@57676.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1172) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@57677.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_78( // @[:freechips.rocketchip.system.LowRiscConfig.fir@57689.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57690.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57691.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [27:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [27:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@57692.4]
);
reg [2:0] _T_35_opcode [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_opcode__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_opcode__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [2:0] _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_opcode__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_opcode__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_opcode__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [2:0] _T_35_param [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_1;
wire [2:0] _T_35_param__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_param__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [2:0] _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_param__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_param__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_param__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [3:0] _T_35_size [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_2;
wire [3:0] _T_35_size__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_size__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [3:0] _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_size__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_size__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_size__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [4:0] _T_35_source [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_3;
wire [4:0] _T_35_source__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_source__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [4:0] _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_source__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_source__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_source__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [27:0] _T_35_address [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_4;
wire [27:0] _T_35_address__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_address__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [27:0] _T_35_address__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_address__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_address__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_address__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [7:0] _T_35_mask [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_5;
wire [7:0] _T_35_mask__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_mask__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [7:0] _T_35_mask__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_mask__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_mask__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_mask__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [63:0] _T_35_data [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [63:0] _RAND_6;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg _T_35_corrupt [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg [31:0] _RAND_7;
wire _T_35_corrupt__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_corrupt__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_corrupt__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_corrupt__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
wire _T_35_corrupt__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@57695.4]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@57696.4]
reg [31:0] _RAND_9;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@57697.4]
reg [31:0] _RAND_10;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@57698.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@57699.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@57700.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@57701.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57702.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57705.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57720.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57726.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@57729.4]
assign _T_35_opcode__T_58_addr = value_1;
assign _T_35_opcode__T_58_data = _T_35_opcode[_T_35_opcode__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_opcode__T_50_data = io_enq_bits_opcode;
assign _T_35_opcode__T_50_addr = value;
assign _T_35_opcode__T_50_mask = 1'h1;
assign _T_35_opcode__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_param__T_58_addr = value_1;
assign _T_35_param__T_58_data = _T_35_param[_T_35_param__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_param__T_50_data = io_enq_bits_param;
assign _T_35_param__T_50_addr = value;
assign _T_35_param__T_50_mask = 1'h1;
assign _T_35_param__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_58_addr = value_1;
assign _T_35_size__T_58_data = _T_35_size[_T_35_size__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_size__T_50_data = io_enq_bits_size;
assign _T_35_size__T_50_addr = value;
assign _T_35_size__T_50_mask = 1'h1;
assign _T_35_size__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_source__T_58_addr = value_1;
assign _T_35_source__T_58_data = _T_35_source[_T_35_source__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_source__T_50_data = io_enq_bits_source;
assign _T_35_source__T_50_addr = value;
assign _T_35_source__T_50_mask = 1'h1;
assign _T_35_source__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_address__T_58_addr = value_1;
assign _T_35_address__T_58_data = _T_35_address[_T_35_address__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_address__T_50_data = io_enq_bits_address;
assign _T_35_address__T_50_addr = value;
assign _T_35_address__T_50_mask = 1'h1;
assign _T_35_address__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_mask__T_58_addr = value_1;
assign _T_35_mask__T_58_data = _T_35_mask[_T_35_mask__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_mask__T_50_data = io_enq_bits_mask;
assign _T_35_mask__T_50_addr = value;
assign _T_35_mask__T_50_mask = 1'h1;
assign _T_35_mask__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_corrupt__T_58_addr = value_1;
assign _T_35_corrupt__T_58_data = _T_35_corrupt[_T_35_corrupt__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
assign _T_35_corrupt__T_50_data = io_enq_bits_corrupt;
assign _T_35_corrupt__T_50_addr = value;
assign _T_35_corrupt__T_50_mask = 1'h1;
assign _T_35_corrupt__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@57698.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@57699.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@57700.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@57701.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57702.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57705.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57720.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57726.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@57729.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@57736.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@57734.4]
assign io_deq_bits_opcode = _T_35_opcode__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57745.4]
assign io_deq_bits_param = _T_35_param__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57744.4]
assign io_deq_bits_size = _T_35_size__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57743.4]
assign io_deq_bits_source = _T_35_source__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57742.4]
assign io_deq_bits_address = _T_35_address__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57741.4]
assign io_deq_bits_mask = _T_35_mask__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57740.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57739.4]
assign io_deq_bits_corrupt = _T_35_corrupt__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57738.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_address[initvar] = _RAND_4[27:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_mask[initvar] = _RAND_5[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_data[initvar] = _RAND_6[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_39 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_opcode__T_50_en & _T_35_opcode__T_50_mask) begin
_T_35_opcode[_T_35_opcode__T_50_addr] <= _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_param__T_50_en & _T_35_param__T_50_mask) begin
_T_35_param[_T_35_param__T_50_addr] <= _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_size__T_50_en & _T_35_size__T_50_mask) begin
_T_35_size[_T_35_size__T_50_addr] <= _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_source__T_50_en & _T_35_source__T_50_mask) begin
_T_35_source[_T_35_source__T_50_addr] <= _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_address__T_50_en & _T_35_address__T_50_mask) begin
_T_35_address[_T_35_address__T_50_addr] <= _T_35_address__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_mask__T_50_en & _T_35_mask__T_50_mask) begin
_T_35_mask[_T_35_mask__T_50_addr] <= _T_35_mask__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if(_T_35_corrupt__T_50_en & _T_35_corrupt__T_50_mask) begin
_T_35_corrupt[_T_35_corrupt__T_50_addr] <= _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57694.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module Queue_79( // @[:freechips.rocketchip.system.LowRiscConfig.fir@57753.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57754.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57755.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input [1:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input io_enq_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input io_enq_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output [1:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output io_deq_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output io_deq_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@57756.4]
);
reg [2:0] _T_35_opcode [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_opcode__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_opcode__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire [2:0] _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_opcode__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_opcode__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_opcode__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [1:0] _T_35_param [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_1;
wire [1:0] _T_35_param__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_param__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire [1:0] _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_param__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_param__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_param__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [3:0] _T_35_size [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_2;
wire [3:0] _T_35_size__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_size__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire [3:0] _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_size__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_size__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_size__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [4:0] _T_35_source [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_3;
wire [4:0] _T_35_source__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_source__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire [4:0] _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_source__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_source__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_source__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg _T_35_sink [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_4;
wire _T_35_sink__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_sink__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_sink__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_sink__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_sink__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_sink__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg _T_35_denied [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_5;
wire _T_35_denied__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_denied__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_denied__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_denied__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_denied__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_denied__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [63:0] _T_35_data [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [63:0] _RAND_6;
wire [63:0] _T_35_data__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_data__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire [63:0] _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_data__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_data__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_data__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg _T_35_corrupt [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg [31:0] _RAND_7;
wire _T_35_corrupt__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_corrupt__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_corrupt__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_corrupt__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
wire _T_35_corrupt__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@57759.4]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@57760.4]
reg [31:0] _RAND_9;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@57761.4]
reg [31:0] _RAND_10;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@57762.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@57763.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@57764.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@57765.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57766.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57769.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57784.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57790.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@57793.4]
assign _T_35_opcode__T_58_addr = value_1;
assign _T_35_opcode__T_58_data = _T_35_opcode[_T_35_opcode__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_opcode__T_50_data = io_enq_bits_opcode;
assign _T_35_opcode__T_50_addr = value;
assign _T_35_opcode__T_50_mask = 1'h1;
assign _T_35_opcode__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_param__T_58_addr = value_1;
assign _T_35_param__T_58_data = _T_35_param[_T_35_param__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_param__T_50_data = io_enq_bits_param;
assign _T_35_param__T_50_addr = value;
assign _T_35_param__T_50_mask = 1'h1;
assign _T_35_param__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_58_addr = value_1;
assign _T_35_size__T_58_data = _T_35_size[_T_35_size__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_size__T_50_data = io_enq_bits_size;
assign _T_35_size__T_50_addr = value;
assign _T_35_size__T_50_mask = 1'h1;
assign _T_35_size__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_source__T_58_addr = value_1;
assign _T_35_source__T_58_data = _T_35_source[_T_35_source__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_source__T_50_data = io_enq_bits_source;
assign _T_35_source__T_50_addr = value;
assign _T_35_source__T_50_mask = 1'h1;
assign _T_35_source__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_sink__T_58_addr = value_1;
assign _T_35_sink__T_58_data = _T_35_sink[_T_35_sink__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_sink__T_50_data = io_enq_bits_sink;
assign _T_35_sink__T_50_addr = value;
assign _T_35_sink__T_50_mask = 1'h1;
assign _T_35_sink__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_denied__T_58_addr = value_1;
assign _T_35_denied__T_58_data = _T_35_denied[_T_35_denied__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_denied__T_50_data = io_enq_bits_denied;
assign _T_35_denied__T_50_addr = value;
assign _T_35_denied__T_50_mask = 1'h1;
assign _T_35_denied__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_58_addr = value_1;
assign _T_35_data__T_58_data = _T_35_data[_T_35_data__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_data__T_50_data = io_enq_bits_data;
assign _T_35_data__T_50_addr = value;
assign _T_35_data__T_50_mask = 1'h1;
assign _T_35_data__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_corrupt__T_58_addr = value_1;
assign _T_35_corrupt__T_58_data = _T_35_corrupt[_T_35_corrupt__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
assign _T_35_corrupt__T_50_data = io_enq_bits_corrupt;
assign _T_35_corrupt__T_50_addr = value;
assign _T_35_corrupt__T_50_mask = 1'h1;
assign _T_35_corrupt__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@57762.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@57763.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@57764.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@57765.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57766.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@57769.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57784.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@57790.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@57793.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@57800.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@57798.4]
assign io_deq_bits_opcode = _T_35_opcode__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57809.4]
assign io_deq_bits_param = _T_35_param__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57808.4]
assign io_deq_bits_size = _T_35_size__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57807.4]
assign io_deq_bits_source = _T_35_source__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57806.4]
assign io_deq_bits_sink = _T_35_sink__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57805.4]
assign io_deq_bits_denied = _T_35_denied__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57804.4]
assign io_deq_bits_data = _T_35_data__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57803.4]
assign io_deq_bits_corrupt = _T_35_corrupt__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@57802.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_param[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_sink[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_denied[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_data[initvar] = _RAND_6[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_39 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_opcode__T_50_en & _T_35_opcode__T_50_mask) begin
_T_35_opcode[_T_35_opcode__T_50_addr] <= _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_param__T_50_en & _T_35_param__T_50_mask) begin
_T_35_param[_T_35_param__T_50_addr] <= _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_size__T_50_en & _T_35_size__T_50_mask) begin
_T_35_size[_T_35_size__T_50_addr] <= _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_source__T_50_en & _T_35_source__T_50_mask) begin
_T_35_source[_T_35_source__T_50_addr] <= _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_sink__T_50_en & _T_35_sink__T_50_mask) begin
_T_35_sink[_T_35_sink__T_50_addr] <= _T_35_sink__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_denied__T_50_en & _T_35_denied__T_50_mask) begin
_T_35_denied[_T_35_denied__T_50_addr] <= _T_35_denied__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_data__T_50_en & _T_35_data__T_50_mask) begin
_T_35_data[_T_35_data__T_50_addr] <= _T_35_data__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if(_T_35_corrupt__T_50_en & _T_35_corrupt__T_50_mask) begin
_T_35_corrupt[_T_35_corrupt__T_50_addr] <= _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@57758.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module TLBuffer_7( // @[:freechips.rocketchip.system.LowRiscConfig.fir@57817.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57818.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57819.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@57820.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [4:0] Queue_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [27:0] Queue_io_enq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [7:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [4:0] Queue_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [27:0] Queue_io_deq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [7:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [4:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [63:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [4:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire [63:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
TLMonitor_22 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@57827.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_78 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57868.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_opcode(Queue_io_enq_bits_opcode),
.io_enq_bits_param(Queue_io_enq_bits_param),
.io_enq_bits_size(Queue_io_enq_bits_size),
.io_enq_bits_source(Queue_io_enq_bits_source),
.io_enq_bits_address(Queue_io_enq_bits_address),
.io_enq_bits_mask(Queue_io_enq_bits_mask),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_io_enq_bits_corrupt),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_opcode(Queue_io_deq_bits_opcode),
.io_deq_bits_param(Queue_io_deq_bits_param),
.io_deq_bits_size(Queue_io_deq_bits_size),
.io_deq_bits_source(Queue_io_deq_bits_source),
.io_deq_bits_address(Queue_io_deq_bits_address),
.io_deq_bits_mask(Queue_io_deq_bits_mask),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_io_deq_bits_corrupt)
);
Queue_79 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@57882.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_opcode(Queue_1_io_enq_bits_opcode),
.io_enq_bits_param(Queue_1_io_enq_bits_param),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_source(Queue_1_io_enq_bits_source),
.io_enq_bits_sink(Queue_1_io_enq_bits_sink),
.io_enq_bits_denied(Queue_1_io_enq_bits_denied),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_opcode(Queue_1_io_deq_bits_opcode),
.io_deq_bits_param(Queue_1_io_deq_bits_param),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_source(Queue_1_io_deq_bits_source),
.io_deq_bits_sink(Queue_1_io_deq_bits_sink),
.io_deq_bits_denied(Queue_1_io_deq_bits_denied),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt)
);
assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@57867.4]
assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_data = Queue_io_deq_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@57866.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57829.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57830.4]
assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@57863.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57869.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57870.4]
assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@57871.4]
assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57879.4]
assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57878.4]
assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57877.4]
assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57876.4]
assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57875.4]
assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57874.4]
assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57873.4]
assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57872.4]
assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.LowRiscConfig.fir@57881.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57883.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@57884.4]
assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@57885.4]
assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57893.4]
assign Queue_1_io_enq_bits_param = auto_out_d_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57892.4]
assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57891.4]
assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57890.4]
assign Queue_1_io_enq_bits_sink = auto_out_d_bits_sink; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57889.4]
assign Queue_1_io_enq_bits_denied = auto_out_d_bits_denied; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57888.4]
assign Queue_1_io_enq_bits_data = auto_out_d_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57887.4]
assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@57886.4]
assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.LowRiscConfig.fir@57895.4]
endmodule
module TLMonitor_23( // @[:freechips.rocketchip.system.LowRiscConfig.fir@57910.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57911.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57912.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@57913.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@59500.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57930.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57931.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57936.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57937.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57940.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57941.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57949.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57961.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57962.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57963.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57964.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@57966.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@57967.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@57968.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@57969.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@57969.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@57970.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@57972.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@57973.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@57974.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@57975.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@57976.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@57977.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@57978.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@57979.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57981.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57982.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57984.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57985.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@57986.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@57987.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@57988.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57989.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57990.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57991.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57992.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57993.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57994.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57995.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57996.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57997.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57998.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57999.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58000.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@58001.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@58002.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@58003.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58004.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58005.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58006.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58007.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58008.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58009.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58010.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58011.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58012.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58013.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58014.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58015.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58016.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58017.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58018.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58019.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58020.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58021.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58022.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58023.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58024.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58025.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58026.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58027.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@58034.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58045.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@58107.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58110.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58111.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58112.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58113.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58114.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58115.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58116.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58117.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58118.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58119.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58120.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58121.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58122.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58123.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58124.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58127.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58128.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58129.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58130.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58131.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58132.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58133.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58134.8]
wire _T_226; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58135.8]
wire _T_227; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58136.8]
wire _T_228; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58137.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@58143.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@58181.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@58182.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@58194.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@58195.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@58201.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@58202.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@58209.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@58210.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@58216.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@58217.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@58222.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@58224.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@58225.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@58230.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@58231.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@58233.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@58234.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@58239.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@58241.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@58242.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@58248.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@58371.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@58373.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@58374.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@58397.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@58400.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58423.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58424.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58425.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58426.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@58428.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58436.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@58438.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58440.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58441.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@58460.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@58462.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@58463.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@58468.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@58470.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@58471.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@58485.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58515.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@58528.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58530.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58531.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@58567.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@58640.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@58641.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@58642.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@58644.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@58645.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@58651.6]
wire _T_620; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@58661.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58687.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58691.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58692.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@58711.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@58713.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@58714.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@58728.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@58788.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@58790.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@58791.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@58805.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58845.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58846.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@58884.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@58886.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@58887.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@58894.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@58895.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@58900.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@58901.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@58904.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@58905.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@58913.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58925.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58926.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58927.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58928.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@58930.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58933.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58934.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@58939.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@58941.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@58942.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@58947.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@58949.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@58950.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@58955.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@58957.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@58958.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@58963.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@58965.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@58966.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@58972.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@58996.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@58998.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@58999.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@59004.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@59006.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@59007.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@59030.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@59071.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@59073.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@59074.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@59089.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@59124.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@59160.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@59220.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@59225.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@59226.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@59227.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@59229.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59230.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59231.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59232.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59233.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@59244.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@59245.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@59246.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@59247.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@59248.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@59249.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@59250.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@59252.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@59254.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@59255.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@59260.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@59262.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@59263.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@59268.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@59270.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@59271.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@59276.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@59278.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@59279.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@59284.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@59286.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@59287.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@59294.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@59302.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@59304.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@59305.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@59306.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@59307.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@59308.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@59310.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59311.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59312.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59313.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59314.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@59325.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@59326.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@59327.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@59328.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@59329.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@59330.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@59331.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@59332.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@59334.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@59336.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@59337.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@59342.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@59344.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@59345.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@59350.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@59352.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@59353.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@59358.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@59360.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@59361.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@59366.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@59368.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@59369.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@59374.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@59376.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@59377.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@59384.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@59393.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@59403.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59404.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59405.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59406.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59407.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@59426.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59427.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59428.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59429.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59430.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@59445.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@59448.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@59450.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@59451.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@59452.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@59454.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@59455.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@59447.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@59466.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@59468.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@59469.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@59471.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@59441.4 :freechips.rocketchip.system.LowRiscConfig.fir@59443.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@59449.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@59473.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@59474.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@59475.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@59477.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@59478.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@59470.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@59461.4 :freechips.rocketchip.system.LowRiscConfig.fir@59463.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@59472.6]
wire _T_1152; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@59484.4]
wire _T_1153; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@59485.4]
wire _T_1154; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@59486.4]
wire _T_1155; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@59487.4]
wire _T_1157; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@59489.4]
wire _T_1158; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@59490.4]
wire [24:0] _T_1159; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@59495.4]
wire [24:0] _T_1160; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@59496.4]
wire [24:0] _T_1161; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@59497.4]
reg [31:0] _T_1163; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@59499.4]
reg [31:0] _RAND_16;
wire _T_1164; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@59502.4]
wire _T_1165; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@59503.4]
wire _T_1166; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@59504.4]
wire _T_1167; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@59505.4]
wire _T_1168; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@59506.4]
wire _T_1169; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@59507.4]
wire _T_1171; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@59509.4]
wire _T_1172; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@59510.4]
wire [31:0] _T_1174; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@59516.4]
wire _T_1177; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@59520.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@58145.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@58286.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58443.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58533.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@58615.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58694.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@58771.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58848.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58936.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@58978.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@59036.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@59095.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@59130.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@59166.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@59500.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57930.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57931.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57936.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@57937.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@57940.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57941.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@57949.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57961.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57962.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57963.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@57964.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@57966.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@57967.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@57968.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@57969.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@57969.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@57970.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@57972.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@57973.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@57974.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@57975.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@57976.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@57977.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@57978.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@57979.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57981.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57982.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57984.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57985.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@57986.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@57987.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@57988.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57989.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57990.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57991.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57992.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57993.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57994.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57995.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57996.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@57997.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@57998.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@57999.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58000.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@58001.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@58002.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@58003.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58004.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58005.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58006.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58007.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58008.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58009.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58010.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58011.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58012.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58013.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58014.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58015.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58016.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58017.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58018.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58019.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58020.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58021.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58022.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58023.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58024.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@58025.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@58026.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@58027.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@58034.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58045.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@58107.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58110.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58111.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58112.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58113.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58114.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58115.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58116.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58117.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58118.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58119.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58120.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58121.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58122.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58123.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58124.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58127.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58128.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58129.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@58130.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@58131.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58132.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@58133.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@58134.8]
assign _T_226 = _T_205 | _T_210; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58135.8]
assign _T_227 = _T_226 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58136.8]
assign _T_228 = _T_227 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58137.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@58143.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@58181.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@58182.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@58194.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@58195.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@58201.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@58202.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@58209.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@58210.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@58216.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@58217.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@58222.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@58224.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@58225.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@58230.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@58231.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@58233.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@58234.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@58239.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@58241.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@58242.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@58248.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@58371.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@58373.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@58374.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@58397.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@58400.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58423.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58424.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@58425.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58426.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@58428.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58436.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@58438.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58440.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58441.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@58460.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@58462.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@58463.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@58468.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@58470.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@58471.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@58485.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58515.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@58528.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58530.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58531.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@58567.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@58640.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@58641.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@58642.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@58644.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@58645.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@58651.6]
assign _T_620 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@58661.8]
assign _T_646 = _T_620 & _T_228; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@58687.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58691.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58692.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@58711.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@58713.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@58714.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@58728.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@58788.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@58790.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@58791.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@58805.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58845.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58846.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@58884.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@58886.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@58887.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@58894.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@58895.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@58900.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@58901.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@58904.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@58905.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@58913.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58925.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58926.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58927.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@58928.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@58930.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58933.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58934.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@58939.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@58941.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@58942.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@58947.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@58949.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@58950.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@58955.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@58957.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@58958.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@58963.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@58965.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@58966.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@58972.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@58996.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@58998.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@58999.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@59004.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@59006.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@59007.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@59030.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@59071.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@59073.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@59074.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@59089.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@59124.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@59160.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@59220.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@59225.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@59226.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@59227.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59230.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59231.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59232.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59233.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@59249.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@59250.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@59252.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@59254.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@59255.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@59260.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@59262.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@59263.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@59268.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@59270.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@59271.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@59276.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@59278.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@59279.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@59284.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@59286.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@59287.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@59294.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@59302.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@59304.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@59305.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@59306.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@59307.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@59308.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59311.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59312.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59313.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59314.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@59331.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@59332.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@59334.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@59336.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@59337.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@59342.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@59344.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@59345.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@59350.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@59352.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@59353.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@59358.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@59360.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@59361.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@59366.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@59368.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@59369.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@59374.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@59376.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@59377.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@59384.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59404.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59405.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59406.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59407.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59427.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59428.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@59429.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@59430.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@59445.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@59448.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@59450.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@59451.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@59452.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@59454.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@59455.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@59447.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@59466.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@59468.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@59469.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@59471.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@59441.4 :freechips.rocketchip.system.LowRiscConfig.fir@59443.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@59449.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@59473.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@59474.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@59475.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@59477.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@59478.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@59470.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@59461.4 :freechips.rocketchip.system.LowRiscConfig.fir@59463.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@59472.6]
assign _T_1152 = _T_1126 != _T_1138; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@59484.4]
assign _T_1153 = _T_1126 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@59485.4]
assign _T_1154 = _T_1153 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@59486.4]
assign _T_1155 = _T_1152 | _T_1154; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@59487.4]
assign _T_1157 = _T_1155 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@59489.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@59490.4]
assign _T_1159 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@59495.4]
assign _T_1160 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@59496.4]
assign _T_1161 = _T_1159 & _T_1160; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@59497.4]
assign _T_1164 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@59502.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@59503.4]
assign _T_1166 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@59504.4]
assign _T_1167 = _T_1165 | _T_1166; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@59505.4]
assign _T_1168 = _T_1163 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@59506.4]
assign _T_1169 = _T_1167 | _T_1168; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@59507.4]
assign _T_1171 = _T_1169 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@59509.4]
assign _T_1172 = _T_1171 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@59510.4]
assign _T_1174 = _T_1163 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@59516.4]
assign _T_1177 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@59520.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@58145.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@58286.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58443.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58533.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@58615.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58694.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@58771.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58848.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58936.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@58978.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@59036.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@59095.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@59130.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@59166.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1163 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1161;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1163 <= 32'h0;
end else begin
if (_T_1177) begin
_T_1163 <= 32'h0;
end else begin
_T_1163 <= _T_1174;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@57925.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@57926.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@58104.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@58105.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@58145.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@58146.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@58197.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@58198.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@58204.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@58205.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@58212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@58213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@58219.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@58220.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@58227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@58228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@58236.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@58237.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@58244.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@58245.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@58286.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@58287.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@58338.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@58339.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@58345.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@58346.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@58353.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@58354.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@58360.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@58361.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@58368.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@58369.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@58376.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@58377.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@58385.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@58386.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@58393.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@58394.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58443.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@58444.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@58450.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@58451.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@58457.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@58458.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@58465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@58466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@58473.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@58474.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@58481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@58482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58533.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@58534.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@58540.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@58541.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@58547.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@58548.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@58555.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@58556.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@58563.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@58564.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@58615.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@58616.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@58622.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@58623.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@58629.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@58630.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@58637.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@58638.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@58647.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@58648.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58694.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@58695.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@58701.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@58702.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@58708.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@58709.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@58716.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@58717.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@58724.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@58725.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@58771.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@58772.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@58778.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@58779.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@58785.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@58786.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@58793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@58794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@58801.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@58802.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58848.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@58849.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@58855.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@58856.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@58862.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@58863.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@58870.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@58871.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@58878.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@58879.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@58889.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@58890.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58936.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@58937.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@58944.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@58945.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@58952.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@58953.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@58960.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@58961.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@58968.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@58969.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@58978.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@58979.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@58985.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@58986.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@58993.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@58994.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@59001.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@59002.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@59009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@59010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@59017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@59018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@59026.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@59027.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@59036.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@59037.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@59043.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@59044.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@59051.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@59052.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@59059.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@59060.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@59067.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@59068.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@59076.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@59077.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@59085.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@59086.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@59095.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@59096.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@59103.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@59104.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@59111.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@59112.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@59120.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@59121.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@59130.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@59131.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@59138.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@59139.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@59147.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@59148.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@59156.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@59157.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@59166.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@59167.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@59174.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@59175.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@59182.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@59183.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@59191.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@59192.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@59201.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@59202.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@59209.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@59210.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@59217.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@59218.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@59257.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@59258.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@59265.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@59266.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@59273.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@59274.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@59281.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@59282.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@59289.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@59290.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@59339.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@59340.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@59347.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@59348.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@59355.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@59356.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@59363.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@59364.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@59371.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@59372.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@59379.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@59380.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@59457.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@59458.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@59480.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@59481.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1158) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@59492.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1158) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@59493.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1172) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at PeripheryBus.scala:46:7)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@59512.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1172) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@59513.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLAtomicAutomata_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@59525.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59526.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59527.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@59528.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
reg [1:0] _T_258_0_state; // @[AtomicAutomata.scala 74:28:freechips.rocketchip.system.LowRiscConfig.fir@59582.4]
reg [31:0] _RAND_0;
reg [2:0] _T_269_0_bits_opcode; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_1;
reg [2:0] _T_269_0_bits_param; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_2;
reg [3:0] _T_269_0_bits_size; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_3;
reg [4:0] _T_269_0_bits_source; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_4;
reg [27:0] _T_269_0_bits_address; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_5;
reg [7:0] _T_269_0_bits_mask; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_6;
reg [63:0] _T_269_0_bits_data; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [63:0] _RAND_7;
reg _T_269_0_bits_corrupt; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_8;
reg _T_269_0_fifoId; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_9;
reg [3:0] _T_269_0_lut; // @[AtomicAutomata.scala 75:24:freechips.rocketchip.system.LowRiscConfig.fir@59583.4]
reg [31:0] _RAND_10;
reg [63:0] _T_276_0_data; // @[AtomicAutomata.scala 76:24:freechips.rocketchip.system.LowRiscConfig.fir@59584.4]
reg [63:0] _RAND_11;
reg _T_276_0_denied; // @[AtomicAutomata.scala 76:24:freechips.rocketchip.system.LowRiscConfig.fir@59584.4]
reg [31:0] _RAND_12;
reg _T_276_0_corrupt; // @[AtomicAutomata.scala 76:24:freechips.rocketchip.system.LowRiscConfig.fir@59584.4]
reg [31:0] _RAND_13;
wire _T_280; // @[AtomicAutomata.scala 78:44:freechips.rocketchip.system.LowRiscConfig.fir@59585.4]
wire _T_281; // @[AtomicAutomata.scala 79:44:freechips.rocketchip.system.LowRiscConfig.fir@59586.4]
wire _T_282; // @[AtomicAutomata.scala 80:49:freechips.rocketchip.system.LowRiscConfig.fir@59587.4]
wire _T_284; // @[AtomicAutomata.scala 80:57:freechips.rocketchip.system.LowRiscConfig.fir@59589.4]
wire _T_285; // @[AtomicAutomata.scala 81:49:freechips.rocketchip.system.LowRiscConfig.fir@59590.4]
wire _T_312; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@59617.4]
wire [27:0] _T_315; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@59620.4]
wire [28:0] _T_316; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@59621.4]
wire [28:0] _T_317; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@59622.4]
wire [28:0] _T_318; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@59623.4]
wire _T_319; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@59624.4]
wire _T_320; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@59625.4]
wire _T_362; // @[AtomicAutomata.scala 88:47:freechips.rocketchip.system.LowRiscConfig.fir@59667.4]
wire _T_363; // @[AtomicAutomata.scala 89:47:freechips.rocketchip.system.LowRiscConfig.fir@59668.4]
wire _T_364; // @[AtomicAutomata.scala 90:63:freechips.rocketchip.system.LowRiscConfig.fir@59669.4]
wire _T_365; // @[AtomicAutomata.scala 90:32:freechips.rocketchip.system.LowRiscConfig.fir@59670.4]
wire _T_374; // @[AtomicAutomata.scala 103:60:freechips.rocketchip.system.LowRiscConfig.fir@59679.4]
wire _T_375; // @[AtomicAutomata.scala 103:96:freechips.rocketchip.system.LowRiscConfig.fir@59680.4]
wire _T_379; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59684.4]
wire _T_380; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59685.4]
wire [1:0] _T_381; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59686.4]
wire _T_382; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59687.4]
wire _T_383; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59688.4]
wire [1:0] _T_384; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59689.4]
wire _T_385; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59690.4]
wire _T_386; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59691.4]
wire [1:0] _T_387; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59692.4]
wire _T_388; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59693.4]
wire _T_389; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59694.4]
wire [1:0] _T_390; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59695.4]
wire _T_391; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59696.4]
wire _T_392; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59697.4]
wire [1:0] _T_393; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59698.4]
wire _T_394; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59699.4]
wire _T_395; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59700.4]
wire [1:0] _T_396; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59701.4]
wire _T_397; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59702.4]
wire _T_398; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59703.4]
wire [1:0] _T_399; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59704.4]
wire _T_400; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59705.4]
wire _T_401; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59706.4]
wire [1:0] _T_402; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59707.4]
wire _T_403; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59708.4]
wire _T_404; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59709.4]
wire [1:0] _T_405; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59710.4]
wire _T_406; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59711.4]
wire _T_407; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59712.4]
wire [1:0] _T_408; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59713.4]
wire _T_409; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59714.4]
wire _T_410; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59715.4]
wire [1:0] _T_411; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59716.4]
wire _T_412; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59717.4]
wire _T_413; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59718.4]
wire [1:0] _T_414; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59719.4]
wire _T_415; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59720.4]
wire _T_416; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59721.4]
wire [1:0] _T_417; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59722.4]
wire _T_418; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59723.4]
wire _T_419; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59724.4]
wire [1:0] _T_420; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59725.4]
wire _T_421; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59726.4]
wire _T_422; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59727.4]
wire [1:0] _T_423; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59728.4]
wire _T_424; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59729.4]
wire _T_425; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59730.4]
wire [1:0] _T_426; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59731.4]
wire _T_427; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59732.4]
wire _T_428; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59733.4]
wire [1:0] _T_429; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59734.4]
wire _T_430; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59735.4]
wire _T_431; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59736.4]
wire [1:0] _T_432; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59737.4]
wire _T_433; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59738.4]
wire _T_434; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59739.4]
wire [1:0] _T_435; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59740.4]
wire _T_436; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59741.4]
wire _T_437; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59742.4]
wire [1:0] _T_438; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59743.4]
wire _T_439; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59744.4]
wire _T_440; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59745.4]
wire [1:0] _T_441; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59746.4]
wire _T_442; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59747.4]
wire _T_443; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59748.4]
wire [1:0] _T_444; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59749.4]
wire _T_445; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59750.4]
wire _T_446; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59751.4]
wire [1:0] _T_447; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59752.4]
wire _T_448; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59753.4]
wire _T_449; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59754.4]
wire [1:0] _T_450; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59755.4]
wire _T_451; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59756.4]
wire _T_452; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59757.4]
wire [1:0] _T_453; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59758.4]
wire _T_454; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59759.4]
wire _T_455; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59760.4]
wire [1:0] _T_456; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59761.4]
wire _T_457; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59762.4]
wire _T_458; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59763.4]
wire [1:0] _T_459; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59764.4]
wire _T_460; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59765.4]
wire _T_461; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59766.4]
wire [1:0] _T_462; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59767.4]
wire _T_463; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59768.4]
wire _T_464; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59769.4]
wire [1:0] _T_465; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59770.4]
wire _T_466; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59771.4]
wire _T_467; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59772.4]
wire [1:0] _T_468; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59773.4]
wire _T_469; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59774.4]
wire _T_470; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59775.4]
wire [1:0] _T_471; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59776.4]
wire _T_472; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59777.4]
wire _T_473; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59778.4]
wire [1:0] _T_474; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59779.4]
wire _T_475; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59780.4]
wire _T_476; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59781.4]
wire [1:0] _T_477; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59782.4]
wire _T_478; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59783.4]
wire _T_479; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59784.4]
wire [1:0] _T_480; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59785.4]
wire _T_481; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59786.4]
wire _T_482; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59787.4]
wire [1:0] _T_483; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59788.4]
wire _T_484; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59789.4]
wire _T_485; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59790.4]
wire [1:0] _T_486; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59791.4]
wire _T_487; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59792.4]
wire _T_488; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59793.4]
wire [1:0] _T_489; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59794.4]
wire _T_490; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59795.4]
wire _T_491; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59796.4]
wire [1:0] _T_492; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59797.4]
wire _T_493; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59798.4]
wire _T_494; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59799.4]
wire [1:0] _T_495; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59800.4]
wire _T_496; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59801.4]
wire _T_497; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59802.4]
wire [1:0] _T_498; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59803.4]
wire _T_499; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59804.4]
wire _T_500; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59805.4]
wire [1:0] _T_501; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59806.4]
wire _T_502; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59807.4]
wire _T_503; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59808.4]
wire [1:0] _T_504; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59809.4]
wire _T_505; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59810.4]
wire _T_506; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59811.4]
wire [1:0] _T_507; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59812.4]
wire _T_508; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59813.4]
wire _T_509; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59814.4]
wire [1:0] _T_510; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59815.4]
wire _T_511; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59816.4]
wire _T_512; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59817.4]
wire [1:0] _T_513; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59818.4]
wire _T_514; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59819.4]
wire _T_515; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59820.4]
wire [1:0] _T_516; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59821.4]
wire _T_517; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59822.4]
wire _T_518; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59823.4]
wire [1:0] _T_519; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59824.4]
wire _T_520; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59825.4]
wire _T_521; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59826.4]
wire [1:0] _T_522; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59827.4]
wire _T_523; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59828.4]
wire _T_524; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59829.4]
wire [1:0] _T_525; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59830.4]
wire _T_526; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59831.4]
wire _T_527; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59832.4]
wire [1:0] _T_528; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59833.4]
wire _T_529; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59834.4]
wire _T_530; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59835.4]
wire [1:0] _T_531; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59836.4]
wire _T_532; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59837.4]
wire _T_533; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59838.4]
wire [1:0] _T_534; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59839.4]
wire _T_535; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59840.4]
wire _T_536; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59841.4]
wire [1:0] _T_537; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59842.4]
wire _T_538; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59843.4]
wire _T_539; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59844.4]
wire [1:0] _T_540; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59845.4]
wire _T_541; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59846.4]
wire _T_542; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59847.4]
wire [1:0] _T_543; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59848.4]
wire _T_544; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59849.4]
wire _T_545; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59850.4]
wire [1:0] _T_546; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59851.4]
wire _T_547; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59852.4]
wire _T_548; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59853.4]
wire [1:0] _T_549; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59854.4]
wire _T_550; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59855.4]
wire _T_551; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59856.4]
wire [1:0] _T_552; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59857.4]
wire _T_553; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59858.4]
wire _T_554; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59859.4]
wire [1:0] _T_555; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59860.4]
wire _T_556; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59861.4]
wire _T_557; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59862.4]
wire [1:0] _T_558; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59863.4]
wire _T_559; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59864.4]
wire _T_560; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59865.4]
wire [1:0] _T_561; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59866.4]
wire _T_562; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59867.4]
wire _T_563; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59868.4]
wire [1:0] _T_564; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59869.4]
wire _T_565; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59870.4]
wire _T_566; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59871.4]
wire [1:0] _T_567; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59872.4]
wire _T_568; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59873.4]
wire _T_569; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59874.4]
wire [1:0] _T_570; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59875.4]
wire [3:0] _T_571; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59876.4]
wire _T_572; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59877.4]
wire [3:0] _T_573; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59878.4]
wire _T_574; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59879.4]
wire [3:0] _T_575; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59880.4]
wire _T_576; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59881.4]
wire [3:0] _T_577; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59882.4]
wire _T_578; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59883.4]
wire [3:0] _T_579; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59884.4]
wire _T_580; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59885.4]
wire [3:0] _T_581; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59886.4]
wire _T_582; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59887.4]
wire [3:0] _T_583; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59888.4]
wire _T_584; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59889.4]
wire [3:0] _T_585; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59890.4]
wire _T_586; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59891.4]
wire [3:0] _T_587; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59892.4]
wire _T_588; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59893.4]
wire [3:0] _T_589; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59894.4]
wire _T_590; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59895.4]
wire [3:0] _T_591; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59896.4]
wire _T_592; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59897.4]
wire [3:0] _T_593; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59898.4]
wire _T_594; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59899.4]
wire [3:0] _T_595; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59900.4]
wire _T_596; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59901.4]
wire [3:0] _T_597; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59902.4]
wire _T_598; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59903.4]
wire [3:0] _T_599; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59904.4]
wire _T_600; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59905.4]
wire [3:0] _T_601; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59906.4]
wire _T_602; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59907.4]
wire [3:0] _T_603; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59908.4]
wire _T_604; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59909.4]
wire [3:0] _T_605; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59910.4]
wire _T_606; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59911.4]
wire [3:0] _T_607; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59912.4]
wire _T_608; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59913.4]
wire [3:0] _T_609; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59914.4]
wire _T_610; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59915.4]
wire [3:0] _T_611; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59916.4]
wire _T_612; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59917.4]
wire [3:0] _T_613; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59918.4]
wire _T_614; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59919.4]
wire [3:0] _T_615; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59920.4]
wire _T_616; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59921.4]
wire [3:0] _T_617; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59922.4]
wire _T_618; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59923.4]
wire [3:0] _T_619; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59924.4]
wire _T_620; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59925.4]
wire [3:0] _T_621; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59926.4]
wire _T_622; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59927.4]
wire [3:0] _T_623; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59928.4]
wire _T_624; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59929.4]
wire [3:0] _T_625; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59930.4]
wire _T_626; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59931.4]
wire [3:0] _T_627; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59932.4]
wire _T_628; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59933.4]
wire [3:0] _T_629; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59934.4]
wire _T_630; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59935.4]
wire [3:0] _T_631; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59936.4]
wire _T_632; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59937.4]
wire [3:0] _T_633; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59938.4]
wire _T_634; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59939.4]
wire [3:0] _T_635; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59940.4]
wire _T_636; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59941.4]
wire [3:0] _T_637; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59942.4]
wire _T_638; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59943.4]
wire [3:0] _T_639; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59944.4]
wire _T_640; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59945.4]
wire [3:0] _T_641; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59946.4]
wire _T_642; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59947.4]
wire [3:0] _T_643; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59948.4]
wire _T_644; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59949.4]
wire [3:0] _T_645; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59950.4]
wire _T_646; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59951.4]
wire [3:0] _T_647; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59952.4]
wire _T_648; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59953.4]
wire [3:0] _T_649; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59954.4]
wire _T_650; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59955.4]
wire [3:0] _T_651; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59956.4]
wire _T_652; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59957.4]
wire [3:0] _T_653; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59958.4]
wire _T_654; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59959.4]
wire [3:0] _T_655; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59960.4]
wire _T_656; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59961.4]
wire [3:0] _T_657; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59962.4]
wire _T_658; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59963.4]
wire [3:0] _T_659; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59964.4]
wire _T_660; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59965.4]
wire [3:0] _T_661; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59966.4]
wire _T_662; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59967.4]
wire [3:0] _T_663; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59968.4]
wire _T_664; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59969.4]
wire [3:0] _T_665; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59970.4]
wire _T_666; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59971.4]
wire [3:0] _T_667; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59972.4]
wire _T_668; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59973.4]
wire [3:0] _T_669; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59974.4]
wire _T_670; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59975.4]
wire [3:0] _T_671; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59976.4]
wire _T_672; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59977.4]
wire [3:0] _T_673; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59978.4]
wire _T_674; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59979.4]
wire [3:0] _T_675; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59980.4]
wire _T_676; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59981.4]
wire [3:0] _T_677; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59982.4]
wire _T_678; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59983.4]
wire [3:0] _T_679; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59984.4]
wire _T_680; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59985.4]
wire [3:0] _T_681; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59986.4]
wire _T_682; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59987.4]
wire [3:0] _T_683; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59988.4]
wire _T_684; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59989.4]
wire [3:0] _T_685; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59990.4]
wire _T_686; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59991.4]
wire [3:0] _T_687; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59992.4]
wire _T_688; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59993.4]
wire [3:0] _T_689; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59994.4]
wire _T_690; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59995.4]
wire [3:0] _T_691; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59996.4]
wire _T_692; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59997.4]
wire [3:0] _T_693; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59998.4]
wire _T_694; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59999.4]
wire [3:0] _T_695; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60000.4]
wire _T_696; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60001.4]
wire [3:0] _T_697; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60002.4]
wire _T_698; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60003.4]
wire [7:0] _T_705; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60010.4]
wire [15:0] _T_713; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60018.4]
wire [7:0] _T_720; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60025.4]
wire [31:0] _T_729; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60034.4]
wire [7:0] _T_736; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60041.4]
wire [15:0] _T_744; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60049.4]
wire [7:0] _T_751; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60056.4]
wire [31:0] _T_760; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60065.4]
wire [63:0] _T_761; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60066.4]
wire _T_762; // @[AtomicAutomata.scala 115:42:freechips.rocketchip.system.LowRiscConfig.fir@60067.4]
wire _T_763; // @[AtomicAutomata.scala 116:42:freechips.rocketchip.system.LowRiscConfig.fir@60068.4]
wire _T_764; // @[AtomicAutomata.scala 117:39:freechips.rocketchip.system.LowRiscConfig.fir@60069.4]
wire [7:0] _T_765; // @[AtomicAutomata.scala 119:25:freechips.rocketchip.system.LowRiscConfig.fir@60070.4]
wire [6:0] _T_766; // @[AtomicAutomata.scala 119:39:freechips.rocketchip.system.LowRiscConfig.fir@60071.4]
wire [7:0] _GEN_39; // @[AtomicAutomata.scala 119:31:freechips.rocketchip.system.LowRiscConfig.fir@60072.4]
wire [7:0] _T_767; // @[AtomicAutomata.scala 119:31:freechips.rocketchip.system.LowRiscConfig.fir@60072.4]
wire [7:0] _T_768; // @[AtomicAutomata.scala 119:23:freechips.rocketchip.system.LowRiscConfig.fir@60073.4]
wire [7:0] _T_783; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60088.4]
wire [7:0] _T_798; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60103.4]
wire [7:0] _T_799; // @[AtomicAutomata.scala 123:38:freechips.rocketchip.system.LowRiscConfig.fir@60104.4]
wire [8:0] _GEN_40; // @[AtomicAutomata.scala 123:49:freechips.rocketchip.system.LowRiscConfig.fir@60105.4]
wire [8:0] _T_800; // @[AtomicAutomata.scala 123:49:freechips.rocketchip.system.LowRiscConfig.fir@60105.4]
wire [7:0] _T_801; // @[AtomicAutomata.scala 123:54:freechips.rocketchip.system.LowRiscConfig.fir@60106.4]
wire [7:0] _T_802; // @[AtomicAutomata.scala 124:38:freechips.rocketchip.system.LowRiscConfig.fir@60107.4]
wire [8:0] _GEN_41; // @[AtomicAutomata.scala 124:49:freechips.rocketchip.system.LowRiscConfig.fir@60108.4]
wire [8:0] _T_803; // @[AtomicAutomata.scala 124:49:freechips.rocketchip.system.LowRiscConfig.fir@60108.4]
wire [7:0] _T_804; // @[AtomicAutomata.scala 124:54:freechips.rocketchip.system.LowRiscConfig.fir@60109.4]
wire [8:0] _GEN_42; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60110.4]
wire [8:0] _T_805; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60110.4]
wire [7:0] _T_806; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60111.4]
wire [7:0] _T_807; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60112.4]
wire [9:0] _GEN_43; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60113.4]
wire [9:0] _T_808; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60113.4]
wire [7:0] _T_809; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60114.4]
wire [7:0] _T_810; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60115.4]
wire [11:0] _GEN_44; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60116.4]
wire [11:0] _T_811; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60116.4]
wire [7:0] _T_812; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60117.4]
wire [7:0] _T_813; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60118.4]
wire _T_815; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60120.4]
wire _T_816; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60121.4]
wire _T_817; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60122.4]
wire _T_818; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60123.4]
wire _T_819; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60124.4]
wire _T_820; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60125.4]
wire _T_821; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60126.4]
wire _T_822; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60127.4]
wire [7:0] _T_824; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60129.4]
wire [7:0] _T_826; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60131.4]
wire [7:0] _T_828; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60133.4]
wire [7:0] _T_830; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60135.4]
wire [7:0] _T_832; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60137.4]
wire [7:0] _T_834; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60139.4]
wire [7:0] _T_836; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60141.4]
wire [7:0] _T_838; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60143.4]
wire [63:0] _T_845; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60150.4]
wire [8:0] _GEN_45; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60151.4]
wire [8:0] _T_846; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60151.4]
wire [7:0] _T_847; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60152.4]
wire [7:0] _T_848; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60153.4]
wire [9:0] _GEN_46; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60154.4]
wire [9:0] _T_849; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60154.4]
wire [7:0] _T_850; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60155.4]
wire [7:0] _T_851; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60156.4]
wire [11:0] _GEN_47; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60157.4]
wire [11:0] _T_852; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60157.4]
wire [7:0] _T_853; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60158.4]
wire [7:0] _T_854; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60159.4]
wire _T_856; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60161.4]
wire _T_857; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60162.4]
wire _T_858; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60163.4]
wire _T_859; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60164.4]
wire _T_860; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60165.4]
wire _T_861; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60166.4]
wire _T_862; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60167.4]
wire _T_863; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60168.4]
wire [7:0] _T_865; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60170.4]
wire [7:0] _T_867; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60172.4]
wire [7:0] _T_869; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60174.4]
wire [7:0] _T_871; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60176.4]
wire [7:0] _T_873; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60178.4]
wire [7:0] _T_875; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60180.4]
wire [7:0] _T_877; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60182.4]
wire [7:0] _T_879; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60184.4]
wire [63:0] _T_886; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60191.4]
wire _T_887; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60192.4]
wire _T_888; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60193.4]
wire _T_889; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60194.4]
wire _T_890; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60195.4]
wire _T_891; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60196.4]
wire _T_892; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60197.4]
wire _T_893; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60198.4]
wire _T_894; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60199.4]
wire [7:0] _T_896; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60201.4]
wire [7:0] _T_898; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60203.4]
wire [7:0] _T_900; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60205.4]
wire [7:0] _T_902; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60207.4]
wire [7:0] _T_904; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60209.4]
wire [7:0] _T_906; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60211.4]
wire [7:0] _T_908; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60213.4]
wire [7:0] _T_910; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60215.4]
wire [63:0] _T_917; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60222.4]
wire [63:0] _T_918; // @[AtomicAutomata.scala 129:28:freechips.rocketchip.system.LowRiscConfig.fir@60223.4]
wire [63:0] _T_919; // @[AtomicAutomata.scala 129:41:freechips.rocketchip.system.LowRiscConfig.fir@60224.4]
wire [63:0] _T_920; // @[AtomicAutomata.scala 130:28:freechips.rocketchip.system.LowRiscConfig.fir@60225.4]
wire [63:0] _T_921; // @[AtomicAutomata.scala 130:41:freechips.rocketchip.system.LowRiscConfig.fir@60226.4]
wire [63:0] _T_922; // @[AtomicAutomata.scala 131:43:freechips.rocketchip.system.LowRiscConfig.fir@60227.4]
wire [63:0] _T_923; // @[AtomicAutomata.scala 131:26:freechips.rocketchip.system.LowRiscConfig.fir@60228.4]
wire [63:0] _T_925; // @[AtomicAutomata.scala 132:33:freechips.rocketchip.system.LowRiscConfig.fir@60230.4]
wire _T_926; // @[AtomicAutomata.scala 134:49:freechips.rocketchip.system.LowRiscConfig.fir@60231.4]
wire _T_927; // @[AtomicAutomata.scala 134:38:freechips.rocketchip.system.LowRiscConfig.fir@60232.4]
wire _T_929; // @[AtomicAutomata.scala 135:50:freechips.rocketchip.system.LowRiscConfig.fir@60234.4]
wire _T_930; // @[AtomicAutomata.scala 135:39:freechips.rocketchip.system.LowRiscConfig.fir@60235.4]
wire _T_931; // @[AtomicAutomata.scala 135:65:freechips.rocketchip.system.LowRiscConfig.fir@60236.4]
wire _T_932; // @[AtomicAutomata.scala 135:55:freechips.rocketchip.system.LowRiscConfig.fir@60237.4]
wire _T_933; // @[AtomicAutomata.scala 135:27:freechips.rocketchip.system.LowRiscConfig.fir@60238.4]
wire _T_934; // @[AtomicAutomata.scala 136:31:freechips.rocketchip.system.LowRiscConfig.fir@60239.4]
wire [63:0] _T_935; // @[AtomicAutomata.scala 137:50:freechips.rocketchip.system.LowRiscConfig.fir@60240.4]
wire [63:0] _T_936; // @[AtomicAutomata.scala 137:28:freechips.rocketchip.system.LowRiscConfig.fir@60241.4]
wire _T_937; // @[AtomicAutomata.scala 143:34:freechips.rocketchip.system.LowRiscConfig.fir@60242.4]
wire [63:0] _T_938; // @[AtomicAutomata.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@60243.4]
wire _T_942; // @[AtomicAutomata.scala 147:23:freechips.rocketchip.system.LowRiscConfig.fir@60246.4]
wire _T_943; // @[AtomicAutomata.scala 147:53:freechips.rocketchip.system.LowRiscConfig.fir@60247.4]
wire _T_944; // @[AtomicAutomata.scala 147:35:freechips.rocketchip.system.LowRiscConfig.fir@60248.4]
reg [8:0] _T_1069; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@60388.4]
reg [31:0] _RAND_14;
wire _T_1070; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@60389.4]
wire _T_946; // @[AtomicAutomata.scala 149:38:freechips.rocketchip.system.LowRiscConfig.fir@60251.4]
wire [1:0] _T_1072; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60391.4]
wire [2:0] _GEN_48; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60392.4]
wire [2:0] _T_1073; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60392.4]
wire [1:0] _T_1074; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60393.4]
wire [1:0] _T_1075; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60394.4]
wire [2:0] _GEN_49; // @[Arbiter.scala 15:78:freechips.rocketchip.system.LowRiscConfig.fir@60396.4]
wire [2:0] _T_1077; // @[Arbiter.scala 15:78:freechips.rocketchip.system.LowRiscConfig.fir@60396.4]
wire [1:0] _T_1078; // @[Arbiter.scala 15:83:freechips.rocketchip.system.LowRiscConfig.fir@60397.4]
wire [1:0] _T_1079; // @[Arbiter.scala 15:61:freechips.rocketchip.system.LowRiscConfig.fir@60398.4]
wire _T_1081; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@60400.4]
reg _T_1143_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@60451.4]
reg [31:0] _RAND_15;
wire _T_1162_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@60454.4]
wire _T_1171; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@60457.4]
wire _T_947; // @[AtomicAutomata.scala 151:15:freechips.rocketchip.system.LowRiscConfig.fir@60254.4]
wire [2:0] _GEN_0; // @[AtomicAutomata.scala 151:31:freechips.rocketchip.system.LowRiscConfig.fir@60255.4]
wire [2:0] _GEN_1; // @[AtomicAutomata.scala 151:31:freechips.rocketchip.system.LowRiscConfig.fir@60255.4]
wire _T_951; // @[AtomicAutomata.scala 164:45:freechips.rocketchip.system.LowRiscConfig.fir@60262.4]
wire [1:0] _T_997; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@60313.4]
wire [3:0] _T_998; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@60314.4]
wire [2:0] _T_999; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@60315.4]
wire [2:0] _T_1000; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@60316.4]
wire _T_1001; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@60317.4]
wire _T_1002; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60318.4]
wire _T_1003; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60319.4]
wire _T_1004; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60320.4]
wire _T_1006; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60322.4]
wire _T_1007; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60323.4]
wire _T_1009; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60325.4]
wire _T_1010; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60326.4]
wire _T_1011; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60327.4]
wire _T_1012; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60328.4]
wire _T_1013; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60329.4]
wire _T_1014; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60330.4]
wire _T_1015; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60331.4]
wire _T_1016; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60332.4]
wire _T_1017; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60333.4]
wire _T_1018; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60334.4]
wire _T_1019; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60335.4]
wire _T_1020; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60336.4]
wire _T_1021; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60337.4]
wire _T_1022; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60338.4]
wire _T_1023; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60339.4]
wire _T_1024; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60340.4]
wire _T_1025; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60341.4]
wire _T_1026; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60342.4]
wire _T_1027; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60343.4]
wire _T_1028; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60344.4]
wire _T_1029; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60345.4]
wire _T_1030; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60346.4]
wire _T_1031; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60347.4]
wire _T_1032; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60348.4]
wire _T_1033; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60349.4]
wire _T_1034; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60350.4]
wire _T_1035; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60351.4]
wire _T_1036; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60352.4]
wire _T_1037; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60353.4]
wire _T_1038; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60354.4]
wire _T_1039; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60355.4]
wire _T_1040; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60356.4]
wire _T_1041; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60357.4]
wire _T_1042; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60358.4]
wire _T_1043; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60359.4]
wire _T_1044; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60360.4]
wire _T_1045; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60361.4]
wire _T_1046; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60362.4]
wire _T_1047; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60363.4]
wire _T_1048; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60364.4]
wire _T_1049; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60365.4]
wire _T_1050; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60366.4]
wire _T_1051; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60367.4]
wire _T_1052; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60368.4]
wire [26:0] _T_1061; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@60381.4]
wire [11:0] _T_1062; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@60382.4]
wire [11:0] _T_1063; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@60383.4]
wire [8:0] _T_1064; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@60384.4]
wire _T_1065; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@60385.4]
wire _T_1066; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@60386.4]
wire _T_1071; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@60390.4]
wire _T_1080; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@60399.4]
wire _T_1090; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@60405.4]
wire _T_1091; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@60406.4]
wire _T_1101; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@60412.4]
wire _T_1103; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@60414.4]
wire _T_1106; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@60417.4]
wire _T_1107; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@60418.4]
wire _T_1110; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@60421.4]
wire _T_1111; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@60422.4]
wire _T_1112; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@60427.4]
wire _T_1113; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@60428.4]
wire _T_1115; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@60430.4]
wire _T_1117; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@60432.4]
wire _T_1118; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@60433.4]
reg _T_1143_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@60451.4]
reg [31:0] _RAND_16;
wire _T_1174; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60460.4]
wire _T_1175; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60461.4]
wire _T_1176; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60462.4]
wire _T_1179; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@60465.4]
wire _T_1122; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60441.4]
wire [8:0] _GEN_50; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60442.4]
wire [9:0] _T_1123; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60442.4]
wire [9:0] _T_1124; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60443.4]
wire [8:0] _T_1125; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60444.4]
wire _T_1154_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@60452.4]
wire _T_1154_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@60452.4]
wire _T_1162_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@60454.4]
wire _T_1170; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@60455.4]
wire [64:0] _T_1181; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60467.4]
wire [100:0] _T_1183; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60469.4]
wire [115:0] _T_1187; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60473.4]
wire [115:0] _T_1188; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60474.4]
wire [115:0] _T_1195; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60481.4]
wire [115:0] _T_1196; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60482.4]
wire [115:0] _T_1197; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60483.4]
wire _T_1210; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60504.4]
wire _T_1212; // @[AtomicAutomata.scala 170:31:freechips.rocketchip.system.LowRiscConfig.fir@60506.4]
wire [1:0] _T_1213; // @[AtomicAutomata.scala 175:52:freechips.rocketchip.system.LowRiscConfig.fir@60511.8]
wire [2:0] _GEN_51; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60512.8]
wire _T_1214; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60512.8]
wire _T_1216; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60514.8]
wire _T_1218; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60516.8]
wire _T_1220; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60518.8]
wire _T_1222; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60526.4]
reg [8:0] _T_1232; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@60540.4]
reg [31:0] _RAND_17;
wire _T_1236; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@60544.4]
wire _T_1248; // @[AtomicAutomata.scala 209:40:freechips.rocketchip.system.LowRiscConfig.fir@60559.4]
wire _T_1254; // @[AtomicAutomata.scala 228:30:freechips.rocketchip.system.LowRiscConfig.fir@60575.4]
wire _T_1244; // @[AtomicAutomata.scala 200:53:freechips.rocketchip.system.LowRiscConfig.fir@60555.4]
wire _T_1245; // @[AtomicAutomata.scala 201:83:freechips.rocketchip.system.LowRiscConfig.fir@60556.4]
wire _T_1255; // @[AtomicAutomata.scala 228:40:freechips.rocketchip.system.LowRiscConfig.fir@60576.4]
wire _T_1260; // @[AtomicAutomata.scala 232:35:freechips.rocketchip.system.LowRiscConfig.fir@60582.4]
wire _T_1223; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60532.4]
wire [26:0] _T_1225; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@60534.4]
wire [11:0] _T_1226; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@60535.4]
wire [11:0] _T_1227; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@60536.4]
wire [8:0] _T_1228; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@60537.4]
wire _T_1229; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@60538.4]
wire [9:0] _T_1233; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@60541.4]
wire [9:0] _T_1234; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@60542.4]
wire [8:0] _T_1235; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@60543.4]
wire _T_1249; // @[AtomicAutomata.scala 210:40:freechips.rocketchip.system.LowRiscConfig.fir@60560.4]
wire _T_1251; // @[AtomicAutomata.scala 212:28:freechips.rocketchip.system.LowRiscConfig.fir@60562.4]
wire _T_1252; // @[AtomicAutomata.scala 214:22:freechips.rocketchip.system.LowRiscConfig.fir@60564.6]
wire _T_1256; // @[AtomicAutomata.scala 229:33:freechips.rocketchip.system.LowRiscConfig.fir@60577.4]
wire _T_1257; // @[AtomicAutomata.scala 229:42:freechips.rocketchip.system.LowRiscConfig.fir@60578.4]
wire _T_1258; // @[AtomicAutomata.scala 231:38:freechips.rocketchip.system.LowRiscConfig.fir@60579.4]
wire _T_1261; // @[AtomicAutomata.scala 238:46:freechips.rocketchip.system.LowRiscConfig.fir@60588.6]
wire _T_1262; // @[AtomicAutomata.scala 239:46:freechips.rocketchip.system.LowRiscConfig.fir@60590.6]
TLMonitor_23 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@59535.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign _T_280 = _T_258_0_state == 2'h0; // @[AtomicAutomata.scala 78:44:freechips.rocketchip.system.LowRiscConfig.fir@59585.4]
assign _T_281 = _T_258_0_state == 2'h2; // @[AtomicAutomata.scala 79:44:freechips.rocketchip.system.LowRiscConfig.fir@59586.4]
assign _T_282 = _T_258_0_state == 2'h3; // @[AtomicAutomata.scala 80:49:freechips.rocketchip.system.LowRiscConfig.fir@59587.4]
assign _T_284 = _T_282 | _T_281; // @[AtomicAutomata.scala 80:57:freechips.rocketchip.system.LowRiscConfig.fir@59589.4]
assign _T_285 = _T_258_0_state != 2'h0; // @[AtomicAutomata.scala 81:49:freechips.rocketchip.system.LowRiscConfig.fir@59590.4]
assign _T_312 = auto_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@59617.4]
assign _T_315 = auto_in_a_bits_address ^ 28'h2000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@59620.4]
assign _T_316 = {1'b0,$signed(_T_315)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@59621.4]
assign _T_317 = $signed(_T_316) & $signed(29'sha012000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@59622.4]
assign _T_318 = $signed(_T_317); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@59623.4]
assign _T_319 = $signed(_T_318) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@59624.4]
assign _T_320 = _T_312 & _T_319; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@59625.4]
assign _T_362 = auto_in_a_bits_opcode == 3'h3; // @[AtomicAutomata.scala 88:47:freechips.rocketchip.system.LowRiscConfig.fir@59667.4]
assign _T_363 = auto_in_a_bits_opcode == 3'h2; // @[AtomicAutomata.scala 89:47:freechips.rocketchip.system.LowRiscConfig.fir@59668.4]
assign _T_364 = _T_363 ? _T_320 : 1'h1; // @[AtomicAutomata.scala 90:63:freechips.rocketchip.system.LowRiscConfig.fir@59669.4]
assign _T_365 = _T_362 ? _T_320 : _T_364; // @[AtomicAutomata.scala 90:32:freechips.rocketchip.system.LowRiscConfig.fir@59670.4]
assign _T_374 = _T_269_0_fifoId == 1'h0; // @[AtomicAutomata.scala 103:60:freechips.rocketchip.system.LowRiscConfig.fir@59679.4]
assign _T_375 = _T_284 & _T_374; // @[AtomicAutomata.scala 103:96:freechips.rocketchip.system.LowRiscConfig.fir@59680.4]
assign _T_379 = _T_269_0_bits_data[0]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59684.4]
assign _T_380 = _T_276_0_data[0]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59685.4]
assign _T_381 = {_T_379,_T_380}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59686.4]
assign _T_382 = _T_269_0_bits_data[1]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59687.4]
assign _T_383 = _T_276_0_data[1]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59688.4]
assign _T_384 = {_T_382,_T_383}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59689.4]
assign _T_385 = _T_269_0_bits_data[2]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59690.4]
assign _T_386 = _T_276_0_data[2]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59691.4]
assign _T_387 = {_T_385,_T_386}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59692.4]
assign _T_388 = _T_269_0_bits_data[3]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59693.4]
assign _T_389 = _T_276_0_data[3]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59694.4]
assign _T_390 = {_T_388,_T_389}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59695.4]
assign _T_391 = _T_269_0_bits_data[4]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59696.4]
assign _T_392 = _T_276_0_data[4]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59697.4]
assign _T_393 = {_T_391,_T_392}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59698.4]
assign _T_394 = _T_269_0_bits_data[5]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59699.4]
assign _T_395 = _T_276_0_data[5]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59700.4]
assign _T_396 = {_T_394,_T_395}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59701.4]
assign _T_397 = _T_269_0_bits_data[6]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59702.4]
assign _T_398 = _T_276_0_data[6]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59703.4]
assign _T_399 = {_T_397,_T_398}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59704.4]
assign _T_400 = _T_269_0_bits_data[7]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59705.4]
assign _T_401 = _T_276_0_data[7]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59706.4]
assign _T_402 = {_T_400,_T_401}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59707.4]
assign _T_403 = _T_269_0_bits_data[8]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59708.4]
assign _T_404 = _T_276_0_data[8]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59709.4]
assign _T_405 = {_T_403,_T_404}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59710.4]
assign _T_406 = _T_269_0_bits_data[9]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59711.4]
assign _T_407 = _T_276_0_data[9]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59712.4]
assign _T_408 = {_T_406,_T_407}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59713.4]
assign _T_409 = _T_269_0_bits_data[10]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59714.4]
assign _T_410 = _T_276_0_data[10]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59715.4]
assign _T_411 = {_T_409,_T_410}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59716.4]
assign _T_412 = _T_269_0_bits_data[11]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59717.4]
assign _T_413 = _T_276_0_data[11]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59718.4]
assign _T_414 = {_T_412,_T_413}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59719.4]
assign _T_415 = _T_269_0_bits_data[12]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59720.4]
assign _T_416 = _T_276_0_data[12]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59721.4]
assign _T_417 = {_T_415,_T_416}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59722.4]
assign _T_418 = _T_269_0_bits_data[13]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59723.4]
assign _T_419 = _T_276_0_data[13]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59724.4]
assign _T_420 = {_T_418,_T_419}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59725.4]
assign _T_421 = _T_269_0_bits_data[14]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59726.4]
assign _T_422 = _T_276_0_data[14]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59727.4]
assign _T_423 = {_T_421,_T_422}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59728.4]
assign _T_424 = _T_269_0_bits_data[15]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59729.4]
assign _T_425 = _T_276_0_data[15]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59730.4]
assign _T_426 = {_T_424,_T_425}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59731.4]
assign _T_427 = _T_269_0_bits_data[16]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59732.4]
assign _T_428 = _T_276_0_data[16]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59733.4]
assign _T_429 = {_T_427,_T_428}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59734.4]
assign _T_430 = _T_269_0_bits_data[17]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59735.4]
assign _T_431 = _T_276_0_data[17]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59736.4]
assign _T_432 = {_T_430,_T_431}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59737.4]
assign _T_433 = _T_269_0_bits_data[18]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59738.4]
assign _T_434 = _T_276_0_data[18]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59739.4]
assign _T_435 = {_T_433,_T_434}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59740.4]
assign _T_436 = _T_269_0_bits_data[19]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59741.4]
assign _T_437 = _T_276_0_data[19]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59742.4]
assign _T_438 = {_T_436,_T_437}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59743.4]
assign _T_439 = _T_269_0_bits_data[20]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59744.4]
assign _T_440 = _T_276_0_data[20]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59745.4]
assign _T_441 = {_T_439,_T_440}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59746.4]
assign _T_442 = _T_269_0_bits_data[21]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59747.4]
assign _T_443 = _T_276_0_data[21]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59748.4]
assign _T_444 = {_T_442,_T_443}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59749.4]
assign _T_445 = _T_269_0_bits_data[22]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59750.4]
assign _T_446 = _T_276_0_data[22]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59751.4]
assign _T_447 = {_T_445,_T_446}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59752.4]
assign _T_448 = _T_269_0_bits_data[23]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59753.4]
assign _T_449 = _T_276_0_data[23]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59754.4]
assign _T_450 = {_T_448,_T_449}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59755.4]
assign _T_451 = _T_269_0_bits_data[24]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59756.4]
assign _T_452 = _T_276_0_data[24]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59757.4]
assign _T_453 = {_T_451,_T_452}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59758.4]
assign _T_454 = _T_269_0_bits_data[25]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59759.4]
assign _T_455 = _T_276_0_data[25]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59760.4]
assign _T_456 = {_T_454,_T_455}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59761.4]
assign _T_457 = _T_269_0_bits_data[26]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59762.4]
assign _T_458 = _T_276_0_data[26]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59763.4]
assign _T_459 = {_T_457,_T_458}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59764.4]
assign _T_460 = _T_269_0_bits_data[27]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59765.4]
assign _T_461 = _T_276_0_data[27]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59766.4]
assign _T_462 = {_T_460,_T_461}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59767.4]
assign _T_463 = _T_269_0_bits_data[28]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59768.4]
assign _T_464 = _T_276_0_data[28]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59769.4]
assign _T_465 = {_T_463,_T_464}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59770.4]
assign _T_466 = _T_269_0_bits_data[29]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59771.4]
assign _T_467 = _T_276_0_data[29]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59772.4]
assign _T_468 = {_T_466,_T_467}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59773.4]
assign _T_469 = _T_269_0_bits_data[30]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59774.4]
assign _T_470 = _T_276_0_data[30]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59775.4]
assign _T_471 = {_T_469,_T_470}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59776.4]
assign _T_472 = _T_269_0_bits_data[31]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59777.4]
assign _T_473 = _T_276_0_data[31]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59778.4]
assign _T_474 = {_T_472,_T_473}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59779.4]
assign _T_475 = _T_269_0_bits_data[32]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59780.4]
assign _T_476 = _T_276_0_data[32]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59781.4]
assign _T_477 = {_T_475,_T_476}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59782.4]
assign _T_478 = _T_269_0_bits_data[33]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59783.4]
assign _T_479 = _T_276_0_data[33]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59784.4]
assign _T_480 = {_T_478,_T_479}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59785.4]
assign _T_481 = _T_269_0_bits_data[34]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59786.4]
assign _T_482 = _T_276_0_data[34]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59787.4]
assign _T_483 = {_T_481,_T_482}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59788.4]
assign _T_484 = _T_269_0_bits_data[35]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59789.4]
assign _T_485 = _T_276_0_data[35]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59790.4]
assign _T_486 = {_T_484,_T_485}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59791.4]
assign _T_487 = _T_269_0_bits_data[36]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59792.4]
assign _T_488 = _T_276_0_data[36]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59793.4]
assign _T_489 = {_T_487,_T_488}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59794.4]
assign _T_490 = _T_269_0_bits_data[37]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59795.4]
assign _T_491 = _T_276_0_data[37]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59796.4]
assign _T_492 = {_T_490,_T_491}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59797.4]
assign _T_493 = _T_269_0_bits_data[38]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59798.4]
assign _T_494 = _T_276_0_data[38]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59799.4]
assign _T_495 = {_T_493,_T_494}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59800.4]
assign _T_496 = _T_269_0_bits_data[39]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59801.4]
assign _T_497 = _T_276_0_data[39]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59802.4]
assign _T_498 = {_T_496,_T_497}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59803.4]
assign _T_499 = _T_269_0_bits_data[40]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59804.4]
assign _T_500 = _T_276_0_data[40]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59805.4]
assign _T_501 = {_T_499,_T_500}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59806.4]
assign _T_502 = _T_269_0_bits_data[41]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59807.4]
assign _T_503 = _T_276_0_data[41]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59808.4]
assign _T_504 = {_T_502,_T_503}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59809.4]
assign _T_505 = _T_269_0_bits_data[42]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59810.4]
assign _T_506 = _T_276_0_data[42]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59811.4]
assign _T_507 = {_T_505,_T_506}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59812.4]
assign _T_508 = _T_269_0_bits_data[43]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59813.4]
assign _T_509 = _T_276_0_data[43]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59814.4]
assign _T_510 = {_T_508,_T_509}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59815.4]
assign _T_511 = _T_269_0_bits_data[44]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59816.4]
assign _T_512 = _T_276_0_data[44]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59817.4]
assign _T_513 = {_T_511,_T_512}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59818.4]
assign _T_514 = _T_269_0_bits_data[45]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59819.4]
assign _T_515 = _T_276_0_data[45]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59820.4]
assign _T_516 = {_T_514,_T_515}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59821.4]
assign _T_517 = _T_269_0_bits_data[46]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59822.4]
assign _T_518 = _T_276_0_data[46]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59823.4]
assign _T_519 = {_T_517,_T_518}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59824.4]
assign _T_520 = _T_269_0_bits_data[47]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59825.4]
assign _T_521 = _T_276_0_data[47]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59826.4]
assign _T_522 = {_T_520,_T_521}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59827.4]
assign _T_523 = _T_269_0_bits_data[48]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59828.4]
assign _T_524 = _T_276_0_data[48]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59829.4]
assign _T_525 = {_T_523,_T_524}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59830.4]
assign _T_526 = _T_269_0_bits_data[49]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59831.4]
assign _T_527 = _T_276_0_data[49]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59832.4]
assign _T_528 = {_T_526,_T_527}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59833.4]
assign _T_529 = _T_269_0_bits_data[50]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59834.4]
assign _T_530 = _T_276_0_data[50]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59835.4]
assign _T_531 = {_T_529,_T_530}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59836.4]
assign _T_532 = _T_269_0_bits_data[51]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59837.4]
assign _T_533 = _T_276_0_data[51]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59838.4]
assign _T_534 = {_T_532,_T_533}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59839.4]
assign _T_535 = _T_269_0_bits_data[52]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59840.4]
assign _T_536 = _T_276_0_data[52]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59841.4]
assign _T_537 = {_T_535,_T_536}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59842.4]
assign _T_538 = _T_269_0_bits_data[53]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59843.4]
assign _T_539 = _T_276_0_data[53]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59844.4]
assign _T_540 = {_T_538,_T_539}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59845.4]
assign _T_541 = _T_269_0_bits_data[54]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59846.4]
assign _T_542 = _T_276_0_data[54]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59847.4]
assign _T_543 = {_T_541,_T_542}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59848.4]
assign _T_544 = _T_269_0_bits_data[55]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59849.4]
assign _T_545 = _T_276_0_data[55]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59850.4]
assign _T_546 = {_T_544,_T_545}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59851.4]
assign _T_547 = _T_269_0_bits_data[56]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59852.4]
assign _T_548 = _T_276_0_data[56]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59853.4]
assign _T_549 = {_T_547,_T_548}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59854.4]
assign _T_550 = _T_269_0_bits_data[57]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59855.4]
assign _T_551 = _T_276_0_data[57]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59856.4]
assign _T_552 = {_T_550,_T_551}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59857.4]
assign _T_553 = _T_269_0_bits_data[58]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59858.4]
assign _T_554 = _T_276_0_data[58]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59859.4]
assign _T_555 = {_T_553,_T_554}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59860.4]
assign _T_556 = _T_269_0_bits_data[59]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59861.4]
assign _T_557 = _T_276_0_data[59]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59862.4]
assign _T_558 = {_T_556,_T_557}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59863.4]
assign _T_559 = _T_269_0_bits_data[60]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59864.4]
assign _T_560 = _T_276_0_data[60]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59865.4]
assign _T_561 = {_T_559,_T_560}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59866.4]
assign _T_562 = _T_269_0_bits_data[61]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59867.4]
assign _T_563 = _T_276_0_data[61]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59868.4]
assign _T_564 = {_T_562,_T_563}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59869.4]
assign _T_565 = _T_269_0_bits_data[62]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59870.4]
assign _T_566 = _T_276_0_data[62]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59871.4]
assign _T_567 = {_T_565,_T_566}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59872.4]
assign _T_568 = _T_269_0_bits_data[63]; // @[AtomicAutomata.scala 111:63:freechips.rocketchip.system.LowRiscConfig.fir@59873.4]
assign _T_569 = _T_276_0_data[63]; // @[AtomicAutomata.scala 111:73:freechips.rocketchip.system.LowRiscConfig.fir@59874.4]
assign _T_570 = {_T_568,_T_569}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@59875.4]
assign _T_571 = _T_269_0_lut >> _T_381; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59876.4]
assign _T_572 = _T_571[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59877.4]
assign _T_573 = _T_269_0_lut >> _T_384; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59878.4]
assign _T_574 = _T_573[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59879.4]
assign _T_575 = _T_269_0_lut >> _T_387; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59880.4]
assign _T_576 = _T_575[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59881.4]
assign _T_577 = _T_269_0_lut >> _T_390; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59882.4]
assign _T_578 = _T_577[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59883.4]
assign _T_579 = _T_269_0_lut >> _T_393; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59884.4]
assign _T_580 = _T_579[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59885.4]
assign _T_581 = _T_269_0_lut >> _T_396; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59886.4]
assign _T_582 = _T_581[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59887.4]
assign _T_583 = _T_269_0_lut >> _T_399; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59888.4]
assign _T_584 = _T_583[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59889.4]
assign _T_585 = _T_269_0_lut >> _T_402; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59890.4]
assign _T_586 = _T_585[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59891.4]
assign _T_587 = _T_269_0_lut >> _T_405; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59892.4]
assign _T_588 = _T_587[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59893.4]
assign _T_589 = _T_269_0_lut >> _T_408; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59894.4]
assign _T_590 = _T_589[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59895.4]
assign _T_591 = _T_269_0_lut >> _T_411; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59896.4]
assign _T_592 = _T_591[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59897.4]
assign _T_593 = _T_269_0_lut >> _T_414; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59898.4]
assign _T_594 = _T_593[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59899.4]
assign _T_595 = _T_269_0_lut >> _T_417; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59900.4]
assign _T_596 = _T_595[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59901.4]
assign _T_597 = _T_269_0_lut >> _T_420; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59902.4]
assign _T_598 = _T_597[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59903.4]
assign _T_599 = _T_269_0_lut >> _T_423; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59904.4]
assign _T_600 = _T_599[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59905.4]
assign _T_601 = _T_269_0_lut >> _T_426; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59906.4]
assign _T_602 = _T_601[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59907.4]
assign _T_603 = _T_269_0_lut >> _T_429; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59908.4]
assign _T_604 = _T_603[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59909.4]
assign _T_605 = _T_269_0_lut >> _T_432; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59910.4]
assign _T_606 = _T_605[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59911.4]
assign _T_607 = _T_269_0_lut >> _T_435; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59912.4]
assign _T_608 = _T_607[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59913.4]
assign _T_609 = _T_269_0_lut >> _T_438; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59914.4]
assign _T_610 = _T_609[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59915.4]
assign _T_611 = _T_269_0_lut >> _T_441; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59916.4]
assign _T_612 = _T_611[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59917.4]
assign _T_613 = _T_269_0_lut >> _T_444; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59918.4]
assign _T_614 = _T_613[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59919.4]
assign _T_615 = _T_269_0_lut >> _T_447; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59920.4]
assign _T_616 = _T_615[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59921.4]
assign _T_617 = _T_269_0_lut >> _T_450; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59922.4]
assign _T_618 = _T_617[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59923.4]
assign _T_619 = _T_269_0_lut >> _T_453; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59924.4]
assign _T_620 = _T_619[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59925.4]
assign _T_621 = _T_269_0_lut >> _T_456; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59926.4]
assign _T_622 = _T_621[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59927.4]
assign _T_623 = _T_269_0_lut >> _T_459; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59928.4]
assign _T_624 = _T_623[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59929.4]
assign _T_625 = _T_269_0_lut >> _T_462; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59930.4]
assign _T_626 = _T_625[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59931.4]
assign _T_627 = _T_269_0_lut >> _T_465; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59932.4]
assign _T_628 = _T_627[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59933.4]
assign _T_629 = _T_269_0_lut >> _T_468; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59934.4]
assign _T_630 = _T_629[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59935.4]
assign _T_631 = _T_269_0_lut >> _T_471; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59936.4]
assign _T_632 = _T_631[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59937.4]
assign _T_633 = _T_269_0_lut >> _T_474; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59938.4]
assign _T_634 = _T_633[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59939.4]
assign _T_635 = _T_269_0_lut >> _T_477; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59940.4]
assign _T_636 = _T_635[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59941.4]
assign _T_637 = _T_269_0_lut >> _T_480; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59942.4]
assign _T_638 = _T_637[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59943.4]
assign _T_639 = _T_269_0_lut >> _T_483; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59944.4]
assign _T_640 = _T_639[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59945.4]
assign _T_641 = _T_269_0_lut >> _T_486; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59946.4]
assign _T_642 = _T_641[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59947.4]
assign _T_643 = _T_269_0_lut >> _T_489; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59948.4]
assign _T_644 = _T_643[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59949.4]
assign _T_645 = _T_269_0_lut >> _T_492; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59950.4]
assign _T_646 = _T_645[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59951.4]
assign _T_647 = _T_269_0_lut >> _T_495; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59952.4]
assign _T_648 = _T_647[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59953.4]
assign _T_649 = _T_269_0_lut >> _T_498; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59954.4]
assign _T_650 = _T_649[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59955.4]
assign _T_651 = _T_269_0_lut >> _T_501; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59956.4]
assign _T_652 = _T_651[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59957.4]
assign _T_653 = _T_269_0_lut >> _T_504; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59958.4]
assign _T_654 = _T_653[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59959.4]
assign _T_655 = _T_269_0_lut >> _T_507; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59960.4]
assign _T_656 = _T_655[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59961.4]
assign _T_657 = _T_269_0_lut >> _T_510; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59962.4]
assign _T_658 = _T_657[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59963.4]
assign _T_659 = _T_269_0_lut >> _T_513; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59964.4]
assign _T_660 = _T_659[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59965.4]
assign _T_661 = _T_269_0_lut >> _T_516; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59966.4]
assign _T_662 = _T_661[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59967.4]
assign _T_663 = _T_269_0_lut >> _T_519; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59968.4]
assign _T_664 = _T_663[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59969.4]
assign _T_665 = _T_269_0_lut >> _T_522; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59970.4]
assign _T_666 = _T_665[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59971.4]
assign _T_667 = _T_269_0_lut >> _T_525; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59972.4]
assign _T_668 = _T_667[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59973.4]
assign _T_669 = _T_269_0_lut >> _T_528; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59974.4]
assign _T_670 = _T_669[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59975.4]
assign _T_671 = _T_269_0_lut >> _T_531; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59976.4]
assign _T_672 = _T_671[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59977.4]
assign _T_673 = _T_269_0_lut >> _T_534; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59978.4]
assign _T_674 = _T_673[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59979.4]
assign _T_675 = _T_269_0_lut >> _T_537; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59980.4]
assign _T_676 = _T_675[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59981.4]
assign _T_677 = _T_269_0_lut >> _T_540; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59982.4]
assign _T_678 = _T_677[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59983.4]
assign _T_679 = _T_269_0_lut >> _T_543; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59984.4]
assign _T_680 = _T_679[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59985.4]
assign _T_681 = _T_269_0_lut >> _T_546; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59986.4]
assign _T_682 = _T_681[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59987.4]
assign _T_683 = _T_269_0_lut >> _T_549; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59988.4]
assign _T_684 = _T_683[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59989.4]
assign _T_685 = _T_269_0_lut >> _T_552; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59990.4]
assign _T_686 = _T_685[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59991.4]
assign _T_687 = _T_269_0_lut >> _T_555; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59992.4]
assign _T_688 = _T_687[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59993.4]
assign _T_689 = _T_269_0_lut >> _T_558; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59994.4]
assign _T_690 = _T_689[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59995.4]
assign _T_691 = _T_269_0_lut >> _T_561; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59996.4]
assign _T_692 = _T_691[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59997.4]
assign _T_693 = _T_269_0_lut >> _T_564; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59998.4]
assign _T_694 = _T_693[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@59999.4]
assign _T_695 = _T_269_0_lut >> _T_567; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60000.4]
assign _T_696 = _T_695[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60001.4]
assign _T_697 = _T_269_0_lut >> _T_570; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60002.4]
assign _T_698 = _T_697[0]; // @[AtomicAutomata.scala 112:57:freechips.rocketchip.system.LowRiscConfig.fir@60003.4]
assign _T_705 = {_T_586,_T_584,_T_582,_T_580,_T_578,_T_576,_T_574,_T_572}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60010.4]
assign _T_713 = {_T_602,_T_600,_T_598,_T_596,_T_594,_T_592,_T_590,_T_588,_T_705}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60018.4]
assign _T_720 = {_T_618,_T_616,_T_614,_T_612,_T_610,_T_608,_T_606,_T_604}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60025.4]
assign _T_729 = {_T_634,_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_720,_T_713}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60034.4]
assign _T_736 = {_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60041.4]
assign _T_744 = {_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654,_T_652,_T_736}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60049.4]
assign _T_751 = {_T_682,_T_680,_T_678,_T_676,_T_674,_T_672,_T_670,_T_668}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60056.4]
assign _T_760 = {_T_698,_T_696,_T_694,_T_692,_T_690,_T_688,_T_686,_T_684,_T_751,_T_744}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60065.4]
assign _T_761 = {_T_760,_T_729}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60066.4]
assign _T_762 = _T_269_0_bits_param[1]; // @[AtomicAutomata.scala 115:42:freechips.rocketchip.system.LowRiscConfig.fir@60067.4]
assign _T_763 = _T_269_0_bits_param[0]; // @[AtomicAutomata.scala 116:42:freechips.rocketchip.system.LowRiscConfig.fir@60068.4]
assign _T_764 = _T_269_0_bits_param[2]; // @[AtomicAutomata.scala 117:39:freechips.rocketchip.system.LowRiscConfig.fir@60069.4]
assign _T_765 = ~ _T_269_0_bits_mask; // @[AtomicAutomata.scala 119:25:freechips.rocketchip.system.LowRiscConfig.fir@60070.4]
assign _T_766 = _T_269_0_bits_mask[7:1]; // @[AtomicAutomata.scala 119:39:freechips.rocketchip.system.LowRiscConfig.fir@60071.4]
assign _GEN_39 = {{1'd0}, _T_766}; // @[AtomicAutomata.scala 119:31:freechips.rocketchip.system.LowRiscConfig.fir@60072.4]
assign _T_767 = _T_765 | _GEN_39; // @[AtomicAutomata.scala 119:31:freechips.rocketchip.system.LowRiscConfig.fir@60072.4]
assign _T_768 = ~ _T_767; // @[AtomicAutomata.scala 119:23:freechips.rocketchip.system.LowRiscConfig.fir@60073.4]
assign _T_783 = {_T_568,_T_544,_T_520,_T_496,_T_472,_T_448,_T_424,_T_400}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60088.4]
assign _T_798 = {_T_569,_T_545,_T_521,_T_497,_T_473,_T_449,_T_425,_T_401}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60103.4]
assign _T_799 = _T_783 & _T_768; // @[AtomicAutomata.scala 123:38:freechips.rocketchip.system.LowRiscConfig.fir@60104.4]
assign _GEN_40 = {{1'd0}, _T_799}; // @[AtomicAutomata.scala 123:49:freechips.rocketchip.system.LowRiscConfig.fir@60105.4]
assign _T_800 = _GEN_40 << 1; // @[AtomicAutomata.scala 123:49:freechips.rocketchip.system.LowRiscConfig.fir@60105.4]
assign _T_801 = _T_800[7:0]; // @[AtomicAutomata.scala 123:54:freechips.rocketchip.system.LowRiscConfig.fir@60106.4]
assign _T_802 = _T_798 & _T_768; // @[AtomicAutomata.scala 124:38:freechips.rocketchip.system.LowRiscConfig.fir@60107.4]
assign _GEN_41 = {{1'd0}, _T_802}; // @[AtomicAutomata.scala 124:49:freechips.rocketchip.system.LowRiscConfig.fir@60108.4]
assign _T_803 = _GEN_41 << 1; // @[AtomicAutomata.scala 124:49:freechips.rocketchip.system.LowRiscConfig.fir@60108.4]
assign _T_804 = _T_803[7:0]; // @[AtomicAutomata.scala 124:54:freechips.rocketchip.system.LowRiscConfig.fir@60109.4]
assign _GEN_42 = {{1'd0}, _T_801}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60110.4]
assign _T_805 = _GEN_42 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60110.4]
assign _T_806 = _T_805[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60111.4]
assign _T_807 = _T_801 | _T_806; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60112.4]
assign _GEN_43 = {{2'd0}, _T_807}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60113.4]
assign _T_808 = _GEN_43 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60113.4]
assign _T_809 = _T_808[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60114.4]
assign _T_810 = _T_807 | _T_809; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60115.4]
assign _GEN_44 = {{4'd0}, _T_810}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60116.4]
assign _T_811 = _GEN_44 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60116.4]
assign _T_812 = _T_811[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60117.4]
assign _T_813 = _T_810 | _T_812; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60118.4]
assign _T_815 = _T_813[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60120.4]
assign _T_816 = _T_813[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60121.4]
assign _T_817 = _T_813[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60122.4]
assign _T_818 = _T_813[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60123.4]
assign _T_819 = _T_813[4]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60124.4]
assign _T_820 = _T_813[5]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60125.4]
assign _T_821 = _T_813[6]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60126.4]
assign _T_822 = _T_813[7]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60127.4]
assign _T_824 = _T_815 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60129.4]
assign _T_826 = _T_816 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60131.4]
assign _T_828 = _T_817 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60133.4]
assign _T_830 = _T_818 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60135.4]
assign _T_832 = _T_819 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60137.4]
assign _T_834 = _T_820 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60139.4]
assign _T_836 = _T_821 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60141.4]
assign _T_838 = _T_822 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60143.4]
assign _T_845 = {_T_838,_T_836,_T_834,_T_832,_T_830,_T_828,_T_826,_T_824}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60150.4]
assign _GEN_45 = {{1'd0}, _T_804}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60151.4]
assign _T_846 = _GEN_45 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60151.4]
assign _T_847 = _T_846[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60152.4]
assign _T_848 = _T_804 | _T_847; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60153.4]
assign _GEN_46 = {{2'd0}, _T_848}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60154.4]
assign _T_849 = _GEN_46 << 2; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60154.4]
assign _T_850 = _T_849[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60155.4]
assign _T_851 = _T_848 | _T_850; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60156.4]
assign _GEN_47 = {{4'd0}, _T_851}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60157.4]
assign _T_852 = _GEN_47 << 4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60157.4]
assign _T_853 = _T_852[7:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60158.4]
assign _T_854 = _T_851 | _T_853; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60159.4]
assign _T_856 = _T_854[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60161.4]
assign _T_857 = _T_854[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60162.4]
assign _T_858 = _T_854[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60163.4]
assign _T_859 = _T_854[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60164.4]
assign _T_860 = _T_854[4]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60165.4]
assign _T_861 = _T_854[5]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60166.4]
assign _T_862 = _T_854[6]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60167.4]
assign _T_863 = _T_854[7]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60168.4]
assign _T_865 = _T_856 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60170.4]
assign _T_867 = _T_857 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60172.4]
assign _T_869 = _T_858 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60174.4]
assign _T_871 = _T_859 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60176.4]
assign _T_873 = _T_860 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60178.4]
assign _T_875 = _T_861 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60180.4]
assign _T_877 = _T_862 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60182.4]
assign _T_879 = _T_863 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60184.4]
assign _T_886 = {_T_879,_T_877,_T_875,_T_873,_T_871,_T_869,_T_867,_T_865}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60191.4]
assign _T_887 = _T_269_0_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60192.4]
assign _T_888 = _T_269_0_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60193.4]
assign _T_889 = _T_269_0_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60194.4]
assign _T_890 = _T_269_0_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60195.4]
assign _T_891 = _T_269_0_bits_mask[4]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60196.4]
assign _T_892 = _T_269_0_bits_mask[5]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60197.4]
assign _T_893 = _T_269_0_bits_mask[6]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60198.4]
assign _T_894 = _T_269_0_bits_mask[7]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@60199.4]
assign _T_896 = _T_887 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60201.4]
assign _T_898 = _T_888 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60203.4]
assign _T_900 = _T_889 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60205.4]
assign _T_902 = _T_890 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60207.4]
assign _T_904 = _T_891 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60209.4]
assign _T_906 = _T_892 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60211.4]
assign _T_908 = _T_893 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60213.4]
assign _T_910 = _T_894 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@60215.4]
assign _T_917 = {_T_910,_T_908,_T_906,_T_904,_T_902,_T_900,_T_898,_T_896}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60222.4]
assign _T_918 = _T_269_0_bits_data & _T_917; // @[AtomicAutomata.scala 129:28:freechips.rocketchip.system.LowRiscConfig.fir@60223.4]
assign _T_919 = _T_918 | _T_845; // @[AtomicAutomata.scala 129:41:freechips.rocketchip.system.LowRiscConfig.fir@60224.4]
assign _T_920 = _T_276_0_data & _T_917; // @[AtomicAutomata.scala 130:28:freechips.rocketchip.system.LowRiscConfig.fir@60225.4]
assign _T_921 = _T_920 | _T_886; // @[AtomicAutomata.scala 130:41:freechips.rocketchip.system.LowRiscConfig.fir@60226.4]
assign _T_922 = ~ _T_921; // @[AtomicAutomata.scala 131:43:freechips.rocketchip.system.LowRiscConfig.fir@60227.4]
assign _T_923 = _T_764 ? _T_921 : _T_922; // @[AtomicAutomata.scala 131:26:freechips.rocketchip.system.LowRiscConfig.fir@60228.4]
assign _T_925 = _T_919 + _T_923; // @[AtomicAutomata.scala 132:33:freechips.rocketchip.system.LowRiscConfig.fir@60230.4]
assign _T_926 = _T_919[63]; // @[AtomicAutomata.scala 134:49:freechips.rocketchip.system.LowRiscConfig.fir@60231.4]
assign _T_927 = _T_762 == _T_926; // @[AtomicAutomata.scala 134:38:freechips.rocketchip.system.LowRiscConfig.fir@60232.4]
assign _T_929 = _T_921[63]; // @[AtomicAutomata.scala 135:50:freechips.rocketchip.system.LowRiscConfig.fir@60234.4]
assign _T_930 = _T_926 == _T_929; // @[AtomicAutomata.scala 135:39:freechips.rocketchip.system.LowRiscConfig.fir@60235.4]
assign _T_931 = _T_925[63]; // @[AtomicAutomata.scala 135:65:freechips.rocketchip.system.LowRiscConfig.fir@60236.4]
assign _T_932 = _T_931 == 1'h0; // @[AtomicAutomata.scala 135:55:freechips.rocketchip.system.LowRiscConfig.fir@60237.4]
assign _T_933 = _T_930 ? _T_932 : _T_927; // @[AtomicAutomata.scala 135:27:freechips.rocketchip.system.LowRiscConfig.fir@60238.4]
assign _T_934 = _T_763 == _T_933; // @[AtomicAutomata.scala 136:31:freechips.rocketchip.system.LowRiscConfig.fir@60239.4]
assign _T_935 = _T_934 ? _T_269_0_bits_data : _T_276_0_data; // @[AtomicAutomata.scala 137:50:freechips.rocketchip.system.LowRiscConfig.fir@60240.4]
assign _T_936 = _T_764 ? _T_925 : _T_935; // @[AtomicAutomata.scala 137:28:freechips.rocketchip.system.LowRiscConfig.fir@60241.4]
assign _T_937 = _T_269_0_bits_opcode[0]; // @[AtomicAutomata.scala 143:34:freechips.rocketchip.system.LowRiscConfig.fir@60242.4]
assign _T_938 = _T_937 ? _T_761 : _T_936; // @[AtomicAutomata.scala 143:14:freechips.rocketchip.system.LowRiscConfig.fir@60243.4]
assign _T_942 = _T_375 == 1'h0; // @[AtomicAutomata.scala 147:23:freechips.rocketchip.system.LowRiscConfig.fir@60246.4]
assign _T_943 = _T_365 | _T_280; // @[AtomicAutomata.scala 147:53:freechips.rocketchip.system.LowRiscConfig.fir@60247.4]
assign _T_944 = _T_942 & _T_943; // @[AtomicAutomata.scala 147:35:freechips.rocketchip.system.LowRiscConfig.fir@60248.4]
assign _T_1070 = _T_1069 == 9'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@60389.4]
assign _T_946 = auto_in_a_valid & _T_944; // @[AtomicAutomata.scala 149:38:freechips.rocketchip.system.LowRiscConfig.fir@60251.4]
assign _T_1072 = {_T_946,_T_281}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60391.4]
assign _GEN_48 = {{1'd0}, _T_1072}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60392.4]
assign _T_1073 = _GEN_48 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@60392.4]
assign _T_1074 = _T_1073[1:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@60393.4]
assign _T_1075 = _T_1072 | _T_1074; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@60394.4]
assign _GEN_49 = {{1'd0}, _T_1075}; // @[Arbiter.scala 15:78:freechips.rocketchip.system.LowRiscConfig.fir@60396.4]
assign _T_1077 = _GEN_49 << 1; // @[Arbiter.scala 15:78:freechips.rocketchip.system.LowRiscConfig.fir@60396.4]
assign _T_1078 = _T_1077[1:0]; // @[Arbiter.scala 15:83:freechips.rocketchip.system.LowRiscConfig.fir@60397.4]
assign _T_1079 = ~ _T_1078; // @[Arbiter.scala 15:61:freechips.rocketchip.system.LowRiscConfig.fir@60398.4]
assign _T_1081 = _T_1079[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@60400.4]
assign _T_1162_1 = _T_1070 ? _T_1081 : _T_1143_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@60454.4]
assign _T_1171 = auto_out_a_ready & _T_1162_1; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@60457.4]
assign _T_947 = _T_365 == 1'h0; // @[AtomicAutomata.scala 151:15:freechips.rocketchip.system.LowRiscConfig.fir@60254.4]
assign _GEN_0 = _T_947 ? 3'h4 : auto_in_a_bits_opcode; // @[AtomicAutomata.scala 151:31:freechips.rocketchip.system.LowRiscConfig.fir@60255.4]
assign _GEN_1 = _T_947 ? 3'h0 : auto_in_a_bits_param; // @[AtomicAutomata.scala 151:31:freechips.rocketchip.system.LowRiscConfig.fir@60255.4]
assign _T_951 = _T_269_0_bits_corrupt | _T_276_0_corrupt; // @[AtomicAutomata.scala 164:45:freechips.rocketchip.system.LowRiscConfig.fir@60262.4]
assign _T_997 = _T_269_0_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@60313.4]
assign _T_998 = 4'h1 << _T_997; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@60314.4]
assign _T_999 = _T_998[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@60315.4]
assign _T_1000 = _T_999 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@60316.4]
assign _T_1001 = _T_269_0_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@60317.4]
assign _T_1002 = _T_1000[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60318.4]
assign _T_1003 = _T_269_0_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60319.4]
assign _T_1004 = _T_1003 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60320.4]
assign _T_1006 = _T_1002 & _T_1004; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60322.4]
assign _T_1007 = _T_1001 | _T_1006; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60323.4]
assign _T_1009 = _T_1002 & _T_1003; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60325.4]
assign _T_1010 = _T_1001 | _T_1009; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60326.4]
assign _T_1011 = _T_1000[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60327.4]
assign _T_1012 = _T_269_0_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60328.4]
assign _T_1013 = _T_1012 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60329.4]
assign _T_1014 = _T_1004 & _T_1013; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60330.4]
assign _T_1015 = _T_1011 & _T_1014; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60331.4]
assign _T_1016 = _T_1007 | _T_1015; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60332.4]
assign _T_1017 = _T_1004 & _T_1012; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60333.4]
assign _T_1018 = _T_1011 & _T_1017; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60334.4]
assign _T_1019 = _T_1007 | _T_1018; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60335.4]
assign _T_1020 = _T_1003 & _T_1013; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60336.4]
assign _T_1021 = _T_1011 & _T_1020; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60337.4]
assign _T_1022 = _T_1010 | _T_1021; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60338.4]
assign _T_1023 = _T_1003 & _T_1012; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60339.4]
assign _T_1024 = _T_1011 & _T_1023; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60340.4]
assign _T_1025 = _T_1010 | _T_1024; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60341.4]
assign _T_1026 = _T_1000[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60342.4]
assign _T_1027 = _T_269_0_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60343.4]
assign _T_1028 = _T_1027 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60344.4]
assign _T_1029 = _T_1014 & _T_1028; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60345.4]
assign _T_1030 = _T_1026 & _T_1029; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60346.4]
assign _T_1031 = _T_1016 | _T_1030; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60347.4]
assign _T_1032 = _T_1014 & _T_1027; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60348.4]
assign _T_1033 = _T_1026 & _T_1032; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60349.4]
assign _T_1034 = _T_1016 | _T_1033; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60350.4]
assign _T_1035 = _T_1017 & _T_1028; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60351.4]
assign _T_1036 = _T_1026 & _T_1035; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60352.4]
assign _T_1037 = _T_1019 | _T_1036; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60353.4]
assign _T_1038 = _T_1017 & _T_1027; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60354.4]
assign _T_1039 = _T_1026 & _T_1038; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60355.4]
assign _T_1040 = _T_1019 | _T_1039; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60356.4]
assign _T_1041 = _T_1020 & _T_1028; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60357.4]
assign _T_1042 = _T_1026 & _T_1041; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60358.4]
assign _T_1043 = _T_1022 | _T_1042; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60359.4]
assign _T_1044 = _T_1020 & _T_1027; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60360.4]
assign _T_1045 = _T_1026 & _T_1044; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60361.4]
assign _T_1046 = _T_1022 | _T_1045; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60362.4]
assign _T_1047 = _T_1023 & _T_1028; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60363.4]
assign _T_1048 = _T_1026 & _T_1047; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60364.4]
assign _T_1049 = _T_1025 | _T_1048; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60365.4]
assign _T_1050 = _T_1023 & _T_1027; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60366.4]
assign _T_1051 = _T_1026 & _T_1050; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60367.4]
assign _T_1052 = _T_1025 | _T_1051; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60368.4]
assign _T_1061 = 27'hfff << auto_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@60381.4]
assign _T_1062 = _T_1061[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@60382.4]
assign _T_1063 = ~ _T_1062; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@60383.4]
assign _T_1064 = _T_1063[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@60384.4]
assign _T_1065 = auto_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@60385.4]
assign _T_1066 = _T_1065 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@60386.4]
assign _T_1071 = _T_1070 & auto_out_a_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@60390.4]
assign _T_1080 = _T_1079[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@60399.4]
assign _T_1090 = _T_1080 & _T_281; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@60405.4]
assign _T_1091 = _T_1081 & _T_946; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@60406.4]
assign _T_1101 = _T_1090 | _T_1091; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@60412.4]
assign _T_1103 = _T_1090 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@60414.4]
assign _T_1106 = _T_1091 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@60417.4]
assign _T_1107 = _T_1103 | _T_1106; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@60418.4]
assign _T_1110 = _T_1107 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@60421.4]
assign _T_1111 = _T_1110 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@60422.4]
assign _T_1112 = _T_281 | _T_946; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@60427.4]
assign _T_1113 = _T_1112 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@60428.4]
assign _T_1115 = _T_1113 | _T_1101; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@60430.4]
assign _T_1117 = _T_1115 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@60432.4]
assign _T_1118 = _T_1117 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@60433.4]
assign _T_1174 = _T_1143_0 ? _T_281 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60460.4]
assign _T_1175 = _T_1143_1 ? _T_946 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60461.4]
assign _T_1176 = _T_1174 | _T_1175; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60462.4]
assign _T_1179 = _T_1070 ? _T_1112 : _T_1176; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@60465.4]
assign _T_1122 = auto_out_a_ready & _T_1179; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60441.4]
assign _GEN_50 = {{8'd0}, _T_1122}; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60442.4]
assign _T_1123 = _T_1069 - _GEN_50; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60442.4]
assign _T_1124 = $unsigned(_T_1123); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60443.4]
assign _T_1125 = _T_1124[8:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@60444.4]
assign _T_1154_0 = _T_1070 ? _T_1090 : _T_1143_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@60452.4]
assign _T_1154_1 = _T_1070 ? _T_1091 : _T_1143_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@60452.4]
assign _T_1162_0 = _T_1070 ? _T_1080 : _T_1143_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@60454.4]
assign _T_1170 = auto_out_a_ready & _T_1162_0; // @[Arbiter.scala 84:31:freechips.rocketchip.system.LowRiscConfig.fir@60455.4]
assign _T_1181 = {_T_938,_T_951}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60467.4]
assign _T_1183 = {_T_269_0_bits_address,_T_1052,_T_1049,_T_1046,_T_1043,_T_1040,_T_1037,_T_1034,_T_1031,_T_1181}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60469.4]
assign _T_1187 = {6'h0,_T_269_0_bits_size,_T_269_0_bits_source,_T_1183}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60473.4]
assign _T_1188 = _T_1154_0 ? _T_1187 : 116'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60474.4]
assign _T_1195 = {_GEN_0,_GEN_1,auto_in_a_bits_size,auto_in_a_bits_source,auto_in_a_bits_address,auto_in_a_bits_mask,auto_in_a_bits_data,auto_in_a_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60481.4]
assign _T_1196 = _T_1154_1 ? _T_1195 : 116'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60482.4]
assign _T_1197 = _T_1188 | _T_1196; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60483.4]
assign _T_1210 = _T_1171 & _T_946; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60504.4]
assign _T_1212 = _T_1210 & _T_947; // @[AtomicAutomata.scala 170:31:freechips.rocketchip.system.LowRiscConfig.fir@60506.4]
assign _T_1213 = auto_in_a_bits_param[1:0]; // @[AtomicAutomata.scala 175:52:freechips.rocketchip.system.LowRiscConfig.fir@60511.8]
assign _GEN_51 = {{1'd0}, _T_1213}; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60512.8]
assign _T_1214 = 3'h3 == _GEN_51; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60512.8]
assign _T_1216 = 3'h0 == _GEN_51; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60514.8]
assign _T_1218 = 3'h1 == _GEN_51; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60516.8]
assign _T_1220 = 3'h2 == _GEN_51; // @[Mux.scala 46:19:freechips.rocketchip.system.LowRiscConfig.fir@60518.8]
assign _T_1222 = _T_1170 & _T_281; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60526.4]
assign _T_1236 = _T_1232 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@60544.4]
assign _T_1248 = auto_out_d_bits_opcode == 3'h1; // @[AtomicAutomata.scala 209:40:freechips.rocketchip.system.LowRiscConfig.fir@60559.4]
assign _T_1254 = _T_1236 & _T_1248; // @[AtomicAutomata.scala 228:30:freechips.rocketchip.system.LowRiscConfig.fir@60575.4]
assign _T_1244 = _T_269_0_bits_source == auto_out_d_bits_source; // @[AtomicAutomata.scala 200:53:freechips.rocketchip.system.LowRiscConfig.fir@60555.4]
assign _T_1245 = _T_1244 & _T_285; // @[AtomicAutomata.scala 201:83:freechips.rocketchip.system.LowRiscConfig.fir@60556.4]
assign _T_1255 = _T_1254 & _T_1245; // @[AtomicAutomata.scala 228:40:freechips.rocketchip.system.LowRiscConfig.fir@60576.4]
assign _T_1260 = auto_in_d_ready | _T_1255; // @[AtomicAutomata.scala 232:35:freechips.rocketchip.system.LowRiscConfig.fir@60582.4]
assign _T_1223 = _T_1260 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@60532.4]
assign _T_1225 = 27'hfff << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@60534.4]
assign _T_1226 = _T_1225[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@60535.4]
assign _T_1227 = ~ _T_1226; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@60536.4]
assign _T_1228 = _T_1227[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@60537.4]
assign _T_1229 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@60538.4]
assign _T_1233 = _T_1232 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@60541.4]
assign _T_1234 = $unsigned(_T_1233); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@60542.4]
assign _T_1235 = _T_1234[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@60543.4]
assign _T_1249 = auto_out_d_bits_opcode == 3'h0; // @[AtomicAutomata.scala 210:40:freechips.rocketchip.system.LowRiscConfig.fir@60560.4]
assign _T_1251 = _T_1223 & _T_1236; // @[AtomicAutomata.scala 212:28:freechips.rocketchip.system.LowRiscConfig.fir@60562.4]
assign _T_1252 = _T_1245 & _T_1248; // @[AtomicAutomata.scala 214:22:freechips.rocketchip.system.LowRiscConfig.fir@60564.6]
assign _T_1256 = _T_1236 & _T_1249; // @[AtomicAutomata.scala 229:33:freechips.rocketchip.system.LowRiscConfig.fir@60577.4]
assign _T_1257 = _T_1256 & _T_1245; // @[AtomicAutomata.scala 229:42:freechips.rocketchip.system.LowRiscConfig.fir@60578.4]
assign _T_1258 = _T_1255 == 1'h0; // @[AtomicAutomata.scala 231:38:freechips.rocketchip.system.LowRiscConfig.fir@60579.4]
assign _T_1261 = _T_276_0_corrupt | auto_out_d_bits_denied; // @[AtomicAutomata.scala 238:46:freechips.rocketchip.system.LowRiscConfig.fir@60588.6]
assign _T_1262 = _T_276_0_denied | auto_out_d_bits_denied; // @[AtomicAutomata.scala 239:46:freechips.rocketchip.system.LowRiscConfig.fir@60590.6]
assign auto_in_a_ready = _T_1171 & _T_944; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_valid = auto_out_d_valid & _T_1258; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_opcode = _T_1257 ? 3'h1 : auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_denied = _T_1257 ? _T_1262 : auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_data = _T_1257 ? _T_276_0_data : auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_in_d_bits_corrupt = _T_1257 ? _T_1261 : auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@59575.4]
assign auto_out_a_valid = _T_1070 ? _T_1112 : _T_1176; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_opcode = _T_1197[115:113]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_param = _T_1197[112:110]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_size = _T_1197[109:106]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_source = _T_1197[105:101]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_address = _T_1197[100:73]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_mask = _T_1197[72:65]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_data = _T_1197[64:1]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_a_bits_corrupt = _T_1197[0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign auto_out_d_ready = auto_in_d_ready | _T_1255; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@59574.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@59537.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@59538.4]
assign TLMonitor_io_in_a_ready = _T_1171 & _T_944; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_1258; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_opcode = _T_1257 ? 3'h1 : auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_denied = _T_1257 ? _T_1262 : auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
assign TLMonitor_io_in_d_bits_corrupt = _T_1257 ? _T_1261 : auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@59571.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_258_0_state = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_269_0_bits_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_269_0_bits_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_269_0_bits_size = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_269_0_bits_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_269_0_bits_address = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_269_0_bits_mask = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {2{`RANDOM}};
_T_269_0_bits_data = _RAND_7[63:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_269_0_bits_corrupt = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_269_0_fifoId = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_269_0_lut = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {2{`RANDOM}};
_T_276_0_data = _RAND_11[63:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_276_0_denied = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_276_0_corrupt = _RAND_13[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1069 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1143_1 = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1143_0 = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_1232 = _RAND_17[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_258_0_state <= 2'h0;
end else begin
if (_T_1251) begin
if (_T_1245) begin
if (_T_1248) begin
_T_258_0_state <= 2'h2;
end else begin
_T_258_0_state <= 2'h0;
end
end else begin
if (_T_1222) begin
if (_T_281) begin
_T_258_0_state <= 2'h1;
end else begin
if (_T_1212) begin
if (_T_280) begin
_T_258_0_state <= 2'h3;
end
end
end
end else begin
if (_T_1212) begin
if (_T_280) begin
_T_258_0_state <= 2'h3;
end
end
end
end
end else begin
if (_T_1222) begin
if (_T_281) begin
_T_258_0_state <= 2'h1;
end else begin
if (_T_1212) begin
if (_T_280) begin
_T_258_0_state <= 2'h3;
end
end
end
end else begin
if (_T_1212) begin
if (_T_280) begin
_T_258_0_state <= 2'h3;
end
end
end
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_opcode <= auto_in_a_bits_opcode;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_param <= auto_in_a_bits_param;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_size <= auto_in_a_bits_size;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_source <= auto_in_a_bits_source;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_address <= auto_in_a_bits_address;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_mask <= auto_in_a_bits_mask;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_data <= auto_in_a_bits_data;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_bits_corrupt <= auto_in_a_bits_corrupt;
end
end
if (_T_1212) begin
if (_T_280) begin
_T_269_0_fifoId <= 1'h0;
end
end
if (_T_1212) begin
if (_T_280) begin
if (_T_1220) begin
_T_269_0_lut <= 4'h8;
end else begin
if (_T_1218) begin
_T_269_0_lut <= 4'he;
end else begin
if (_T_1216) begin
_T_269_0_lut <= 4'h6;
end else begin
if (_T_1214) begin
_T_269_0_lut <= 4'hc;
end else begin
_T_269_0_lut <= 4'h0;
end
end
end
end
end
end
if (_T_1251) begin
if (_T_1252) begin
_T_276_0_data <= auto_out_d_bits_data;
end
end
if (_T_1251) begin
if (_T_1252) begin
_T_276_0_denied <= auto_out_d_bits_denied;
end
end
if (_T_1251) begin
if (_T_1252) begin
_T_276_0_corrupt <= auto_out_d_bits_corrupt;
end
end
if (reset) begin
_T_1069 <= 9'h0;
end else begin
if (_T_1071) begin
if (_T_1091) begin
if (_T_1066) begin
_T_1069 <= _T_1064;
end else begin
_T_1069 <= 9'h0;
end
end else begin
_T_1069 <= 9'h0;
end
end else begin
_T_1069 <= _T_1125;
end
end
if (reset) begin
_T_1143_1 <= 1'h0;
end else begin
if (_T_1070) begin
_T_1143_1 <= _T_1091;
end
end
if (reset) begin
_T_1143_0 <= 1'h0;
end else begin
if (_T_1070) begin
_T_1143_0 <= _T_1090;
end
end
if (reset) begin
_T_1232 <= 9'h0;
end else begin
if (_T_1223) begin
if (_T_1236) begin
if (_T_1229) begin
_T_1232 <= _T_1228;
end else begin
_T_1232 <= 9'h0;
end
end else begin
_T_1232 <= _T_1235;
end
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1111) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@60424.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1111) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@60425.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1118) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@60435.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1118) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@60436.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_24( // @[:freechips.rocketchip.system.LowRiscConfig.fir@60607.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60608.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60609.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [13:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@60610.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@61980.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@60627.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@60628.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@60633.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@60634.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@60637.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@60638.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@60646.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60658.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60659.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60660.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60661.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@60663.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@60664.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@60665.6]
wire [13:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@60666.6]
wire [13:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@60666.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@60667.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@60669.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@60670.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@60671.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@60672.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@60673.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60674.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60675.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60676.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60678.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60679.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60681.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60682.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60683.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60684.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60685.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60686.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60687.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60688.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60689.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60690.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60691.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60692.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60693.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60694.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60695.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60696.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60697.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60698.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60699.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60700.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60701.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60702.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60703.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60704.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60705.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60706.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60707.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60708.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60709.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60710.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60711.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60712.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60713.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60714.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60715.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60716.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60717.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60718.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60719.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60720.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60721.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60722.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60723.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60724.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60731.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@60804.6]
wire [13:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@60807.8]
wire [14:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@60808.8]
wire [14:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@60809.8]
wire [14:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@60810.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@60811.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@60816.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@60854.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60855.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@60867.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@60868.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@60874.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@60875.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@60882.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@60883.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@60889.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@60890.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@60895.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@60897.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@60898.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@60903.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@60904.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@60906.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@60907.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@60912.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@60914.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@60915.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@60921.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@61020.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@61022.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@61023.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@61046.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@61049.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@61057.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61060.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61061.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@61080.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@61082.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@61083.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@61088.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@61090.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@61091.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@61105.6]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@61156.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@61198.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@61199.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@61200.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@61202.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@61203.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@61209.6]
wire _T_474; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@61212.8]
wire _T_482; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@61220.8]
wire _T_485; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61223.8]
wire _T_486; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61224.8]
wire _T_493; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@61243.8]
wire _T_495; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@61245.8]
wire _T_496; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@61246.8]
wire _T_501; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@61260.6]
wire _T_522; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@61294.8]
wire _T_524; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@61296.8]
wire _T_525; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@61297.8]
wire _T_530; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@61311.6]
wire _T_559; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@61364.6]
wire _T_561; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@61366.6]
wire _T_562; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@61367.6]
wire [2:0] _T_565; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@61374.6]
wire _T_566; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@61375.6]
wire _T_571; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@61380.6]
wire _T_572; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@61381.6]
wire [1:0] _T_575; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@61384.6]
wire _T_576; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@61385.6]
wire _T_584; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@61393.6]
wire _T_600; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61405.6]
wire _T_601; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61406.6]
wire _T_602; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61407.6]
wire _T_603; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61408.6]
wire _T_605; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@61410.6]
wire _T_607; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61413.8]
wire _T_608; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61414.8]
wire _T_609; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@61419.8]
wire _T_611; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@61421.8]
wire _T_612; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@61422.8]
wire _T_617; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@61435.8]
wire _T_619; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@61437.8]
wire _T_620; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@61438.8]
wire _T_625; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@61452.6]
wire _T_653; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@61510.6]
wire _T_675; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@61553.8]
wire _T_676; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@61554.8]
wire _T_682; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@61569.6]
wire _T_699; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@61604.6]
wire _T_717; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@61640.6]
wire _T_746; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@61700.4]
wire [8:0] _T_751; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@61705.4]
wire _T_752; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@61706.4]
wire _T_753; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@61707.4]
reg [8:0] _T_756; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@61709.4]
reg [31:0] _RAND_0;
wire [9:0] _T_757; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61710.4]
wire [9:0] _T_758; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61711.4]
wire [8:0] _T_759; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61712.4]
wire _T_760; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61713.4]
reg [2:0] _T_769; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@61724.4]
reg [31:0] _RAND_1;
reg [2:0] _T_771; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@61725.4]
reg [31:0] _RAND_2;
reg [3:0] _T_773; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@61726.4]
reg [31:0] _RAND_3;
reg [4:0] _T_775; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@61727.4]
reg [31:0] _RAND_4;
reg [13:0] _T_777; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@61728.4]
reg [31:0] _RAND_5;
wire _T_778; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@61729.4]
wire _T_779; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@61730.4]
wire _T_780; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@61732.6]
wire _T_782; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@61734.6]
wire _T_783; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@61735.6]
wire _T_784; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@61740.6]
wire _T_786; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@61742.6]
wire _T_787; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@61743.6]
wire _T_788; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@61748.6]
wire _T_790; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@61750.6]
wire _T_791; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@61751.6]
wire _T_792; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@61756.6]
wire _T_794; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@61758.6]
wire _T_795; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@61759.6]
wire _T_796; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@61764.6]
wire _T_798; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@61766.6]
wire _T_799; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@61767.6]
wire _T_801; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@61774.4]
wire _T_802; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@61782.4]
wire [26:0] _T_804; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@61784.4]
wire [11:0] _T_805; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@61785.4]
wire [11:0] _T_806; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@61786.4]
wire [8:0] _T_807; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@61787.4]
wire _T_808; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@61788.4]
reg [8:0] _T_811; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@61790.4]
reg [31:0] _RAND_6;
wire [9:0] _T_812; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61791.4]
wire [9:0] _T_813; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61792.4]
wire [8:0] _T_814; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61793.4]
wire _T_815; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61794.4]
reg [2:0] _T_824; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@61805.4]
reg [31:0] _RAND_7;
reg [3:0] _T_828; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@61807.4]
reg [31:0] _RAND_8;
reg [4:0] _T_830; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@61808.4]
reg [31:0] _RAND_9;
wire _T_835; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@61811.4]
wire _T_836; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@61812.4]
wire _T_837; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@61814.6]
wire _T_839; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@61816.6]
wire _T_840; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@61817.6]
wire _T_845; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@61830.6]
wire _T_847; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@61832.6]
wire _T_848; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@61833.6]
wire _T_849; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@61838.6]
wire _T_851; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@61840.6]
wire _T_852; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@61841.6]
wire _T_862; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@61864.4]
reg [24:0] _T_864; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@61873.4]
reg [31:0] _RAND_10;
reg [8:0] _T_875; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@61883.4]
reg [31:0] _RAND_11;
wire [9:0] _T_876; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61884.4]
wire [9:0] _T_877; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61885.4]
wire [8:0] _T_878; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61886.4]
wire _T_879; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61887.4]
reg [8:0] _T_896; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@61906.4]
reg [31:0] _RAND_12;
wire [9:0] _T_897; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61907.4]
wire [9:0] _T_898; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61908.4]
wire [8:0] _T_899; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61909.4]
wire _T_900; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61910.4]
wire _T_911; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@61925.4]
wire [31:0] _T_913; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@61928.6]
wire [24:0] _T_914; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@61930.6]
wire _T_915; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@61931.6]
wire _T_916; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@61932.6]
wire _T_918; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@61934.6]
wire _T_919; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@61935.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@61927.4]
wire _T_924; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@61946.4]
wire _T_926; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@61948.4]
wire _T_927; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@61949.4]
wire [31:0] _T_928; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@61951.6]
wire [24:0] _T_909; // @[:freechips.rocketchip.system.LowRiscConfig.fir@61921.4 :freechips.rocketchip.system.LowRiscConfig.fir@61923.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@61929.6]
wire [24:0] _T_929; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@61953.6]
wire [24:0] _T_930; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@61954.6]
wire _T_931; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@61955.6]
wire _T_933; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@61957.6]
wire _T_934; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@61958.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@61950.4]
wire [24:0] _T_921; // @[:freechips.rocketchip.system.LowRiscConfig.fir@61941.4 :freechips.rocketchip.system.LowRiscConfig.fir@61943.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@61952.6]
wire _T_935; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@61964.4]
wire _T_936; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@61965.4]
wire _T_937; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@61966.4]
wire _T_938; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@61967.4]
wire _T_940; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@61969.4]
wire _T_941; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@61970.4]
wire [24:0] _T_942; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@61975.4]
wire [24:0] _T_943; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@61976.4]
wire [24:0] _T_944; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@61977.4]
reg [31:0] _T_946; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@61979.4]
reg [31:0] _RAND_13;
wire _T_947; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@61982.4]
wire _T_948; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@61983.4]
wire _T_949; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@61984.4]
wire _T_950; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@61985.4]
wire _T_951; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@61986.4]
wire _T_952; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@61987.4]
wire _T_954; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@61989.4]
wire _T_955; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@61990.4]
wire [31:0] _T_957; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@61996.4]
wire _T_960; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@62000.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@60818.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@60935.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61063.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@61122.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@61173.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61226.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@61277.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@61328.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61416.10]
wire _GEN_123; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@61458.10]
wire _GEN_131; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@61516.10]
wire _GEN_139; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@61575.10]
wire _GEN_143; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@61610.10]
wire _GEN_147; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@61646.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@61980.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@60627.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@60628.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@60633.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@60634.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@60637.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@60638.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@60646.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60658.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60659.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60660.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@60661.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@60663.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@60664.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@60665.6]
assign _GEN_18 = {{2'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@60666.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@60666.6]
assign _T_66 = _T_65 == 14'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@60667.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@60669.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@60670.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@60671.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@60672.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@60673.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60674.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60675.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60676.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60678.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60679.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60681.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60682.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60683.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60684.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60685.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60686.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60687.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60688.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60689.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60690.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60691.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60692.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60693.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60694.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60695.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60696.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60697.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@60698.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@60699.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@60700.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60701.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60702.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60703.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60704.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60705.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60706.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60707.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60708.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60709.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60710.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60711.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60712.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60713.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60714.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60715.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60716.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60717.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60718.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60719.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60720.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60721.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@60722.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@60723.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@60724.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@60731.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@60804.6]
assign _T_201 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@60807.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@60808.8]
assign _T_203 = $signed(_T_202) & $signed(-15'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@60809.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@60810.8]
assign _T_205 = $signed(_T_204) == $signed(15'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@60811.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@60816.8]
assign _T_248 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@60854.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@60855.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@60867.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@60868.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@60874.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@60875.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@60882.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@60883.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@60889.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@60890.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@60895.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@60897.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@60898.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@60903.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@60904.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@60906.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@60907.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@60912.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@60914.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@60915.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@60921.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@61020.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@61022.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@61023.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@61046.6]
assign _T_381 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@61049.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@61057.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61060.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61061.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@61080.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@61082.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@61083.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@61088.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@61090.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@61091.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@61105.6]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@61156.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@61198.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@61199.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@61200.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@61202.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@61203.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@61209.6]
assign _T_474 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@61212.8]
assign _T_482 = _T_474 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@61220.8]
assign _T_485 = _T_482 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61223.8]
assign _T_486 = _T_485 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61224.8]
assign _T_493 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@61243.8]
assign _T_495 = _T_493 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@61245.8]
assign _T_496 = _T_495 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@61246.8]
assign _T_501 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@61260.6]
assign _T_522 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@61294.8]
assign _T_524 = _T_522 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@61296.8]
assign _T_525 = _T_524 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@61297.8]
assign _T_530 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@61311.6]
assign _T_559 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@61364.6]
assign _T_561 = _T_559 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@61366.6]
assign _T_562 = _T_561 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@61367.6]
assign _T_565 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@61374.6]
assign _T_566 = _T_565 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@61375.6]
assign _T_571 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@61380.6]
assign _T_572 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@61381.6]
assign _T_575 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@61384.6]
assign _T_576 = _T_575 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@61385.6]
assign _T_584 = _T_575 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@61393.6]
assign _T_600 = _T_566 | _T_571; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61405.6]
assign _T_601 = _T_600 | _T_572; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61406.6]
assign _T_602 = _T_601 | _T_576; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61407.6]
assign _T_603 = _T_602 | _T_584; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@61408.6]
assign _T_605 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@61410.6]
assign _T_607 = _T_603 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61413.8]
assign _T_608 = _T_607 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61414.8]
assign _T_609 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@61419.8]
assign _T_611 = _T_609 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@61421.8]
assign _T_612 = _T_611 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@61422.8]
assign _T_617 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@61435.8]
assign _T_619 = _T_617 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@61437.8]
assign _T_620 = _T_619 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@61438.8]
assign _T_625 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@61452.6]
assign _T_653 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@61510.6]
assign _T_675 = io_in_d_bits_corrupt | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@61553.8]
assign _T_676 = _T_675 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@61554.8]
assign _T_682 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@61569.6]
assign _T_699 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@61604.6]
assign _T_717 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@61640.6]
assign _T_746 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@61700.4]
assign _T_751 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@61705.4]
assign _T_752 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@61706.4]
assign _T_753 = _T_752 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@61707.4]
assign _T_757 = _T_756 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61710.4]
assign _T_758 = $unsigned(_T_757); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61711.4]
assign _T_759 = _T_758[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61712.4]
assign _T_760 = _T_756 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61713.4]
assign _T_778 = _T_760 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@61729.4]
assign _T_779 = io_in_a_valid & _T_778; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@61730.4]
assign _T_780 = io_in_a_bits_opcode == _T_769; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@61732.6]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@61734.6]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@61735.6]
assign _T_784 = io_in_a_bits_param == _T_771; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@61740.6]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@61742.6]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@61743.6]
assign _T_788 = io_in_a_bits_size == _T_773; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@61748.6]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@61750.6]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@61751.6]
assign _T_792 = io_in_a_bits_source == _T_775; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@61756.6]
assign _T_794 = _T_792 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@61758.6]
assign _T_795 = _T_794 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@61759.6]
assign _T_796 = io_in_a_bits_address == _T_777; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@61764.6]
assign _T_798 = _T_796 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@61766.6]
assign _T_799 = _T_798 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@61767.6]
assign _T_801 = _T_746 & _T_760; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@61774.4]
assign _T_802 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@61782.4]
assign _T_804 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@61784.4]
assign _T_805 = _T_804[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@61785.4]
assign _T_806 = ~ _T_805; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@61786.4]
assign _T_807 = _T_806[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@61787.4]
assign _T_808 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@61788.4]
assign _T_812 = _T_811 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61791.4]
assign _T_813 = $unsigned(_T_812); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61792.4]
assign _T_814 = _T_813[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61793.4]
assign _T_815 = _T_811 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61794.4]
assign _T_835 = _T_815 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@61811.4]
assign _T_836 = io_in_d_valid & _T_835; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@61812.4]
assign _T_837 = io_in_d_bits_opcode == _T_824; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@61814.6]
assign _T_839 = _T_837 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@61816.6]
assign _T_840 = _T_839 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@61817.6]
assign _T_845 = io_in_d_bits_size == _T_828; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@61830.6]
assign _T_847 = _T_845 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@61832.6]
assign _T_848 = _T_847 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@61833.6]
assign _T_849 = io_in_d_bits_source == _T_830; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@61838.6]
assign _T_851 = _T_849 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@61840.6]
assign _T_852 = _T_851 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@61841.6]
assign _T_862 = _T_802 & _T_815; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@61864.4]
assign _T_876 = _T_875 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61884.4]
assign _T_877 = $unsigned(_T_876); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61885.4]
assign _T_878 = _T_877[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61886.4]
assign _T_879 = _T_875 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61887.4]
assign _T_897 = _T_896 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61907.4]
assign _T_898 = $unsigned(_T_897); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61908.4]
assign _T_899 = _T_898[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@61909.4]
assign _T_900 = _T_896 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@61910.4]
assign _T_911 = _T_746 & _T_879; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@61925.4]
assign _T_913 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@61928.6]
assign _T_914 = _T_864 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@61930.6]
assign _T_915 = _T_914[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@61931.6]
assign _T_916 = _T_915 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@61932.6]
assign _T_918 = _T_916 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@61934.6]
assign _T_919 = _T_918 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@61935.6]
assign _GEN_15 = _T_911 ? _T_913 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@61927.4]
assign _T_924 = _T_802 & _T_900; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@61946.4]
assign _T_926 = _T_605 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@61948.4]
assign _T_927 = _T_924 & _T_926; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@61949.4]
assign _T_928 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@61951.6]
assign _T_909 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@61921.4 :freechips.rocketchip.system.LowRiscConfig.fir@61923.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@61929.6]
assign _T_929 = _T_909 | _T_864; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@61953.6]
assign _T_930 = _T_929 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@61954.6]
assign _T_931 = _T_930[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@61955.6]
assign _T_933 = _T_931 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@61957.6]
assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@61958.6]
assign _GEN_16 = _T_927 ? _T_928 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@61950.4]
assign _T_921 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@61941.4 :freechips.rocketchip.system.LowRiscConfig.fir@61943.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@61952.6]
assign _T_935 = _T_909 != _T_921; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@61964.4]
assign _T_936 = _T_909 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@61965.4]
assign _T_937 = _T_936 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@61966.4]
assign _T_938 = _T_935 | _T_937; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@61967.4]
assign _T_940 = _T_938 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@61969.4]
assign _T_941 = _T_940 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@61970.4]
assign _T_942 = _T_864 | _T_909; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@61975.4]
assign _T_943 = ~ _T_921; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@61976.4]
assign _T_944 = _T_942 & _T_943; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@61977.4]
assign _T_947 = _T_864 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@61982.4]
assign _T_948 = _T_947 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@61983.4]
assign _T_949 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@61984.4]
assign _T_950 = _T_948 | _T_949; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@61985.4]
assign _T_951 = _T_946 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@61986.4]
assign _T_952 = _T_950 | _T_951; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@61987.4]
assign _T_954 = _T_952 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@61989.4]
assign _T_955 = _T_954 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@61990.4]
assign _T_957 = _T_946 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@61996.4]
assign _T_960 = _T_746 | _T_802; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@62000.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@60818.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@60935.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61063.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@61122.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@61173.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61226.10]
assign _GEN_95 = io_in_a_valid & _T_501; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@61277.10]
assign _GEN_105 = io_in_a_valid & _T_530; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@61328.10]
assign _GEN_115 = io_in_d_valid & _T_605; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61416.10]
assign _GEN_123 = io_in_d_valid & _T_625; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@61458.10]
assign _GEN_131 = io_in_d_valid & _T_653; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@61516.10]
assign _GEN_139 = io_in_d_valid & _T_682; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@61575.10]
assign _GEN_143 = io_in_d_valid & _T_699; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@61610.10]
assign _GEN_147 = io_in_d_valid & _T_717; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@61646.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_756 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_769 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_771 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_773 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_775 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_777 = _RAND_5[13:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_811 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_824 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_828 = _RAND_8[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_830 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_864 = _RAND_10[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_875 = _RAND_11[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_896 = _RAND_12[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_946 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_756 <= 9'h0;
end else begin
if (_T_746) begin
if (_T_760) begin
if (_T_753) begin
_T_756 <= _T_751;
end else begin
_T_756 <= 9'h0;
end
end else begin
_T_756 <= _T_759;
end
end
end
if (_T_801) begin
_T_769 <= io_in_a_bits_opcode;
end
if (_T_801) begin
_T_771 <= io_in_a_bits_param;
end
if (_T_801) begin
_T_773 <= io_in_a_bits_size;
end
if (_T_801) begin
_T_775 <= io_in_a_bits_source;
end
if (_T_801) begin
_T_777 <= io_in_a_bits_address;
end
if (reset) begin
_T_811 <= 9'h0;
end else begin
if (_T_802) begin
if (_T_815) begin
if (_T_808) begin
_T_811 <= _T_807;
end else begin
_T_811 <= 9'h0;
end
end else begin
_T_811 <= _T_814;
end
end
end
if (_T_862) begin
_T_824 <= io_in_d_bits_opcode;
end
if (_T_862) begin
_T_828 <= io_in_d_bits_size;
end
if (_T_862) begin
_T_830 <= io_in_d_bits_source;
end
if (reset) begin
_T_864 <= 25'h0;
end else begin
_T_864 <= _T_944;
end
if (reset) begin
_T_875 <= 9'h0;
end else begin
if (_T_746) begin
if (_T_879) begin
if (_T_753) begin
_T_875 <= _T_751;
end else begin
_T_875 <= 9'h0;
end
end else begin
_T_875 <= _T_878;
end
end
end
if (reset) begin
_T_896 <= 9'h0;
end else begin
if (_T_802) begin
if (_T_900) begin
if (_T_808) begin
_T_896 <= _T_807;
end else begin
_T_896 <= 9'h0;
end
end else begin
_T_896 <= _T_899;
end
end
end
if (reset) begin
_T_946 <= 32'h0;
end else begin
if (_T_960) begin
_T_946 <= 32'h0;
end else begin
_T_946 <= _T_957;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@60622.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@60623.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@60801.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@60802.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@60818.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@60819.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@60870.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@60871.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@60877.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@60878.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@60885.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@60886.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@60892.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@60893.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@60900.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@60901.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@60909.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@60910.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@60917.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@60918.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@60935.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@60936.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@60987.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@60988.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@60994.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@60995.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@61002.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@61003.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@61009.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@61010.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@61017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@61018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@61025.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@61026.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@61034.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@61035.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@61042.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@61043.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@61064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@61070.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@61071.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@61077.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@61078.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@61085.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@61086.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@61093.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@61094.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@61101.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@61102.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@61122.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@61123.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@61129.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@61130.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@61136.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@61137.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@61144.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@61145.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@61152.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@61153.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@61173.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@61174.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@61180.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@61181.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@61187.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@61188.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@61195.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@61196.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@61205.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@61206.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_486) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61226.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_486) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@61227.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@61233.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@61234.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@61240.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@61241.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_496) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@61248.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_496) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@61249.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@61256.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@61257.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_486) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@61277.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_486) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@61278.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@61284.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@61285.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@61291.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@61292.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_525) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@61299.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_525) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@61300.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@61307.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@61308.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@61328.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_393) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@61329.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@61335.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@61336.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@61342.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@61343.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@61350.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@61351.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@61358.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@61359.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_562) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@61369.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_562) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@61370.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61416.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_608) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@61417.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_612) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@61424.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_612) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@61425.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@61432.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@61433.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@61440.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_620) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@61441.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@61448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_210) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@61449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@61458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_608) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@61459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@61465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@61466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_612) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@61473.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_612) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@61474.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@61481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@61482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@61489.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@61490.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_123 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@61497.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_123 & _T_620) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@61498.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@61506.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@61507.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@61516.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_608) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@61517.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@61523.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@61524.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_612) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@61531.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_612) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@61532.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@61539.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@61540.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@61547.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@61548.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_676) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@61556.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_676) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@61557.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@61565.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@61566.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@61575.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_608) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@61576.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@61583.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@61584.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_139 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@61591.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_139 & _T_620) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@61592.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@61600.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@61601.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@61610.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_608) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@61611.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@61618.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@61619.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_143 & _T_676) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@61627.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_143 & _T_676) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@61628.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@61636.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@61637.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@61646.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_608) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@61647.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@61654.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@61655.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_147 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@61662.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_147 & _T_620) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@61663.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@61671.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@61672.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@61681.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@61682.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@61689.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@61690.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@61697.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@61698.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@61737.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_783) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@61738.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@61745.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_787) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@61746.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@61753.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_791) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@61754.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_795) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@61761.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_795) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@61762.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_799) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@61769.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_799) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@61770.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_840) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@61819.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_840) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@61820.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@61827.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@61828.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_848) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@61835.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_848) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@61836.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_852) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@61843.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_852) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@61844.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@61851.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@61852.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@61859.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@61860.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_911 & _T_919) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@61937.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_911 & _T_919) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@61938.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_927 & _T_934) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@61960.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_927 & _T_934) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@61961.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_941) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@61972.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_941) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@61973.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_955) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:22:18)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@61992.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_955) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@61993.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_80( // @[:freechips.rocketchip.system.LowRiscConfig.fir@62005.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62006.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62007.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
output [4:0] io_deq_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@62008.4]
);
reg [2:0] _T_35_opcode [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_opcode__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_opcode__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire [2:0] _T_35_opcode__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_opcode__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_opcode__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_opcode__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
reg [3:0] _T_35_size [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
reg [31:0] _RAND_1;
wire [3:0] _T_35_size__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_size__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire [3:0] _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_size__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_size__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_size__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
reg [4:0] _T_35_source [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
reg [31:0] _RAND_2;
wire [4:0] _T_35_source__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_source__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire [4:0] _T_35_source__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_source__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_source__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
wire _T_35_source__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@62011.4]
reg [31:0] _RAND_3;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@62013.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62016.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62019.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@62035.4]
assign _T_35_opcode__T_52_addr = 1'h0;
assign _T_35_opcode__T_52_data = _T_35_opcode[_T_35_opcode__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
assign _T_35_opcode__T_48_data = io_enq_bits_opcode;
assign _T_35_opcode__T_48_addr = 1'h0;
assign _T_35_opcode__T_48_mask = 1'h1;
assign _T_35_opcode__T_48_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_52_addr = 1'h0;
assign _T_35_size__T_52_data = _T_35_size[_T_35_size__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
assign _T_35_size__T_48_data = io_enq_bits_size;
assign _T_35_size__T_48_addr = 1'h0;
assign _T_35_size__T_48_mask = 1'h1;
assign _T_35_size__T_48_en = io_enq_ready & io_enq_valid;
assign _T_35_source__T_52_addr = 1'h0;
assign _T_35_source__T_52_data = _T_35_source[_T_35_source__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
assign _T_35_source__T_48_data = io_enq_bits_source;
assign _T_35_source__T_48_addr = 1'h0;
assign _T_35_source__T_48_mask = 1'h1;
assign _T_35_source__T_48_en = io_enq_ready & io_enq_valid;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@62013.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62016.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62019.4]
assign _T_49 = _T_42 != _T_45; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@62035.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@62042.4]
assign io_deq_valid = _T_39 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@62040.4]
assign io_deq_bits_opcode = _T_35_opcode__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@62051.4]
assign io_deq_bits_size = _T_35_size__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@62049.4]
assign io_deq_bits_source = _T_35_source__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@62048.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_size[initvar] = _RAND_1[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_source[initvar] = _RAND_2[4:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_37 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_opcode__T_48_en & _T_35_opcode__T_48_mask) begin
_T_35_opcode[_T_35_opcode__T_48_addr] <= _T_35_opcode__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
end
if(_T_35_size__T_48_en & _T_35_size__T_48_mask) begin
_T_35_size[_T_35_size__T_48_addr] <= _T_35_size__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
end
if(_T_35_source__T_48_en & _T_35_source__T_48_mask) begin
_T_35_source[_T_35_source__T_48_addr] <= _T_35_source__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@62010.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
_T_37 <= _T_42;
end
end
end
endmodule
module TLError( // @[:freechips.rocketchip.system.LowRiscConfig.fir@62059.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62060.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62061.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input [13:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
output auto_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@62062.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [13:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
wire a_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire a_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire a_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire a_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire [2:0] a_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire [3:0] a_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire [4:0] a_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire a_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire a_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire [2:0] a_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire [3:0] a_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire [4:0] a_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
wire _T_159; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62123.4]
wire [26:0] _T_161; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@62125.4]
wire [11:0] _T_162; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@62126.4]
wire [11:0] _T_163; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@62127.4]
wire [8:0] _T_164; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@62128.4]
wire _T_165; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@62129.4]
wire _T_166; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@62130.4]
wire [8:0] _T_167; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@62131.4]
reg [8:0] _T_169; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@62132.4]
reg [31:0] _RAND_0;
wire [9:0] _T_170; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62133.4]
wire [9:0] _T_171; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62134.4]
wire [8:0] _T_172; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62135.4]
wire _T_173; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@62136.4]
wire _T_174; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@62137.4]
wire _T_175; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@62138.4]
wire a_last; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@62139.4]
wire da_valid; // @[Error.scala 30:25:freechips.rocketchip.system.LowRiscConfig.fir@62183.4]
wire _T_180; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62147.4]
wire [3:0] da_bits_size; // @[Error.scala 22:18:freechips.rocketchip.system.LowRiscConfig.fir@62120.4 Error.scala 34:21:freechips.rocketchip.system.LowRiscConfig.fir@62198.4]
wire [26:0] _T_182; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@62149.4]
wire [11:0] _T_183; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@62150.4]
wire [11:0] _T_184; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@62151.4]
wire [8:0] _T_185; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@62152.4]
wire [2:0] _GEN_4; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
wire [2:0] _GEN_5; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
wire [2:0] _GEN_6; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
wire [2:0] _GEN_7; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
wire [2:0] _GEN_8; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
wire [2:0] da_bits_opcode; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
wire _T_186; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@62153.4]
wire [8:0] _T_187; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@62154.4]
reg [8:0] _T_189; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@62155.4]
reg [31:0] _RAND_1;
wire [9:0] _T_190; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62156.4]
wire [9:0] _T_191; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62157.4]
wire [8:0] _T_192; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62158.4]
wire da_first; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@62159.4]
wire _T_193; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@62160.4]
wire _T_194; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@62161.4]
wire da_last; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@62162.4]
wire _T_203; // @[Error.scala 29:26:freechips.rocketchip.system.LowRiscConfig.fir@62178.4]
wire _T_205; // @[Error.scala 29:49:freechips.rocketchip.system.LowRiscConfig.fir@62180.4]
TLMonitor_24 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@62069.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_80 a ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@62107.4]
.clock(a_clock),
.reset(a_reset),
.io_enq_ready(a_io_enq_ready),
.io_enq_valid(a_io_enq_valid),
.io_enq_bits_opcode(a_io_enq_bits_opcode),
.io_enq_bits_size(a_io_enq_bits_size),
.io_enq_bits_source(a_io_enq_bits_source),
.io_deq_ready(a_io_deq_ready),
.io_deq_valid(a_io_deq_valid),
.io_deq_bits_opcode(a_io_deq_bits_opcode),
.io_deq_bits_size(a_io_deq_bits_size),
.io_deq_bits_source(a_io_deq_bits_source)
);
assign _T_159 = a_io_deq_ready & a_io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62123.4]
assign _T_161 = 27'hfff << a_io_deq_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@62125.4]
assign _T_162 = _T_161[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@62126.4]
assign _T_163 = ~ _T_162; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@62127.4]
assign _T_164 = _T_163[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@62128.4]
assign _T_165 = a_io_deq_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@62129.4]
assign _T_166 = _T_165 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@62130.4]
assign _T_167 = _T_166 ? _T_164 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@62131.4]
assign _T_170 = _T_169 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62133.4]
assign _T_171 = $unsigned(_T_170); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62134.4]
assign _T_172 = _T_171[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62135.4]
assign _T_173 = _T_169 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@62136.4]
assign _T_174 = _T_169 == 9'h1; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@62137.4]
assign _T_175 = _T_167 == 9'h0; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@62138.4]
assign a_last = _T_174 | _T_175; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@62139.4]
assign da_valid = a_io_deq_valid & a_last; // @[Error.scala 30:25:freechips.rocketchip.system.LowRiscConfig.fir@62183.4]
assign _T_180 = auto_in_d_ready & da_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@62147.4]
assign da_bits_size = a_io_deq_bits_size; // @[Error.scala 22:18:freechips.rocketchip.system.LowRiscConfig.fir@62120.4 Error.scala 34:21:freechips.rocketchip.system.LowRiscConfig.fir@62198.4]
assign _T_182 = 27'hfff << da_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@62149.4]
assign _T_183 = _T_182[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@62150.4]
assign _T_184 = ~ _T_183; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@62151.4]
assign _T_185 = _T_184[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@62152.4]
assign _GEN_4 = 3'h2 == a_io_deq_bits_opcode ? 3'h1 : 3'h0; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
assign _GEN_5 = 3'h3 == a_io_deq_bits_opcode ? 3'h1 : _GEN_4; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
assign _GEN_6 = 3'h4 == a_io_deq_bits_opcode ? 3'h1 : _GEN_5; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
assign _GEN_7 = 3'h5 == a_io_deq_bits_opcode ? 3'h2 : _GEN_6; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
assign _GEN_8 = 3'h6 == a_io_deq_bits_opcode ? 3'h4 : _GEN_7; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
assign da_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Error.scala 32:21:freechips.rocketchip.system.LowRiscConfig.fir@62196.4]
assign _T_186 = da_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@62153.4]
assign _T_187 = _T_186 ? _T_185 : 9'h0; // @[Edges.scala 221:14:freechips.rocketchip.system.LowRiscConfig.fir@62154.4]
assign _T_190 = _T_189 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62156.4]
assign _T_191 = $unsigned(_T_190); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62157.4]
assign _T_192 = _T_191[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@62158.4]
assign da_first = _T_189 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@62159.4]
assign _T_193 = _T_189 == 9'h1; // @[Edges.scala 232:25:freechips.rocketchip.system.LowRiscConfig.fir@62160.4]
assign _T_194 = _T_187 == 9'h0; // @[Edges.scala 232:47:freechips.rocketchip.system.LowRiscConfig.fir@62161.4]
assign da_last = _T_193 | _T_194; // @[Edges.scala 232:37:freechips.rocketchip.system.LowRiscConfig.fir@62162.4]
assign _T_203 = auto_in_d_ready & da_last; // @[Error.scala 29:26:freechips.rocketchip.system.LowRiscConfig.fir@62178.4]
assign _T_205 = a_last == 1'h0; // @[Error.scala 29:49:freechips.rocketchip.system.LowRiscConfig.fir@62180.4]
assign auto_in_a_ready = a_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@62106.4]
assign auto_in_d_valid = a_io_deq_valid & a_last; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@62106.4]
assign auto_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@62106.4]
assign auto_in_d_bits_size = a_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@62106.4]
assign auto_in_d_bits_source = a_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@62106.4]
assign auto_in_d_bits_corrupt = da_bits_opcode[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@62106.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@62071.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@62072.4]
assign TLMonitor_io_in_a_ready = a_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_d_valid = a_io_deq_valid & a_last; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_d_bits_opcode = 3'h7 == a_io_deq_bits_opcode ? 3'h4 : _GEN_8; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_d_bits_size = a_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_d_bits_source = a_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign TLMonitor_io_in_d_bits_corrupt = da_bits_opcode[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@62105.4]
assign a_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@62108.4]
assign a_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@62109.4]
assign a_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@62110.4]
assign a_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@62118.4]
assign a_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@62116.4]
assign a_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@62115.4]
assign a_io_deq_ready = _T_203 | _T_205; // @[Error.scala 29:13:freechips.rocketchip.system.LowRiscConfig.fir@62182.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_169 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_189 = _RAND_1[8:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_169 <= 9'h0;
end else begin
if (_T_159) begin
if (_T_173) begin
if (_T_166) begin
_T_169 <= _T_164;
end else begin
_T_169 <= 9'h0;
end
end else begin
_T_169 <= _T_172;
end
end
end
if (reset) begin
_T_189 <= 9'h0;
end else begin
if (_T_180) begin
if (da_first) begin
if (_T_186) begin
_T_189 <= _T_185;
end else begin
_T_189 <= 9'h0;
end
end else begin
_T_189 <= _T_192;
end
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Error.scala:28 assert (idle || da_first) // we only send Grant, never GrantData => simplified flow control below\n"); // @[Error.scala 28:12:freechips.rocketchip.system.LowRiscConfig.fir@62175.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Error.scala 28:12:freechips.rocketchip.system.LowRiscConfig.fir@62176.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_25( // @[:freechips.rocketchip.system.LowRiscConfig.fir@62216.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62217.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62218.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [13:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@62219.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@63589.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62236.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62237.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62242.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62243.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62246.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62247.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62255.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62267.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62268.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62269.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62270.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@62272.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@62273.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@62274.6]
wire [13:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@62275.6]
wire [13:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@62275.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@62276.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@62278.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@62279.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@62280.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@62281.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@62282.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@62283.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@62284.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@62285.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62287.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62288.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62290.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62291.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@62292.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@62293.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@62294.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62295.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62296.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62297.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62298.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62299.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62300.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62301.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62302.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62303.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62304.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62305.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62306.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@62307.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@62308.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@62309.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62310.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62311.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62312.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62313.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62314.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62315.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62316.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62317.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62318.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62319.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62320.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62321.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62322.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62323.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62324.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62325.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62326.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62327.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62328.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62329.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62330.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62331.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62332.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62333.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@62340.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@62413.6]
wire [13:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@62416.8]
wire [14:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@62417.8]
wire [14:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@62418.8]
wire [14:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@62419.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@62420.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@62425.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@62463.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@62464.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@62476.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@62477.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@62483.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@62484.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@62491.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@62492.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@62498.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@62499.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@62504.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@62506.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@62507.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@62512.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@62513.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@62515.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@62516.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@62521.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@62523.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@62524.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@62530.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@62629.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@62631.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@62632.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@62655.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@62658.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@62666.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62669.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62670.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@62689.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@62691.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@62692.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@62697.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@62699.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@62700.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@62714.6]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@62765.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@62807.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@62808.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@62809.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@62811.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@62812.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@62818.6]
wire _T_474; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@62821.8]
wire _T_482; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@62829.8]
wire _T_485; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62832.8]
wire _T_486; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62833.8]
wire _T_493; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@62852.8]
wire _T_495; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@62854.8]
wire _T_496; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@62855.8]
wire _T_501; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@62869.6]
wire _T_522; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@62903.8]
wire _T_524; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@62905.8]
wire _T_525; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@62906.8]
wire _T_530; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@62920.6]
wire _T_559; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@62973.6]
wire _T_561; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@62975.6]
wire _T_562; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@62976.6]
wire [2:0] _T_565; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62983.6]
wire _T_566; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62984.6]
wire _T_571; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62989.6]
wire _T_572; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62990.6]
wire [1:0] _T_575; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62993.6]
wire _T_576; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62994.6]
wire _T_584; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63002.6]
wire _T_600; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63014.6]
wire _T_601; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63015.6]
wire _T_602; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63016.6]
wire _T_603; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63017.6]
wire _T_605; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@63019.6]
wire _T_607; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63022.8]
wire _T_608; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63023.8]
wire _T_609; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@63028.8]
wire _T_611; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@63030.8]
wire _T_612; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@63031.8]
wire _T_613; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@63036.8]
wire _T_615; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@63038.8]
wire _T_616; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@63039.8]
wire _T_617; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@63044.8]
wire _T_619; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@63046.8]
wire _T_620; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@63047.8]
wire _T_621; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@63052.8]
wire _T_623; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@63054.8]
wire _T_624; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@63055.8]
wire _T_625; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@63061.6]
wire _T_636; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@63085.8]
wire _T_638; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@63087.8]
wire _T_639; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@63088.8]
wire _T_640; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@63093.8]
wire _T_642; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@63095.8]
wire _T_643; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@63096.8]
wire _T_653; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@63119.6]
wire _T_673; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@63160.8]
wire _T_675; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@63162.8]
wire _T_676; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@63163.8]
wire _T_682; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@63178.6]
wire _T_699; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@63213.6]
wire _T_717; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@63249.6]
wire _T_746; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@63309.4]
wire [8:0] _T_751; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@63314.4]
wire _T_752; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@63315.4]
wire _T_753; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@63316.4]
reg [8:0] _T_756; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@63318.4]
reg [31:0] _RAND_0;
wire [9:0] _T_757; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63319.4]
wire [9:0] _T_758; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63320.4]
wire [8:0] _T_759; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63321.4]
wire _T_760; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63322.4]
reg [2:0] _T_769; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@63333.4]
reg [31:0] _RAND_1;
reg [2:0] _T_771; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@63334.4]
reg [31:0] _RAND_2;
reg [3:0] _T_773; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@63335.4]
reg [31:0] _RAND_3;
reg [4:0] _T_775; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@63336.4]
reg [31:0] _RAND_4;
reg [13:0] _T_777; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@63337.4]
reg [31:0] _RAND_5;
wire _T_778; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@63338.4]
wire _T_779; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@63339.4]
wire _T_780; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@63341.6]
wire _T_782; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@63343.6]
wire _T_783; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@63344.6]
wire _T_784; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@63349.6]
wire _T_786; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@63351.6]
wire _T_787; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@63352.6]
wire _T_788; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@63357.6]
wire _T_790; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@63359.6]
wire _T_791; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@63360.6]
wire _T_792; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@63365.6]
wire _T_794; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@63367.6]
wire _T_795; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@63368.6]
wire _T_796; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@63373.6]
wire _T_798; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@63375.6]
wire _T_799; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@63376.6]
wire _T_801; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@63383.4]
wire _T_802; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@63391.4]
wire [26:0] _T_804; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@63393.4]
wire [11:0] _T_805; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@63394.4]
wire [11:0] _T_806; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@63395.4]
wire [8:0] _T_807; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@63396.4]
wire _T_808; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@63397.4]
reg [8:0] _T_811; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@63399.4]
reg [31:0] _RAND_6;
wire [9:0] _T_812; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63400.4]
wire [9:0] _T_813; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63401.4]
wire [8:0] _T_814; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63402.4]
wire _T_815; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63403.4]
reg [2:0] _T_824; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@63414.4]
reg [31:0] _RAND_7;
reg [1:0] _T_826; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@63415.4]
reg [31:0] _RAND_8;
reg [3:0] _T_828; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@63416.4]
reg [31:0] _RAND_9;
reg [4:0] _T_830; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@63417.4]
reg [31:0] _RAND_10;
reg _T_832; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@63418.4]
reg [31:0] _RAND_11;
reg _T_834; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@63419.4]
reg [31:0] _RAND_12;
wire _T_835; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@63420.4]
wire _T_836; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@63421.4]
wire _T_837; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@63423.6]
wire _T_839; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@63425.6]
wire _T_840; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@63426.6]
wire _T_841; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@63431.6]
wire _T_843; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@63433.6]
wire _T_844; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@63434.6]
wire _T_845; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@63439.6]
wire _T_847; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@63441.6]
wire _T_848; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@63442.6]
wire _T_849; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@63447.6]
wire _T_851; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@63449.6]
wire _T_852; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@63450.6]
wire _T_853; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@63455.6]
wire _T_855; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@63457.6]
wire _T_856; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@63458.6]
wire _T_857; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@63463.6]
wire _T_859; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@63465.6]
wire _T_860; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@63466.6]
wire _T_862; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@63473.4]
reg [24:0] _T_864; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@63482.4]
reg [31:0] _RAND_13;
reg [8:0] _T_875; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@63492.4]
reg [31:0] _RAND_14;
wire [9:0] _T_876; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63493.4]
wire [9:0] _T_877; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63494.4]
wire [8:0] _T_878; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63495.4]
wire _T_879; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63496.4]
reg [8:0] _T_896; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@63515.4]
reg [31:0] _RAND_15;
wire [9:0] _T_897; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63516.4]
wire [9:0] _T_898; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63517.4]
wire [8:0] _T_899; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63518.4]
wire _T_900; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63519.4]
wire _T_911; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@63534.4]
wire [31:0] _T_913; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@63537.6]
wire [24:0] _T_914; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@63539.6]
wire _T_915; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@63540.6]
wire _T_916; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@63541.6]
wire _T_918; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@63543.6]
wire _T_919; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@63544.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@63536.4]
wire _T_924; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@63555.4]
wire _T_926; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@63557.4]
wire _T_927; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@63558.4]
wire [31:0] _T_928; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@63560.6]
wire [24:0] _T_909; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63530.4 :freechips.rocketchip.system.LowRiscConfig.fir@63532.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@63538.6]
wire [24:0] _T_929; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@63562.6]
wire [24:0] _T_930; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@63563.6]
wire _T_931; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@63564.6]
wire _T_933; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@63566.6]
wire _T_934; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@63567.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@63559.4]
wire [24:0] _T_921; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63550.4 :freechips.rocketchip.system.LowRiscConfig.fir@63552.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@63561.6]
wire _T_935; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@63573.4]
wire _T_936; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@63574.4]
wire _T_937; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@63575.4]
wire _T_938; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@63576.4]
wire _T_940; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@63578.4]
wire _T_941; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@63579.4]
wire [24:0] _T_942; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@63584.4]
wire [24:0] _T_943; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@63585.4]
wire [24:0] _T_944; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@63586.4]
reg [31:0] _T_946; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@63588.4]
reg [31:0] _RAND_16;
wire _T_947; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@63591.4]
wire _T_948; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@63592.4]
wire _T_949; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@63593.4]
wire _T_950; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@63594.4]
wire _T_951; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@63595.4]
wire _T_952; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@63596.4]
wire _T_954; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@63598.4]
wire _T_955; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@63599.4]
wire [31:0] _T_957; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@63605.4]
wire _T_960; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@63609.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@62427.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@62544.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62672.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@62731.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@62782.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62835.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@62886.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@62937.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63025.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@63067.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@63125.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@63184.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@63219.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@63255.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@63589.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62236.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62237.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62242.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62243.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62246.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62247.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62255.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62267.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62268.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62269.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@62270.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@62272.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@62273.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@62274.6]
assign _GEN_18 = {{2'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@62275.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@62275.6]
assign _T_66 = _T_65 == 14'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@62276.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@62278.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@62279.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@62280.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@62281.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@62282.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@62283.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@62284.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@62285.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62287.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62288.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62290.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62291.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@62292.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@62293.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@62294.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62295.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62296.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62297.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62298.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62299.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62300.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62301.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62302.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62303.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62304.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62305.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62306.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@62307.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@62308.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@62309.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62310.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62311.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62312.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62313.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62314.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62315.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62316.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62317.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62318.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62319.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62320.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62321.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62322.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62323.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62324.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62325.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62326.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62327.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62328.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62329.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62330.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@62331.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@62332.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@62333.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@62340.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@62413.6]
assign _T_201 = io_in_a_bits_address ^ 14'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@62416.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@62417.8]
assign _T_203 = $signed(_T_202) & $signed(-15'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@62418.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@62419.8]
assign _T_205 = $signed(_T_204) == $signed(15'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@62420.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@62425.8]
assign _T_248 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@62463.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@62464.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@62476.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@62477.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@62483.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@62484.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@62491.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@62492.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@62498.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@62499.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@62504.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@62506.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@62507.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@62512.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@62513.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@62515.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@62516.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@62521.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@62523.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@62524.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@62530.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@62629.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@62631.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@62632.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@62655.6]
assign _T_381 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@62658.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@62666.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62669.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62670.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@62689.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@62691.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@62692.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@62697.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@62699.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@62700.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@62714.6]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@62765.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@62807.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@62808.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@62809.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@62811.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@62812.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@62818.6]
assign _T_474 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@62821.8]
assign _T_482 = _T_474 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@62829.8]
assign _T_485 = _T_482 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62832.8]
assign _T_486 = _T_485 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62833.8]
assign _T_493 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@62852.8]
assign _T_495 = _T_493 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@62854.8]
assign _T_496 = _T_495 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@62855.8]
assign _T_501 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@62869.6]
assign _T_522 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@62903.8]
assign _T_524 = _T_522 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@62905.8]
assign _T_525 = _T_524 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@62906.8]
assign _T_530 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@62920.6]
assign _T_559 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@62973.6]
assign _T_561 = _T_559 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@62975.6]
assign _T_562 = _T_561 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@62976.6]
assign _T_565 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62983.6]
assign _T_566 = _T_565 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62984.6]
assign _T_571 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62989.6]
assign _T_572 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@62990.6]
assign _T_575 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@62993.6]
assign _T_576 = _T_575 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@62994.6]
assign _T_584 = _T_575 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63002.6]
assign _T_600 = _T_566 | _T_571; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63014.6]
assign _T_601 = _T_600 | _T_572; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63015.6]
assign _T_602 = _T_601 | _T_576; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63016.6]
assign _T_603 = _T_602 | _T_584; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63017.6]
assign _T_605 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@63019.6]
assign _T_607 = _T_603 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63022.8]
assign _T_608 = _T_607 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63023.8]
assign _T_609 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@63028.8]
assign _T_611 = _T_609 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@63030.8]
assign _T_612 = _T_611 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@63031.8]
assign _T_613 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@63036.8]
assign _T_615 = _T_613 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@63038.8]
assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@63039.8]
assign _T_617 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@63044.8]
assign _T_619 = _T_617 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@63046.8]
assign _T_620 = _T_619 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@63047.8]
assign _T_621 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@63052.8]
assign _T_623 = _T_621 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@63054.8]
assign _T_624 = _T_623 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@63055.8]
assign _T_625 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@63061.6]
assign _T_636 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@63085.8]
assign _T_638 = _T_636 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@63087.8]
assign _T_639 = _T_638 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@63088.8]
assign _T_640 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@63093.8]
assign _T_642 = _T_640 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@63095.8]
assign _T_643 = _T_642 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@63096.8]
assign _T_653 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@63119.6]
assign _T_673 = _T_621 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@63160.8]
assign _T_675 = _T_673 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@63162.8]
assign _T_676 = _T_675 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@63163.8]
assign _T_682 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@63178.6]
assign _T_699 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@63213.6]
assign _T_717 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@63249.6]
assign _T_746 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@63309.4]
assign _T_751 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@63314.4]
assign _T_752 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@63315.4]
assign _T_753 = _T_752 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@63316.4]
assign _T_757 = _T_756 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63319.4]
assign _T_758 = $unsigned(_T_757); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63320.4]
assign _T_759 = _T_758[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63321.4]
assign _T_760 = _T_756 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63322.4]
assign _T_778 = _T_760 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@63338.4]
assign _T_779 = io_in_a_valid & _T_778; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@63339.4]
assign _T_780 = io_in_a_bits_opcode == _T_769; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@63341.6]
assign _T_782 = _T_780 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@63343.6]
assign _T_783 = _T_782 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@63344.6]
assign _T_784 = io_in_a_bits_param == _T_771; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@63349.6]
assign _T_786 = _T_784 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@63351.6]
assign _T_787 = _T_786 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@63352.6]
assign _T_788 = io_in_a_bits_size == _T_773; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@63357.6]
assign _T_790 = _T_788 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@63359.6]
assign _T_791 = _T_790 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@63360.6]
assign _T_792 = io_in_a_bits_source == _T_775; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@63365.6]
assign _T_794 = _T_792 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@63367.6]
assign _T_795 = _T_794 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@63368.6]
assign _T_796 = io_in_a_bits_address == _T_777; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@63373.6]
assign _T_798 = _T_796 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@63375.6]
assign _T_799 = _T_798 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@63376.6]
assign _T_801 = _T_746 & _T_760; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@63383.4]
assign _T_802 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@63391.4]
assign _T_804 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@63393.4]
assign _T_805 = _T_804[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@63394.4]
assign _T_806 = ~ _T_805; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@63395.4]
assign _T_807 = _T_806[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@63396.4]
assign _T_808 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@63397.4]
assign _T_812 = _T_811 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63400.4]
assign _T_813 = $unsigned(_T_812); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63401.4]
assign _T_814 = _T_813[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63402.4]
assign _T_815 = _T_811 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63403.4]
assign _T_835 = _T_815 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@63420.4]
assign _T_836 = io_in_d_valid & _T_835; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@63421.4]
assign _T_837 = io_in_d_bits_opcode == _T_824; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@63423.6]
assign _T_839 = _T_837 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@63425.6]
assign _T_840 = _T_839 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@63426.6]
assign _T_841 = io_in_d_bits_param == _T_826; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@63431.6]
assign _T_843 = _T_841 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@63433.6]
assign _T_844 = _T_843 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@63434.6]
assign _T_845 = io_in_d_bits_size == _T_828; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@63439.6]
assign _T_847 = _T_845 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@63441.6]
assign _T_848 = _T_847 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@63442.6]
assign _T_849 = io_in_d_bits_source == _T_830; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@63447.6]
assign _T_851 = _T_849 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@63449.6]
assign _T_852 = _T_851 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@63450.6]
assign _T_853 = io_in_d_bits_sink == _T_832; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@63455.6]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@63457.6]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@63458.6]
assign _T_857 = io_in_d_bits_denied == _T_834; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@63463.6]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@63465.6]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@63466.6]
assign _T_862 = _T_802 & _T_815; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@63473.4]
assign _T_876 = _T_875 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63493.4]
assign _T_877 = $unsigned(_T_876); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63494.4]
assign _T_878 = _T_877[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63495.4]
assign _T_879 = _T_875 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63496.4]
assign _T_897 = _T_896 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63516.4]
assign _T_898 = $unsigned(_T_897); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63517.4]
assign _T_899 = _T_898[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@63518.4]
assign _T_900 = _T_896 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@63519.4]
assign _T_911 = _T_746 & _T_879; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@63534.4]
assign _T_913 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@63537.6]
assign _T_914 = _T_864 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@63539.6]
assign _T_915 = _T_914[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@63540.6]
assign _T_916 = _T_915 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@63541.6]
assign _T_918 = _T_916 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@63543.6]
assign _T_919 = _T_918 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@63544.6]
assign _GEN_15 = _T_911 ? _T_913 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@63536.4]
assign _T_924 = _T_802 & _T_900; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@63555.4]
assign _T_926 = _T_605 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@63557.4]
assign _T_927 = _T_924 & _T_926; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@63558.4]
assign _T_928 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@63560.6]
assign _T_909 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63530.4 :freechips.rocketchip.system.LowRiscConfig.fir@63532.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@63538.6]
assign _T_929 = _T_909 | _T_864; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@63562.6]
assign _T_930 = _T_929 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@63563.6]
assign _T_931 = _T_930[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@63564.6]
assign _T_933 = _T_931 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@63566.6]
assign _T_934 = _T_933 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@63567.6]
assign _GEN_16 = _T_927 ? _T_928 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@63559.4]
assign _T_921 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63550.4 :freechips.rocketchip.system.LowRiscConfig.fir@63552.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@63561.6]
assign _T_935 = _T_909 != _T_921; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@63573.4]
assign _T_936 = _T_909 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@63574.4]
assign _T_937 = _T_936 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@63575.4]
assign _T_938 = _T_935 | _T_937; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@63576.4]
assign _T_940 = _T_938 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@63578.4]
assign _T_941 = _T_940 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@63579.4]
assign _T_942 = _T_864 | _T_909; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@63584.4]
assign _T_943 = ~ _T_921; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@63585.4]
assign _T_944 = _T_942 & _T_943; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@63586.4]
assign _T_947 = _T_864 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@63591.4]
assign _T_948 = _T_947 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@63592.4]
assign _T_949 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@63593.4]
assign _T_950 = _T_948 | _T_949; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@63594.4]
assign _T_951 = _T_946 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@63595.4]
assign _T_952 = _T_950 | _T_951; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@63596.4]
assign _T_954 = _T_952 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@63598.4]
assign _T_955 = _T_954 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@63599.4]
assign _T_957 = _T_946 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@63605.4]
assign _T_960 = _T_746 | _T_802; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@63609.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@62427.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@62544.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62672.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@62731.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@62782.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62835.10]
assign _GEN_95 = io_in_a_valid & _T_501; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@62886.10]
assign _GEN_105 = io_in_a_valid & _T_530; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@62937.10]
assign _GEN_115 = io_in_d_valid & _T_605; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63025.10]
assign _GEN_125 = io_in_d_valid & _T_625; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@63067.10]
assign _GEN_137 = io_in_d_valid & _T_653; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@63125.10]
assign _GEN_149 = io_in_d_valid & _T_682; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@63184.10]
assign _GEN_155 = io_in_d_valid & _T_699; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@63219.10]
assign _GEN_161 = io_in_d_valid & _T_717; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@63255.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_756 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_769 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_771 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_773 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_775 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_777 = _RAND_5[13:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_811 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_824 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_826 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_828 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_830 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_832 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_834 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_864 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_875 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_896 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_946 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_756 <= 9'h0;
end else begin
if (_T_746) begin
if (_T_760) begin
if (_T_753) begin
_T_756 <= _T_751;
end else begin
_T_756 <= 9'h0;
end
end else begin
_T_756 <= _T_759;
end
end
end
if (_T_801) begin
_T_769 <= io_in_a_bits_opcode;
end
if (_T_801) begin
_T_771 <= io_in_a_bits_param;
end
if (_T_801) begin
_T_773 <= io_in_a_bits_size;
end
if (_T_801) begin
_T_775 <= io_in_a_bits_source;
end
if (_T_801) begin
_T_777 <= io_in_a_bits_address;
end
if (reset) begin
_T_811 <= 9'h0;
end else begin
if (_T_802) begin
if (_T_815) begin
if (_T_808) begin
_T_811 <= _T_807;
end else begin
_T_811 <= 9'h0;
end
end else begin
_T_811 <= _T_814;
end
end
end
if (_T_862) begin
_T_824 <= io_in_d_bits_opcode;
end
if (_T_862) begin
_T_826 <= io_in_d_bits_param;
end
if (_T_862) begin
_T_828 <= io_in_d_bits_size;
end
if (_T_862) begin
_T_830 <= io_in_d_bits_source;
end
if (_T_862) begin
_T_832 <= io_in_d_bits_sink;
end
if (_T_862) begin
_T_834 <= io_in_d_bits_denied;
end
if (reset) begin
_T_864 <= 25'h0;
end else begin
_T_864 <= _T_944;
end
if (reset) begin
_T_875 <= 9'h0;
end else begin
if (_T_746) begin
if (_T_879) begin
if (_T_753) begin
_T_875 <= _T_751;
end else begin
_T_875 <= 9'h0;
end
end else begin
_T_875 <= _T_878;
end
end
end
if (reset) begin
_T_896 <= 9'h0;
end else begin
if (_T_802) begin
if (_T_900) begin
if (_T_808) begin
_T_896 <= _T_807;
end else begin
_T_896 <= 9'h0;
end
end else begin
_T_896 <= _T_899;
end
end
end
if (reset) begin
_T_946 <= 32'h0;
end else begin
if (_T_960) begin
_T_946 <= 32'h0;
end else begin
_T_946 <= _T_957;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@62231.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@62232.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@62410.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@62411.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@62427.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@62428.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@62479.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@62480.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@62486.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@62487.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@62494.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@62495.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@62501.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@62502.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@62509.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@62510.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@62518.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@62519.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@62526.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@62527.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@62544.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@62545.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@62596.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@62597.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@62603.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@62604.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@62611.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@62612.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@62618.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@62619.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@62626.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@62627.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@62634.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@62635.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@62643.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@62644.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@62651.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@62652.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62672.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@62673.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@62679.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@62680.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@62686.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@62687.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@62694.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@62695.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@62702.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@62703.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@62710.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@62711.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@62731.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@62732.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@62738.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@62739.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@62745.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@62746.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@62753.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@62754.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@62761.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@62762.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@62782.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@62783.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@62789.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@62790.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@62796.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@62797.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@62804.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@62805.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@62814.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@62815.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_486) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62835.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_486) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@62836.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@62842.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@62843.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@62849.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@62850.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_496) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@62857.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_496) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@62858.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@62865.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@62866.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_486) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@62886.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_486) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@62887.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@62893.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@62894.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@62900.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@62901.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_525) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@62908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_525) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@62909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@62916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@62917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@62937.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_393) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@62938.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@62944.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@62945.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@62951.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@62952.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@62959.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@62960.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@62967.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@62968.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_562) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@62978.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_562) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@62979.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63025.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_608) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@63026.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_612) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@63033.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_612) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@63034.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_616) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@63041.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_616) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@63042.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@63049.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_620) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@63050.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_624) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@63057.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_624) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@63058.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@63067.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_608) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@63068.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@63074.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@63075.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_612) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@63082.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_612) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@63083.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_639) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@63090.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_639) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@63091.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_643) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@63098.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_643) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@63099.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@63106.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_620) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@63107.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@63115.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@63116.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@63125.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_608) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@63126.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@63132.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@63133.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_612) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@63140.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_612) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@63141.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_639) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@63148.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_639) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@63149.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_643) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@63156.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_643) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@63157.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_676) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@63165.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_676) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@63166.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@63174.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@63175.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@63184.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_608) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@63185.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_616) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@63192.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_616) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@63193.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@63200.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_620) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@63201.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@63209.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@63210.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@63219.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_608) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@63220.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_616) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@63227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_616) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@63228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_676) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@63236.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_676) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@63237.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@63245.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@63246.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_608) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@63255.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_608) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@63256.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_616) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@63263.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_616) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@63264.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@63271.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_620) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@63272.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@63280.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@63281.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@63290.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@63291.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@63298.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@63299.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@63306.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@63307.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_783) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@63346.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_783) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@63347.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_787) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@63354.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_787) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@63355.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_791) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@63362.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_791) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@63363.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_795) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@63370.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_795) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@63371.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_779 & _T_799) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@63378.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_779 & _T_799) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@63379.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_840) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@63428.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_840) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@63429.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_844) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@63436.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_844) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@63437.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_848) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@63444.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_848) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@63445.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_852) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@63452.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_852) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@63453.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@63460.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_856) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@63461.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_836 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@63468.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_836 & _T_860) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@63469.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_911 & _T_919) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@63546.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_911 & _T_919) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@63547.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_927 & _T_934) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@63569.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_927 & _T_934) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@63570.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_941) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@63581.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_941) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@63582.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_955) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CanHaveBuiltInDevices.scala:22:32)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@63601.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_955) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@63602.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Queue_81( // @[:freechips.rocketchip.system.LowRiscConfig.fir@63614.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63615.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63616.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input [3:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input [13:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output [3:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output [13:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@63617.4]
);
reg [2:0] _T_35_opcode [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_0;
wire [2:0] _T_35_opcode__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_opcode__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire [2:0] _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_opcode__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_opcode__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_opcode__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [2:0] _T_35_param [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_1;
wire [2:0] _T_35_param__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_param__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire [2:0] _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_param__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_param__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_param__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [3:0] _T_35_size [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_2;
wire [3:0] _T_35_size__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_size__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire [3:0] _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_size__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_size__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_size__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [4:0] _T_35_source [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_3;
wire [4:0] _T_35_source__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_source__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire [4:0] _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_source__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_source__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_source__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [13:0] _T_35_address [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_4;
wire [13:0] _T_35_address__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_address__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire [13:0] _T_35_address__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_address__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_address__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_address__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [7:0] _T_35_mask [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_5;
wire [7:0] _T_35_mask__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_mask__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire [7:0] _T_35_mask__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_mask__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_mask__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_mask__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg _T_35_corrupt [0:1]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg [31:0] _RAND_6;
wire _T_35_corrupt__T_58_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_corrupt__T_58_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_corrupt__T_50_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_corrupt__T_50_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
wire _T_35_corrupt__T_50_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
reg value; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@63620.4]
reg [31:0] _RAND_7;
reg value_1; // @[Counter.scala 26:33:freechips.rocketchip.system.LowRiscConfig.fir@63621.4]
reg [31:0] _RAND_8;
reg _T_39; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@63622.4]
reg [31:0] _RAND_9;
wire _T_40; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@63623.4]
wire _T_41; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@63624.4]
wire _T_42; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@63625.4]
wire _T_43; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@63626.4]
wire _T_44; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@63627.4]
wire _T_47; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@63630.4]
wire _T_52; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@63645.6]
wire _T_54; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@63651.6]
wire _T_55; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@63654.4]
assign _T_35_opcode__T_58_addr = value_1;
assign _T_35_opcode__T_58_data = _T_35_opcode[_T_35_opcode__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_opcode__T_50_data = io_enq_bits_opcode;
assign _T_35_opcode__T_50_addr = value;
assign _T_35_opcode__T_50_mask = 1'h1;
assign _T_35_opcode__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_param__T_58_addr = value_1;
assign _T_35_param__T_58_data = _T_35_param[_T_35_param__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_param__T_50_data = io_enq_bits_param;
assign _T_35_param__T_50_addr = value;
assign _T_35_param__T_50_mask = 1'h1;
assign _T_35_param__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_size__T_58_addr = value_1;
assign _T_35_size__T_58_data = _T_35_size[_T_35_size__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_size__T_50_data = io_enq_bits_size;
assign _T_35_size__T_50_addr = value;
assign _T_35_size__T_50_mask = 1'h1;
assign _T_35_size__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_source__T_58_addr = value_1;
assign _T_35_source__T_58_data = _T_35_source[_T_35_source__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_source__T_50_data = io_enq_bits_source;
assign _T_35_source__T_50_addr = value;
assign _T_35_source__T_50_mask = 1'h1;
assign _T_35_source__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_address__T_58_addr = value_1;
assign _T_35_address__T_58_data = _T_35_address[_T_35_address__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_address__T_50_data = io_enq_bits_address;
assign _T_35_address__T_50_addr = value;
assign _T_35_address__T_50_mask = 1'h1;
assign _T_35_address__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_mask__T_58_addr = value_1;
assign _T_35_mask__T_58_data = _T_35_mask[_T_35_mask__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_mask__T_50_data = io_enq_bits_mask;
assign _T_35_mask__T_50_addr = value;
assign _T_35_mask__T_50_mask = 1'h1;
assign _T_35_mask__T_50_en = io_enq_ready & io_enq_valid;
assign _T_35_corrupt__T_58_addr = value_1;
assign _T_35_corrupt__T_58_data = _T_35_corrupt[_T_35_corrupt__T_58_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
assign _T_35_corrupt__T_50_data = io_enq_bits_corrupt;
assign _T_35_corrupt__T_50_addr = value;
assign _T_35_corrupt__T_50_mask = 1'h1;
assign _T_35_corrupt__T_50_en = io_enq_ready & io_enq_valid;
assign _T_40 = value == value_1; // @[Decoupled.scala 219:41:freechips.rocketchip.system.LowRiscConfig.fir@63623.4]
assign _T_41 = _T_39 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@63624.4]
assign _T_42 = _T_40 & _T_41; // @[Decoupled.scala 220:33:freechips.rocketchip.system.LowRiscConfig.fir@63625.4]
assign _T_43 = _T_40 & _T_39; // @[Decoupled.scala 221:32:freechips.rocketchip.system.LowRiscConfig.fir@63626.4]
assign _T_44 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@63627.4]
assign _T_47 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@63630.4]
assign _T_52 = value + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@63645.6]
assign _T_54 = value_1 + 1'h1; // @[Counter.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@63651.6]
assign _T_55 = _T_44 != _T_47; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@63654.4]
assign io_enq_ready = _T_43 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@63661.4]
assign io_deq_valid = _T_42 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@63659.4]
assign io_deq_bits_opcode = _T_35_opcode__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63670.4]
assign io_deq_bits_param = _T_35_param__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63669.4]
assign io_deq_bits_size = _T_35_size__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63668.4]
assign io_deq_bits_source = _T_35_source__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63667.4]
assign io_deq_bits_address = _T_35_address__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63666.4]
assign io_deq_bits_mask = _T_35_mask__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63665.4]
assign io_deq_bits_corrupt = _T_35_corrupt__T_58_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@63663.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_address[initvar] = _RAND_4[13:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_mask[initvar] = _RAND_5[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_35_corrupt[initvar] = _RAND_6[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
value = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value_1 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_39 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_opcode__T_50_en & _T_35_opcode__T_50_mask) begin
_T_35_opcode[_T_35_opcode__T_50_addr] <= _T_35_opcode__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if(_T_35_param__T_50_en & _T_35_param__T_50_mask) begin
_T_35_param[_T_35_param__T_50_addr] <= _T_35_param__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if(_T_35_size__T_50_en & _T_35_size__T_50_mask) begin
_T_35_size[_T_35_size__T_50_addr] <= _T_35_size__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if(_T_35_source__T_50_en & _T_35_source__T_50_mask) begin
_T_35_source[_T_35_source__T_50_addr] <= _T_35_source__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if(_T_35_address__T_50_en & _T_35_address__T_50_mask) begin
_T_35_address[_T_35_address__T_50_addr] <= _T_35_address__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if(_T_35_mask__T_50_en & _T_35_mask__T_50_mask) begin
_T_35_mask[_T_35_mask__T_50_addr] <= _T_35_mask__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if(_T_35_corrupt__T_50_en & _T_35_corrupt__T_50_mask) begin
_T_35_corrupt[_T_35_corrupt__T_50_addr] <= _T_35_corrupt__T_50_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@63619.4]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_44) begin
value <= _T_52;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_47) begin
value_1 <= _T_54;
end
end
if (reset) begin
_T_39 <= 1'h0;
end else begin
if (_T_55) begin
_T_39 <= _T_44;
end
end
end
endmodule
module TLBuffer_8( // @[:freechips.rocketchip.system.LowRiscConfig.fir@63742.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63743.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63744.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [13:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [13:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@63745.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [13:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [2:0] Queue_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [2:0] Queue_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [3:0] Queue_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [4:0] Queue_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [13:0] Queue_io_enq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [7:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [2:0] Queue_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [2:0] Queue_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [3:0] Queue_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [4:0] Queue_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [13:0] Queue_io_deq_bits_address; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire [7:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
wire Queue_1_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [2:0] Queue_1_io_enq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [1:0] Queue_1_io_enq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [3:0] Queue_1_io_enq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [4:0] Queue_1_io_enq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_enq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_enq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [63:0] Queue_1_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_enq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [2:0] Queue_1_io_deq_bits_opcode; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [1:0] Queue_1_io_deq_bits_param; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [3:0] Queue_1_io_deq_bits_size; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [4:0] Queue_1_io_deq_bits_source; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_deq_bits_sink; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_deq_bits_denied; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire [63:0] Queue_1_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
wire Queue_1_io_deq_bits_corrupt; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
TLMonitor_25 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@63752.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
Queue_81 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63793.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_opcode(Queue_io_enq_bits_opcode),
.io_enq_bits_param(Queue_io_enq_bits_param),
.io_enq_bits_size(Queue_io_enq_bits_size),
.io_enq_bits_source(Queue_io_enq_bits_source),
.io_enq_bits_address(Queue_io_enq_bits_address),
.io_enq_bits_mask(Queue_io_enq_bits_mask),
.io_enq_bits_corrupt(Queue_io_enq_bits_corrupt),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_opcode(Queue_io_deq_bits_opcode),
.io_deq_bits_param(Queue_io_deq_bits_param),
.io_deq_bits_size(Queue_io_deq_bits_size),
.io_deq_bits_source(Queue_io_deq_bits_source),
.io_deq_bits_address(Queue_io_deq_bits_address),
.io_deq_bits_mask(Queue_io_deq_bits_mask),
.io_deq_bits_corrupt(Queue_io_deq_bits_corrupt)
);
Queue_79 Queue_1 ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@63807.4]
.clock(Queue_1_clock),
.reset(Queue_1_reset),
.io_enq_ready(Queue_1_io_enq_ready),
.io_enq_valid(Queue_1_io_enq_valid),
.io_enq_bits_opcode(Queue_1_io_enq_bits_opcode),
.io_enq_bits_param(Queue_1_io_enq_bits_param),
.io_enq_bits_size(Queue_1_io_enq_bits_size),
.io_enq_bits_source(Queue_1_io_enq_bits_source),
.io_enq_bits_sink(Queue_1_io_enq_bits_sink),
.io_enq_bits_denied(Queue_1_io_enq_bits_denied),
.io_enq_bits_data(Queue_1_io_enq_bits_data),
.io_enq_bits_corrupt(Queue_1_io_enq_bits_corrupt),
.io_deq_ready(Queue_1_io_deq_ready),
.io_deq_valid(Queue_1_io_deq_valid),
.io_deq_bits_opcode(Queue_1_io_deq_bits_opcode),
.io_deq_bits_param(Queue_1_io_deq_bits_param),
.io_deq_bits_size(Queue_1_io_deq_bits_size),
.io_deq_bits_source(Queue_1_io_deq_bits_source),
.io_deq_bits_sink(Queue_1_io_deq_bits_sink),
.io_deq_bits_denied(Queue_1_io_deq_bits_denied),
.io_deq_bits_data(Queue_1_io_deq_bits_data),
.io_deq_bits_corrupt(Queue_1_io_deq_bits_corrupt)
);
assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_valid = Queue_1_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_param = Queue_1_io_deq_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_size = Queue_1_io_deq_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_source = Queue_1_io_deq_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_data = Queue_1_io_deq_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63792.4]
assign auto_out_a_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_opcode = Queue_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_param = Queue_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_size = Queue_io_deq_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_source = Queue_io_deq_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_address = Queue_io_deq_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_mask = Queue_io_deq_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_a_bits_corrupt = Queue_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign auto_out_d_ready = Queue_1_io_enq_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@63791.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63754.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63755.4]
assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_valid = Queue_1_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_opcode = Queue_1_io_deq_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_param = Queue_1_io_deq_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_size = Queue_1_io_deq_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_source = Queue_1_io_deq_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_sink = Queue_1_io_deq_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_denied = Queue_1_io_deq_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign TLMonitor_io_in_d_bits_corrupt = Queue_1_io_deq_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@63788.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63794.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63795.4]
assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@63796.4]
assign Queue_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63804.4]
assign Queue_io_enq_bits_param = auto_in_a_bits_param; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63803.4]
assign Queue_io_enq_bits_size = auto_in_a_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63802.4]
assign Queue_io_enq_bits_source = auto_in_a_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63801.4]
assign Queue_io_enq_bits_address = auto_in_a_bits_address; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63800.4]
assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63799.4]
assign Queue_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63797.4]
assign Queue_io_deq_ready = auto_out_a_ready; // @[Buffer.scala 38:13:freechips.rocketchip.system.LowRiscConfig.fir@63806.4]
assign Queue_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63808.4]
assign Queue_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63809.4]
assign Queue_1_io_enq_valid = auto_out_d_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@63810.4]
assign Queue_1_io_enq_bits_opcode = auto_out_d_bits_opcode; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63818.4]
assign Queue_1_io_enq_bits_param = 2'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63817.4]
assign Queue_1_io_enq_bits_size = auto_out_d_bits_size; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63816.4]
assign Queue_1_io_enq_bits_source = auto_out_d_bits_source; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63815.4]
assign Queue_1_io_enq_bits_sink = 1'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63814.4]
assign Queue_1_io_enq_bits_denied = 1'h1; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63813.4]
assign Queue_1_io_enq_bits_data = 64'h0; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63812.4]
assign Queue_1_io_enq_bits_corrupt = auto_out_d_bits_corrupt; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@63811.4]
assign Queue_1_io_deq_ready = auto_in_d_ready; // @[Buffer.scala 39:13:freechips.rocketchip.system.LowRiscConfig.fir@63820.4]
endmodule
module SimpleLazyModule_8( // @[:freechips.rocketchip.system.LowRiscConfig.fir@63828.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63829.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63830.4]
output auto_buffer_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input auto_buffer_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input [2:0] auto_buffer_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input [2:0] auto_buffer_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input [3:0] auto_buffer_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input [4:0] auto_buffer_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input [13:0] auto_buffer_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input [7:0] auto_buffer_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input auto_buffer_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
input auto_buffer_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output auto_buffer_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output [2:0] auto_buffer_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output [1:0] auto_buffer_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output [3:0] auto_buffer_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output [4:0] auto_buffer_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output auto_buffer_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output auto_buffer_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output [63:0] auto_buffer_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
output auto_buffer_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@63831.4]
);
wire error_clock; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_reset; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_auto_in_a_ready; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_auto_in_a_valid; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [2:0] error_auto_in_a_bits_opcode; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [2:0] error_auto_in_a_bits_param; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [3:0] error_auto_in_a_bits_size; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [4:0] error_auto_in_a_bits_source; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [13:0] error_auto_in_a_bits_address; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [7:0] error_auto_in_a_bits_mask; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_auto_in_a_bits_corrupt; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_auto_in_d_ready; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_auto_in_d_valid; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [2:0] error_auto_in_d_bits_opcode; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [3:0] error_auto_in_d_bits_size; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire [4:0] error_auto_in_d_bits_source; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire error_auto_in_d_bits_corrupt; // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [13:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [13:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
TLError error ( // @[CanHaveBuiltInDevices.scala 19:29:freechips.rocketchip.system.LowRiscConfig.fir@63836.4]
.clock(error_clock),
.reset(error_reset),
.auto_in_a_ready(error_auto_in_a_ready),
.auto_in_a_valid(error_auto_in_a_valid),
.auto_in_a_bits_opcode(error_auto_in_a_bits_opcode),
.auto_in_a_bits_param(error_auto_in_a_bits_param),
.auto_in_a_bits_size(error_auto_in_a_bits_size),
.auto_in_a_bits_source(error_auto_in_a_bits_source),
.auto_in_a_bits_address(error_auto_in_a_bits_address),
.auto_in_a_bits_mask(error_auto_in_a_bits_mask),
.auto_in_a_bits_corrupt(error_auto_in_a_bits_corrupt),
.auto_in_d_ready(error_auto_in_d_ready),
.auto_in_d_valid(error_auto_in_d_valid),
.auto_in_d_bits_opcode(error_auto_in_d_bits_opcode),
.auto_in_d_bits_size(error_auto_in_d_bits_size),
.auto_in_d_bits_source(error_auto_in_d_bits_source),
.auto_in_d_bits_corrupt(error_auto_in_d_bits_corrupt)
);
TLBuffer_8 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@63842.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(buffer_auto_in_d_bits_param),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
);
assign auto_buffer_in_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign auto_buffer_in_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign error_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63840.4]
assign error_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63841.4]
assign error_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign error_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63846.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@63847.4]
assign buffer_auto_in_a_valid = auto_buffer_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_opcode = auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_param = auto_buffer_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_size = auto_buffer_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_source = auto_buffer_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_address = auto_buffer_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_mask = auto_buffer_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_a_bits_corrupt = auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_in_d_ready = auto_buffer_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@63849.4]
assign buffer_auto_out_a_ready = error_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign buffer_auto_out_d_valid = error_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign buffer_auto_out_d_bits_opcode = error_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign buffer_auto_out_d_bits_size = error_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign buffer_auto_out_d_bits_source = error_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
assign buffer_auto_out_d_bits_corrupt = error_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@63848.4]
endmodule
module TLMonitor_26( // @[:freechips.rocketchip.system.LowRiscConfig.fir@63858.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63859.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63860.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@63861.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@65222.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@63878.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63879.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@63884.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@63885.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@63888.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63889.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63897.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63909.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63910.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63911.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63912.6]
wire [12:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@63914.6]
wire [5:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@63915.6]
wire [5:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@63916.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@63917.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@63917.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@63918.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@63920.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@63921.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@63922.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@63923.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@63924.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@63925.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@63926.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@63927.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63929.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63930.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63932.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63933.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@63934.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@63935.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@63936.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63937.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63938.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63939.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63940.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63941.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63942.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63943.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63944.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63945.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63946.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63947.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63948.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@63949.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@63950.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@63951.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63952.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63953.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63954.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63955.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63956.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63957.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63958.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63959.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63960.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63961.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63962.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63963.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63964.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63965.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63966.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63967.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63968.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63969.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63970.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63971.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63972.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63973.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63974.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63975.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@63982.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@64055.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@64058.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@64059.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@64060.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@64061.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@64062.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@64067.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@64105.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@64106.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@64118.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@64119.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@64125.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@64126.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@64133.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@64134.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@64140.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@64141.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@64146.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@64148.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@64149.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@64154.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@64155.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@64157.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@64158.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@64163.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@64165.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@64166.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@64172.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@64271.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@64273.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@64274.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@64297.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@64300.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@64308.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64311.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64312.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@64331.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@64333.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@64334.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@64339.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@64341.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@64342.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@64356.6]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@64407.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@64449.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@64450.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@64451.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@64453.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@64454.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@64460.6]
wire _T_490; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@64491.8]
wire _T_492; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@64493.8]
wire _T_493; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@64494.8]
wire _T_498; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@64508.6]
wire _T_516; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@64539.8]
wire _T_518; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@64541.8]
wire _T_519; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@64542.8]
wire _T_524; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@64556.6]
wire _T_550; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@64606.6]
wire _T_552; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@64608.6]
wire _T_553; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@64609.6]
wire [2:0] _T_556; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@64616.6]
wire _T_557; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@64617.6]
wire _T_562; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@64622.6]
wire _T_563; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@64623.6]
wire [1:0] _T_566; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@64626.6]
wire _T_567; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@64627.6]
wire _T_575; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@64635.6]
wire _T_591; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64647.6]
wire _T_592; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64648.6]
wire _T_593; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64649.6]
wire _T_594; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64650.6]
wire _T_596; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@64652.6]
wire _T_598; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64655.8]
wire _T_599; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64656.8]
wire _T_600; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@64661.8]
wire _T_602; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@64663.8]
wire _T_603; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@64664.8]
wire _T_616; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@64694.6]
wire _T_644; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@64752.6]
wire _T_673; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@64811.6]
wire _T_690; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@64846.6]
wire _T_708; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@64882.6]
wire _T_737; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@64942.4]
wire [2:0] _T_742; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@64947.4]
wire _T_743; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@64948.4]
wire _T_744; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@64949.4]
reg [2:0] _T_747; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@64951.4]
reg [31:0] _RAND_0;
wire [3:0] _T_748; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@64952.4]
wire [3:0] _T_749; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@64953.4]
wire [2:0] _T_750; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@64954.4]
wire _T_751; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@64955.4]
reg [2:0] _T_760; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@64966.4]
reg [31:0] _RAND_1;
reg [2:0] _T_762; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@64967.4]
reg [31:0] _RAND_2;
reg [2:0] _T_764; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@64968.4]
reg [31:0] _RAND_3;
reg [4:0] _T_766; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@64969.4]
reg [31:0] _RAND_4;
reg [27:0] _T_768; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@64970.4]
reg [31:0] _RAND_5;
wire _T_769; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@64971.4]
wire _T_770; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@64972.4]
wire _T_771; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@64974.6]
wire _T_773; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@64976.6]
wire _T_774; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@64977.6]
wire _T_775; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@64982.6]
wire _T_777; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@64984.6]
wire _T_778; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@64985.6]
wire _T_779; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@64990.6]
wire _T_781; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@64992.6]
wire _T_782; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@64993.6]
wire _T_783; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@64998.6]
wire _T_785; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@65000.6]
wire _T_786; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@65001.6]
wire _T_787; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@65006.6]
wire _T_789; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@65008.6]
wire _T_790; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@65009.6]
wire _T_792; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@65016.4]
wire _T_793; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@65024.4]
wire [12:0] _T_795; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65026.4]
wire [5:0] _T_796; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65027.4]
wire [5:0] _T_797; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65028.4]
wire [2:0] _T_798; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@65029.4]
wire _T_799; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@65030.4]
reg [2:0] _T_802; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@65032.4]
reg [31:0] _RAND_6;
wire [3:0] _T_803; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65033.4]
wire [3:0] _T_804; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65034.4]
wire [2:0] _T_805; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65035.4]
wire _T_806; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@65036.4]
reg [2:0] _T_815; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@65047.4]
reg [31:0] _RAND_7;
reg [2:0] _T_819; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@65049.4]
reg [31:0] _RAND_8;
reg [4:0] _T_821; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@65050.4]
reg [31:0] _RAND_9;
wire _T_826; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@65053.4]
wire _T_827; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@65054.4]
wire _T_828; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@65056.6]
wire _T_830; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@65058.6]
wire _T_831; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@65059.6]
wire _T_836; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@65072.6]
wire _T_838; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@65074.6]
wire _T_839; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@65075.6]
wire _T_840; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@65080.6]
wire _T_842; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@65082.6]
wire _T_843; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@65083.6]
wire _T_853; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@65106.4]
reg [24:0] _T_855; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@65115.4]
reg [31:0] _RAND_10;
reg [2:0] _T_866; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@65125.4]
reg [31:0] _RAND_11;
wire [3:0] _T_867; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65126.4]
wire [3:0] _T_868; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65127.4]
wire [2:0] _T_869; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65128.4]
wire _T_870; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@65129.4]
reg [2:0] _T_887; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@65148.4]
reg [31:0] _RAND_12;
wire [3:0] _T_888; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65149.4]
wire [3:0] _T_889; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65150.4]
wire [2:0] _T_890; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65151.4]
wire _T_891; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@65152.4]
wire _T_902; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@65167.4]
wire [31:0] _T_904; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@65170.6]
wire [24:0] _T_905; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@65172.6]
wire _T_906; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@65173.6]
wire _T_907; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@65174.6]
wire _T_909; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@65176.6]
wire _T_910; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@65177.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@65169.4]
wire _T_915; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@65188.4]
wire _T_917; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@65190.4]
wire _T_918; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@65191.4]
wire [31:0] _T_919; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@65193.6]
wire [24:0] _T_900; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65163.4 :freechips.rocketchip.system.LowRiscConfig.fir@65165.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@65171.6]
wire [24:0] _T_920; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@65195.6]
wire [24:0] _T_921; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@65196.6]
wire _T_922; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@65197.6]
wire _T_924; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@65199.6]
wire _T_925; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@65200.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@65192.4]
wire [24:0] _T_912; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65183.4 :freechips.rocketchip.system.LowRiscConfig.fir@65185.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@65194.6]
wire _T_926; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@65206.4]
wire _T_927; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@65207.4]
wire _T_928; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@65208.4]
wire _T_929; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@65209.4]
wire _T_931; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@65211.4]
wire _T_932; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@65212.4]
wire [24:0] _T_933; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@65217.4]
wire [24:0] _T_934; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@65218.4]
wire [24:0] _T_935; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@65219.4]
reg [31:0] _T_937; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@65221.4]
reg [31:0] _RAND_13;
wire _T_938; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@65224.4]
wire _T_939; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@65225.4]
wire _T_940; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@65226.4]
wire _T_941; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@65227.4]
wire _T_942; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@65228.4]
wire _T_943; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@65229.4]
wire _T_945; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@65231.4]
wire _T_946; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@65232.4]
wire [31:0] _T_948; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@65238.4]
wire _T_951; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@65242.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@64069.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@64186.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64314.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@64373.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@64424.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@64474.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@64522.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@64570.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64658.10]
wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@64700.10]
wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@64758.10]
wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@64817.10]
wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@64852.10]
wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@64888.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@65222.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@63878.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63879.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@63884.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@63885.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@63888.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63889.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@63897.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63909.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63910.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63911.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@63912.6]
assign _T_62 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@63914.6]
assign _T_63 = _T_62[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@63915.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@63916.6]
assign _GEN_18 = {{22'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@63917.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@63917.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@63918.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@63920.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@63921.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@63922.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@63923.6]
assign _T_72 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@63924.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@63925.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@63926.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@63927.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63929.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63930.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63932.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63933.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@63934.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@63935.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@63936.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63937.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63938.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63939.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63940.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63941.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63942.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63943.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63944.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63945.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63946.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63947.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63948.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@63949.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@63950.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@63951.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63952.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63953.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63954.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63955.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63956.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63957.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63958.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63959.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63960.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63961.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63962.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63963.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63964.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63965.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63966.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63967.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63968.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63969.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63970.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63971.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63972.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@63973.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@63974.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@63975.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@63982.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@64055.6]
assign _T_201 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@64058.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@64059.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@64060.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@64061.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@64062.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@64067.8]
assign _T_248 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@64105.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@64106.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@64118.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@64119.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@64125.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@64126.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@64133.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@64134.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@64140.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@64141.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@64146.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@64148.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@64149.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@64154.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@64155.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@64157.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@64158.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@64163.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@64165.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@64166.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@64172.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@64271.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@64273.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@64274.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@64297.6]
assign _T_381 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@64300.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@64308.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64311.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64312.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@64331.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@64333.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@64334.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@64339.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@64341.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@64342.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@64356.6]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@64407.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@64449.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@64450.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@64451.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@64453.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@64454.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@64460.6]
assign _T_490 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@64491.8]
assign _T_492 = _T_490 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@64493.8]
assign _T_493 = _T_492 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@64494.8]
assign _T_498 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@64508.6]
assign _T_516 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@64539.8]
assign _T_518 = _T_516 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@64541.8]
assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@64542.8]
assign _T_524 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@64556.6]
assign _T_550 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@64606.6]
assign _T_552 = _T_550 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@64608.6]
assign _T_553 = _T_552 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@64609.6]
assign _T_556 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@64616.6]
assign _T_557 = _T_556 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@64617.6]
assign _T_562 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@64622.6]
assign _T_563 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@64623.6]
assign _T_566 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@64626.6]
assign _T_567 = _T_566 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@64627.6]
assign _T_575 = _T_566 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@64635.6]
assign _T_591 = _T_557 | _T_562; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64647.6]
assign _T_592 = _T_591 | _T_563; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64648.6]
assign _T_593 = _T_592 | _T_567; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64649.6]
assign _T_594 = _T_593 | _T_575; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@64650.6]
assign _T_596 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@64652.6]
assign _T_598 = _T_594 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64655.8]
assign _T_599 = _T_598 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64656.8]
assign _T_600 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@64661.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@64663.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@64664.8]
assign _T_616 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@64694.6]
assign _T_644 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@64752.6]
assign _T_673 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@64811.6]
assign _T_690 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@64846.6]
assign _T_708 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@64882.6]
assign _T_737 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@64942.4]
assign _T_742 = _T_64[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@64947.4]
assign _T_743 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@64948.4]
assign _T_744 = _T_743 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@64949.4]
assign _T_748 = _T_747 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@64952.4]
assign _T_749 = $unsigned(_T_748); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@64953.4]
assign _T_750 = _T_749[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@64954.4]
assign _T_751 = _T_747 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@64955.4]
assign _T_769 = _T_751 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@64971.4]
assign _T_770 = io_in_a_valid & _T_769; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@64972.4]
assign _T_771 = io_in_a_bits_opcode == _T_760; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@64974.6]
assign _T_773 = _T_771 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@64976.6]
assign _T_774 = _T_773 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@64977.6]
assign _T_775 = io_in_a_bits_param == _T_762; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@64982.6]
assign _T_777 = _T_775 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@64984.6]
assign _T_778 = _T_777 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@64985.6]
assign _T_779 = io_in_a_bits_size == _T_764; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@64990.6]
assign _T_781 = _T_779 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@64992.6]
assign _T_782 = _T_781 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@64993.6]
assign _T_783 = io_in_a_bits_source == _T_766; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@64998.6]
assign _T_785 = _T_783 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@65000.6]
assign _T_786 = _T_785 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@65001.6]
assign _T_787 = io_in_a_bits_address == _T_768; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@65006.6]
assign _T_789 = _T_787 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@65008.6]
assign _T_790 = _T_789 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@65009.6]
assign _T_792 = _T_737 & _T_751; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@65016.4]
assign _T_793 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@65024.4]
assign _T_795 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65026.4]
assign _T_796 = _T_795[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65027.4]
assign _T_797 = ~ _T_796; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65028.4]
assign _T_798 = _T_797[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@65029.4]
assign _T_799 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@65030.4]
assign _T_803 = _T_802 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65033.4]
assign _T_804 = $unsigned(_T_803); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65034.4]
assign _T_805 = _T_804[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65035.4]
assign _T_806 = _T_802 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@65036.4]
assign _T_826 = _T_806 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@65053.4]
assign _T_827 = io_in_d_valid & _T_826; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@65054.4]
assign _T_828 = io_in_d_bits_opcode == _T_815; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@65056.6]
assign _T_830 = _T_828 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@65058.6]
assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@65059.6]
assign _T_836 = io_in_d_bits_size == _T_819; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@65072.6]
assign _T_838 = _T_836 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@65074.6]
assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@65075.6]
assign _T_840 = io_in_d_bits_source == _T_821; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@65080.6]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@65082.6]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@65083.6]
assign _T_853 = _T_793 & _T_806; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@65106.4]
assign _T_867 = _T_866 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65126.4]
assign _T_868 = $unsigned(_T_867); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65127.4]
assign _T_869 = _T_868[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65128.4]
assign _T_870 = _T_866 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@65129.4]
assign _T_888 = _T_887 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65149.4]
assign _T_889 = $unsigned(_T_888); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65150.4]
assign _T_890 = _T_889[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@65151.4]
assign _T_891 = _T_887 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@65152.4]
assign _T_902 = _T_737 & _T_870; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@65167.4]
assign _T_904 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@65170.6]
assign _T_905 = _T_855 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@65172.6]
assign _T_906 = _T_905[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@65173.6]
assign _T_907 = _T_906 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@65174.6]
assign _T_909 = _T_907 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@65176.6]
assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@65177.6]
assign _GEN_15 = _T_902 ? _T_904 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@65169.4]
assign _T_915 = _T_793 & _T_891; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@65188.4]
assign _T_917 = _T_596 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@65190.4]
assign _T_918 = _T_915 & _T_917; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@65191.4]
assign _T_919 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@65193.6]
assign _T_900 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65163.4 :freechips.rocketchip.system.LowRiscConfig.fir@65165.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@65171.6]
assign _T_920 = _T_900 | _T_855; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@65195.6]
assign _T_921 = _T_920 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@65196.6]
assign _T_922 = _T_921[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@65197.6]
assign _T_924 = _T_922 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@65199.6]
assign _T_925 = _T_924 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@65200.6]
assign _GEN_16 = _T_918 ? _T_919 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@65192.4]
assign _T_912 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65183.4 :freechips.rocketchip.system.LowRiscConfig.fir@65185.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@65194.6]
assign _T_926 = _T_900 != _T_912; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@65206.4]
assign _T_927 = _T_900 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@65207.4]
assign _T_928 = _T_927 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@65208.4]
assign _T_929 = _T_926 | _T_928; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@65209.4]
assign _T_931 = _T_929 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@65211.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@65212.4]
assign _T_933 = _T_855 | _T_900; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@65217.4]
assign _T_934 = ~ _T_912; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@65218.4]
assign _T_935 = _T_933 & _T_934; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@65219.4]
assign _T_938 = _T_855 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@65224.4]
assign _T_939 = _T_938 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@65225.4]
assign _T_940 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@65226.4]
assign _T_941 = _T_939 | _T_940; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@65227.4]
assign _T_942 = _T_937 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@65228.4]
assign _T_943 = _T_941 | _T_942; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@65229.4]
assign _T_945 = _T_943 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@65231.4]
assign _T_946 = _T_945 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@65232.4]
assign _T_948 = _T_937 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@65238.4]
assign _T_951 = _T_737 | _T_793; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@65242.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@64069.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@64186.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64314.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@64373.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@64424.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@64474.10]
assign _GEN_95 = io_in_a_valid & _T_498; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@64522.10]
assign _GEN_105 = io_in_a_valid & _T_524; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@64570.10]
assign _GEN_115 = io_in_d_valid & _T_596; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64658.10]
assign _GEN_119 = io_in_d_valid & _T_616; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@64700.10]
assign _GEN_125 = io_in_d_valid & _T_644; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@64758.10]
assign _GEN_131 = io_in_d_valid & _T_673; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@64817.10]
assign _GEN_133 = io_in_d_valid & _T_690; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@64852.10]
assign _GEN_135 = io_in_d_valid & _T_708; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@64888.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_747 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_760 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_762 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_764 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_766 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_768 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_802 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_815 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_819 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_821 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_855 = _RAND_10[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_866 = _RAND_11[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_887 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_937 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_747 <= 3'h0;
end else begin
if (_T_737) begin
if (_T_751) begin
if (_T_744) begin
_T_747 <= _T_742;
end else begin
_T_747 <= 3'h0;
end
end else begin
_T_747 <= _T_750;
end
end
end
if (_T_792) begin
_T_760 <= io_in_a_bits_opcode;
end
if (_T_792) begin
_T_762 <= io_in_a_bits_param;
end
if (_T_792) begin
_T_764 <= io_in_a_bits_size;
end
if (_T_792) begin
_T_766 <= io_in_a_bits_source;
end
if (_T_792) begin
_T_768 <= io_in_a_bits_address;
end
if (reset) begin
_T_802 <= 3'h0;
end else begin
if (_T_793) begin
if (_T_806) begin
if (_T_799) begin
_T_802 <= _T_798;
end else begin
_T_802 <= 3'h0;
end
end else begin
_T_802 <= _T_805;
end
end
end
if (_T_853) begin
_T_815 <= io_in_d_bits_opcode;
end
if (_T_853) begin
_T_819 <= io_in_d_bits_size;
end
if (_T_853) begin
_T_821 <= io_in_d_bits_source;
end
if (reset) begin
_T_855 <= 25'h0;
end else begin
_T_855 <= _T_935;
end
if (reset) begin
_T_866 <= 3'h0;
end else begin
if (_T_737) begin
if (_T_870) begin
if (_T_744) begin
_T_866 <= _T_742;
end else begin
_T_866 <= 3'h0;
end
end else begin
_T_866 <= _T_869;
end
end
end
if (reset) begin
_T_887 <= 3'h0;
end else begin
if (_T_793) begin
if (_T_891) begin
if (_T_799) begin
_T_887 <= _T_798;
end else begin
_T_887 <= 3'h0;
end
end else begin
_T_887 <= _T_890;
end
end
end
if (reset) begin
_T_937 <= 32'h0;
end else begin
if (_T_951) begin
_T_937 <= 32'h0;
end else begin
_T_937 <= _T_948;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Plic.scala:366:61)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@63873.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@63874.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@64052.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@64053.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@64069.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@64070.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:366:61)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@64121.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@64122.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@64128.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@64129.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:366:61)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@64136.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@64137.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@64143.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@64144.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:366:61)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@64151.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@64152.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@64160.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@64161.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@64168.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@64169.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@64186.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@64187.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:366:61)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@64238.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@64239.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@64245.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@64246.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:366:61)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@64253.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@64254.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@64260.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@64261.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:366:61)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@64268.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@64269.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:366:61)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@64276.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@64277.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@64285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@64286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@64293.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@64294.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64314.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@64315.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@64321.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@64322.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@64328.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@64329.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@64336.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@64337.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@64344.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@64345.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@64352.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@64353.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@64373.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@64374.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@64380.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@64381.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@64387.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@64388.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@64395.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@64396.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@64403.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@64404.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@64424.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@64425.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@64431.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@64432.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@64438.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@64439.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@64446.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@64447.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@64456.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@64457.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@64474.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@64475.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@64481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@64482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@64488.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@64489.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:366:61)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@64496.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@64497.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@64504.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@64505.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@64522.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@64523.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@64529.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@64530.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@64536.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@64537.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:366:61)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@64544.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@64545.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@64552.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@64553.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Plic.scala:366:61)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@64570.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@64571.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@64577.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@64578.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:366:61)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@64584.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@64585.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:366:61)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@64592.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@64593.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@64600.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@64601.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:366:61)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@64611.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@64612.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64658.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@64659.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:366:61)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@64666.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@64667.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@64674.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@64675.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@64682.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@64683.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Plic.scala:366:61)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@64690.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@64691.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@64700.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_599) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@64701.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:366:61)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@64707.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@64708.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:366:61)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@64715.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_603) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@64716.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Plic.scala:366:61)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@64723.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@64724.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Plic.scala:366:61)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@64731.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@64732.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@64739.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@64740.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Plic.scala:366:61)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@64748.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@64749.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@64758.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_599) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@64759.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:366:61)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@64765.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@64766.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:366:61)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@64773.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_603) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@64774.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Plic.scala:366:61)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@64781.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@64782.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Plic.scala:366:61)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@64789.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@64790.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@64798.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@64799.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Plic.scala:366:61)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@64807.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@64808.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@64817.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@64818.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@64825.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@64826.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@64833.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@64834.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Plic.scala:366:61)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@64842.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@64843.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_133 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@64852.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_133 & _T_599) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@64853.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@64860.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@64861.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@64869.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@64870.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Plic.scala:366:61)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@64878.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@64879.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:366:61)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@64888.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_599) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@64889.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Plic.scala:366:61)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@64896.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@64897.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Plic.scala:366:61)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@64904.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@64905.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Plic.scala:366:61)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@64913.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@64914.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Plic.scala:366:61)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@64923.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@64924.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Plic.scala:366:61)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@64931.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@64932.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Plic.scala:366:61)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@64939.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@64940.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_774) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@64979.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_774) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@64980.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_778) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@64987.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_778) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@64988.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_782) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@64995.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_782) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@64996.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_786) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@65003.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_786) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@65004.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_790) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@65011.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_790) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@65012.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_831) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@65061.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_831) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@65062.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@65069.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@65070.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_839) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@65077.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_839) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@65078.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@65085.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_843) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@65086.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@65093.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@65094.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Plic.scala:366:61)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@65101.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@65102.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_902 & _T_910) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:366:61)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@65179.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_902 & _T_910) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@65180.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918 & _T_925) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:366:61)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@65202.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918 & _T_925) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@65203.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_932) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:366:61)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@65214.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_932) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@65215.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_946) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Plic.scala:366:61)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@65234.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_946) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@65235.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Repeater( // @[:freechips.rocketchip.system.LowRiscConfig.fir@65247.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65248.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65249.4]
input io_repeat, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output io_full, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input [27:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output [27:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@65250.4]
);
reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.LowRiscConfig.fir@65255.4]
reg [31:0] _RAND_0;
reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_1;
reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_2;
reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_3;
reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_4;
reg [27:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_5;
reg [7:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_6;
reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@65256.4]
reg [31:0] _RAND_7;
wire _T_18; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@65259.4]
wire _T_21; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65265.4]
wire _T_22; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@65266.4]
wire _T_23; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65271.4]
wire _T_24; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@65272.4]
wire _T_25; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@65273.4]
assign _T_18 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@65259.4]
assign _T_21 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65265.4]
assign _T_22 = _T_21 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@65266.4]
assign _T_23 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65271.4]
assign _T_24 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@65272.4]
assign _T_25 = _T_23 & _T_24; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@65273.4]
assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.LowRiscConfig.fir@65264.4]
assign io_enq_ready = io_deq_ready & _T_18; // @[Repeater.scala 23:16:freechips.rocketchip.system.LowRiscConfig.fir@65261.4]
assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.LowRiscConfig.fir@65258.4]
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@65263.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
saved_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
saved_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
saved_size = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
saved_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
saved_address = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
saved_mask = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
full <= 1'h0;
end else begin
if (_T_25) begin
full <= 1'h0;
end else begin
if (_T_22) begin
full <= 1'h1;
end
end
end
if (_T_22) begin
saved_opcode <= io_enq_bits_opcode;
end
if (_T_22) begin
saved_param <= io_enq_bits_param;
end
if (_T_22) begin
saved_size <= io_enq_bits_size;
end
if (_T_22) begin
saved_source <= io_enq_bits_source;
end
if (_T_22) begin
saved_address <= io_enq_bits_address;
end
if (_T_22) begin
saved_mask <= io_enq_bits_mask;
end
if (_T_22) begin
saved_corrupt <= io_enq_bits_corrupt;
end
end
endmodule
module TLFragmenter( // @[:freechips.rocketchip.system.LowRiscConfig.fir@65278.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65279.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65280.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [8:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [8:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
input [63:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@65281.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [27:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [7:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [27:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire [7:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
reg [2:0] _T_244; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.LowRiscConfig.fir@65329.4]
reg [31:0] _RAND_0;
reg [2:0] _T_246; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.LowRiscConfig.fir@65330.4]
reg [31:0] _RAND_1;
reg _T_248; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.LowRiscConfig.fir@65331.4]
reg [31:0] _RAND_2;
wire [2:0] _T_249; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@65332.4]
wire _T_250; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@65333.4]
wire _T_251; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.LowRiscConfig.fir@65334.4]
wire [3:0] _T_253; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@65336.4]
wire [5:0] _T_256; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65339.4]
wire [2:0] _T_257; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65340.4]
wire [2:0] _T_258; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65341.4]
wire _T_259; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@65342.4]
wire _T_271; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.LowRiscConfig.fir@65358.4]
wire _T_272; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.LowRiscConfig.fir@65359.4]
wire [5:0] _GEN_7; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@65360.4]
wire [5:0] _T_273; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@65360.4]
wire [5:0] _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@65361.4]
wire [5:0] _T_274; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@65361.4]
wire [6:0] _GEN_9; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@65362.4]
wire [6:0] _T_275; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@65362.4]
wire [6:0] _T_276; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@65363.4]
wire [6:0] _T_277; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65364.4]
wire [6:0] _T_278; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@65365.4]
wire [6:0] _T_279; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@65366.4]
wire [2:0] _T_280; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@65367.4]
wire [3:0] _T_281; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@65368.4]
wire _T_282; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@65369.4]
wire [3:0] _GEN_10; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@65370.4]
wire [3:0] _T_283; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@65370.4]
wire [1:0] _T_284; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@65371.4]
wire [1:0] _T_285; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@65372.4]
wire _T_286; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@65373.4]
wire [1:0] _T_287; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@65374.4]
wire _T_288; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@65375.4]
wire [2:0] _T_290; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65377.4]
wire _T_297; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.LowRiscConfig.fir@65391.4]
wire _T_299; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.LowRiscConfig.fir@65393.4]
wire _T_300; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.LowRiscConfig.fir@65394.4]
wire _T_301; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.LowRiscConfig.fir@65395.4]
wire _T_291; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65378.4]
wire [2:0] _GEN_11; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65380.6]
wire [3:0] _T_292; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65380.6]
wire [3:0] _T_293; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65381.6]
wire [2:0] _T_294; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65382.6]
wire _T_296; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@65387.8]
wire _T_302; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.LowRiscConfig.fir@65397.4]
wire _T_330; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@65430.4]
wire [2:0] _T_331; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@65431.4]
wire [12:0] _T_333; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65433.4]
wire [5:0] _T_334; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65434.4]
wire [5:0] _T_335; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65435.4]
wire [9:0] _T_337; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65437.4]
wire [2:0] _T_338; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65438.4]
wire [2:0] _T_339; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65439.4]
wire _T_340; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@65440.4]
wire _T_341; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@65441.4]
reg [2:0] _T_344; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.LowRiscConfig.fir@65443.4]
reg [31:0] _RAND_3;
wire _T_345; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@65444.4]
wire [2:0] _T_346; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@65445.4]
wire [3:0] _T_347; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@65446.4]
wire [3:0] _T_348; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@65447.4]
wire [2:0] _T_349; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@65448.4]
wire [2:0] _T_350; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@65449.4]
wire [2:0] _T_351; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@65450.4]
wire [2:0] _T_354; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@65453.4]
reg _T_362; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@65460.4]
reg [31:0] _RAND_4;
wire _GEN_5; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@65461.4]
wire _T_364; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@65465.4]
wire _T_92_a_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@65325.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@65474.4]
wire _T_365; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65466.4]
wire _T_366; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.LowRiscConfig.fir@65470.4]
wire _T_367; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.LowRiscConfig.fir@65471.4]
wire [5:0] _GEN_12; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@65475.4]
wire [5:0] _T_369; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@65475.4]
wire [5:0] _T_370; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@65476.4]
wire [5:0] _T_371; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@65477.4]
wire [5:0] _GEN_13; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@65478.4]
wire [5:0] _T_372; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@65478.4]
wire [5:0] _T_373; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@65479.4]
wire [5:0] _T_374; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@65480.4]
wire [27:0] _GEN_14; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@65481.4]
wire [5:0] _T_376; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65483.4]
wire _T_378; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@65487.4]
wire _T_380; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.LowRiscConfig.fir@65489.4]
wire _T_382; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@65491.4]
wire _T_383; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@65492.4]
wire _T_385; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@65499.4]
wire _T_386; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@65500.4]
wire _T_388; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@65502.4]
wire _T_389; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@65503.4]
TLMonitor_26 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@65288.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source)
);
Repeater Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@65405.4]
.clock(Repeater_clock),
.reset(Repeater_reset),
.io_repeat(Repeater_io_repeat),
.io_full(Repeater_io_full),
.io_enq_ready(Repeater_io_enq_ready),
.io_enq_valid(Repeater_io_enq_valid),
.io_enq_bits_opcode(Repeater_io_enq_bits_opcode),
.io_enq_bits_param(Repeater_io_enq_bits_param),
.io_enq_bits_size(Repeater_io_enq_bits_size),
.io_enq_bits_source(Repeater_io_enq_bits_source),
.io_enq_bits_address(Repeater_io_enq_bits_address),
.io_enq_bits_mask(Repeater_io_enq_bits_mask),
.io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt),
.io_deq_ready(Repeater_io_deq_ready),
.io_deq_valid(Repeater_io_deq_valid),
.io_deq_bits_opcode(Repeater_io_deq_bits_opcode),
.io_deq_bits_param(Repeater_io_deq_bits_param),
.io_deq_bits_size(Repeater_io_deq_bits_size),
.io_deq_bits_source(Repeater_io_deq_bits_source),
.io_deq_bits_address(Repeater_io_deq_bits_address),
.io_deq_bits_mask(Repeater_io_deq_bits_mask),
.io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt)
);
assign _T_249 = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@65332.4]
assign _T_250 = _T_244 == 3'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@65333.4]
assign _T_251 = _T_249 == 3'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.LowRiscConfig.fir@65334.4]
assign _T_253 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@65336.4]
assign _T_256 = 6'h7 << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65339.4]
assign _T_257 = _T_256[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65340.4]
assign _T_258 = ~ _T_257; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65341.4]
assign _T_259 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@65342.4]
assign _T_271 = _T_253[3:3]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.LowRiscConfig.fir@65358.4]
assign _T_272 = _T_259 ? 1'h1 : _T_271; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.LowRiscConfig.fir@65359.4]
assign _GEN_7 = {{3'd0}, _T_249}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@65360.4]
assign _T_273 = _GEN_7 << 3; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@65360.4]
assign _GEN_8 = {{3'd0}, _T_258}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@65361.4]
assign _T_274 = _T_273 | _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@65361.4]
assign _GEN_9 = {{1'd0}, _T_274}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@65362.4]
assign _T_275 = _GEN_9 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@65362.4]
assign _T_276 = _T_275 | 7'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@65363.4]
assign _T_277 = {1'h0,_T_274}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65364.4]
assign _T_278 = ~ _T_277; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@65365.4]
assign _T_279 = _T_276 & _T_278; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@65366.4]
assign _T_280 = _T_279[6:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@65367.4]
assign _T_281 = _T_279[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@65368.4]
assign _T_282 = _T_280 != 3'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@65369.4]
assign _GEN_10 = {{1'd0}, _T_280}; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@65370.4]
assign _T_283 = _GEN_10 | _T_281; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@65370.4]
assign _T_284 = _T_283[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@65371.4]
assign _T_285 = _T_283[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@65372.4]
assign _T_286 = _T_284 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@65373.4]
assign _T_287 = _T_284 | _T_285; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@65374.4]
assign _T_288 = _T_287[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@65375.4]
assign _T_290 = {_T_282,_T_286,_T_288}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65377.4]
assign _T_297 = _T_259 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.LowRiscConfig.fir@65391.4]
assign _T_299 = _T_251 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.LowRiscConfig.fir@65393.4]
assign _T_300 = _T_297 & _T_299; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.LowRiscConfig.fir@65394.4]
assign _T_301 = auto_in_d_ready | _T_300; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.LowRiscConfig.fir@65395.4]
assign _T_291 = _T_301 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65378.4]
assign _GEN_11 = {{2'd0}, _T_272}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65380.6]
assign _T_292 = _T_244 - _GEN_11; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65380.6]
assign _T_293 = $unsigned(_T_292); // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65381.6]
assign _T_294 = _T_293[2:0]; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@65382.6]
assign _T_296 = auto_out_d_bits_source[3]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@65387.8]
assign _T_302 = _T_300 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.LowRiscConfig.fir@65397.4]
assign _T_330 = Repeater_io_deq_bits_size > 3'h3; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@65430.4]
assign _T_331 = _T_330 ? 3'h3 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@65431.4]
assign _T_333 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65433.4]
assign _T_334 = _T_333[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65434.4]
assign _T_335 = ~ _T_334; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65435.4]
assign _T_337 = 10'h7 << _T_331; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65437.4]
assign _T_338 = _T_337[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65438.4]
assign _T_339 = ~ _T_338; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65439.4]
assign _T_340 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@65440.4]
assign _T_341 = _T_340 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@65441.4]
assign _T_345 = _T_344 == 3'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@65444.4]
assign _T_346 = _T_335[5:3]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@65445.4]
assign _T_347 = _T_344 - 3'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@65446.4]
assign _T_348 = $unsigned(_T_347); // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@65447.4]
assign _T_349 = _T_348[2:0]; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@65448.4]
assign _T_350 = _T_345 ? _T_346 : _T_349; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@65449.4]
assign _T_351 = ~ _T_350; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@65450.4]
assign _T_354 = ~ _T_351; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@65453.4]
assign _GEN_5 = _T_345 ? _T_248 : _T_362; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@65461.4]
assign _T_364 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@65465.4]
assign _T_92_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@65325.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@65474.4]
assign _T_365 = auto_out_a_ready & _T_92_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@65466.4]
assign _T_366 = _T_341 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.LowRiscConfig.fir@65470.4]
assign _T_367 = _T_354 != 3'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.LowRiscConfig.fir@65471.4]
assign _GEN_12 = {{3'd0}, _T_350}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@65475.4]
assign _T_369 = _GEN_12 << 3; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@65475.4]
assign _T_370 = ~ _T_335; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@65476.4]
assign _T_371 = _T_369 | _T_370; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@65477.4]
assign _GEN_13 = {{3'd0}, _T_339}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@65478.4]
assign _T_372 = _T_371 | _GEN_13; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@65478.4]
assign _T_373 = _T_372 | 6'h7; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@65479.4]
assign _T_374 = ~ _T_373; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@65480.4]
assign _GEN_14 = {{22'd0}, _T_374}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@65481.4]
assign _T_376 = {Repeater_io_deq_bits_source,_T_364}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65483.4]
assign _T_378 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@65487.4]
assign _T_380 = _T_378 | _T_366; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.LowRiscConfig.fir@65489.4]
assign _T_382 = _T_380 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@65491.4]
assign _T_383 = _T_382 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@65492.4]
assign _T_385 = Repeater_io_deq_bits_mask == 8'hff; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@65499.4]
assign _T_386 = _T_378 | _T_385; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@65500.4]
assign _T_388 = _T_386 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@65502.4]
assign _T_389 = _T_388 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@65503.4]
assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65328.4]
assign auto_in_d_valid = auto_out_d_valid & _T_302; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65328.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65328.4]
assign auto_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65328.4]
assign auto_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65328.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65328.4]
assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_size = _T_331[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_source = {_T_376,_T_354}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_14; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_mask = Repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign auto_out_d_ready = auto_in_d_ready | _T_300; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65327.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65290.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65291.4]
assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_302; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@65324.4]
assign Repeater_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65407.4]
assign Repeater_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65408.4]
assign Repeater_io_repeat = _T_366 & _T_367; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.LowRiscConfig.fir@65473.4]
assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@65409.4]
assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@65474.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_244 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_246 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_248 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_344 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_362 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_244 <= 3'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_244 <= _T_249;
end else begin
_T_244 <= _T_294;
end
end
end
if (_T_291) begin
if (_T_250) begin
_T_246 <= _T_290;
end
end
if (reset) begin
_T_248 <= 1'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_248 <= _T_296;
end
end
end
if (reset) begin
_T_344 <= 3'h0;
end else begin
if (_T_365) begin
_T_344 <= _T_354;
end
end
if (_T_345) begin
_T_362 <= _T_248;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:183 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"); // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@65353.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@65354.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_383) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@65494.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_383) begin
$fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@65495.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_389) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@65505.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_389) begin
$fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@65506.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module SimpleLazyModule_9( // @[:freechips.rocketchip.system.LowRiscConfig.fir@65517.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65518.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65519.4]
output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [27:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [7:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [63:0] auto_fragmenter_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [2:0] auto_fragmenter_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [63:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [8:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [27:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [7:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output [63:0] auto_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [2:0] auto_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [8:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
input [63:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@65520.4]
);
wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [27:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [8:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [27:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [8:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
TLFragmenter fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@65525.4]
.clock(fragmenter_clock),
.reset(fragmenter_reset),
.auto_in_a_ready(fragmenter_auto_in_a_ready),
.auto_in_a_valid(fragmenter_auto_in_a_valid),
.auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
.auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
.auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
.auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
.auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
.auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
.auto_in_d_ready(fragmenter_auto_in_d_ready),
.auto_in_d_valid(fragmenter_auto_in_d_valid),
.auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
.auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
.auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
.auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
.auto_out_a_ready(fragmenter_auto_out_a_ready),
.auto_out_a_valid(fragmenter_auto_out_a_valid),
.auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
.auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
.auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
.auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
.auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
.auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
.auto_out_d_ready(fragmenter_auto_out_d_ready),
.auto_out_d_valid(fragmenter_auto_out_d_valid),
.auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
.auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
.auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
.auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
);
assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign auto_fragmenter_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65529.4]
assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@65530.4]
assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_data = auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@65532.4]
assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@65531.4]
endmodule
module TLMonitor_27( // @[:freechips.rocketchip.system.LowRiscConfig.fir@65541.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65542.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65543.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [25:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@65544.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@66894.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@65561.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@65562.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@65567.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@65568.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@65571.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@65572.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@65580.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65592.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65593.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65594.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65595.6]
wire [12:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65597.6]
wire [5:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65598.6]
wire [5:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65599.6]
wire [25:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@65600.6]
wire [25:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@65600.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@65601.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@65603.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@65604.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@65605.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@65606.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@65607.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@65608.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@65609.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@65610.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65612.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65613.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65615.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65616.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@65617.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@65618.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@65619.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65620.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65621.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65622.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65623.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65624.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65625.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65626.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65627.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65628.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65629.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65630.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65631.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@65632.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@65633.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@65634.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65635.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65636.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65637.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65638.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65639.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65640.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65641.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65642.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65643.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65644.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65645.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65646.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65647.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65648.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65649.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65650.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65651.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65652.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65653.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65654.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65655.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65656.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65657.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65658.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65665.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@65738.6]
wire [25:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@65741.8]
wire [26:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@65742.8]
wire [26:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@65743.8]
wire [26:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@65744.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@65745.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@65750.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@65788.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@65789.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@65801.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@65802.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@65808.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@65809.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@65816.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@65817.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@65823.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@65824.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@65829.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@65831.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@65832.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@65837.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@65838.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@65840.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@65841.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@65846.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@65848.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@65849.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@65855.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@65954.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@65956.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@65957.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@65980.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@65983.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@65991.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65994.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65995.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@66014.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@66016.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@66017.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@66022.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@66024.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@66025.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@66039.6]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@66090.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@66132.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@66133.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@66134.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@66136.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@66137.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@66143.6]
wire _T_490; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@66174.8]
wire _T_492; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@66176.8]
wire _T_493; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@66177.8]
wire _T_498; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@66191.6]
wire _T_516; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@66222.8]
wire _T_518; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@66224.8]
wire _T_519; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@66225.8]
wire _T_524; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@66239.6]
wire _T_550; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@66289.6]
wire _T_552; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@66291.6]
wire _T_553; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@66292.6]
wire [2:0] _T_556; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@66299.6]
wire _T_557; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@66300.6]
wire _T_562; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@66305.6]
wire _T_563; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@66306.6]
wire [1:0] _T_566; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@66309.6]
wire _T_567; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@66310.6]
wire _T_575; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@66318.6]
wire _T_591; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66330.6]
wire _T_592; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66331.6]
wire _T_593; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66332.6]
wire _T_594; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66333.6]
wire _T_596; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@66335.6]
wire _T_598; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66338.8]
wire _T_599; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66339.8]
wire _T_600; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@66344.8]
wire _T_602; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@66346.8]
wire _T_603; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@66347.8]
wire _T_616; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@66377.6]
wire _T_644; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@66435.6]
wire _T_673; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@66494.6]
wire _T_690; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@66529.6]
wire _T_708; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@66565.6]
wire _T_737; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@66625.4]
wire [2:0] _T_742; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@66630.4]
wire _T_743; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@66631.4]
wire _T_744; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@66632.4]
reg [2:0] _T_747; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@66634.4]
reg [31:0] _RAND_0;
wire [3:0] _T_748; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66635.4]
wire [3:0] _T_749; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66636.4]
wire [2:0] _T_750; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66637.4]
wire _T_751; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66638.4]
reg [2:0] _T_760; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@66649.4]
reg [31:0] _RAND_1;
reg [2:0] _T_762; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@66650.4]
reg [31:0] _RAND_2;
reg [2:0] _T_764; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@66651.4]
reg [31:0] _RAND_3;
reg [4:0] _T_766; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@66652.4]
reg [31:0] _RAND_4;
reg [25:0] _T_768; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@66653.4]
reg [31:0] _RAND_5;
wire _T_769; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@66654.4]
wire _T_770; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@66655.4]
wire _T_771; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@66657.6]
wire _T_773; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@66659.6]
wire _T_774; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@66660.6]
wire _T_775; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@66665.6]
wire _T_777; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@66667.6]
wire _T_778; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@66668.6]
wire _T_779; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@66673.6]
wire _T_781; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@66675.6]
wire _T_782; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@66676.6]
wire _T_783; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@66681.6]
wire _T_785; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@66683.6]
wire _T_786; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@66684.6]
wire _T_787; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@66689.6]
wire _T_789; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@66691.6]
wire _T_790; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@66692.6]
wire _T_792; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@66699.4]
wire _T_793; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@66707.4]
wire [12:0] _T_795; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@66709.4]
wire [5:0] _T_796; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@66710.4]
wire [5:0] _T_797; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@66711.4]
wire [2:0] _T_798; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@66712.4]
wire _T_799; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@66713.4]
reg [2:0] _T_802; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@66715.4]
reg [31:0] _RAND_6;
wire [3:0] _T_803; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66716.4]
wire [3:0] _T_804; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66717.4]
wire [2:0] _T_805; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66718.4]
wire _T_806; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66719.4]
reg [2:0] _T_815; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@66730.4]
reg [31:0] _RAND_7;
reg [2:0] _T_819; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@66732.4]
reg [31:0] _RAND_8;
reg [4:0] _T_821; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@66733.4]
reg [31:0] _RAND_9;
wire _T_826; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@66736.4]
wire _T_827; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@66737.4]
wire _T_828; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@66739.6]
wire _T_830; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@66741.6]
wire _T_831; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@66742.6]
wire _T_836; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@66755.6]
wire _T_838; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@66757.6]
wire _T_839; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@66758.6]
wire _T_840; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@66763.6]
wire _T_842; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@66765.6]
wire _T_843; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@66766.6]
wire _T_853; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@66789.4]
reg [24:0] _T_855; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@66798.4]
reg [31:0] _RAND_10;
reg [2:0] _T_866; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@66808.4]
reg [31:0] _RAND_11;
wire [3:0] _T_867; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66809.4]
wire [3:0] _T_868; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66810.4]
wire [2:0] _T_869; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66811.4]
wire _T_870; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66812.4]
reg [2:0] _T_887; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@66831.4]
reg [31:0] _RAND_12;
wire [3:0] _T_888; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66832.4]
wire [3:0] _T_889; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66833.4]
wire [2:0] _T_890; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66834.4]
wire _T_891; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66835.4]
wire _T_902; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@66850.4]
wire [31:0] _T_904; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@66853.6]
wire [24:0] _T_905; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@66855.6]
wire _T_906; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@66856.6]
wire _T_907; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@66857.6]
wire _T_909; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@66859.6]
wire _T_910; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@66860.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@66852.4]
wire _T_915; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@66871.4]
wire _T_917; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@66873.4]
wire _T_918; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@66874.4]
wire [31:0] _T_919; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@66876.6]
wire [24:0] _T_900; // @[:freechips.rocketchip.system.LowRiscConfig.fir@66846.4 :freechips.rocketchip.system.LowRiscConfig.fir@66848.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@66854.6]
wire [24:0] _T_920; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@66878.6]
wire [24:0] _T_921; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@66879.6]
wire _T_922; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@66880.6]
wire _T_924; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@66882.6]
wire _T_925; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@66883.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@66875.4]
wire [24:0] _T_926; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@66889.4]
wire [24:0] _T_912; // @[:freechips.rocketchip.system.LowRiscConfig.fir@66866.4 :freechips.rocketchip.system.LowRiscConfig.fir@66868.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@66877.6]
wire [24:0] _T_927; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@66890.4]
wire [24:0] _T_928; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@66891.4]
reg [31:0] _T_930; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@66893.4]
reg [31:0] _RAND_13;
wire _T_931; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@66896.4]
wire _T_932; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@66897.4]
wire _T_933; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@66898.4]
wire _T_934; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@66899.4]
wire _T_935; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@66900.4]
wire _T_936; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@66901.4]
wire _T_938; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@66903.4]
wire _T_939; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@66904.4]
wire [31:0] _T_941; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@66910.4]
wire _T_944; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@66914.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@65752.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@65869.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65997.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@66056.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@66107.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@66157.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@66205.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@66253.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66341.10]
wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@66383.10]
wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@66441.10]
wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@66500.10]
wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@66535.10]
wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@66571.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@66894.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@65561.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@65562.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@65567.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@65568.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@65571.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@65572.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@65580.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65592.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65593.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65594.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@65595.6]
assign _T_62 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@65597.6]
assign _T_63 = _T_62[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@65598.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@65599.6]
assign _GEN_18 = {{20'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@65600.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@65600.6]
assign _T_66 = _T_65 == 26'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@65601.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@65603.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@65604.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@65605.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@65606.6]
assign _T_72 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@65607.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@65608.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@65609.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@65610.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65612.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65613.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65615.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65616.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@65617.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@65618.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@65619.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65620.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65621.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65622.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65623.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65624.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65625.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65626.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65627.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65628.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65629.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65630.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65631.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@65632.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@65633.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@65634.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65635.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65636.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65637.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65638.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65639.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65640.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65641.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65642.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65643.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65644.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65645.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65646.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65647.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65648.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65649.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65650.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65651.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65652.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65653.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65654.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65655.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@65656.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@65657.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@65658.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@65665.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@65738.6]
assign _T_201 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@65741.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@65742.8]
assign _T_203 = $signed(_T_202) & $signed(-27'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@65743.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@65744.8]
assign _T_205 = $signed(_T_204) == $signed(27'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@65745.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@65750.8]
assign _T_248 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@65788.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@65789.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@65801.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@65802.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@65808.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@65809.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@65816.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@65817.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@65823.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@65824.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@65829.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@65831.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@65832.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@65837.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@65838.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@65840.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@65841.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@65846.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@65848.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@65849.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@65855.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@65954.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@65956.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@65957.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@65980.6]
assign _T_381 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@65983.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@65991.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65994.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65995.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@66014.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@66016.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@66017.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@66022.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@66024.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@66025.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@66039.6]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@66090.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@66132.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@66133.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@66134.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@66136.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@66137.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@66143.6]
assign _T_490 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@66174.8]
assign _T_492 = _T_490 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@66176.8]
assign _T_493 = _T_492 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@66177.8]
assign _T_498 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@66191.6]
assign _T_516 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@66222.8]
assign _T_518 = _T_516 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@66224.8]
assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@66225.8]
assign _T_524 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@66239.6]
assign _T_550 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@66289.6]
assign _T_552 = _T_550 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@66291.6]
assign _T_553 = _T_552 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@66292.6]
assign _T_556 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@66299.6]
assign _T_557 = _T_556 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@66300.6]
assign _T_562 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@66305.6]
assign _T_563 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@66306.6]
assign _T_566 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@66309.6]
assign _T_567 = _T_566 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@66310.6]
assign _T_575 = _T_566 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@66318.6]
assign _T_591 = _T_557 | _T_562; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66330.6]
assign _T_592 = _T_591 | _T_563; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66331.6]
assign _T_593 = _T_592 | _T_567; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66332.6]
assign _T_594 = _T_593 | _T_575; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@66333.6]
assign _T_596 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@66335.6]
assign _T_598 = _T_594 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66338.8]
assign _T_599 = _T_598 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66339.8]
assign _T_600 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@66344.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@66346.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@66347.8]
assign _T_616 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@66377.6]
assign _T_644 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@66435.6]
assign _T_673 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@66494.6]
assign _T_690 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@66529.6]
assign _T_708 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@66565.6]
assign _T_737 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@66625.4]
assign _T_742 = _T_64[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@66630.4]
assign _T_743 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@66631.4]
assign _T_744 = _T_743 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@66632.4]
assign _T_748 = _T_747 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66635.4]
assign _T_749 = $unsigned(_T_748); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66636.4]
assign _T_750 = _T_749[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66637.4]
assign _T_751 = _T_747 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66638.4]
assign _T_769 = _T_751 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@66654.4]
assign _T_770 = io_in_a_valid & _T_769; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@66655.4]
assign _T_771 = io_in_a_bits_opcode == _T_760; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@66657.6]
assign _T_773 = _T_771 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@66659.6]
assign _T_774 = _T_773 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@66660.6]
assign _T_775 = io_in_a_bits_param == _T_762; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@66665.6]
assign _T_777 = _T_775 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@66667.6]
assign _T_778 = _T_777 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@66668.6]
assign _T_779 = io_in_a_bits_size == _T_764; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@66673.6]
assign _T_781 = _T_779 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@66675.6]
assign _T_782 = _T_781 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@66676.6]
assign _T_783 = io_in_a_bits_source == _T_766; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@66681.6]
assign _T_785 = _T_783 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@66683.6]
assign _T_786 = _T_785 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@66684.6]
assign _T_787 = io_in_a_bits_address == _T_768; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@66689.6]
assign _T_789 = _T_787 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@66691.6]
assign _T_790 = _T_789 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@66692.6]
assign _T_792 = _T_737 & _T_751; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@66699.4]
assign _T_793 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@66707.4]
assign _T_795 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@66709.4]
assign _T_796 = _T_795[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@66710.4]
assign _T_797 = ~ _T_796; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@66711.4]
assign _T_798 = _T_797[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@66712.4]
assign _T_799 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@66713.4]
assign _T_803 = _T_802 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66716.4]
assign _T_804 = $unsigned(_T_803); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66717.4]
assign _T_805 = _T_804[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66718.4]
assign _T_806 = _T_802 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66719.4]
assign _T_826 = _T_806 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@66736.4]
assign _T_827 = io_in_d_valid & _T_826; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@66737.4]
assign _T_828 = io_in_d_bits_opcode == _T_815; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@66739.6]
assign _T_830 = _T_828 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@66741.6]
assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@66742.6]
assign _T_836 = io_in_d_bits_size == _T_819; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@66755.6]
assign _T_838 = _T_836 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@66757.6]
assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@66758.6]
assign _T_840 = io_in_d_bits_source == _T_821; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@66763.6]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@66765.6]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@66766.6]
assign _T_853 = _T_793 & _T_806; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@66789.4]
assign _T_867 = _T_866 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66809.4]
assign _T_868 = $unsigned(_T_867); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66810.4]
assign _T_869 = _T_868[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66811.4]
assign _T_870 = _T_866 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66812.4]
assign _T_888 = _T_887 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66832.4]
assign _T_889 = $unsigned(_T_888); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66833.4]
assign _T_890 = _T_889[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@66834.4]
assign _T_891 = _T_887 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@66835.4]
assign _T_902 = _T_737 & _T_870; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@66850.4]
assign _T_904 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@66853.6]
assign _T_905 = _T_855 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@66855.6]
assign _T_906 = _T_905[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@66856.6]
assign _T_907 = _T_906 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@66857.6]
assign _T_909 = _T_907 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@66859.6]
assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@66860.6]
assign _GEN_15 = _T_902 ? _T_904 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@66852.4]
assign _T_915 = _T_793 & _T_891; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@66871.4]
assign _T_917 = _T_596 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@66873.4]
assign _T_918 = _T_915 & _T_917; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@66874.4]
assign _T_919 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@66876.6]
assign _T_900 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@66846.4 :freechips.rocketchip.system.LowRiscConfig.fir@66848.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@66854.6]
assign _T_920 = _T_900 | _T_855; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@66878.6]
assign _T_921 = _T_920 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@66879.6]
assign _T_922 = _T_921[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@66880.6]
assign _T_924 = _T_922 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@66882.6]
assign _T_925 = _T_924 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@66883.6]
assign _GEN_16 = _T_918 ? _T_919 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@66875.4]
assign _T_926 = _T_855 | _T_900; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@66889.4]
assign _T_912 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@66866.4 :freechips.rocketchip.system.LowRiscConfig.fir@66868.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@66877.6]
assign _T_927 = ~ _T_912; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@66890.4]
assign _T_928 = _T_926 & _T_927; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@66891.4]
assign _T_931 = _T_855 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@66896.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@66897.4]
assign _T_933 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@66898.4]
assign _T_934 = _T_932 | _T_933; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@66899.4]
assign _T_935 = _T_930 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@66900.4]
assign _T_936 = _T_934 | _T_935; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@66901.4]
assign _T_938 = _T_936 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@66903.4]
assign _T_939 = _T_938 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@66904.4]
assign _T_941 = _T_930 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@66910.4]
assign _T_944 = _T_737 | _T_793; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@66914.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@65752.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@65869.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65997.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@66056.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@66107.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@66157.10]
assign _GEN_95 = io_in_a_valid & _T_498; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@66205.10]
assign _GEN_105 = io_in_a_valid & _T_524; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@66253.10]
assign _GEN_115 = io_in_d_valid & _T_596; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66341.10]
assign _GEN_119 = io_in_d_valid & _T_616; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@66383.10]
assign _GEN_125 = io_in_d_valid & _T_644; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@66441.10]
assign _GEN_131 = io_in_d_valid & _T_673; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@66500.10]
assign _GEN_133 = io_in_d_valid & _T_690; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@66535.10]
assign _GEN_135 = io_in_d_valid & _T_708; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@66571.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_747 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_760 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_762 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_764 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_766 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_768 = _RAND_5[25:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_802 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_815 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_819 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_821 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_855 = _RAND_10[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_866 = _RAND_11[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_887 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_930 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_747 <= 3'h0;
end else begin
if (_T_737) begin
if (_T_751) begin
if (_T_744) begin
_T_747 <= _T_742;
end else begin
_T_747 <= 3'h0;
end
end else begin
_T_747 <= _T_750;
end
end
end
if (_T_792) begin
_T_760 <= io_in_a_bits_opcode;
end
if (_T_792) begin
_T_762 <= io_in_a_bits_param;
end
if (_T_792) begin
_T_764 <= io_in_a_bits_size;
end
if (_T_792) begin
_T_766 <= io_in_a_bits_source;
end
if (_T_792) begin
_T_768 <= io_in_a_bits_address;
end
if (reset) begin
_T_802 <= 3'h0;
end else begin
if (_T_793) begin
if (_T_806) begin
if (_T_799) begin
_T_802 <= _T_798;
end else begin
_T_802 <= 3'h0;
end
end else begin
_T_802 <= _T_805;
end
end
end
if (_T_853) begin
_T_815 <= io_in_d_bits_opcode;
end
if (_T_853) begin
_T_819 <= io_in_d_bits_size;
end
if (_T_853) begin
_T_821 <= io_in_d_bits_source;
end
if (reset) begin
_T_855 <= 25'h0;
end else begin
_T_855 <= _T_928;
end
if (reset) begin
_T_866 <= 3'h0;
end else begin
if (_T_737) begin
if (_T_870) begin
if (_T_744) begin
_T_866 <= _T_742;
end else begin
_T_866 <= 3'h0;
end
end else begin
_T_866 <= _T_869;
end
end
end
if (reset) begin
_T_887 <= 3'h0;
end else begin
if (_T_793) begin
if (_T_891) begin
if (_T_799) begin
_T_887 <= _T_798;
end else begin
_T_887 <= 3'h0;
end
end else begin
_T_887 <= _T_890;
end
end
end
if (reset) begin
_T_930 <= 32'h0;
end else begin
if (_T_944) begin
_T_930 <= 32'h0;
end else begin
_T_930 <= _T_941;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CLINT.scala:122:63)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@65556.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@65557.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@65735.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@65736.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@65752.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@65753.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:122:63)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@65804.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@65805.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@65811.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@65812.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:122:63)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@65819.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@65820.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@65826.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@65827.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:122:63)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@65834.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@65835.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@65843.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@65844.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@65851.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@65852.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@65869.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@65870.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:122:63)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@65921.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@65922.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@65928.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@65929.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:122:63)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@65936.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@65937.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@65943.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@65944.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:122:63)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@65951.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@65952.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:122:63)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@65959.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@65960.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@65968.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@65969.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@65976.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@65977.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65997.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@65998.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@66004.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@66005.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@66011.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@66012.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@66019.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@66020.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@66027.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@66028.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@66035.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@66036.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@66056.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@66057.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@66063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@66064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@66070.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@66071.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@66078.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@66079.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@66086.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@66087.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@66107.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@66108.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@66114.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@66115.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@66121.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@66122.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@66129.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@66130.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@66139.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@66140.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@66157.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@66158.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@66164.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@66165.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@66171.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@66172.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:122:63)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@66179.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@66180.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@66187.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@66188.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@66205.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@66206.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@66212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@66213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@66219.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@66220.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:122:63)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@66227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@66228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@66235.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@66236.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CLINT.scala:122:63)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@66253.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@66254.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@66260.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@66261.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:122:63)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@66267.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@66268.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:122:63)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@66275.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@66276.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@66283.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@66284.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:122:63)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@66294.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@66295.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66341.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@66342.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:122:63)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@66349.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@66350.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@66357.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@66358.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@66365.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@66366.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CLINT.scala:122:63)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@66373.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@66374.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@66383.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_599) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@66384.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:122:63)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@66390.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@66391.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:122:63)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@66398.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_603) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@66399.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CLINT.scala:122:63)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@66406.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@66407.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CLINT.scala:122:63)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@66414.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@66415.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@66422.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@66423.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CLINT.scala:122:63)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@66431.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@66432.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@66441.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_599) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@66442.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:122:63)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@66448.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@66449.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:122:63)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@66456.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_603) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@66457.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CLINT.scala:122:63)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@66464.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@66465.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CLINT.scala:122:63)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@66472.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@66473.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@66481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@66482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CLINT.scala:122:63)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@66490.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@66491.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@66500.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@66501.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@66508.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@66509.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@66516.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@66517.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CLINT.scala:122:63)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@66525.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@66526.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_133 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@66535.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_133 & _T_599) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@66536.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@66543.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@66544.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@66552.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@66553.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CLINT.scala:122:63)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@66561.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@66562.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@66571.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_599) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@66572.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CLINT.scala:122:63)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@66579.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@66580.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CLINT.scala:122:63)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@66587.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@66588.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CLINT.scala:122:63)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@66596.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@66597.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CLINT.scala:122:63)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@66606.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@66607.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CLINT.scala:122:63)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@66614.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@66615.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CLINT.scala:122:63)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@66622.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@66623.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_774) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@66662.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_774) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@66663.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_778) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@66670.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_778) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@66671.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_782) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@66678.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_782) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@66679.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_786) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@66686.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_786) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@66687.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_790) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@66694.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_790) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@66695.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_831) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@66744.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_831) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@66745.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@66752.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@66753.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_839) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@66760.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_839) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@66761.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@66768.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_843) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@66769.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@66776.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@66777.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CLINT.scala:122:63)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@66784.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@66785.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_902 & _T_910) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:122:63)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@66862.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_902 & _T_910) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@66863.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918 & _T_925) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:122:63)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@66885.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918 & _T_925) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@66886.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_939) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CLINT.scala:122:63)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@66906.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_939) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@66907.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Repeater_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@66919.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66920.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66921.4]
input io_repeat, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output io_full, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input [25:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output [25:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@66922.4]
);
reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.LowRiscConfig.fir@66927.4]
reg [31:0] _RAND_0;
reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_1;
reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_2;
reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_3;
reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_4;
reg [25:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_5;
reg [7:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_6;
reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@66928.4]
reg [31:0] _RAND_7;
wire _T_18; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@66931.4]
wire _T_21; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@66937.4]
wire _T_22; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@66938.4]
wire _T_23; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@66943.4]
wire _T_24; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@66944.4]
wire _T_25; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@66945.4]
assign _T_18 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@66931.4]
assign _T_21 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@66937.4]
assign _T_22 = _T_21 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@66938.4]
assign _T_23 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@66943.4]
assign _T_24 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@66944.4]
assign _T_25 = _T_23 & _T_24; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@66945.4]
assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.LowRiscConfig.fir@66936.4]
assign io_enq_ready = io_deq_ready & _T_18; // @[Repeater.scala 23:16:freechips.rocketchip.system.LowRiscConfig.fir@66933.4]
assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.LowRiscConfig.fir@66930.4]
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@66935.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
saved_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
saved_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
saved_size = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
saved_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
saved_address = _RAND_5[25:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
saved_mask = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
full <= 1'h0;
end else begin
if (_T_25) begin
full <= 1'h0;
end else begin
if (_T_22) begin
full <= 1'h1;
end
end
end
if (_T_22) begin
saved_opcode <= io_enq_bits_opcode;
end
if (_T_22) begin
saved_param <= io_enq_bits_param;
end
if (_T_22) begin
saved_size <= io_enq_bits_size;
end
if (_T_22) begin
saved_source <= io_enq_bits_source;
end
if (_T_22) begin
saved_address <= io_enq_bits_address;
end
if (_T_22) begin
saved_mask <= io_enq_bits_mask;
end
if (_T_22) begin
saved_corrupt <= io_enq_bits_corrupt;
end
end
endmodule
module TLFragmenter_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@66950.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66951.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66952.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [25:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [8:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [25:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [8:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
input [63:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@66953.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [25:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [25:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [7:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [25:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire [7:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
reg [2:0] _T_244; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.LowRiscConfig.fir@67001.4]
reg [31:0] _RAND_0;
reg [2:0] _T_246; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.LowRiscConfig.fir@67002.4]
reg [31:0] _RAND_1;
reg _T_248; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.LowRiscConfig.fir@67003.4]
reg [31:0] _RAND_2;
wire [2:0] _T_249; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@67004.4]
wire _T_250; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@67005.4]
wire _T_251; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.LowRiscConfig.fir@67006.4]
wire [3:0] _T_253; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@67008.4]
wire [5:0] _T_256; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67011.4]
wire [2:0] _T_257; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67012.4]
wire [2:0] _T_258; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67013.4]
wire _T_259; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@67014.4]
wire _T_271; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.LowRiscConfig.fir@67030.4]
wire _T_272; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.LowRiscConfig.fir@67031.4]
wire [5:0] _GEN_7; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@67032.4]
wire [5:0] _T_273; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@67032.4]
wire [5:0] _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@67033.4]
wire [5:0] _T_274; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@67033.4]
wire [6:0] _GEN_9; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@67034.4]
wire [6:0] _T_275; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@67034.4]
wire [6:0] _T_276; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@67035.4]
wire [6:0] _T_277; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67036.4]
wire [6:0] _T_278; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@67037.4]
wire [6:0] _T_279; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@67038.4]
wire [2:0] _T_280; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@67039.4]
wire [3:0] _T_281; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@67040.4]
wire _T_282; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@67041.4]
wire [3:0] _GEN_10; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@67042.4]
wire [3:0] _T_283; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@67042.4]
wire [1:0] _T_284; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@67043.4]
wire [1:0] _T_285; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@67044.4]
wire _T_286; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@67045.4]
wire [1:0] _T_287; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@67046.4]
wire _T_288; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@67047.4]
wire [2:0] _T_290; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67049.4]
wire _T_297; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.LowRiscConfig.fir@67063.4]
wire _T_299; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.LowRiscConfig.fir@67065.4]
wire _T_300; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.LowRiscConfig.fir@67066.4]
wire _T_301; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.LowRiscConfig.fir@67067.4]
wire _T_291; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@67050.4]
wire [2:0] _GEN_11; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67052.6]
wire [3:0] _T_292; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67052.6]
wire [3:0] _T_293; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67053.6]
wire [2:0] _T_294; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67054.6]
wire _T_296; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@67059.8]
wire _T_302; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.LowRiscConfig.fir@67069.4]
wire _T_330; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@67102.4]
wire [2:0] _T_331; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@67103.4]
wire [12:0] _T_333; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67105.4]
wire [5:0] _T_334; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67106.4]
wire [5:0] _T_335; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67107.4]
wire [9:0] _T_337; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67109.4]
wire [2:0] _T_338; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67110.4]
wire [2:0] _T_339; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67111.4]
wire _T_340; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@67112.4]
wire _T_341; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@67113.4]
reg [2:0] _T_344; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.LowRiscConfig.fir@67115.4]
reg [31:0] _RAND_3;
wire _T_345; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@67116.4]
wire [2:0] _T_346; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@67117.4]
wire [3:0] _T_347; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@67118.4]
wire [3:0] _T_348; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@67119.4]
wire [2:0] _T_349; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@67120.4]
wire [2:0] _T_350; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@67121.4]
wire [2:0] _T_351; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@67122.4]
wire [2:0] _T_354; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@67125.4]
reg _T_362; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@67132.4]
reg [31:0] _RAND_4;
wire _GEN_5; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@67133.4]
wire _T_364; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@67137.4]
wire _T_92_a_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@66997.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@67146.4]
wire _T_365; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@67138.4]
wire _T_366; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.LowRiscConfig.fir@67142.4]
wire _T_367; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.LowRiscConfig.fir@67143.4]
wire [5:0] _GEN_12; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@67147.4]
wire [5:0] _T_369; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@67147.4]
wire [5:0] _T_370; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@67148.4]
wire [5:0] _T_371; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@67149.4]
wire [5:0] _GEN_13; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@67150.4]
wire [5:0] _T_372; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@67150.4]
wire [5:0] _T_373; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@67151.4]
wire [5:0] _T_374; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@67152.4]
wire [25:0] _GEN_14; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@67153.4]
wire [5:0] _T_376; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67155.4]
wire _T_378; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@67159.4]
wire _T_380; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.LowRiscConfig.fir@67161.4]
wire _T_382; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@67163.4]
wire _T_383; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@67164.4]
wire _T_385; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@67171.4]
wire _T_386; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@67172.4]
wire _T_388; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@67174.4]
wire _T_389; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@67175.4]
TLMonitor_27 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@66960.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source)
);
Repeater_1 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@67077.4]
.clock(Repeater_clock),
.reset(Repeater_reset),
.io_repeat(Repeater_io_repeat),
.io_full(Repeater_io_full),
.io_enq_ready(Repeater_io_enq_ready),
.io_enq_valid(Repeater_io_enq_valid),
.io_enq_bits_opcode(Repeater_io_enq_bits_opcode),
.io_enq_bits_param(Repeater_io_enq_bits_param),
.io_enq_bits_size(Repeater_io_enq_bits_size),
.io_enq_bits_source(Repeater_io_enq_bits_source),
.io_enq_bits_address(Repeater_io_enq_bits_address),
.io_enq_bits_mask(Repeater_io_enq_bits_mask),
.io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt),
.io_deq_ready(Repeater_io_deq_ready),
.io_deq_valid(Repeater_io_deq_valid),
.io_deq_bits_opcode(Repeater_io_deq_bits_opcode),
.io_deq_bits_param(Repeater_io_deq_bits_param),
.io_deq_bits_size(Repeater_io_deq_bits_size),
.io_deq_bits_source(Repeater_io_deq_bits_source),
.io_deq_bits_address(Repeater_io_deq_bits_address),
.io_deq_bits_mask(Repeater_io_deq_bits_mask),
.io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt)
);
assign _T_249 = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@67004.4]
assign _T_250 = _T_244 == 3'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@67005.4]
assign _T_251 = _T_249 == 3'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.LowRiscConfig.fir@67006.4]
assign _T_253 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@67008.4]
assign _T_256 = 6'h7 << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67011.4]
assign _T_257 = _T_256[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67012.4]
assign _T_258 = ~ _T_257; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67013.4]
assign _T_259 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@67014.4]
assign _T_271 = _T_253[3:3]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.LowRiscConfig.fir@67030.4]
assign _T_272 = _T_259 ? 1'h1 : _T_271; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.LowRiscConfig.fir@67031.4]
assign _GEN_7 = {{3'd0}, _T_249}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@67032.4]
assign _T_273 = _GEN_7 << 3; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@67032.4]
assign _GEN_8 = {{3'd0}, _T_258}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@67033.4]
assign _T_274 = _T_273 | _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@67033.4]
assign _GEN_9 = {{1'd0}, _T_274}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@67034.4]
assign _T_275 = _GEN_9 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@67034.4]
assign _T_276 = _T_275 | 7'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@67035.4]
assign _T_277 = {1'h0,_T_274}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67036.4]
assign _T_278 = ~ _T_277; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@67037.4]
assign _T_279 = _T_276 & _T_278; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@67038.4]
assign _T_280 = _T_279[6:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@67039.4]
assign _T_281 = _T_279[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@67040.4]
assign _T_282 = _T_280 != 3'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@67041.4]
assign _GEN_10 = {{1'd0}, _T_280}; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@67042.4]
assign _T_283 = _GEN_10 | _T_281; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@67042.4]
assign _T_284 = _T_283[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@67043.4]
assign _T_285 = _T_283[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@67044.4]
assign _T_286 = _T_284 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@67045.4]
assign _T_287 = _T_284 | _T_285; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@67046.4]
assign _T_288 = _T_287[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@67047.4]
assign _T_290 = {_T_282,_T_286,_T_288}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67049.4]
assign _T_297 = _T_259 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.LowRiscConfig.fir@67063.4]
assign _T_299 = _T_251 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.LowRiscConfig.fir@67065.4]
assign _T_300 = _T_297 & _T_299; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.LowRiscConfig.fir@67066.4]
assign _T_301 = auto_in_d_ready | _T_300; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.LowRiscConfig.fir@67067.4]
assign _T_291 = _T_301 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@67050.4]
assign _GEN_11 = {{2'd0}, _T_272}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67052.6]
assign _T_292 = _T_244 - _GEN_11; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67052.6]
assign _T_293 = $unsigned(_T_292); // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67053.6]
assign _T_294 = _T_293[2:0]; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@67054.6]
assign _T_296 = auto_out_d_bits_source[3]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@67059.8]
assign _T_302 = _T_300 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.LowRiscConfig.fir@67069.4]
assign _T_330 = Repeater_io_deq_bits_size > 3'h3; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@67102.4]
assign _T_331 = _T_330 ? 3'h3 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@67103.4]
assign _T_333 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67105.4]
assign _T_334 = _T_333[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67106.4]
assign _T_335 = ~ _T_334; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67107.4]
assign _T_337 = 10'h7 << _T_331; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67109.4]
assign _T_338 = _T_337[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67110.4]
assign _T_339 = ~ _T_338; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67111.4]
assign _T_340 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@67112.4]
assign _T_341 = _T_340 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@67113.4]
assign _T_345 = _T_344 == 3'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@67116.4]
assign _T_346 = _T_335[5:3]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@67117.4]
assign _T_347 = _T_344 - 3'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@67118.4]
assign _T_348 = $unsigned(_T_347); // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@67119.4]
assign _T_349 = _T_348[2:0]; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@67120.4]
assign _T_350 = _T_345 ? _T_346 : _T_349; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@67121.4]
assign _T_351 = ~ _T_350; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@67122.4]
assign _T_354 = ~ _T_351; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@67125.4]
assign _GEN_5 = _T_345 ? _T_248 : _T_362; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@67133.4]
assign _T_364 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@67137.4]
assign _T_92_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@66997.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@67146.4]
assign _T_365 = auto_out_a_ready & _T_92_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@67138.4]
assign _T_366 = _T_341 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.LowRiscConfig.fir@67142.4]
assign _T_367 = _T_354 != 3'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.LowRiscConfig.fir@67143.4]
assign _GEN_12 = {{3'd0}, _T_350}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@67147.4]
assign _T_369 = _GEN_12 << 3; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@67147.4]
assign _T_370 = ~ _T_335; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@67148.4]
assign _T_371 = _T_369 | _T_370; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@67149.4]
assign _GEN_13 = {{3'd0}, _T_339}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@67150.4]
assign _T_372 = _T_371 | _GEN_13; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@67150.4]
assign _T_373 = _T_372 | 6'h7; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@67151.4]
assign _T_374 = ~ _T_373; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@67152.4]
assign _GEN_14 = {{20'd0}, _T_374}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@67153.4]
assign _T_376 = {Repeater_io_deq_bits_source,_T_364}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67155.4]
assign _T_378 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@67159.4]
assign _T_380 = _T_378 | _T_366; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.LowRiscConfig.fir@67161.4]
assign _T_382 = _T_380 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@67163.4]
assign _T_383 = _T_382 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@67164.4]
assign _T_385 = Repeater_io_deq_bits_mask == 8'hff; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@67171.4]
assign _T_386 = _T_378 | _T_385; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@67172.4]
assign _T_388 = _T_386 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@67174.4]
assign _T_389 = _T_388 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@67175.4]
assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67000.4]
assign auto_in_d_valid = auto_out_d_valid & _T_302; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67000.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67000.4]
assign auto_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67000.4]
assign auto_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67000.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67000.4]
assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_size = _T_331[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_source = {_T_376,_T_354}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_14; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_mask = Repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign auto_out_d_ready = auto_in_d_ready | _T_300; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@66999.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@66962.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@66963.4]
assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_302; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@66996.4]
assign Repeater_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@67079.4]
assign Repeater_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@67080.4]
assign Repeater_io_repeat = _T_366 & _T_367; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.LowRiscConfig.fir@67145.4]
assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@67081.4]
assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@67146.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_244 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_246 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_248 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_344 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_362 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_244 <= 3'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_244 <= _T_249;
end else begin
_T_244 <= _T_294;
end
end
end
if (_T_291) begin
if (_T_250) begin
_T_246 <= _T_290;
end
end
if (reset) begin
_T_248 <= 1'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_248 <= _T_296;
end
end
end
if (reset) begin
_T_344 <= 3'h0;
end else begin
if (_T_365) begin
_T_344 <= _T_354;
end
end
if (_T_345) begin
_T_362 <= _T_248;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:183 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"); // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@67025.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@67026.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_383) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@67166.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_383) begin
$fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@67167.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_389) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@67177.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_389) begin
$fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@67178.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module SimpleLazyModule_10( // @[:freechips.rocketchip.system.LowRiscConfig.fir@67189.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67190.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67191.4]
output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [25:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [7:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [63:0] auto_fragmenter_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [2:0] auto_fragmenter_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [63:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [8:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [25:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [7:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output [63:0] auto_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [2:0] auto_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [8:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
input [63:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@67192.4]
);
wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [25:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [8:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [25:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [8:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
TLFragmenter_1 fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@67197.4]
.clock(fragmenter_clock),
.reset(fragmenter_reset),
.auto_in_a_ready(fragmenter_auto_in_a_ready),
.auto_in_a_valid(fragmenter_auto_in_a_valid),
.auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
.auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
.auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
.auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
.auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
.auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
.auto_in_d_ready(fragmenter_auto_in_d_ready),
.auto_in_d_valid(fragmenter_auto_in_d_valid),
.auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
.auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
.auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
.auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
.auto_out_a_ready(fragmenter_auto_out_a_ready),
.auto_out_a_valid(fragmenter_auto_out_a_valid),
.auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
.auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
.auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
.auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
.auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
.auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
.auto_out_d_ready(fragmenter_auto_out_d_ready),
.auto_out_d_valid(fragmenter_auto_out_d_valid),
.auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
.auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
.auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
.auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
);
assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign auto_fragmenter_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@67201.4]
assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@67202.4]
assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_data = auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@67204.4]
assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@67203.4]
endmodule
module TLMonitor_28( // @[:freechips.rocketchip.system.LowRiscConfig.fir@67213.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67214.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67215.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [11:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@67216.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@68566.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67233.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67234.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67239.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67240.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67243.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67244.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67252.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67264.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67265.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67266.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67267.6]
wire [12:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67269.6]
wire [5:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67270.6]
wire [5:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67271.6]
wire [11:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@67272.6]
wire [11:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@67272.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@67273.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@67275.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@67276.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@67277.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@67278.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@67279.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@67280.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@67281.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@67282.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67284.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67285.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67287.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67288.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@67289.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@67290.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@67291.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67292.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67293.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67294.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67295.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67296.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67297.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67298.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67299.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67300.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67301.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67302.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67303.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@67304.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@67305.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@67306.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67307.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67308.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67309.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67310.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67311.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67312.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67313.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67314.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67315.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67316.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67317.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67318.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67319.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67320.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67321.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67322.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67323.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67324.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67325.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67326.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67327.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67328.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67329.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67330.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67337.6]
wire [12:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@67348.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@67410.6]
wire [12:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@67415.8]
wire [12:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@67416.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@67417.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@67422.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@67460.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@67461.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@67473.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@67474.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@67480.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@67481.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@67488.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@67489.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@67495.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@67496.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@67501.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@67503.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@67504.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@67509.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@67510.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@67512.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@67513.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@67518.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@67520.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@67521.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@67527.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@67626.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@67628.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@67629.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@67652.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@67655.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@67663.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67666.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67667.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@67686.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@67688.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@67689.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@67694.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@67696.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@67697.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@67711.6]
wire _T_441; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@67762.6]
wire [7:0] _T_466; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@67804.8]
wire [7:0] _T_467; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@67805.8]
wire _T_468; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@67806.8]
wire _T_470; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@67808.8]
wire _T_471; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@67809.8]
wire _T_472; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@67815.6]
wire _T_490; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@67846.8]
wire _T_492; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@67848.8]
wire _T_493; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@67849.8]
wire _T_498; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@67863.6]
wire _T_516; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@67894.8]
wire _T_518; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@67896.8]
wire _T_519; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@67897.8]
wire _T_524; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@67911.6]
wire _T_550; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@67961.6]
wire _T_552; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@67963.6]
wire _T_553; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@67964.6]
wire [2:0] _T_556; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67971.6]
wire _T_557; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67972.6]
wire _T_562; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67977.6]
wire _T_563; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67978.6]
wire [1:0] _T_566; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67981.6]
wire _T_567; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67982.6]
wire _T_575; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67990.6]
wire _T_591; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68002.6]
wire _T_592; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68003.6]
wire _T_593; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68004.6]
wire _T_594; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68005.6]
wire _T_596; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@68007.6]
wire _T_598; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68010.8]
wire _T_599; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68011.8]
wire _T_600; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@68016.8]
wire _T_602; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@68018.8]
wire _T_603; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@68019.8]
wire _T_616; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@68049.6]
wire _T_644; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@68107.6]
wire _T_673; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@68166.6]
wire _T_690; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@68201.6]
wire _T_708; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@68237.6]
wire _T_737; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@68297.4]
wire [2:0] _T_742; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@68302.4]
wire _T_743; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@68303.4]
wire _T_744; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@68304.4]
reg [2:0] _T_747; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@68306.4]
reg [31:0] _RAND_0;
wire [3:0] _T_748; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68307.4]
wire [3:0] _T_749; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68308.4]
wire [2:0] _T_750; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68309.4]
wire _T_751; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68310.4]
reg [2:0] _T_760; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@68321.4]
reg [31:0] _RAND_1;
reg [2:0] _T_762; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@68322.4]
reg [31:0] _RAND_2;
reg [2:0] _T_764; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@68323.4]
reg [31:0] _RAND_3;
reg [4:0] _T_766; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@68324.4]
reg [31:0] _RAND_4;
reg [11:0] _T_768; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@68325.4]
reg [31:0] _RAND_5;
wire _T_769; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@68326.4]
wire _T_770; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@68327.4]
wire _T_771; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@68329.6]
wire _T_773; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@68331.6]
wire _T_774; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@68332.6]
wire _T_775; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@68337.6]
wire _T_777; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@68339.6]
wire _T_778; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@68340.6]
wire _T_779; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@68345.6]
wire _T_781; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@68347.6]
wire _T_782; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@68348.6]
wire _T_783; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@68353.6]
wire _T_785; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@68355.6]
wire _T_786; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@68356.6]
wire _T_787; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@68361.6]
wire _T_789; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@68363.6]
wire _T_790; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@68364.6]
wire _T_792; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@68371.4]
wire _T_793; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@68379.4]
wire [12:0] _T_795; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68381.4]
wire [5:0] _T_796; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68382.4]
wire [5:0] _T_797; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68383.4]
wire [2:0] _T_798; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@68384.4]
wire _T_799; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@68385.4]
reg [2:0] _T_802; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@68387.4]
reg [31:0] _RAND_6;
wire [3:0] _T_803; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68388.4]
wire [3:0] _T_804; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68389.4]
wire [2:0] _T_805; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68390.4]
wire _T_806; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68391.4]
reg [2:0] _T_815; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@68402.4]
reg [31:0] _RAND_7;
reg [2:0] _T_819; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@68404.4]
reg [31:0] _RAND_8;
reg [4:0] _T_821; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@68405.4]
reg [31:0] _RAND_9;
wire _T_826; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@68408.4]
wire _T_827; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@68409.4]
wire _T_828; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@68411.6]
wire _T_830; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@68413.6]
wire _T_831; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@68414.6]
wire _T_836; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@68427.6]
wire _T_838; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@68429.6]
wire _T_839; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@68430.6]
wire _T_840; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@68435.6]
wire _T_842; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@68437.6]
wire _T_843; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@68438.6]
wire _T_853; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@68461.4]
reg [24:0] _T_855; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@68470.4]
reg [31:0] _RAND_10;
reg [2:0] _T_866; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@68480.4]
reg [31:0] _RAND_11;
wire [3:0] _T_867; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68481.4]
wire [3:0] _T_868; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68482.4]
wire [2:0] _T_869; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68483.4]
wire _T_870; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68484.4]
reg [2:0] _T_887; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@68503.4]
reg [31:0] _RAND_12;
wire [3:0] _T_888; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68504.4]
wire [3:0] _T_889; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68505.4]
wire [2:0] _T_890; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68506.4]
wire _T_891; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68507.4]
wire _T_902; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@68522.4]
wire [31:0] _T_904; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@68525.6]
wire [24:0] _T_905; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@68527.6]
wire _T_906; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@68528.6]
wire _T_907; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@68529.6]
wire _T_909; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@68531.6]
wire _T_910; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@68532.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@68524.4]
wire _T_915; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@68543.4]
wire _T_917; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@68545.4]
wire _T_918; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@68546.4]
wire [31:0] _T_919; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@68548.6]
wire [24:0] _T_900; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68518.4 :freechips.rocketchip.system.LowRiscConfig.fir@68520.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@68526.6]
wire [24:0] _T_920; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@68550.6]
wire [24:0] _T_921; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@68551.6]
wire _T_922; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@68552.6]
wire _T_924; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@68554.6]
wire _T_925; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@68555.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@68547.4]
wire [24:0] _T_926; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@68561.4]
wire [24:0] _T_912; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68538.4 :freechips.rocketchip.system.LowRiscConfig.fir@68540.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@68549.6]
wire [24:0] _T_927; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@68562.4]
wire [24:0] _T_928; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@68563.4]
reg [31:0] _T_930; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@68565.4]
reg [31:0] _RAND_13;
wire _T_931; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@68568.4]
wire _T_932; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@68569.4]
wire _T_933; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@68570.4]
wire _T_934; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@68571.4]
wire _T_935; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@68572.4]
wire _T_936; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@68573.4]
wire _T_938; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@68575.4]
wire _T_939; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@68576.4]
wire [31:0] _T_941; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@68582.4]
wire _T_944; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@68586.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@67424.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@67541.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67669.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@67728.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@67779.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@67829.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@67877.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@67925.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68013.10]
wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@68055.10]
wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@68113.10]
wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@68172.10]
wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@68207.10]
wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@68243.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@68566.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67233.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67234.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67239.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67240.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67243.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67244.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67252.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67264.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67265.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67266.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@67267.6]
assign _T_62 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@67269.6]
assign _T_63 = _T_62[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@67270.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@67271.6]
assign _GEN_18 = {{6'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@67272.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@67272.6]
assign _T_66 = _T_65 == 12'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@67273.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@67275.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@67276.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@67277.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@67278.6]
assign _T_72 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@67279.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@67280.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@67281.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@67282.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67284.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67285.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67287.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67288.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@67289.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@67290.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@67291.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67292.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67293.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67294.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67295.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67296.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67297.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67298.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67299.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67300.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67301.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67302.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67303.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@67304.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@67305.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@67306.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67307.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67308.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67309.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67310.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67311.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67312.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67313.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67314.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67315.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67316.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67317.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67318.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67319.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67320.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67321.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67322.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67323.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67324.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67325.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67326.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67327.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@67328.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@67329.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@67330.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@67337.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@67348.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@67410.6]
assign _T_203 = $signed(_T_141) & $signed(-13'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@67415.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@67416.8]
assign _T_205 = $signed(_T_204) == $signed(13'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@67417.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@67422.8]
assign _T_248 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@67460.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@67461.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@67473.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@67474.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@67480.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@67481.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@67488.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@67489.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@67495.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@67496.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@67501.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@67503.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@67504.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@67509.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@67510.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@67512.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@67513.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@67518.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@67520.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@67521.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@67527.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@67626.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@67628.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@67629.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@67652.6]
assign _T_381 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@67655.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@67663.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67666.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67667.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@67686.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@67688.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@67689.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@67694.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@67696.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@67697.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@67711.6]
assign _T_441 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@67762.6]
assign _T_466 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@67804.8]
assign _T_467 = io_in_a_bits_mask & _T_466; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@67805.8]
assign _T_468 = _T_467 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@67806.8]
assign _T_470 = _T_468 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@67808.8]
assign _T_471 = _T_470 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@67809.8]
assign _T_472 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@67815.6]
assign _T_490 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@67846.8]
assign _T_492 = _T_490 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@67848.8]
assign _T_493 = _T_492 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@67849.8]
assign _T_498 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@67863.6]
assign _T_516 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@67894.8]
assign _T_518 = _T_516 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@67896.8]
assign _T_519 = _T_518 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@67897.8]
assign _T_524 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@67911.6]
assign _T_550 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@67961.6]
assign _T_552 = _T_550 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@67963.6]
assign _T_553 = _T_552 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@67964.6]
assign _T_556 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67971.6]
assign _T_557 = _T_556 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67972.6]
assign _T_562 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67977.6]
assign _T_563 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@67978.6]
assign _T_566 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@67981.6]
assign _T_567 = _T_566 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67982.6]
assign _T_575 = _T_566 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@67990.6]
assign _T_591 = _T_557 | _T_562; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68002.6]
assign _T_592 = _T_591 | _T_563; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68003.6]
assign _T_593 = _T_592 | _T_567; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68004.6]
assign _T_594 = _T_593 | _T_575; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68005.6]
assign _T_596 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@68007.6]
assign _T_598 = _T_594 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68010.8]
assign _T_599 = _T_598 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68011.8]
assign _T_600 = io_in_d_bits_size >= 3'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@68016.8]
assign _T_602 = _T_600 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@68018.8]
assign _T_603 = _T_602 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@68019.8]
assign _T_616 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@68049.6]
assign _T_644 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@68107.6]
assign _T_673 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@68166.6]
assign _T_690 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@68201.6]
assign _T_708 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@68237.6]
assign _T_737 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@68297.4]
assign _T_742 = _T_64[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@68302.4]
assign _T_743 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@68303.4]
assign _T_744 = _T_743 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@68304.4]
assign _T_748 = _T_747 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68307.4]
assign _T_749 = $unsigned(_T_748); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68308.4]
assign _T_750 = _T_749[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68309.4]
assign _T_751 = _T_747 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68310.4]
assign _T_769 = _T_751 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@68326.4]
assign _T_770 = io_in_a_valid & _T_769; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@68327.4]
assign _T_771 = io_in_a_bits_opcode == _T_760; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@68329.6]
assign _T_773 = _T_771 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@68331.6]
assign _T_774 = _T_773 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@68332.6]
assign _T_775 = io_in_a_bits_param == _T_762; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@68337.6]
assign _T_777 = _T_775 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@68339.6]
assign _T_778 = _T_777 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@68340.6]
assign _T_779 = io_in_a_bits_size == _T_764; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@68345.6]
assign _T_781 = _T_779 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@68347.6]
assign _T_782 = _T_781 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@68348.6]
assign _T_783 = io_in_a_bits_source == _T_766; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@68353.6]
assign _T_785 = _T_783 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@68355.6]
assign _T_786 = _T_785 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@68356.6]
assign _T_787 = io_in_a_bits_address == _T_768; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@68361.6]
assign _T_789 = _T_787 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@68363.6]
assign _T_790 = _T_789 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@68364.6]
assign _T_792 = _T_737 & _T_751; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@68371.4]
assign _T_793 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@68379.4]
assign _T_795 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68381.4]
assign _T_796 = _T_795[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68382.4]
assign _T_797 = ~ _T_796; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68383.4]
assign _T_798 = _T_797[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@68384.4]
assign _T_799 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@68385.4]
assign _T_803 = _T_802 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68388.4]
assign _T_804 = $unsigned(_T_803); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68389.4]
assign _T_805 = _T_804[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68390.4]
assign _T_806 = _T_802 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68391.4]
assign _T_826 = _T_806 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@68408.4]
assign _T_827 = io_in_d_valid & _T_826; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@68409.4]
assign _T_828 = io_in_d_bits_opcode == _T_815; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@68411.6]
assign _T_830 = _T_828 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@68413.6]
assign _T_831 = _T_830 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@68414.6]
assign _T_836 = io_in_d_bits_size == _T_819; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@68427.6]
assign _T_838 = _T_836 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@68429.6]
assign _T_839 = _T_838 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@68430.6]
assign _T_840 = io_in_d_bits_source == _T_821; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@68435.6]
assign _T_842 = _T_840 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@68437.6]
assign _T_843 = _T_842 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@68438.6]
assign _T_853 = _T_793 & _T_806; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@68461.4]
assign _T_867 = _T_866 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68481.4]
assign _T_868 = $unsigned(_T_867); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68482.4]
assign _T_869 = _T_868[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68483.4]
assign _T_870 = _T_866 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68484.4]
assign _T_888 = _T_887 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68504.4]
assign _T_889 = $unsigned(_T_888); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68505.4]
assign _T_890 = _T_889[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@68506.4]
assign _T_891 = _T_887 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@68507.4]
assign _T_902 = _T_737 & _T_870; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@68522.4]
assign _T_904 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@68525.6]
assign _T_905 = _T_855 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@68527.6]
assign _T_906 = _T_905[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@68528.6]
assign _T_907 = _T_906 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@68529.6]
assign _T_909 = _T_907 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@68531.6]
assign _T_910 = _T_909 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@68532.6]
assign _GEN_15 = _T_902 ? _T_904 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@68524.4]
assign _T_915 = _T_793 & _T_891; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@68543.4]
assign _T_917 = _T_596 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@68545.4]
assign _T_918 = _T_915 & _T_917; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@68546.4]
assign _T_919 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@68548.6]
assign _T_900 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68518.4 :freechips.rocketchip.system.LowRiscConfig.fir@68520.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@68526.6]
assign _T_920 = _T_900 | _T_855; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@68550.6]
assign _T_921 = _T_920 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@68551.6]
assign _T_922 = _T_921[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@68552.6]
assign _T_924 = _T_922 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@68554.6]
assign _T_925 = _T_924 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@68555.6]
assign _GEN_16 = _T_918 ? _T_919 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@68547.4]
assign _T_926 = _T_855 | _T_900; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@68561.4]
assign _T_912 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68538.4 :freechips.rocketchip.system.LowRiscConfig.fir@68540.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@68549.6]
assign _T_927 = ~ _T_912; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@68562.4]
assign _T_928 = _T_926 & _T_927; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@68563.4]
assign _T_931 = _T_855 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@68568.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@68569.4]
assign _T_933 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@68570.4]
assign _T_934 = _T_932 | _T_933; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@68571.4]
assign _T_935 = _T_930 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@68572.4]
assign _T_936 = _T_934 | _T_935; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@68573.4]
assign _T_938 = _T_936 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@68575.4]
assign _T_939 = _T_938 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@68576.4]
assign _T_941 = _T_930 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@68582.4]
assign _T_944 = _T_737 | _T_793; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@68586.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@67424.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@67541.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67669.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@67728.10]
assign _GEN_75 = io_in_a_valid & _T_441; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@67779.10]
assign _GEN_85 = io_in_a_valid & _T_472; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@67829.10]
assign _GEN_95 = io_in_a_valid & _T_498; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@67877.10]
assign _GEN_105 = io_in_a_valid & _T_524; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@67925.10]
assign _GEN_115 = io_in_d_valid & _T_596; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68013.10]
assign _GEN_119 = io_in_d_valid & _T_616; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@68055.10]
assign _GEN_125 = io_in_d_valid & _T_644; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@68113.10]
assign _GEN_131 = io_in_d_valid & _T_673; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@68172.10]
assign _GEN_133 = io_in_d_valid & _T_690; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@68207.10]
assign _GEN_135 = io_in_d_valid & _T_708; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@68243.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_747 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_760 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_762 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_764 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_766 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_768 = _RAND_5[11:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_802 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_815 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_819 = _RAND_8[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_821 = _RAND_9[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_855 = _RAND_10[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_866 = _RAND_11[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_887 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_930 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_747 <= 3'h0;
end else begin
if (_T_737) begin
if (_T_751) begin
if (_T_744) begin
_T_747 <= _T_742;
end else begin
_T_747 <= 3'h0;
end
end else begin
_T_747 <= _T_750;
end
end
end
if (_T_792) begin
_T_760 <= io_in_a_bits_opcode;
end
if (_T_792) begin
_T_762 <= io_in_a_bits_param;
end
if (_T_792) begin
_T_764 <= io_in_a_bits_size;
end
if (_T_792) begin
_T_766 <= io_in_a_bits_source;
end
if (_T_792) begin
_T_768 <= io_in_a_bits_address;
end
if (reset) begin
_T_802 <= 3'h0;
end else begin
if (_T_793) begin
if (_T_806) begin
if (_T_799) begin
_T_802 <= _T_798;
end else begin
_T_802 <= 3'h0;
end
end else begin
_T_802 <= _T_805;
end
end
end
if (_T_853) begin
_T_815 <= io_in_d_bits_opcode;
end
if (_T_853) begin
_T_819 <= io_in_d_bits_size;
end
if (_T_853) begin
_T_821 <= io_in_d_bits_source;
end
if (reset) begin
_T_855 <= 25'h0;
end else begin
_T_855 <= _T_928;
end
if (reset) begin
_T_866 <= 3'h0;
end else begin
if (_T_737) begin
if (_T_870) begin
if (_T_744) begin
_T_866 <= _T_742;
end else begin
_T_866 <= 3'h0;
end
end else begin
_T_866 <= _T_869;
end
end
end
if (reset) begin
_T_887 <= 3'h0;
end else begin
if (_T_793) begin
if (_T_891) begin
if (_T_799) begin
_T_887 <= _T_798;
end else begin
_T_887 <= 3'h0;
end
end else begin
_T_887 <= _T_890;
end
end
end
if (reset) begin
_T_930 <= 32'h0;
end else begin
if (_T_944) begin
_T_930 <= 32'h0;
end else begin
_T_930 <= _T_941;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Periphery.scala:35:60)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@67228.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@67229.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@67407.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@67408.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@67424.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@67425.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Periphery.scala:35:60)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@67476.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@67477.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@67483.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@67484.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Periphery.scala:35:60)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@67491.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@67492.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@67498.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@67499.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Periphery.scala:35:60)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@67506.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@67507.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@67515.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@67516.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@67523.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@67524.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@67541.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@67542.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Periphery.scala:35:60)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@67593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@67594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@67600.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@67601.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Periphery.scala:35:60)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@67608.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@67609.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@67615.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@67616.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Periphery.scala:35:60)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@67623.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@67624.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Periphery.scala:35:60)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@67631.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@67632.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@67640.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@67641.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@67648.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@67649.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67669.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@67670.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@67676.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@67677.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@67683.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@67684.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@67691.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@67692.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@67699.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@67700.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@67707.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@67708.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@67728.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_393) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@67729.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@67735.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@67736.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@67742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@67743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@67750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@67751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@67758.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@67759.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@67779.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_393) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@67780.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@67786.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@67787.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@67793.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@67794.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@67801.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@67802.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@67811.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_471) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@67812.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@67829.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@67830.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@67836.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@67837.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@67843.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@67844.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Periphery.scala:35:60)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@67851.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_493) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@67852.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@67859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@67860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@67877.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@67878.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@67884.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@67885.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@67891.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@67892.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Periphery.scala:35:60)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@67899.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_519) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@67900.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@67907.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@67908.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Periphery.scala:35:60)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@67925.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@67926.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@67932.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@67933.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Periphery.scala:35:60)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@67939.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@67940.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Periphery.scala:35:60)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@67947.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@67948.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@67955.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@67956.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Periphery.scala:35:60)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@67966.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_553) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@67967.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68013.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_599) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@68014.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Periphery.scala:35:60)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@68021.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_603) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@68022.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@68029.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@68030.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@68037.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@68038.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Periphery.scala:35:60)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@68045.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@68046.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@68055.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_599) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@68056.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Periphery.scala:35:60)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@68062.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_210) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@68063.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Periphery.scala:35:60)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@68070.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_603) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@68071.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Periphery.scala:35:60)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@68078.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@68079.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Periphery.scala:35:60)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@68086.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@68087.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@68094.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@68095.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Periphery.scala:35:60)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@68103.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@68104.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@68113.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_599) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@68114.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Periphery.scala:35:60)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@68120.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_210) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@68121.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_603) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Periphery.scala:35:60)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@68128.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_603) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@68129.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Periphery.scala:35:60)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@68136.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@68137.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Periphery.scala:35:60)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@68144.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@68145.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@68153.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@68154.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Periphery.scala:35:60)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@68162.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@68163.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@68172.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_599) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@68173.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@68180.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@68181.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@68188.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@68189.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Periphery.scala:35:60)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@68197.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@68198.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_133 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@68207.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_133 & _T_599) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@68208.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@68215.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@68216.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@68224.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@68225.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Periphery.scala:35:60)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@68233.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@68234.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_599) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@68243.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_599) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@68244.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Periphery.scala:35:60)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@68251.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@68252.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Periphery.scala:35:60)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@68259.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@68260.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Periphery.scala:35:60)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@68268.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@68269.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Periphery.scala:35:60)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@68278.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@68279.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Periphery.scala:35:60)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@68286.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@68287.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Periphery.scala:35:60)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@68294.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@68295.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_774) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@68334.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_774) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@68335.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_778) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@68342.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_778) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@68343.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_782) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@68350.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_782) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@68351.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_786) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@68358.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_786) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@68359.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_770 & _T_790) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@68366.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_770 & _T_790) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@68367.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_831) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@68416.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_831) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@68417.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@68424.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@68425.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_839) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@68432.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_839) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@68433.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_827 & _T_843) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@68440.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_827 & _T_843) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@68441.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@68448.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@68449.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Periphery.scala:35:60)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@68456.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@68457.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_902 & _T_910) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Periphery.scala:35:60)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@68534.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_902 & _T_910) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@68535.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918 & _T_925) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Periphery.scala:35:60)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@68557.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918 & _T_925) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@68558.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_939) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Periphery.scala:35:60)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@68578.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_939) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@68579.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Repeater_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@68591.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68592.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68593.4]
input io_repeat, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output io_full, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input [11:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output [11:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@68594.4]
);
reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.LowRiscConfig.fir@68599.4]
reg [31:0] _RAND_0;
reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_1;
reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_2;
reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_3;
reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_4;
reg [11:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_5;
reg [7:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_6;
reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@68600.4]
reg [31:0] _RAND_7;
wire _T_18; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@68603.4]
wire _T_21; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68609.4]
wire _T_22; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@68610.4]
wire _T_23; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68615.4]
wire _T_24; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@68616.4]
wire _T_25; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@68617.4]
assign _T_18 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@68603.4]
assign _T_21 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68609.4]
assign _T_22 = _T_21 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@68610.4]
assign _T_23 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68615.4]
assign _T_24 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@68616.4]
assign _T_25 = _T_23 & _T_24; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@68617.4]
assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.LowRiscConfig.fir@68608.4]
assign io_enq_ready = io_deq_ready & _T_18; // @[Repeater.scala 23:16:freechips.rocketchip.system.LowRiscConfig.fir@68605.4]
assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.LowRiscConfig.fir@68602.4]
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@68607.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
saved_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
saved_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
saved_size = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
saved_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
saved_address = _RAND_5[11:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
saved_mask = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
full <= 1'h0;
end else begin
if (_T_25) begin
full <= 1'h0;
end else begin
if (_T_22) begin
full <= 1'h1;
end
end
end
if (_T_22) begin
saved_opcode <= io_enq_bits_opcode;
end
if (_T_22) begin
saved_param <= io_enq_bits_param;
end
if (_T_22) begin
saved_size <= io_enq_bits_size;
end
if (_T_22) begin
saved_source <= io_enq_bits_source;
end
if (_T_22) begin
saved_address <= io_enq_bits_address;
end
if (_T_22) begin
saved_mask <= io_enq_bits_mask;
end
if (_T_22) begin
saved_corrupt <= io_enq_bits_corrupt;
end
end
endmodule
module TLFragmenter_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@68622.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68623.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68624.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [11:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [8:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [11:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [8:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
input [63:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@68625.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [11:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [11:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [7:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [11:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire [7:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
reg [2:0] _T_244; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.LowRiscConfig.fir@68673.4]
reg [31:0] _RAND_0;
reg [2:0] _T_246; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.LowRiscConfig.fir@68674.4]
reg [31:0] _RAND_1;
reg _T_248; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.LowRiscConfig.fir@68675.4]
reg [31:0] _RAND_2;
wire [2:0] _T_249; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@68676.4]
wire _T_250; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@68677.4]
wire _T_251; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.LowRiscConfig.fir@68678.4]
wire [3:0] _T_253; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@68680.4]
wire [5:0] _T_256; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68683.4]
wire [2:0] _T_257; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68684.4]
wire [2:0] _T_258; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68685.4]
wire _T_259; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@68686.4]
wire _T_271; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.LowRiscConfig.fir@68702.4]
wire _T_272; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.LowRiscConfig.fir@68703.4]
wire [5:0] _GEN_7; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@68704.4]
wire [5:0] _T_273; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@68704.4]
wire [5:0] _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@68705.4]
wire [5:0] _T_274; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@68705.4]
wire [6:0] _GEN_9; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@68706.4]
wire [6:0] _T_275; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@68706.4]
wire [6:0] _T_276; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@68707.4]
wire [6:0] _T_277; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@68708.4]
wire [6:0] _T_278; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@68709.4]
wire [6:0] _T_279; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@68710.4]
wire [2:0] _T_280; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@68711.4]
wire [3:0] _T_281; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@68712.4]
wire _T_282; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@68713.4]
wire [3:0] _GEN_10; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@68714.4]
wire [3:0] _T_283; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@68714.4]
wire [1:0] _T_284; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@68715.4]
wire [1:0] _T_285; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@68716.4]
wire _T_286; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@68717.4]
wire [1:0] _T_287; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@68718.4]
wire _T_288; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@68719.4]
wire [2:0] _T_290; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@68721.4]
wire _T_297; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.LowRiscConfig.fir@68735.4]
wire _T_299; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.LowRiscConfig.fir@68737.4]
wire _T_300; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.LowRiscConfig.fir@68738.4]
wire _T_301; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.LowRiscConfig.fir@68739.4]
wire _T_291; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68722.4]
wire [2:0] _GEN_11; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68724.6]
wire [3:0] _T_292; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68724.6]
wire [3:0] _T_293; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68725.6]
wire [2:0] _T_294; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68726.6]
wire _T_296; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@68731.8]
wire _T_302; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.LowRiscConfig.fir@68741.4]
wire _T_330; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@68774.4]
wire [2:0] _T_331; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@68775.4]
wire [12:0] _T_333; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68777.4]
wire [5:0] _T_334; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68778.4]
wire [5:0] _T_335; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68779.4]
wire [9:0] _T_337; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68781.4]
wire [2:0] _T_338; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68782.4]
wire [2:0] _T_339; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68783.4]
wire _T_340; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@68784.4]
wire _T_341; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@68785.4]
reg [2:0] _T_344; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.LowRiscConfig.fir@68787.4]
reg [31:0] _RAND_3;
wire _T_345; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@68788.4]
wire [2:0] _T_346; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@68789.4]
wire [3:0] _T_347; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@68790.4]
wire [3:0] _T_348; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@68791.4]
wire [2:0] _T_349; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@68792.4]
wire [2:0] _T_350; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@68793.4]
wire [2:0] _T_351; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@68794.4]
wire [2:0] _T_354; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@68797.4]
reg _T_362; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@68804.4]
reg [31:0] _RAND_4;
wire _GEN_5; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@68805.4]
wire _T_364; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@68809.4]
wire _T_92_a_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@68669.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@68818.4]
wire _T_365; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68810.4]
wire _T_366; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.LowRiscConfig.fir@68814.4]
wire _T_367; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.LowRiscConfig.fir@68815.4]
wire [5:0] _GEN_12; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@68819.4]
wire [5:0] _T_369; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@68819.4]
wire [5:0] _T_370; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@68820.4]
wire [5:0] _T_371; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@68821.4]
wire [5:0] _GEN_13; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@68822.4]
wire [5:0] _T_372; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@68822.4]
wire [5:0] _T_373; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@68823.4]
wire [5:0] _T_374; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@68824.4]
wire [11:0] _GEN_14; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@68825.4]
wire [5:0] _T_376; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@68827.4]
wire _T_378; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@68831.4]
wire _T_380; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.LowRiscConfig.fir@68833.4]
wire _T_382; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@68835.4]
wire _T_383; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@68836.4]
wire _T_385; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@68843.4]
wire _T_386; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@68844.4]
wire _T_388; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@68846.4]
wire _T_389; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@68847.4]
TLMonitor_28 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@68632.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source)
);
Repeater_2 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@68749.4]
.clock(Repeater_clock),
.reset(Repeater_reset),
.io_repeat(Repeater_io_repeat),
.io_full(Repeater_io_full),
.io_enq_ready(Repeater_io_enq_ready),
.io_enq_valid(Repeater_io_enq_valid),
.io_enq_bits_opcode(Repeater_io_enq_bits_opcode),
.io_enq_bits_param(Repeater_io_enq_bits_param),
.io_enq_bits_size(Repeater_io_enq_bits_size),
.io_enq_bits_source(Repeater_io_enq_bits_source),
.io_enq_bits_address(Repeater_io_enq_bits_address),
.io_enq_bits_mask(Repeater_io_enq_bits_mask),
.io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt),
.io_deq_ready(Repeater_io_deq_ready),
.io_deq_valid(Repeater_io_deq_valid),
.io_deq_bits_opcode(Repeater_io_deq_bits_opcode),
.io_deq_bits_param(Repeater_io_deq_bits_param),
.io_deq_bits_size(Repeater_io_deq_bits_size),
.io_deq_bits_source(Repeater_io_deq_bits_source),
.io_deq_bits_address(Repeater_io_deq_bits_address),
.io_deq_bits_mask(Repeater_io_deq_bits_mask),
.io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt)
);
assign _T_249 = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@68676.4]
assign _T_250 = _T_244 == 3'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@68677.4]
assign _T_251 = _T_249 == 3'h0; // @[Fragmenter.scala 175:30:freechips.rocketchip.system.LowRiscConfig.fir@68678.4]
assign _T_253 = 4'h1 << auto_out_d_bits_size; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@68680.4]
assign _T_256 = 6'h7 << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68683.4]
assign _T_257 = _T_256[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68684.4]
assign _T_258 = ~ _T_257; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68685.4]
assign _T_259 = auto_out_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@68686.4]
assign _T_271 = _T_253[3:3]; // @[Fragmenter.scala 185:60:freechips.rocketchip.system.LowRiscConfig.fir@68702.4]
assign _T_272 = _T_259 ? 1'h1 : _T_271; // @[Fragmenter.scala 185:32:freechips.rocketchip.system.LowRiscConfig.fir@68703.4]
assign _GEN_7 = {{3'd0}, _T_249}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@68704.4]
assign _T_273 = _GEN_7 << 3; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@68704.4]
assign _GEN_8 = {{3'd0}, _T_258}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@68705.4]
assign _T_274 = _T_273 | _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@68705.4]
assign _GEN_9 = {{1'd0}, _T_274}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@68706.4]
assign _T_275 = _GEN_9 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@68706.4]
assign _T_276 = _T_275 | 7'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@68707.4]
assign _T_277 = {1'h0,_T_274}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@68708.4]
assign _T_278 = ~ _T_277; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@68709.4]
assign _T_279 = _T_276 & _T_278; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@68710.4]
assign _T_280 = _T_279[6:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@68711.4]
assign _T_281 = _T_279[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@68712.4]
assign _T_282 = _T_280 != 3'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@68713.4]
assign _GEN_10 = {{1'd0}, _T_280}; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@68714.4]
assign _T_283 = _GEN_10 | _T_281; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@68714.4]
assign _T_284 = _T_283[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@68715.4]
assign _T_285 = _T_283[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@68716.4]
assign _T_286 = _T_284 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@68717.4]
assign _T_287 = _T_284 | _T_285; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@68718.4]
assign _T_288 = _T_287[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@68719.4]
assign _T_290 = {_T_282,_T_286,_T_288}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@68721.4]
assign _T_297 = _T_259 == 1'h0; // @[Fragmenter.scala 203:20:freechips.rocketchip.system.LowRiscConfig.fir@68735.4]
assign _T_299 = _T_251 == 1'h0; // @[Fragmenter.scala 203:33:freechips.rocketchip.system.LowRiscConfig.fir@68737.4]
assign _T_300 = _T_297 & _T_299; // @[Fragmenter.scala 203:30:freechips.rocketchip.system.LowRiscConfig.fir@68738.4]
assign _T_301 = auto_in_d_ready | _T_300; // @[Fragmenter.scala 204:35:freechips.rocketchip.system.LowRiscConfig.fir@68739.4]
assign _T_291 = _T_301 & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68722.4]
assign _GEN_11 = {{2'd0}, _T_272}; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68724.6]
assign _T_292 = _T_244 - _GEN_11; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68724.6]
assign _T_293 = $unsigned(_T_292); // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68725.6]
assign _T_294 = _T_293[2:0]; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@68726.6]
assign _T_296 = auto_out_d_bits_source[3]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@68731.8]
assign _T_302 = _T_300 == 1'h0; // @[Fragmenter.scala 205:39:freechips.rocketchip.system.LowRiscConfig.fir@68741.4]
assign _T_330 = Repeater_io_deq_bits_size > 3'h3; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@68774.4]
assign _T_331 = _T_330 ? 3'h3 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@68775.4]
assign _T_333 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68777.4]
assign _T_334 = _T_333[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68778.4]
assign _T_335 = ~ _T_334; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68779.4]
assign _T_337 = 10'h7 << _T_331; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68781.4]
assign _T_338 = _T_337[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68782.4]
assign _T_339 = ~ _T_338; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68783.4]
assign _T_340 = Repeater_io_deq_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@68784.4]
assign _T_341 = _T_340 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@68785.4]
assign _T_345 = _T_344 == 3'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@68788.4]
assign _T_346 = _T_335[5:3]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@68789.4]
assign _T_347 = _T_344 - 3'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@68790.4]
assign _T_348 = $unsigned(_T_347); // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@68791.4]
assign _T_349 = _T_348[2:0]; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@68792.4]
assign _T_350 = _T_345 ? _T_346 : _T_349; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@68793.4]
assign _T_351 = ~ _T_350; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@68794.4]
assign _T_354 = ~ _T_351; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@68797.4]
assign _GEN_5 = _T_345 ? _T_248 : _T_362; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@68805.4]
assign _T_364 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@68809.4]
assign _T_92_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@68669.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@68818.4]
assign _T_365 = auto_out_a_ready & _T_92_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@68810.4]
assign _T_366 = _T_341 == 1'h0; // @[Fragmenter.scala 282:31:freechips.rocketchip.system.LowRiscConfig.fir@68814.4]
assign _T_367 = _T_354 != 3'h0; // @[Fragmenter.scala 282:53:freechips.rocketchip.system.LowRiscConfig.fir@68815.4]
assign _GEN_12 = {{3'd0}, _T_350}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@68819.4]
assign _T_369 = _GEN_12 << 3; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@68819.4]
assign _T_370 = ~ _T_335; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@68820.4]
assign _T_371 = _T_369 | _T_370; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@68821.4]
assign _GEN_13 = {{3'd0}, _T_339}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@68822.4]
assign _T_372 = _T_371 | _GEN_13; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@68822.4]
assign _T_373 = _T_372 | 6'h7; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@68823.4]
assign _T_374 = ~ _T_373; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@68824.4]
assign _GEN_14 = {{6'd0}, _T_374}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@68825.4]
assign _T_376 = {Repeater_io_deq_bits_source,_T_364}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@68827.4]
assign _T_378 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@68831.4]
assign _T_380 = _T_378 | _T_366; // @[Fragmenter.scala 289:35:freechips.rocketchip.system.LowRiscConfig.fir@68833.4]
assign _T_382 = _T_380 | reset; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@68835.4]
assign _T_383 = _T_382 == 1'h0; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@68836.4]
assign _T_385 = Repeater_io_deq_bits_mask == 8'hff; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@68843.4]
assign _T_386 = _T_378 | _T_385; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@68844.4]
assign _T_388 = _T_386 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@68846.4]
assign _T_389 = _T_388 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@68847.4]
assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68672.4]
assign auto_in_d_valid = auto_out_d_valid & _T_302; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68672.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68672.4]
assign auto_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68672.4]
assign auto_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68672.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68672.4]
assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_size = _T_331[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_source = {_T_376,_T_354}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_14; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_mask = Repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign auto_out_d_ready = auto_in_d_ready | _T_300; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68671.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68634.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68635.4]
assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid & _T_302; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@68668.4]
assign Repeater_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68751.4]
assign Repeater_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68752.4]
assign Repeater_io_repeat = _T_366 & _T_367; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.LowRiscConfig.fir@68817.4]
assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@68753.4]
assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@68818.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_244 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_246 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_248 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_344 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_362 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_244 <= 3'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_244 <= _T_249;
end else begin
_T_244 <= _T_294;
end
end
end
if (_T_291) begin
if (_T_250) begin
_T_246 <= _T_290;
end
end
if (reset) begin
_T_248 <= 1'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_248 <= _T_296;
end
end
end
if (reset) begin
_T_344 <= 3'h0;
end else begin
if (_T_365) begin
_T_344 <= _T_354;
end
end
if (_T_345) begin
_T_362 <= _T_248;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:183 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"); // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@68697.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@68698.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_383) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@68838.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_383) begin
$fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@68839.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_389) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@68849.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_389) begin
$fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@68850.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module SimpleLazyModule_11( // @[:freechips.rocketchip.system.LowRiscConfig.fir@68861.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68862.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68863.4]
output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [11:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [7:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [63:0] auto_fragmenter_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [2:0] auto_fragmenter_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [63:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [8:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [11:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [7:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output [63:0] auto_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [2:0] auto_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [8:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
input [63:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@68864.4]
);
wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [11:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [63:0] fragmenter_auto_in_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_in_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [8:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [11:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [63:0] fragmenter_auto_out_a_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [2:0] fragmenter_auto_out_d_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [8:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
TLFragmenter_2 fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@68869.4]
.clock(fragmenter_clock),
.reset(fragmenter_reset),
.auto_in_a_ready(fragmenter_auto_in_a_ready),
.auto_in_a_valid(fragmenter_auto_in_a_valid),
.auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
.auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
.auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
.auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
.auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
.auto_in_a_bits_data(fragmenter_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
.auto_in_d_ready(fragmenter_auto_in_d_ready),
.auto_in_d_valid(fragmenter_auto_in_d_valid),
.auto_in_d_bits_opcode(fragmenter_auto_in_d_bits_opcode),
.auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
.auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
.auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
.auto_out_a_ready(fragmenter_auto_out_a_ready),
.auto_out_a_valid(fragmenter_auto_out_a_valid),
.auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
.auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
.auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
.auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
.auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
.auto_out_a_bits_data(fragmenter_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
.auto_out_d_ready(fragmenter_auto_out_d_ready),
.auto_out_d_valid(fragmenter_auto_out_d_valid),
.auto_out_d_bits_opcode(fragmenter_auto_out_d_bits_opcode),
.auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
.auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
.auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
);
assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign auto_fragmenter_in_d_bits_opcode = fragmenter_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_data = fragmenter_auto_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68873.4]
assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@68874.4]
assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_data = auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@68876.4]
assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign fragmenter_auto_out_d_bits_opcode = auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@68875.4]
endmodule
module TLMonitor_29( // @[:freechips.rocketchip.system.LowRiscConfig.fir@68924.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68925.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68926.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [2:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [16:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [2:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
input [4:0] io_in_d_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@68927.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@70271.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@68944.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@68945.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@68950.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@68951.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@68954.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@68955.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@68963.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68975.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68976.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68977.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68978.6]
wire [12:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68980.6]
wire [5:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68981.6]
wire [5:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68982.6]
wire [16:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68983.6]
wire [16:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68983.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@68984.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@68986.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@68987.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@68988.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@68989.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@68990.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@68991.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@68992.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@68993.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@68995.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@68996.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@68998.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@68999.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@69000.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@69001.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@69002.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69003.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69004.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69005.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69006.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69007.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69008.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69009.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69010.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69011.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69012.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69013.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69014.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@69015.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@69016.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@69017.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69018.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69019.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69020.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69021.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69022.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69023.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69024.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69025.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69026.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69027.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69028.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69029.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69030.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69031.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69032.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69033.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69034.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69035.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69036.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69037.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69038.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69039.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69040.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69041.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@69048.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@69121.6]
wire [16:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@69124.8]
wire [17:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@69125.8]
wire [17:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@69126.8]
wire [17:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@69127.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@69128.8]
wire _T_210; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@69133.8]
wire _T_248; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@69171.8]
wire _T_250; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@69172.8]
wire _T_262; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@69184.8]
wire _T_263; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@69185.8]
wire _T_265; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@69191.8]
wire _T_266; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@69192.8]
wire _T_269; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@69199.8]
wire _T_270; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@69200.8]
wire _T_272; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@69206.8]
wire _T_273; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@69207.8]
wire _T_274; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@69212.8]
wire _T_276; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@69214.8]
wire _T_277; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@69215.8]
wire [7:0] _T_278; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@69220.8]
wire _T_279; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@69221.8]
wire _T_281; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@69223.8]
wire _T_282; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@69224.8]
wire _T_283; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@69229.8]
wire _T_285; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@69231.8]
wire _T_286; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@69232.8]
wire _T_287; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@69238.6]
wire _T_366; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@69337.8]
wire _T_368; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@69339.8]
wire _T_369; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@69340.8]
wire _T_379; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@69363.6]
wire _T_381; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@69366.8]
wire _T_389; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@69374.8]
wire _T_392; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69377.8]
wire _T_393; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69378.8]
wire _T_400; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@69397.8]
wire _T_402; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@69399.8]
wire _T_403; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@69400.8]
wire _T_404; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@69405.8]
wire _T_406; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@69407.8]
wire _T_407; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@69408.8]
wire _T_412; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@69422.6]
wire _T_438; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@69470.6]
wire [7:0] _T_460; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@69509.8]
wire [7:0] _T_461; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@69510.8]
wire _T_462; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@69511.8]
wire _T_464; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@69513.8]
wire _T_465; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@69514.8]
wire _T_466; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@69520.6]
wire _T_484; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@69551.8]
wire _T_486; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@69553.8]
wire _T_487; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@69554.8]
wire _T_492; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@69568.6]
wire _T_510; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@69599.8]
wire _T_512; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@69601.8]
wire _T_513; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@69602.8]
wire _T_518; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@69616.6]
wire [2:0] _T_550; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@69676.6]
wire _T_551; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@69677.6]
wire _T_556; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@69682.6]
wire _T_557; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@69683.6]
wire [1:0] _T_560; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@69686.6]
wire _T_561; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@69687.6]
wire _T_569; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@69695.6]
wire _T_585; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69707.6]
wire _T_586; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69708.6]
wire _T_587; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69709.6]
wire _T_588; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69710.6]
wire _T_592; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@69715.8]
wire _T_593; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@69716.8]
wire _T_731; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@70002.4]
reg [2:0] _T_741; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@70011.4]
reg [31:0] _RAND_0;
wire [3:0] _T_742; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70012.4]
wire [3:0] _T_743; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70013.4]
wire [2:0] _T_744; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70014.4]
wire _T_745; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70015.4]
reg [2:0] _T_754; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@70026.4]
reg [31:0] _RAND_1;
reg [2:0] _T_756; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@70027.4]
reg [31:0] _RAND_2;
reg [2:0] _T_758; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@70028.4]
reg [31:0] _RAND_3;
reg [4:0] _T_760; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@70029.4]
reg [31:0] _RAND_4;
reg [16:0] _T_762; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@70030.4]
reg [31:0] _RAND_5;
wire _T_763; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@70031.4]
wire _T_764; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@70032.4]
wire _T_765; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@70034.6]
wire _T_767; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@70036.6]
wire _T_768; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@70037.6]
wire _T_769; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@70042.6]
wire _T_771; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@70044.6]
wire _T_772; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@70045.6]
wire _T_773; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@70050.6]
wire _T_775; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@70052.6]
wire _T_776; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@70053.6]
wire _T_777; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@70058.6]
wire _T_779; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@70060.6]
wire _T_780; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@70061.6]
wire _T_781; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@70066.6]
wire _T_783; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@70068.6]
wire _T_784; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@70069.6]
wire _T_786; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@70076.4]
wire _T_787; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@70084.4]
wire [12:0] _T_789; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70086.4]
wire [5:0] _T_790; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70087.4]
wire [5:0] _T_791; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70088.4]
wire [2:0] _T_792; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@70089.4]
reg [2:0] _T_796; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@70092.4]
reg [31:0] _RAND_6;
wire [3:0] _T_797; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70093.4]
wire [3:0] _T_798; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70094.4]
wire [2:0] _T_799; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70095.4]
wire _T_800; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70096.4]
reg [2:0] _T_813; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@70109.4]
reg [31:0] _RAND_7;
reg [4:0] _T_815; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@70110.4]
reg [31:0] _RAND_8;
wire _T_820; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@70113.4]
wire _T_821; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@70114.4]
wire _T_830; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@70132.6]
wire _T_832; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@70134.6]
wire _T_833; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@70135.6]
wire _T_834; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@70140.6]
wire _T_836; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@70142.6]
wire _T_837; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@70143.6]
wire _T_847; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@70166.4]
reg [24:0] _T_849; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@70175.4]
reg [31:0] _RAND_9;
reg [2:0] _T_860; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@70185.4]
reg [31:0] _RAND_10;
wire [3:0] _T_861; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70186.4]
wire [3:0] _T_862; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70187.4]
wire [2:0] _T_863; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70188.4]
wire _T_864; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70189.4]
reg [2:0] _T_881; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@70208.4]
reg [31:0] _RAND_11;
wire [3:0] _T_882; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70209.4]
wire [3:0] _T_883; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70210.4]
wire [2:0] _T_884; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70211.4]
wire _T_885; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70212.4]
wire _T_896; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@70227.4]
wire [31:0] _T_898; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@70230.6]
wire [24:0] _T_899; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@70232.6]
wire _T_900; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@70233.6]
wire _T_901; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@70234.6]
wire _T_903; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@70236.6]
wire _T_904; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@70237.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@70229.4]
wire _T_909; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@70248.4]
wire [31:0] _T_913; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@70253.6]
wire [24:0] _T_894; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70223.4 :freechips.rocketchip.system.LowRiscConfig.fir@70225.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@70231.6]
wire [24:0] _T_914; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@70255.6]
wire [24:0] _T_915; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@70256.6]
wire _T_916; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@70257.6]
wire _T_918; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@70259.6]
wire _T_919; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@70260.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@70252.4]
wire [24:0] _T_920; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@70266.4]
wire [24:0] _T_906; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70243.4 :freechips.rocketchip.system.LowRiscConfig.fir@70245.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@70254.6]
wire [24:0] _T_921; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@70267.4]
wire [24:0] _T_922; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@70268.4]
reg [31:0] _T_924; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@70270.4]
reg [31:0] _RAND_12;
wire _T_925; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@70273.4]
wire _T_926; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@70274.4]
wire _T_927; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@70275.4]
wire _T_928; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@70276.4]
wire _T_929; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@70277.4]
wire _T_930; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@70278.4]
wire _T_932; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@70280.4]
wire _T_933; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@70281.4]
wire [31:0] _T_935; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@70287.4]
wire _T_938; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@70291.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@69135.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@69252.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69380.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@69436.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@69484.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@69534.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@69582.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@69630.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@70271.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@68944.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@68945.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@68950.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@68951.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@68954.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@68955.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@68963.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68975.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68976.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68977.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@68978.6]
assign _T_62 = 13'h3f << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@68980.6]
assign _T_63 = _T_62[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@68981.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@68982.6]
assign _GEN_18 = {{11'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68983.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@68983.6]
assign _T_66 = _T_65 == 17'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@68984.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@68986.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@68987.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@68988.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@68989.6]
assign _T_72 = io_in_a_bits_size >= 3'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@68990.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@68991.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@68992.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@68993.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@68995.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@68996.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@68998.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@68999.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@69000.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@69001.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@69002.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69003.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69004.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69005.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69006.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69007.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69008.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69009.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69010.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69011.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69012.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69013.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69014.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@69015.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@69016.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@69017.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69018.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69019.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69020.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69021.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69022.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69023.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69024.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69025.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69026.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69027.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69028.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69029.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69030.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69031.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69032.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69033.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69034.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69035.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69036.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69037.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69038.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@69039.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@69040.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@69041.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@69048.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@69121.6]
assign _T_201 = io_in_a_bits_address ^ 17'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@69124.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@69125.8]
assign _T_203 = $signed(_T_202) & $signed(-18'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@69126.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@69127.8]
assign _T_205 = $signed(_T_204) == $signed(18'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@69128.8]
assign _T_210 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@69133.8]
assign _T_248 = 3'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@69171.8]
assign _T_250 = _T_23 ? _T_248 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@69172.8]
assign _T_262 = _T_250 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@69184.8]
assign _T_263 = _T_262 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@69185.8]
assign _T_265 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@69191.8]
assign _T_266 = _T_265 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@69192.8]
assign _T_269 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@69199.8]
assign _T_270 = _T_269 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@69200.8]
assign _T_272 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@69206.8]
assign _T_273 = _T_272 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@69207.8]
assign _T_274 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@69212.8]
assign _T_276 = _T_274 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@69214.8]
assign _T_277 = _T_276 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@69215.8]
assign _T_278 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@69220.8]
assign _T_279 = _T_278 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@69221.8]
assign _T_281 = _T_279 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@69223.8]
assign _T_282 = _T_281 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@69224.8]
assign _T_283 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@69229.8]
assign _T_285 = _T_283 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@69231.8]
assign _T_286 = _T_285 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@69232.8]
assign _T_287 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@69238.6]
assign _T_366 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@69337.8]
assign _T_368 = _T_366 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@69339.8]
assign _T_369 = _T_368 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@69340.8]
assign _T_379 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@69363.6]
assign _T_381 = io_in_a_bits_size <= 3'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@69366.8]
assign _T_389 = _T_381 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@69374.8]
assign _T_392 = _T_389 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69377.8]
assign _T_393 = _T_392 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69378.8]
assign _T_400 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@69397.8]
assign _T_402 = _T_400 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@69399.8]
assign _T_403 = _T_402 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@69400.8]
assign _T_404 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@69405.8]
assign _T_406 = _T_404 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@69407.8]
assign _T_407 = _T_406 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@69408.8]
assign _T_412 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@69422.6]
assign _T_438 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@69470.6]
assign _T_460 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@69509.8]
assign _T_461 = io_in_a_bits_mask & _T_460; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@69510.8]
assign _T_462 = _T_461 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@69511.8]
assign _T_464 = _T_462 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@69513.8]
assign _T_465 = _T_464 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@69514.8]
assign _T_466 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@69520.6]
assign _T_484 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@69551.8]
assign _T_486 = _T_484 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@69553.8]
assign _T_487 = _T_486 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@69554.8]
assign _T_492 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@69568.6]
assign _T_510 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@69599.8]
assign _T_512 = _T_510 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@69601.8]
assign _T_513 = _T_512 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@69602.8]
assign _T_518 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@69616.6]
assign _T_550 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@69676.6]
assign _T_551 = _T_550 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@69677.6]
assign _T_556 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@69682.6]
assign _T_557 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@69683.6]
assign _T_560 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@69686.6]
assign _T_561 = _T_560 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@69687.6]
assign _T_569 = _T_560 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@69695.6]
assign _T_585 = _T_551 | _T_556; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69707.6]
assign _T_586 = _T_585 | _T_557; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69708.6]
assign _T_587 = _T_586 | _T_561; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69709.6]
assign _T_588 = _T_587 | _T_569; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@69710.6]
assign _T_592 = _T_588 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@69715.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@69716.8]
assign _T_731 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@70002.4]
assign _T_742 = _T_741 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70012.4]
assign _T_743 = $unsigned(_T_742); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70013.4]
assign _T_744 = _T_743[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70014.4]
assign _T_745 = _T_741 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70015.4]
assign _T_763 = _T_745 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@70031.4]
assign _T_764 = io_in_a_valid & _T_763; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@70032.4]
assign _T_765 = io_in_a_bits_opcode == _T_754; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@70034.6]
assign _T_767 = _T_765 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@70036.6]
assign _T_768 = _T_767 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@70037.6]
assign _T_769 = io_in_a_bits_param == _T_756; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@70042.6]
assign _T_771 = _T_769 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@70044.6]
assign _T_772 = _T_771 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@70045.6]
assign _T_773 = io_in_a_bits_size == _T_758; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@70050.6]
assign _T_775 = _T_773 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@70052.6]
assign _T_776 = _T_775 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@70053.6]
assign _T_777 = io_in_a_bits_source == _T_760; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@70058.6]
assign _T_779 = _T_777 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@70060.6]
assign _T_780 = _T_779 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@70061.6]
assign _T_781 = io_in_a_bits_address == _T_762; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@70066.6]
assign _T_783 = _T_781 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@70068.6]
assign _T_784 = _T_783 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@70069.6]
assign _T_786 = _T_731 & _T_745; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@70076.4]
assign _T_787 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@70084.4]
assign _T_789 = 13'h3f << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70086.4]
assign _T_790 = _T_789[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70087.4]
assign _T_791 = ~ _T_790; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70088.4]
assign _T_792 = _T_791[5:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@70089.4]
assign _T_797 = _T_796 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70093.4]
assign _T_798 = $unsigned(_T_797); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70094.4]
assign _T_799 = _T_798[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70095.4]
assign _T_800 = _T_796 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70096.4]
assign _T_820 = _T_800 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@70113.4]
assign _T_821 = io_in_d_valid & _T_820; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@70114.4]
assign _T_830 = io_in_d_bits_size == _T_813; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@70132.6]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@70134.6]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@70135.6]
assign _T_834 = io_in_d_bits_source == _T_815; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@70140.6]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@70142.6]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@70143.6]
assign _T_847 = _T_787 & _T_800; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@70166.4]
assign _T_861 = _T_860 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70186.4]
assign _T_862 = $unsigned(_T_861); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70187.4]
assign _T_863 = _T_862[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70188.4]
assign _T_864 = _T_860 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70189.4]
assign _T_882 = _T_881 - 3'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70209.4]
assign _T_883 = $unsigned(_T_882); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70210.4]
assign _T_884 = _T_883[2:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@70211.4]
assign _T_885 = _T_881 == 3'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@70212.4]
assign _T_896 = _T_731 & _T_864; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@70227.4]
assign _T_898 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@70230.6]
assign _T_899 = _T_849 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@70232.6]
assign _T_900 = _T_899[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@70233.6]
assign _T_901 = _T_900 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@70234.6]
assign _T_903 = _T_901 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@70236.6]
assign _T_904 = _T_903 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@70237.6]
assign _GEN_15 = _T_896 ? _T_898 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@70229.4]
assign _T_909 = _T_787 & _T_885; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@70248.4]
assign _T_913 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@70253.6]
assign _T_894 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70223.4 :freechips.rocketchip.system.LowRiscConfig.fir@70225.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@70231.6]
assign _T_914 = _T_894 | _T_849; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@70255.6]
assign _T_915 = _T_914 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@70256.6]
assign _T_916 = _T_915[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@70257.6]
assign _T_918 = _T_916 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@70259.6]
assign _T_919 = _T_918 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@70260.6]
assign _GEN_16 = _T_909 ? _T_913 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@70252.4]
assign _T_920 = _T_849 | _T_894; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@70266.4]
assign _T_906 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70243.4 :freechips.rocketchip.system.LowRiscConfig.fir@70245.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@70254.6]
assign _T_921 = ~ _T_906; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@70267.4]
assign _T_922 = _T_920 & _T_921; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@70268.4]
assign _T_925 = _T_849 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@70273.4]
assign _T_926 = _T_925 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@70274.4]
assign _T_927 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@70275.4]
assign _T_928 = _T_926 | _T_927; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@70276.4]
assign _T_929 = _T_924 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@70277.4]
assign _T_930 = _T_928 | _T_929; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@70278.4]
assign _T_932 = _T_930 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@70280.4]
assign _T_933 = _T_932 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@70281.4]
assign _T_935 = _T_924 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@70287.4]
assign _T_938 = _T_731 | _T_787; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@70291.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@69135.10]
assign _GEN_35 = io_in_a_valid & _T_287; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@69252.10]
assign _GEN_53 = io_in_a_valid & _T_379; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69380.10]
assign _GEN_65 = io_in_a_valid & _T_412; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@69436.10]
assign _GEN_75 = io_in_a_valid & _T_438; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@69484.10]
assign _GEN_85 = io_in_a_valid & _T_466; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@69534.10]
assign _GEN_95 = io_in_a_valid & _T_492; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@69582.10]
assign _GEN_105 = io_in_a_valid & _T_518; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@69630.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_741 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_754 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_756 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_758 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_760 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_762 = _RAND_5[16:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_796 = _RAND_6[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_813 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_815 = _RAND_8[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_849 = _RAND_9[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_860 = _RAND_10[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_881 = _RAND_11[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_924 = _RAND_12[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_741 <= 3'h0;
end else begin
if (_T_731) begin
if (_T_745) begin
_T_741 <= 3'h0;
end else begin
_T_741 <= _T_744;
end
end
end
if (_T_786) begin
_T_754 <= io_in_a_bits_opcode;
end
if (_T_786) begin
_T_756 <= io_in_a_bits_param;
end
if (_T_786) begin
_T_758 <= io_in_a_bits_size;
end
if (_T_786) begin
_T_760 <= io_in_a_bits_source;
end
if (_T_786) begin
_T_762 <= io_in_a_bits_address;
end
if (reset) begin
_T_796 <= 3'h0;
end else begin
if (_T_787) begin
if (_T_800) begin
_T_796 <= _T_792;
end else begin
_T_796 <= _T_799;
end
end
end
if (_T_847) begin
_T_813 <= io_in_d_bits_size;
end
if (_T_847) begin
_T_815 <= io_in_d_bits_source;
end
if (reset) begin
_T_849 <= 25'h0;
end else begin
_T_849 <= _T_922;
end
if (reset) begin
_T_860 <= 3'h0;
end else begin
if (_T_731) begin
if (_T_864) begin
_T_860 <= 3'h0;
end else begin
_T_860 <= _T_863;
end
end
end
if (reset) begin
_T_881 <= 3'h0;
end else begin
if (_T_787) begin
if (_T_885) begin
_T_881 <= _T_792;
end else begin
_T_881 <= _T_884;
end
end
end
if (reset) begin
_T_924 <= 32'h0;
end else begin
if (_T_938) begin
_T_924 <= 32'h0;
end else begin
_T_924 <= _T_935;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at BootROM.scala:74:64)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@68939.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@68940.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@69118.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@69119.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@69135.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_210) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@69136.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at BootROM.scala:74:64)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@69187.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_263) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@69188.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@69194.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_266) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@69195.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@69202.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_270) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@69203.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@69209.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_273) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@69210.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at BootROM.scala:74:64)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@69217.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_277) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@69218.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@69226.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_282) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@69227.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@69234.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_286) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@69235.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@69252.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_210) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@69253.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at BootROM.scala:74:64)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@69304.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_263) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@69305.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@69311.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_266) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@69312.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@69319.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_270) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@69320.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@69326.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_273) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@69327.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at BootROM.scala:74:64)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@69334.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_277) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@69335.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at BootROM.scala:74:64)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@69342.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_369) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@69343.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@69351.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_282) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@69352.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@69359.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_286) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@69360.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69380.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_393) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@69381.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@69387.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_266) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@69388.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@69394.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_273) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@69395.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@69402.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_403) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@69403.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@69410.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_407) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@69411.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@69418.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_286) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@69419.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@69436.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_210) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@69437.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@69443.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_266) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@69444.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@69450.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_273) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@69451.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@69458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_403) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@69459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@69466.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_407) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@69467.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@69484.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_210) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@69485.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@69491.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_266) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@69492.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@69498.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_273) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@69499.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@69506.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_403) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@69507.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_465) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@69516.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_465) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@69517.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@69534.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_210) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@69535.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@69541.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_266) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@69542.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@69548.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_273) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@69549.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_487) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at BootROM.scala:74:64)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@69556.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_487) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@69557.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@69564.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_407) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@69565.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@69582.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_210) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@69583.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@69589.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_266) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@69590.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@69596.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_273) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@69597.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_513) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at BootROM.scala:74:64)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@69604.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_513) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@69605.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@69612.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_407) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@69613.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at BootROM.scala:74:64)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@69630.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_210) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@69631.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@69637.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_266) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@69638.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at BootROM.scala:74:64)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@69644.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_273) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@69645.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at BootROM.scala:74:64)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@69652.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_407) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@69653.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@69660.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_286) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@69661.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at BootROM.scala:74:64)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@69671.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@69672.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@69718.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@69719.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@69726.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@69727.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@69734.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@69735.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@69742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@69743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at BootROM.scala:74:64)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@69750.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@69751.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@69760.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@69761.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at BootROM.scala:74:64)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@69767.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@69768.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@69775.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@69776.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at BootROM.scala:74:64)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@69783.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@69784.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at BootROM.scala:74:64)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@69791.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@69792.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@69799.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@69800.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at BootROM.scala:74:64)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@69808.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@69809.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@69818.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@69819.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at BootROM.scala:74:64)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@69825.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@69826.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at BootROM.scala:74:64)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@69833.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@69834.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at BootROM.scala:74:64)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@69841.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@69842.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at BootROM.scala:74:64)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@69849.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@69850.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@69858.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@69859.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at BootROM.scala:74:64)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@69867.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@69868.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@69877.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@69878.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@69885.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@69886.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@69893.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@69894.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at BootROM.scala:74:64)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@69902.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@69903.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@69912.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_593) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@69913.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@69920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@69921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@69929.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@69930.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at BootROM.scala:74:64)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@69938.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@69939.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@69948.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@69949.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at BootROM.scala:74:64)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@69956.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@69957.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at BootROM.scala:74:64)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@69964.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@69965.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at BootROM.scala:74:64)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@69973.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@69974.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at BootROM.scala:74:64)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@69983.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@69984.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at BootROM.scala:74:64)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@69991.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@69992.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at BootROM.scala:74:64)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@69999.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@70000.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_764 & _T_768) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@70039.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_764 & _T_768) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@70040.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_764 & _T_772) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@70047.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_764 & _T_772) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@70048.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_764 & _T_776) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@70055.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_764 & _T_776) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@70056.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_764 & _T_780) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@70063.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_764 & _T_780) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@70064.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_764 & _T_784) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@70071.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_764 & _T_784) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@70072.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@70121.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@70122.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@70129.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@70130.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_821 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@70137.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_821 & _T_833) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@70138.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_821 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@70145.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_821 & _T_837) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@70146.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@70153.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@70154.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at BootROM.scala:74:64)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@70161.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@70162.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_896 & _T_904) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at BootROM.scala:74:64)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@70239.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_896 & _T_904) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@70240.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_909 & _T_919) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at BootROM.scala:74:64)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@70262.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_909 & _T_919) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@70263.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_933) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at BootROM.scala:74:64)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@70283.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_933) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@70284.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module Repeater_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@70296.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70297.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70298.4]
input io_repeat, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output io_full, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input [2:0] io_enq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input [2:0] io_enq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input [4:0] io_enq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input [16:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input io_enq_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output [2:0] io_deq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output [2:0] io_deq_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output [2:0] io_deq_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output [4:0] io_deq_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output [16:0] io_deq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
output io_deq_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@70299.4]
);
reg full; // @[Repeater.scala 18:21:freechips.rocketchip.system.LowRiscConfig.fir@70304.4]
reg [31:0] _RAND_0;
reg [2:0] saved_opcode; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_1;
reg [2:0] saved_param; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_2;
reg [2:0] saved_size; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_3;
reg [4:0] saved_source; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_4;
reg [16:0] saved_address; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_5;
reg [7:0] saved_mask; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_6;
reg saved_corrupt; // @[Repeater.scala 19:18:freechips.rocketchip.system.LowRiscConfig.fir@70305.4]
reg [31:0] _RAND_7;
wire _T_18; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@70308.4]
wire _T_21; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70314.4]
wire _T_22; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@70315.4]
wire _T_23; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70320.4]
wire _T_24; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@70321.4]
wire _T_25; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@70322.4]
assign _T_18 = full == 1'h0; // @[Repeater.scala 23:35:freechips.rocketchip.system.LowRiscConfig.fir@70308.4]
assign _T_21 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70314.4]
assign _T_22 = _T_21 & io_repeat; // @[Repeater.scala 27:23:freechips.rocketchip.system.LowRiscConfig.fir@70315.4]
assign _T_23 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70320.4]
assign _T_24 = io_repeat == 1'h0; // @[Repeater.scala 28:26:freechips.rocketchip.system.LowRiscConfig.fir@70321.4]
assign _T_25 = _T_23 & _T_24; // @[Repeater.scala 28:23:freechips.rocketchip.system.LowRiscConfig.fir@70322.4]
assign io_full = full; // @[Repeater.scala 25:11:freechips.rocketchip.system.LowRiscConfig.fir@70313.4]
assign io_enq_ready = io_deq_ready & _T_18; // @[Repeater.scala 23:16:freechips.rocketchip.system.LowRiscConfig.fir@70310.4]
assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:freechips.rocketchip.system.LowRiscConfig.fir@70307.4]
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
assign io_deq_bits_corrupt = full ? saved_corrupt : io_enq_bits_corrupt; // @[Repeater.scala 24:15:freechips.rocketchip.system.LowRiscConfig.fir@70312.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
saved_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
saved_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
saved_size = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
saved_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
saved_address = _RAND_5[16:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
saved_mask = _RAND_6[7:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
saved_corrupt = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
full <= 1'h0;
end else begin
if (_T_25) begin
full <= 1'h0;
end else begin
if (_T_22) begin
full <= 1'h1;
end
end
end
if (_T_22) begin
saved_opcode <= io_enq_bits_opcode;
end
if (_T_22) begin
saved_param <= io_enq_bits_param;
end
if (_T_22) begin
saved_size <= io_enq_bits_size;
end
if (_T_22) begin
saved_source <= io_enq_bits_source;
end
if (_T_22) begin
saved_address <= io_enq_bits_address;
end
if (_T_22) begin
saved_mask <= io_enq_bits_mask;
end
if (_T_22) begin
saved_corrupt <= io_enq_bits_corrupt;
end
end
endmodule
module TLFragmenter_3( // @[:freechips.rocketchip.system.LowRiscConfig.fir@70327.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70328.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70329.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [2:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [16:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [2:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [1:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [8:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [16:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [1:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [8:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
input [63:0] auto_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@70330.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [2:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [16:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [2:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
wire Repeater_clock; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_reset; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_repeat; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_full; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_enq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_enq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [2:0] Repeater_io_enq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [2:0] Repeater_io_enq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [2:0] Repeater_io_enq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [4:0] Repeater_io_enq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [16:0] Repeater_io_enq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [7:0] Repeater_io_enq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_enq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_deq_ready; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_deq_valid; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [2:0] Repeater_io_deq_bits_opcode; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [2:0] Repeater_io_deq_bits_param; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [2:0] Repeater_io_deq_bits_size; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [4:0] Repeater_io_deq_bits_source; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [16:0] Repeater_io_deq_bits_address; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire [7:0] Repeater_io_deq_bits_mask; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
wire Repeater_io_deq_bits_corrupt; // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
reg [2:0] _T_244; // @[Fragmenter.scala 170:29:freechips.rocketchip.system.LowRiscConfig.fir@70378.4]
reg [31:0] _RAND_0;
reg [2:0] _T_246; // @[Fragmenter.scala 171:24:freechips.rocketchip.system.LowRiscConfig.fir@70379.4]
reg [31:0] _RAND_1;
reg _T_248; // @[Fragmenter.scala 172:30:freechips.rocketchip.system.LowRiscConfig.fir@70380.4]
reg [31:0] _RAND_2;
wire [2:0] _T_249; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@70381.4]
wire _T_250; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@70382.4]
wire [5:0] _T_256; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70388.4]
wire [2:0] _T_257; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70389.4]
wire [2:0] _T_258; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70390.4]
wire [5:0] _GEN_7; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@70409.4]
wire [5:0] _T_273; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@70409.4]
wire [5:0] _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@70410.4]
wire [5:0] _T_274; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@70410.4]
wire [6:0] _GEN_9; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@70411.4]
wire [6:0] _T_275; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@70411.4]
wire [6:0] _T_276; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@70412.4]
wire [6:0] _T_277; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70413.4]
wire [6:0] _T_278; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@70414.4]
wire [6:0] _T_279; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@70415.4]
wire [2:0] _T_280; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@70416.4]
wire [3:0] _T_281; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@70417.4]
wire _T_282; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@70418.4]
wire [3:0] _GEN_10; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@70419.4]
wire [3:0] _T_283; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@70419.4]
wire [1:0] _T_284; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@70420.4]
wire [1:0] _T_285; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@70421.4]
wire _T_286; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@70422.4]
wire [1:0] _T_287; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@70423.4]
wire _T_288; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@70424.4]
wire [2:0] _T_290; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70426.4]
wire _T_291; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70427.4]
wire [3:0] _T_292; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@70429.6]
wire [3:0] _T_293; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@70430.6]
wire [2:0] _T_294; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@70431.6]
wire _T_296; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@70436.8]
wire _T_330; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@70479.4]
wire [2:0] _T_331; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@70480.4]
wire [12:0] _T_333; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70482.4]
wire [5:0] _T_334; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70483.4]
wire [5:0] _T_335; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70484.4]
wire [9:0] _T_337; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70486.4]
wire [2:0] _T_338; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70487.4]
wire [2:0] _T_339; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70488.4]
reg [2:0] _T_344; // @[Fragmenter.scala 271:29:freechips.rocketchip.system.LowRiscConfig.fir@70492.4]
reg [31:0] _RAND_3;
wire _T_345; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@70493.4]
wire [2:0] _T_346; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@70494.4]
wire [3:0] _T_347; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@70495.4]
wire [3:0] _T_348; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@70496.4]
wire [2:0] _T_349; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@70497.4]
wire [2:0] _T_350; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@70498.4]
wire [2:0] _T_351; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@70499.4]
wire [2:0] _T_354; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@70502.4]
reg _T_362; // @[Reg.scala 11:16:freechips.rocketchip.system.LowRiscConfig.fir@70509.4]
reg [31:0] _RAND_4;
wire _GEN_5; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@70510.4]
wire _T_364; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@70514.4]
wire _T_92_a_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@70374.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@70523.4]
wire _T_365; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70515.4]
wire [5:0] _GEN_11; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@70524.4]
wire [5:0] _T_369; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@70524.4]
wire [5:0] _T_370; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@70525.4]
wire [5:0] _T_371; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@70526.4]
wire [5:0] _GEN_12; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@70527.4]
wire [5:0] _T_372; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@70527.4]
wire [5:0] _T_373; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@70528.4]
wire [5:0] _T_374; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@70529.4]
wire [16:0] _GEN_13; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@70530.4]
wire [5:0] _T_376; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70532.4]
wire _T_378; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@70536.4]
wire _T_385; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@70548.4]
wire _T_386; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@70549.4]
wire _T_388; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@70551.4]
wire _T_389; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@70552.4]
TLMonitor_29 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@70337.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source)
);
Repeater_3 Repeater ( // @[Fragmenter.scala 242:30:freechips.rocketchip.system.LowRiscConfig.fir@70454.4]
.clock(Repeater_clock),
.reset(Repeater_reset),
.io_repeat(Repeater_io_repeat),
.io_full(Repeater_io_full),
.io_enq_ready(Repeater_io_enq_ready),
.io_enq_valid(Repeater_io_enq_valid),
.io_enq_bits_opcode(Repeater_io_enq_bits_opcode),
.io_enq_bits_param(Repeater_io_enq_bits_param),
.io_enq_bits_size(Repeater_io_enq_bits_size),
.io_enq_bits_source(Repeater_io_enq_bits_source),
.io_enq_bits_address(Repeater_io_enq_bits_address),
.io_enq_bits_mask(Repeater_io_enq_bits_mask),
.io_enq_bits_corrupt(Repeater_io_enq_bits_corrupt),
.io_deq_ready(Repeater_io_deq_ready),
.io_deq_valid(Repeater_io_deq_valid),
.io_deq_bits_opcode(Repeater_io_deq_bits_opcode),
.io_deq_bits_param(Repeater_io_deq_bits_param),
.io_deq_bits_size(Repeater_io_deq_bits_size),
.io_deq_bits_source(Repeater_io_deq_bits_source),
.io_deq_bits_address(Repeater_io_deq_bits_address),
.io_deq_bits_mask(Repeater_io_deq_bits_mask),
.io_deq_bits_corrupt(Repeater_io_deq_bits_corrupt)
);
assign _T_249 = auto_out_d_bits_source[2:0]; // @[Fragmenter.scala 173:41:freechips.rocketchip.system.LowRiscConfig.fir@70381.4]
assign _T_250 = _T_244 == 3'h0; // @[Fragmenter.scala 174:29:freechips.rocketchip.system.LowRiscConfig.fir@70382.4]
assign _T_256 = 6'h7 << auto_out_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70388.4]
assign _T_257 = _T_256[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70389.4]
assign _T_258 = ~ _T_257; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70390.4]
assign _GEN_7 = {{3'd0}, _T_249}; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@70409.4]
assign _T_273 = _GEN_7 << 3; // @[Fragmenter.scala 187:47:freechips.rocketchip.system.LowRiscConfig.fir@70409.4]
assign _GEN_8 = {{3'd0}, _T_258}; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@70410.4]
assign _T_274 = _T_273 | _GEN_8; // @[Fragmenter.scala 187:69:freechips.rocketchip.system.LowRiscConfig.fir@70410.4]
assign _GEN_9 = {{1'd0}, _T_274}; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@70411.4]
assign _T_275 = _GEN_9 << 1; // @[package.scala 183:35:freechips.rocketchip.system.LowRiscConfig.fir@70411.4]
assign _T_276 = _T_275 | 7'h1; // @[package.scala 183:40:freechips.rocketchip.system.LowRiscConfig.fir@70412.4]
assign _T_277 = {1'h0,_T_274}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70413.4]
assign _T_278 = ~ _T_277; // @[package.scala 183:53:freechips.rocketchip.system.LowRiscConfig.fir@70414.4]
assign _T_279 = _T_276 & _T_278; // @[package.scala 183:51:freechips.rocketchip.system.LowRiscConfig.fir@70415.4]
assign _T_280 = _T_279[6:4]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@70416.4]
assign _T_281 = _T_279[3:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@70417.4]
assign _T_282 = _T_280 != 3'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@70418.4]
assign _GEN_10 = {{1'd0}, _T_280}; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@70419.4]
assign _T_283 = _GEN_10 | _T_281; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@70419.4]
assign _T_284 = _T_283[3:2]; // @[OneHot.scala 26:18:freechips.rocketchip.system.LowRiscConfig.fir@70420.4]
assign _T_285 = _T_283[1:0]; // @[OneHot.scala 27:18:freechips.rocketchip.system.LowRiscConfig.fir@70421.4]
assign _T_286 = _T_284 != 2'h0; // @[OneHot.scala 28:14:freechips.rocketchip.system.LowRiscConfig.fir@70422.4]
assign _T_287 = _T_284 | _T_285; // @[OneHot.scala 28:28:freechips.rocketchip.system.LowRiscConfig.fir@70423.4]
assign _T_288 = _T_287[1]; // @[CircuitMath.scala 30:8:freechips.rocketchip.system.LowRiscConfig.fir@70424.4]
assign _T_290 = {_T_282,_T_286,_T_288}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70426.4]
assign _T_291 = auto_in_d_ready & auto_out_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70427.4]
assign _T_292 = _T_244 - 3'h1; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@70429.6]
assign _T_293 = $unsigned(_T_292); // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@70430.6]
assign _T_294 = _T_293[2:0]; // @[Fragmenter.scala 190:55:freechips.rocketchip.system.LowRiscConfig.fir@70431.6]
assign _T_296 = auto_out_d_bits_source[3]; // @[Fragmenter.scala 193:41:freechips.rocketchip.system.LowRiscConfig.fir@70436.8]
assign _T_330 = Repeater_io_deq_bits_size > 3'h3; // @[Fragmenter.scala 265:31:freechips.rocketchip.system.LowRiscConfig.fir@70479.4]
assign _T_331 = _T_330 ? 3'h3 : Repeater_io_deq_bits_size; // @[Fragmenter.scala 265:24:freechips.rocketchip.system.LowRiscConfig.fir@70480.4]
assign _T_333 = 13'h3f << Repeater_io_deq_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70482.4]
assign _T_334 = _T_333[5:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70483.4]
assign _T_335 = ~ _T_334; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70484.4]
assign _T_337 = 10'h7 << _T_331; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70486.4]
assign _T_338 = _T_337[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70487.4]
assign _T_339 = ~ _T_338; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70488.4]
assign _T_345 = _T_344 == 3'h0; // @[Fragmenter.scala 272:29:freechips.rocketchip.system.LowRiscConfig.fir@70493.4]
assign _T_346 = _T_335[5:3]; // @[Fragmenter.scala 273:48:freechips.rocketchip.system.LowRiscConfig.fir@70494.4]
assign _T_347 = _T_344 - 3'h1; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@70495.4]
assign _T_348 = $unsigned(_T_347); // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@70496.4]
assign _T_349 = _T_348[2:0]; // @[Fragmenter.scala 273:79:freechips.rocketchip.system.LowRiscConfig.fir@70497.4]
assign _T_350 = _T_345 ? _T_346 : _T_349; // @[Fragmenter.scala 273:30:freechips.rocketchip.system.LowRiscConfig.fir@70498.4]
assign _T_351 = ~ _T_350; // @[Fragmenter.scala 274:28:freechips.rocketchip.system.LowRiscConfig.fir@70499.4]
assign _T_354 = ~ _T_351; // @[Fragmenter.scala 274:26:freechips.rocketchip.system.LowRiscConfig.fir@70502.4]
assign _GEN_5 = _T_345 ? _T_248 : _T_362; // @[Reg.scala 12:19:freechips.rocketchip.system.LowRiscConfig.fir@70510.4]
assign _T_364 = _GEN_5 == 1'h0; // @[Fragmenter.scala 277:23:freechips.rocketchip.system.LowRiscConfig.fir@70514.4]
assign _T_92_a_valid = Repeater_io_deq_valid; // @[Nodes.scala 332:76:freechips.rocketchip.system.LowRiscConfig.fir@70374.4 Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@70523.4]
assign _T_365 = auto_out_a_ready & _T_92_a_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@70515.4]
assign _GEN_11 = {{3'd0}, _T_350}; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@70524.4]
assign _T_369 = _GEN_11 << 3; // @[Fragmenter.scala 284:65:freechips.rocketchip.system.LowRiscConfig.fir@70524.4]
assign _T_370 = ~ _T_335; // @[Fragmenter.scala 284:90:freechips.rocketchip.system.LowRiscConfig.fir@70525.4]
assign _T_371 = _T_369 | _T_370; // @[Fragmenter.scala 284:88:freechips.rocketchip.system.LowRiscConfig.fir@70526.4]
assign _GEN_12 = {{3'd0}, _T_339}; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@70527.4]
assign _T_372 = _T_371 | _GEN_12; // @[Fragmenter.scala 284:100:freechips.rocketchip.system.LowRiscConfig.fir@70527.4]
assign _T_373 = _T_372 | 6'h7; // @[Fragmenter.scala 284:111:freechips.rocketchip.system.LowRiscConfig.fir@70528.4]
assign _T_374 = ~ _T_373; // @[Fragmenter.scala 284:51:freechips.rocketchip.system.LowRiscConfig.fir@70529.4]
assign _GEN_13 = {{11'd0}, _T_374}; // @[Fragmenter.scala 284:49:freechips.rocketchip.system.LowRiscConfig.fir@70530.4]
assign _T_376 = {Repeater_io_deq_bits_source,_T_364}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70532.4]
assign _T_378 = Repeater_io_full == 1'h0; // @[Fragmenter.scala 289:17:freechips.rocketchip.system.LowRiscConfig.fir@70536.4]
assign _T_385 = Repeater_io_deq_bits_mask == 8'hff; // @[Fragmenter.scala 292:53:freechips.rocketchip.system.LowRiscConfig.fir@70548.4]
assign _T_386 = _T_378 | _T_385; // @[Fragmenter.scala 292:35:freechips.rocketchip.system.LowRiscConfig.fir@70549.4]
assign _T_388 = _T_386 | reset; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@70551.4]
assign _T_389 = _T_388 == 1'h0; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@70552.4]
assign auto_in_a_ready = Repeater_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70377.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70377.4]
assign auto_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70377.4]
assign auto_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70377.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70377.4]
assign auto_out_a_valid = Repeater_io_deq_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_opcode = Repeater_io_deq_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_param = Repeater_io_deq_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_size = _T_331[1:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_source = {_T_376,_T_354}; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_address = Repeater_io_deq_bits_address | _GEN_13; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_mask = Repeater_io_full ? 8'hff : auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_a_bits_corrupt = Repeater_io_deq_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70376.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70339.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70340.4]
assign TLMonitor_io_in_a_ready = Repeater_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_d_bits_size = _T_250 ? _T_290 : _T_246; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source[8:4]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@70373.4]
assign Repeater_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70456.4]
assign Repeater_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70457.4]
assign Repeater_io_repeat = _T_354 != 3'h0; // @[Fragmenter.scala 282:28:freechips.rocketchip.system.LowRiscConfig.fir@70522.4]
assign Repeater_io_enq_valid = auto_in_a_valid; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_opcode = auto_in_a_bits_opcode; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_param = auto_in_a_bits_param; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_size = auto_in_a_bits_size; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_source = auto_in_a_bits_source; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_address = auto_in_a_bits_address; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_mask = auto_in_a_bits_mask; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_enq_bits_corrupt = auto_in_a_bits_corrupt; // @[Fragmenter.scala 243:25:freechips.rocketchip.system.LowRiscConfig.fir@70458.4]
assign Repeater_io_deq_ready = auto_out_a_ready; // @[Fragmenter.scala 283:15:freechips.rocketchip.system.LowRiscConfig.fir@70523.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_244 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_246 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_248 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_344 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_362 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_244 <= 3'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_244 <= _T_249;
end else begin
_T_244 <= _T_294;
end
end
end
if (_T_291) begin
if (_T_250) begin
_T_246 <= _T_290;
end
end
if (reset) begin
_T_248 <= 1'h0;
end else begin
if (_T_291) begin
if (_T_250) begin
_T_248 <= _T_296;
end
end
end
if (reset) begin
_T_344 <= 3'h0;
end else begin
if (_T_365) begin
_T_344 <= _T_354;
end
end
if (_T_345) begin
_T_362 <= _T_248;
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:183 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n"); // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@70402.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Fragmenter.scala 183:16:freechips.rocketchip.system.LowRiscConfig.fir@70403.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:289 assert (!repeater.io.full || !aHasData)\n"); // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@70543.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Fragmenter.scala 289:16:freechips.rocketchip.system.LowRiscConfig.fir@70544.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_389) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:292 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n"); // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@70554.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_389) begin
$fatal; // @[Fragmenter.scala 292:16:freechips.rocketchip.system.LowRiscConfig.fir@70555.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module SimpleLazyModule_13( // @[:freechips.rocketchip.system.LowRiscConfig.fir@70566.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70567.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70568.4]
output auto_fragmenter_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input auto_fragmenter_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [2:0] auto_fragmenter_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [2:0] auto_fragmenter_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [2:0] auto_fragmenter_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [4:0] auto_fragmenter_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [16:0] auto_fragmenter_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [7:0] auto_fragmenter_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input auto_fragmenter_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input auto_fragmenter_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output auto_fragmenter_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [2:0] auto_fragmenter_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [4:0] auto_fragmenter_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [63:0] auto_fragmenter_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input auto_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output auto_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [2:0] auto_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [2:0] auto_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [1:0] auto_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [8:0] auto_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [16:0] auto_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output [7:0] auto_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output auto_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
output auto_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input auto_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [1:0] auto_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [8:0] auto_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
input [63:0] auto_fragmenter_out_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@70569.4]
);
wire fragmenter_clock; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_reset; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_in_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_in_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [2:0] fragmenter_auto_in_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [2:0] fragmenter_auto_in_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [2:0] fragmenter_auto_in_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [4:0] fragmenter_auto_in_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [16:0] fragmenter_auto_in_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [7:0] fragmenter_auto_in_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_in_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_in_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_in_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [2:0] fragmenter_auto_in_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [4:0] fragmenter_auto_in_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [63:0] fragmenter_auto_in_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_out_a_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_out_a_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [2:0] fragmenter_auto_out_a_bits_opcode; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [2:0] fragmenter_auto_out_a_bits_param; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [1:0] fragmenter_auto_out_a_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [8:0] fragmenter_auto_out_a_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [16:0] fragmenter_auto_out_a_bits_address; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [7:0] fragmenter_auto_out_a_bits_mask; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_out_a_bits_corrupt; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_out_d_ready; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire fragmenter_auto_out_d_valid; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [1:0] fragmenter_auto_out_d_bits_size; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [8:0] fragmenter_auto_out_d_bits_source; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
wire [63:0] fragmenter_auto_out_d_bits_data; // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
TLFragmenter_3 fragmenter ( // @[Fragmenter.scala 311:32:freechips.rocketchip.system.LowRiscConfig.fir@70574.4]
.clock(fragmenter_clock),
.reset(fragmenter_reset),
.auto_in_a_ready(fragmenter_auto_in_a_ready),
.auto_in_a_valid(fragmenter_auto_in_a_valid),
.auto_in_a_bits_opcode(fragmenter_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fragmenter_auto_in_a_bits_param),
.auto_in_a_bits_size(fragmenter_auto_in_a_bits_size),
.auto_in_a_bits_source(fragmenter_auto_in_a_bits_source),
.auto_in_a_bits_address(fragmenter_auto_in_a_bits_address),
.auto_in_a_bits_mask(fragmenter_auto_in_a_bits_mask),
.auto_in_a_bits_corrupt(fragmenter_auto_in_a_bits_corrupt),
.auto_in_d_ready(fragmenter_auto_in_d_ready),
.auto_in_d_valid(fragmenter_auto_in_d_valid),
.auto_in_d_bits_size(fragmenter_auto_in_d_bits_size),
.auto_in_d_bits_source(fragmenter_auto_in_d_bits_source),
.auto_in_d_bits_data(fragmenter_auto_in_d_bits_data),
.auto_out_a_ready(fragmenter_auto_out_a_ready),
.auto_out_a_valid(fragmenter_auto_out_a_valid),
.auto_out_a_bits_opcode(fragmenter_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fragmenter_auto_out_a_bits_param),
.auto_out_a_bits_size(fragmenter_auto_out_a_bits_size),
.auto_out_a_bits_source(fragmenter_auto_out_a_bits_source),
.auto_out_a_bits_address(fragmenter_auto_out_a_bits_address),
.auto_out_a_bits_mask(fragmenter_auto_out_a_bits_mask),
.auto_out_a_bits_corrupt(fragmenter_auto_out_a_bits_corrupt),
.auto_out_d_ready(fragmenter_auto_out_d_ready),
.auto_out_d_valid(fragmenter_auto_out_d_valid),
.auto_out_d_bits_size(fragmenter_auto_out_d_bits_size),
.auto_out_d_bits_source(fragmenter_auto_out_d_bits_source),
.auto_out_d_bits_data(fragmenter_auto_out_d_bits_data)
);
assign auto_fragmenter_in_a_ready = fragmenter_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign auto_fragmenter_in_d_valid = fragmenter_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign auto_fragmenter_in_d_bits_size = fragmenter_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign auto_fragmenter_in_d_bits_source = fragmenter_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign auto_fragmenter_in_d_bits_data = fragmenter_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign auto_fragmenter_out_a_valid = fragmenter_auto_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_opcode = fragmenter_auto_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_param = fragmenter_auto_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_size = fragmenter_auto_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_source = fragmenter_auto_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_address = fragmenter_auto_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_mask = fragmenter_auto_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_a_bits_corrupt = fragmenter_auto_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign auto_fragmenter_out_d_ready = fragmenter_auto_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign fragmenter_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70578.4]
assign fragmenter_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@70579.4]
assign fragmenter_auto_in_a_valid = auto_fragmenter_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_opcode = auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_param = auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_size = auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_source = auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_address = auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_mask = auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_a_bits_corrupt = auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_in_d_ready = auto_fragmenter_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@70581.4]
assign fragmenter_auto_out_a_ready = auto_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign fragmenter_auto_out_d_valid = auto_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign fragmenter_auto_out_d_bits_size = auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign fragmenter_auto_out_d_bits_source = auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
assign fragmenter_auto_out_d_bits_data = auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@70580.4]
endmodule
module TLMonitor_30( // @[:freechips.rocketchip.system.LowRiscConfig.fir@70590.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70591.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70592.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [3:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [4:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [3:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input [4:0] io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@70593.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@72180.4]
wire [2:0] _T_22; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@70610.6]
wire _T_23; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@70611.6]
wire _T_28; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@70616.6]
wire _T_29; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@70617.6]
wire [1:0] _T_32; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@70620.6]
wire _T_33; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@70621.6]
wire _T_41; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@70629.6]
wire _T_57; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70641.6]
wire _T_58; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70642.6]
wire _T_59; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70643.6]
wire _T_60; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70644.6]
wire [26:0] _T_62; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70646.6]
wire [11:0] _T_63; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70647.6]
wire [11:0] _T_64; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70648.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@70649.6]
wire [27:0] _T_65; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@70649.6]
wire _T_66; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@70650.6]
wire [1:0] _T_68; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@70652.6]
wire [3:0] _T_69; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@70653.6]
wire [2:0] _T_70; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@70654.6]
wire [2:0] _T_71; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@70655.6]
wire _T_72; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@70656.6]
wire _T_73; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@70657.6]
wire _T_74; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@70658.6]
wire _T_75; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@70659.6]
wire _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70661.6]
wire _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70662.6]
wire _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70664.6]
wire _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70665.6]
wire _T_82; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@70666.6]
wire _T_83; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@70667.6]
wire _T_84; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@70668.6]
wire _T_85; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70669.6]
wire _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70670.6]
wire _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70671.6]
wire _T_88; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70672.6]
wire _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70673.6]
wire _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70674.6]
wire _T_91; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70675.6]
wire _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70676.6]
wire _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70677.6]
wire _T_94; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70678.6]
wire _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70679.6]
wire _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70680.6]
wire _T_97; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@70681.6]
wire _T_98; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@70682.6]
wire _T_99; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@70683.6]
wire _T_100; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70684.6]
wire _T_101; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70685.6]
wire _T_102; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70686.6]
wire _T_103; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70687.6]
wire _T_104; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70688.6]
wire _T_105; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70689.6]
wire _T_106; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70690.6]
wire _T_107; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70691.6]
wire _T_108; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70692.6]
wire _T_109; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70693.6]
wire _T_110; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70694.6]
wire _T_111; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70695.6]
wire _T_112; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70696.6]
wire _T_113; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70697.6]
wire _T_114; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70698.6]
wire _T_115; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70699.6]
wire _T_116; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70700.6]
wire _T_117; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70701.6]
wire _T_118; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70702.6]
wire _T_119; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70703.6]
wire _T_120; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70704.6]
wire _T_121; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70705.6]
wire _T_122; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70706.6]
wire _T_123; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70707.6]
wire [7:0] _T_130; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70714.6]
wire [28:0] _T_141; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70725.6]
wire _T_199; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@70787.6]
wire [27:0] _T_201; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70790.8]
wire [28:0] _T_202; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70791.8]
wire [28:0] _T_203; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70792.8]
wire [28:0] _T_204; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70793.8]
wire _T_205; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70794.8]
wire [27:0] _T_206; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70795.8]
wire [28:0] _T_207; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70796.8]
wire [28:0] _T_208; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70797.8]
wire [28:0] _T_209; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70798.8]
wire _T_210; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70799.8]
wire [27:0] _T_211; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70800.8]
wire [28:0] _T_212; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70801.8]
wire [28:0] _T_213; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70802.8]
wire [28:0] _T_214; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70803.8]
wire _T_215; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70804.8]
wire [28:0] _T_218; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70807.8]
wire [28:0] _T_219; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70808.8]
wire _T_220; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70809.8]
wire [27:0] _T_221; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70810.8]
wire [28:0] _T_222; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70811.8]
wire [28:0] _T_223; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70812.8]
wire [28:0] _T_224; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70813.8]
wire _T_225; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70814.8]
wire _T_226; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@70815.8]
wire _T_227; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@70816.8]
wire _T_228; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@70817.8]
wire _T_234; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@70823.8]
wire _T_272; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@70861.8]
wire _T_274; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@70862.8]
wire _T_286; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@70874.8]
wire _T_287; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@70875.8]
wire _T_289; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@70881.8]
wire _T_290; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@70882.8]
wire _T_293; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@70889.8]
wire _T_294; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@70890.8]
wire _T_296; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@70896.8]
wire _T_297; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@70897.8]
wire _T_298; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@70902.8]
wire _T_300; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@70904.8]
wire _T_301; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@70905.8]
wire [7:0] _T_302; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@70910.8]
wire _T_303; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@70911.8]
wire _T_305; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@70913.8]
wire _T_306; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@70914.8]
wire _T_307; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@70919.8]
wire _T_309; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@70921.8]
wire _T_310; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@70922.8]
wire _T_311; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@70928.6]
wire _T_414; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@71051.8]
wire _T_416; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@71053.8]
wire _T_417; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@71054.8]
wire _T_427; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@71077.6]
wire _T_429; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@71080.8]
wire _T_452; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@71103.8]
wire _T_453; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@71104.8]
wire _T_454; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@71105.8]
wire _T_455; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71106.8]
wire _T_457; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@71108.8]
wire _T_465; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71116.8]
wire _T_467; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@71118.8]
wire _T_469; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71120.8]
wire _T_470; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71121.8]
wire _T_477; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@71140.8]
wire _T_479; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@71142.8]
wire _T_480; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@71143.8]
wire _T_481; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@71148.8]
wire _T_483; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@71150.8]
wire _T_484; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@71151.8]
wire _T_489; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@71165.6]
wire _T_518; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71195.8]
wire _T_531; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@71208.8]
wire _T_533; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71210.8]
wire _T_534; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71211.8]
wire _T_549; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@71247.6]
wire [7:0] _T_605; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@71320.8]
wire [7:0] _T_606; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@71321.8]
wire _T_607; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@71322.8]
wire _T_609; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@71324.8]
wire _T_610; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@71325.8]
wire _T_611; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@71331.6]
wire _T_620; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@71341.8]
wire _T_646; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71367.8]
wire _T_650; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71371.8]
wire _T_651; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71372.8]
wire _T_658; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@71391.8]
wire _T_660; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@71393.8]
wire _T_661; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@71394.8]
wire _T_666; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@71408.6]
wire _T_713; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@71468.8]
wire _T_715; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@71470.8]
wire _T_716; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@71471.8]
wire _T_721; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@71485.6]
wire _T_760; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71525.8]
wire _T_761; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71526.8]
wire _T_776; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@71564.6]
wire _T_778; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@71566.6]
wire _T_779; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@71567.6]
wire [2:0] _T_782; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@71574.6]
wire _T_783; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@71575.6]
wire _T_788; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@71580.6]
wire _T_789; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@71581.6]
wire [1:0] _T_792; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@71584.6]
wire _T_793; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@71585.6]
wire _T_801; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@71593.6]
wire _T_817; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71605.6]
wire _T_818; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71606.6]
wire _T_819; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71607.6]
wire _T_820; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71608.6]
wire _T_822; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@71610.6]
wire _T_824; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71613.8]
wire _T_825; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71614.8]
wire _T_826; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@71619.8]
wire _T_828; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@71621.8]
wire _T_829; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@71622.8]
wire _T_830; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@71627.8]
wire _T_832; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@71629.8]
wire _T_833; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@71630.8]
wire _T_834; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@71635.8]
wire _T_836; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@71637.8]
wire _T_837; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@71638.8]
wire _T_838; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@71643.8]
wire _T_840; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@71645.8]
wire _T_841; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@71646.8]
wire _T_842; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@71652.6]
wire _T_853; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@71676.8]
wire _T_855; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@71678.8]
wire _T_856; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@71679.8]
wire _T_857; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@71684.8]
wire _T_859; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@71686.8]
wire _T_860; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@71687.8]
wire _T_870; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@71710.6]
wire _T_890; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@71751.8]
wire _T_892; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@71753.8]
wire _T_893; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@71754.8]
wire _T_899; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@71769.6]
wire _T_916; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@71804.6]
wire _T_934; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@71840.6]
wire _T_963; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@71900.4]
wire [8:0] _T_968; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@71905.4]
wire _T_969; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@71906.4]
wire _T_970; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@71907.4]
reg [8:0] _T_973; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@71909.4]
reg [31:0] _RAND_0;
wire [9:0] _T_974; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71910.4]
wire [9:0] _T_975; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71911.4]
wire [8:0] _T_976; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71912.4]
wire _T_977; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@71913.4]
reg [2:0] _T_986; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@71924.4]
reg [31:0] _RAND_1;
reg [2:0] _T_988; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@71925.4]
reg [31:0] _RAND_2;
reg [3:0] _T_990; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@71926.4]
reg [31:0] _RAND_3;
reg [4:0] _T_992; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@71927.4]
reg [31:0] _RAND_4;
reg [27:0] _T_994; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@71928.4]
reg [31:0] _RAND_5;
wire _T_995; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@71929.4]
wire _T_996; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@71930.4]
wire _T_997; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@71932.6]
wire _T_999; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@71934.6]
wire _T_1000; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@71935.6]
wire _T_1001; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@71940.6]
wire _T_1003; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@71942.6]
wire _T_1004; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@71943.6]
wire _T_1005; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@71948.6]
wire _T_1007; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@71950.6]
wire _T_1008; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@71951.6]
wire _T_1009; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@71956.6]
wire _T_1011; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@71958.6]
wire _T_1012; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@71959.6]
wire _T_1013; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@71964.6]
wire _T_1015; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@71966.6]
wire _T_1016; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@71967.6]
wire _T_1018; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@71974.4]
wire _T_1019; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@71982.4]
wire [26:0] _T_1021; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@71984.4]
wire [11:0] _T_1022; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@71985.4]
wire [11:0] _T_1023; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@71986.4]
wire [8:0] _T_1024; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@71987.4]
wire _T_1025; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@71988.4]
reg [8:0] _T_1028; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@71990.4]
reg [31:0] _RAND_6;
wire [9:0] _T_1029; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71991.4]
wire [9:0] _T_1030; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71992.4]
wire [8:0] _T_1031; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71993.4]
wire _T_1032; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@71994.4]
reg [2:0] _T_1041; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@72005.4]
reg [31:0] _RAND_7;
reg [1:0] _T_1043; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@72006.4]
reg [31:0] _RAND_8;
reg [3:0] _T_1045; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@72007.4]
reg [31:0] _RAND_9;
reg [4:0] _T_1047; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@72008.4]
reg [31:0] _RAND_10;
reg _T_1049; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@72009.4]
reg [31:0] _RAND_11;
reg _T_1051; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@72010.4]
reg [31:0] _RAND_12;
wire _T_1052; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@72011.4]
wire _T_1053; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@72012.4]
wire _T_1054; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@72014.6]
wire _T_1056; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@72016.6]
wire _T_1057; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@72017.6]
wire _T_1058; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@72022.6]
wire _T_1060; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@72024.6]
wire _T_1061; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@72025.6]
wire _T_1062; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@72030.6]
wire _T_1064; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@72032.6]
wire _T_1065; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@72033.6]
wire _T_1066; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@72038.6]
wire _T_1068; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@72040.6]
wire _T_1069; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@72041.6]
wire _T_1070; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@72046.6]
wire _T_1072; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@72048.6]
wire _T_1073; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@72049.6]
wire _T_1074; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@72054.6]
wire _T_1076; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@72056.6]
wire _T_1077; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@72057.6]
wire _T_1079; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@72064.4]
reg [24:0] _T_1081; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@72073.4]
reg [31:0] _RAND_13;
reg [8:0] _T_1092; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@72083.4]
reg [31:0] _RAND_14;
wire [9:0] _T_1093; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72084.4]
wire [9:0] _T_1094; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72085.4]
wire [8:0] _T_1095; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72086.4]
wire _T_1096; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@72087.4]
reg [8:0] _T_1113; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@72106.4]
reg [31:0] _RAND_15;
wire [9:0] _T_1114; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72107.4]
wire [9:0] _T_1115; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72108.4]
wire [8:0] _T_1116; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72109.4]
wire _T_1117; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@72110.4]
wire _T_1128; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@72125.4]
wire [31:0] _T_1130; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@72128.6]
wire [24:0] _T_1131; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@72130.6]
wire _T_1132; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@72131.6]
wire _T_1133; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@72132.6]
wire _T_1135; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@72134.6]
wire _T_1136; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@72135.6]
wire [31:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@72127.4]
wire _T_1141; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@72146.4]
wire _T_1143; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@72148.4]
wire _T_1144; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@72149.4]
wire [31:0] _T_1145; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@72151.6]
wire [24:0] _T_1126; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72121.4 :freechips.rocketchip.system.LowRiscConfig.fir@72123.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@72129.6]
wire [24:0] _T_1146; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@72153.6]
wire [24:0] _T_1147; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@72154.6]
wire _T_1148; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@72155.6]
wire _T_1150; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@72157.6]
wire _T_1151; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@72158.6]
wire [31:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@72150.4]
wire [24:0] _T_1138; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72141.4 :freechips.rocketchip.system.LowRiscConfig.fir@72143.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@72152.6]
wire _T_1152; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@72164.4]
wire _T_1153; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@72165.4]
wire _T_1154; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@72166.4]
wire _T_1155; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@72167.4]
wire _T_1157; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@72169.4]
wire _T_1158; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@72170.4]
wire [24:0] _T_1159; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@72175.4]
wire [24:0] _T_1160; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@72176.4]
wire [24:0] _T_1161; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@72177.4]
reg [31:0] _T_1163; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@72179.4]
reg [31:0] _RAND_16;
wire _T_1164; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@72182.4]
wire _T_1165; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@72183.4]
wire _T_1166; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@72184.4]
wire _T_1167; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@72185.4]
wire _T_1168; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@72186.4]
wire _T_1169; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@72187.4]
wire _T_1171; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@72189.4]
wire _T_1172; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@72190.4]
wire [31:0] _T_1174; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@72196.4]
wire _T_1177; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@72200.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@70825.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@70966.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71123.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71213.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@71295.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71374.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@71451.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71528.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71616.10]
wire _GEN_125; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@71658.10]
wire _GEN_137; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@71716.10]
wire _GEN_149; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@71775.10]
wire _GEN_155; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@71810.10]
wire _GEN_161; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@71846.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@72180.4]
.out(plusarg_reader_out)
);
assign _T_22 = io_in_a_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@70610.6]
assign _T_23 = _T_22 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@70611.6]
assign _T_28 = io_in_a_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@70616.6]
assign _T_29 = io_in_a_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@70617.6]
assign _T_32 = io_in_a_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@70620.6]
assign _T_33 = _T_32 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@70621.6]
assign _T_41 = _T_32 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@70629.6]
assign _T_57 = _T_23 | _T_28; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70641.6]
assign _T_58 = _T_57 | _T_29; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70642.6]
assign _T_59 = _T_58 | _T_33; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70643.6]
assign _T_60 = _T_59 | _T_41; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@70644.6]
assign _T_62 = 27'hfff << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@70646.6]
assign _T_63 = _T_62[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@70647.6]
assign _T_64 = ~ _T_63; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@70648.6]
assign _GEN_18 = {{16'd0}, _T_64}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@70649.6]
assign _T_65 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@70649.6]
assign _T_66 = _T_65 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@70650.6]
assign _T_68 = io_in_a_bits_size[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@70652.6]
assign _T_69 = 4'h1 << _T_68; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@70653.6]
assign _T_70 = _T_69[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@70654.6]
assign _T_71 = _T_70 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@70655.6]
assign _T_72 = io_in_a_bits_size >= 4'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@70656.6]
assign _T_73 = _T_71[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@70657.6]
assign _T_74 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@70658.6]
assign _T_75 = _T_74 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@70659.6]
assign _T_77 = _T_73 & _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70661.6]
assign _T_78 = _T_72 | _T_77; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70662.6]
assign _T_80 = _T_73 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70664.6]
assign _T_81 = _T_72 | _T_80; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70665.6]
assign _T_82 = _T_71[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@70666.6]
assign _T_83 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@70667.6]
assign _T_84 = _T_83 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@70668.6]
assign _T_85 = _T_75 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70669.6]
assign _T_86 = _T_82 & _T_85; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70670.6]
assign _T_87 = _T_78 | _T_86; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70671.6]
assign _T_88 = _T_75 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70672.6]
assign _T_89 = _T_82 & _T_88; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70673.6]
assign _T_90 = _T_78 | _T_89; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70674.6]
assign _T_91 = _T_74 & _T_84; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70675.6]
assign _T_92 = _T_82 & _T_91; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70676.6]
assign _T_93 = _T_81 | _T_92; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70677.6]
assign _T_94 = _T_74 & _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70678.6]
assign _T_95 = _T_82 & _T_94; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70679.6]
assign _T_96 = _T_81 | _T_95; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70680.6]
assign _T_97 = _T_71[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@70681.6]
assign _T_98 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@70682.6]
assign _T_99 = _T_98 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@70683.6]
assign _T_100 = _T_85 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70684.6]
assign _T_101 = _T_97 & _T_100; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70685.6]
assign _T_102 = _T_87 | _T_101; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70686.6]
assign _T_103 = _T_85 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70687.6]
assign _T_104 = _T_97 & _T_103; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70688.6]
assign _T_105 = _T_87 | _T_104; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70689.6]
assign _T_106 = _T_88 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70690.6]
assign _T_107 = _T_97 & _T_106; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70691.6]
assign _T_108 = _T_90 | _T_107; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70692.6]
assign _T_109 = _T_88 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70693.6]
assign _T_110 = _T_97 & _T_109; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70694.6]
assign _T_111 = _T_90 | _T_110; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70695.6]
assign _T_112 = _T_91 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70696.6]
assign _T_113 = _T_97 & _T_112; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70697.6]
assign _T_114 = _T_93 | _T_113; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70698.6]
assign _T_115 = _T_91 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70699.6]
assign _T_116 = _T_97 & _T_115; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70700.6]
assign _T_117 = _T_93 | _T_116; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70701.6]
assign _T_118 = _T_94 & _T_99; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70702.6]
assign _T_119 = _T_97 & _T_118; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70703.6]
assign _T_120 = _T_96 | _T_119; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70704.6]
assign _T_121 = _T_94 & _T_98; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@70705.6]
assign _T_122 = _T_97 & _T_121; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@70706.6]
assign _T_123 = _T_96 | _T_122; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@70707.6]
assign _T_130 = {_T_123,_T_120,_T_117,_T_114,_T_111,_T_108,_T_105,_T_102}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@70714.6]
assign _T_141 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70725.6]
assign _T_199 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@70787.6]
assign _T_201 = io_in_a_bits_address ^ 28'h3000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70790.8]
assign _T_202 = {1'b0,$signed(_T_201)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70791.8]
assign _T_203 = $signed(_T_202) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70792.8]
assign _T_204 = $signed(_T_203); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70793.8]
assign _T_205 = $signed(_T_204) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70794.8]
assign _T_206 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70795.8]
assign _T_207 = {1'b0,$signed(_T_206)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70796.8]
assign _T_208 = $signed(_T_207) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70797.8]
assign _T_209 = $signed(_T_208); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70798.8]
assign _T_210 = $signed(_T_209) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70799.8]
assign _T_211 = io_in_a_bits_address ^ 28'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70800.8]
assign _T_212 = {1'b0,$signed(_T_211)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70801.8]
assign _T_213 = $signed(_T_212) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70802.8]
assign _T_214 = $signed(_T_213); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70803.8]
assign _T_215 = $signed(_T_214) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70804.8]
assign _T_218 = $signed(_T_141) & $signed(-29'sh1000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70807.8]
assign _T_219 = $signed(_T_218); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70808.8]
assign _T_220 = $signed(_T_219) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70809.8]
assign _T_221 = io_in_a_bits_address ^ 28'h10000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@70810.8]
assign _T_222 = {1'b0,$signed(_T_221)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@70811.8]
assign _T_223 = $signed(_T_222) & $signed(-29'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70812.8]
assign _T_224 = $signed(_T_223); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@70813.8]
assign _T_225 = $signed(_T_224) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@70814.8]
assign _T_226 = _T_205 | _T_210; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@70815.8]
assign _T_227 = _T_226 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@70816.8]
assign _T_228 = _T_227 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@70817.8]
assign _T_234 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@70823.8]
assign _T_272 = 4'h6 == io_in_a_bits_size; // @[Parameters.scala 89:48:freechips.rocketchip.system.LowRiscConfig.fir@70861.8]
assign _T_274 = _T_23 ? _T_272 : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@70862.8]
assign _T_286 = _T_274 | reset; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@70874.8]
assign _T_287 = _T_286 == 1'h0; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@70875.8]
assign _T_289 = _T_60 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@70881.8]
assign _T_290 = _T_289 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@70882.8]
assign _T_293 = _T_72 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@70889.8]
assign _T_294 = _T_293 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@70890.8]
assign _T_296 = _T_66 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@70896.8]
assign _T_297 = _T_296 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@70897.8]
assign _T_298 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@70902.8]
assign _T_300 = _T_298 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@70904.8]
assign _T_301 = _T_300 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@70905.8]
assign _T_302 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@70910.8]
assign _T_303 = _T_302 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@70911.8]
assign _T_305 = _T_303 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@70913.8]
assign _T_306 = _T_305 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@70914.8]
assign _T_307 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@70919.8]
assign _T_309 = _T_307 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@70921.8]
assign _T_310 = _T_309 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@70922.8]
assign _T_311 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@70928.6]
assign _T_414 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@71051.8]
assign _T_416 = _T_414 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@71053.8]
assign _T_417 = _T_416 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@71054.8]
assign _T_427 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@71077.6]
assign _T_429 = io_in_a_bits_size <= 4'h6; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@71080.8]
assign _T_452 = _T_210 | _T_215; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@71103.8]
assign _T_453 = _T_452 | _T_220; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@71104.8]
assign _T_454 = _T_453 | _T_225; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@71105.8]
assign _T_455 = _T_429 & _T_454; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71106.8]
assign _T_457 = io_in_a_bits_size <= 4'hc; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@71108.8]
assign _T_465 = _T_457 & _T_205; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71116.8]
assign _T_467 = _T_455 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@71118.8]
assign _T_469 = _T_467 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71120.8]
assign _T_470 = _T_469 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71121.8]
assign _T_477 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@71140.8]
assign _T_479 = _T_477 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@71142.8]
assign _T_480 = _T_479 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@71143.8]
assign _T_481 = io_in_a_bits_mask == _T_130; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@71148.8]
assign _T_483 = _T_481 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@71150.8]
assign _T_484 = _T_483 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@71151.8]
assign _T_489 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@71165.6]
assign _T_518 = _T_429 & _T_453; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71195.8]
assign _T_531 = _T_518 | _T_465; // @[Parameters.scala 173:30:freechips.rocketchip.system.LowRiscConfig.fir@71208.8]
assign _T_533 = _T_531 | reset; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71210.8]
assign _T_534 = _T_533 == 1'h0; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71211.8]
assign _T_549 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@71247.6]
assign _T_605 = ~ _T_130; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@71320.8]
assign _T_606 = io_in_a_bits_mask & _T_605; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@71321.8]
assign _T_607 = _T_606 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@71322.8]
assign _T_609 = _T_607 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@71324.8]
assign _T_610 = _T_609 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@71325.8]
assign _T_611 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@71331.6]
assign _T_620 = io_in_a_bits_size <= 4'h3; // @[Parameters.scala 90:42:freechips.rocketchip.system.LowRiscConfig.fir@71341.8]
assign _T_646 = _T_620 & _T_228; // @[Parameters.scala 171:56:freechips.rocketchip.system.LowRiscConfig.fir@71367.8]
assign _T_650 = _T_646 | reset; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71371.8]
assign _T_651 = _T_650 == 1'h0; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71372.8]
assign _T_658 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@71391.8]
assign _T_660 = _T_658 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@71393.8]
assign _T_661 = _T_660 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@71394.8]
assign _T_666 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@71408.6]
assign _T_713 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@71468.8]
assign _T_715 = _T_713 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@71470.8]
assign _T_716 = _T_715 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@71471.8]
assign _T_721 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@71485.6]
assign _T_760 = _T_465 | reset; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71525.8]
assign _T_761 = _T_760 == 1'h0; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71526.8]
assign _T_776 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@71564.6]
assign _T_778 = _T_776 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@71566.6]
assign _T_779 = _T_778 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@71567.6]
assign _T_782 = io_in_d_bits_source[4:2]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@71574.6]
assign _T_783 = _T_782 == 3'h4; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@71575.6]
assign _T_788 = io_in_d_bits_source == 5'h14; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@71580.6]
assign _T_789 = io_in_d_bits_source == 5'h18; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@71581.6]
assign _T_792 = io_in_d_bits_source[4:3]; // @[Parameters.scala 52:10:freechips.rocketchip.system.LowRiscConfig.fir@71584.6]
assign _T_793 = _T_792 == 2'h0; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@71585.6]
assign _T_801 = _T_792 == 2'h1; // @[Parameters.scala 52:32:freechips.rocketchip.system.LowRiscConfig.fir@71593.6]
assign _T_817 = _T_783 | _T_788; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71605.6]
assign _T_818 = _T_817 | _T_789; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71606.6]
assign _T_819 = _T_818 | _T_793; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71607.6]
assign _T_820 = _T_819 | _T_801; // @[Parameters.scala 283:46:freechips.rocketchip.system.LowRiscConfig.fir@71608.6]
assign _T_822 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@71610.6]
assign _T_824 = _T_820 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71613.8]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71614.8]
assign _T_826 = io_in_d_bits_size >= 4'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@71619.8]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@71621.8]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@71622.8]
assign _T_830 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@71627.8]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@71629.8]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@71630.8]
assign _T_834 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@71635.8]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@71637.8]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@71638.8]
assign _T_838 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@71643.8]
assign _T_840 = _T_838 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@71645.8]
assign _T_841 = _T_840 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@71646.8]
assign _T_842 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@71652.6]
assign _T_853 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@71676.8]
assign _T_855 = _T_853 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@71678.8]
assign _T_856 = _T_855 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@71679.8]
assign _T_857 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@71684.8]
assign _T_859 = _T_857 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@71686.8]
assign _T_860 = _T_859 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@71687.8]
assign _T_870 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@71710.6]
assign _T_890 = _T_838 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@71751.8]
assign _T_892 = _T_890 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@71753.8]
assign _T_893 = _T_892 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@71754.8]
assign _T_899 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@71769.6]
assign _T_916 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@71804.6]
assign _T_934 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@71840.6]
assign _T_963 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@71900.4]
assign _T_968 = _T_64[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@71905.4]
assign _T_969 = io_in_a_bits_opcode[2]; // @[Edges.scala 92:37:freechips.rocketchip.system.LowRiscConfig.fir@71906.4]
assign _T_970 = _T_969 == 1'h0; // @[Edges.scala 92:28:freechips.rocketchip.system.LowRiscConfig.fir@71907.4]
assign _T_974 = _T_973 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71910.4]
assign _T_975 = $unsigned(_T_974); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71911.4]
assign _T_976 = _T_975[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71912.4]
assign _T_977 = _T_973 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@71913.4]
assign _T_995 = _T_977 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@71929.4]
assign _T_996 = io_in_a_valid & _T_995; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@71930.4]
assign _T_997 = io_in_a_bits_opcode == _T_986; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@71932.6]
assign _T_999 = _T_997 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@71934.6]
assign _T_1000 = _T_999 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@71935.6]
assign _T_1001 = io_in_a_bits_param == _T_988; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@71940.6]
assign _T_1003 = _T_1001 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@71942.6]
assign _T_1004 = _T_1003 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@71943.6]
assign _T_1005 = io_in_a_bits_size == _T_990; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@71948.6]
assign _T_1007 = _T_1005 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@71950.6]
assign _T_1008 = _T_1007 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@71951.6]
assign _T_1009 = io_in_a_bits_source == _T_992; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@71956.6]
assign _T_1011 = _T_1009 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@71958.6]
assign _T_1012 = _T_1011 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@71959.6]
assign _T_1013 = io_in_a_bits_address == _T_994; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@71964.6]
assign _T_1015 = _T_1013 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@71966.6]
assign _T_1016 = _T_1015 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@71967.6]
assign _T_1018 = _T_963 & _T_977; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@71974.4]
assign _T_1019 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@71982.4]
assign _T_1021 = 27'hfff << io_in_d_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@71984.4]
assign _T_1022 = _T_1021[11:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@71985.4]
assign _T_1023 = ~ _T_1022; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@71986.4]
assign _T_1024 = _T_1023[11:3]; // @[Edges.scala 220:59:freechips.rocketchip.system.LowRiscConfig.fir@71987.4]
assign _T_1025 = io_in_d_bits_opcode[0]; // @[Edges.scala 106:36:freechips.rocketchip.system.LowRiscConfig.fir@71988.4]
assign _T_1029 = _T_1028 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71991.4]
assign _T_1030 = $unsigned(_T_1029); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71992.4]
assign _T_1031 = _T_1030[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@71993.4]
assign _T_1032 = _T_1028 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@71994.4]
assign _T_1052 = _T_1032 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@72011.4]
assign _T_1053 = io_in_d_valid & _T_1052; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@72012.4]
assign _T_1054 = io_in_d_bits_opcode == _T_1041; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@72014.6]
assign _T_1056 = _T_1054 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@72016.6]
assign _T_1057 = _T_1056 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@72017.6]
assign _T_1058 = io_in_d_bits_param == _T_1043; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@72022.6]
assign _T_1060 = _T_1058 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@72024.6]
assign _T_1061 = _T_1060 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@72025.6]
assign _T_1062 = io_in_d_bits_size == _T_1045; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@72030.6]
assign _T_1064 = _T_1062 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@72032.6]
assign _T_1065 = _T_1064 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@72033.6]
assign _T_1066 = io_in_d_bits_source == _T_1047; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@72038.6]
assign _T_1068 = _T_1066 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@72040.6]
assign _T_1069 = _T_1068 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@72041.6]
assign _T_1070 = io_in_d_bits_sink == _T_1049; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@72046.6]
assign _T_1072 = _T_1070 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@72048.6]
assign _T_1073 = _T_1072 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@72049.6]
assign _T_1074 = io_in_d_bits_denied == _T_1051; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@72054.6]
assign _T_1076 = _T_1074 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@72056.6]
assign _T_1077 = _T_1076 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@72057.6]
assign _T_1079 = _T_1019 & _T_1032; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@72064.4]
assign _T_1093 = _T_1092 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72084.4]
assign _T_1094 = $unsigned(_T_1093); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72085.4]
assign _T_1095 = _T_1094[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72086.4]
assign _T_1096 = _T_1092 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@72087.4]
assign _T_1114 = _T_1113 - 9'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72107.4]
assign _T_1115 = $unsigned(_T_1114); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72108.4]
assign _T_1116 = _T_1115[8:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@72109.4]
assign _T_1117 = _T_1113 == 9'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@72110.4]
assign _T_1128 = _T_963 & _T_1096; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@72125.4]
assign _T_1130 = 32'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@72128.6]
assign _T_1131 = _T_1081 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@72130.6]
assign _T_1132 = _T_1131[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@72131.6]
assign _T_1133 = _T_1132 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@72132.6]
assign _T_1135 = _T_1133 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@72134.6]
assign _T_1136 = _T_1135 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@72135.6]
assign _GEN_15 = _T_1128 ? _T_1130 : 32'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@72127.4]
assign _T_1141 = _T_1019 & _T_1117; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@72146.4]
assign _T_1143 = _T_822 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@72148.4]
assign _T_1144 = _T_1141 & _T_1143; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@72149.4]
assign _T_1145 = 32'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@72151.6]
assign _T_1126 = _GEN_15[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72121.4 :freechips.rocketchip.system.LowRiscConfig.fir@72123.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@72129.6]
assign _T_1146 = _T_1126 | _T_1081; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@72153.6]
assign _T_1147 = _T_1146 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@72154.6]
assign _T_1148 = _T_1147[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@72155.6]
assign _T_1150 = _T_1148 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@72157.6]
assign _T_1151 = _T_1150 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@72158.6]
assign _GEN_16 = _T_1144 ? _T_1145 : 32'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@72150.4]
assign _T_1138 = _GEN_16[24:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72141.4 :freechips.rocketchip.system.LowRiscConfig.fir@72143.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@72152.6]
assign _T_1152 = _T_1126 != _T_1138; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@72164.4]
assign _T_1153 = _T_1126 != 25'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@72165.4]
assign _T_1154 = _T_1153 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@72166.4]
assign _T_1155 = _T_1152 | _T_1154; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@72167.4]
assign _T_1157 = _T_1155 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@72169.4]
assign _T_1158 = _T_1157 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@72170.4]
assign _T_1159 = _T_1081 | _T_1126; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@72175.4]
assign _T_1160 = ~ _T_1138; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@72176.4]
assign _T_1161 = _T_1159 & _T_1160; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@72177.4]
assign _T_1164 = _T_1081 != 25'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@72182.4]
assign _T_1165 = _T_1164 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@72183.4]
assign _T_1166 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@72184.4]
assign _T_1167 = _T_1165 | _T_1166; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@72185.4]
assign _T_1168 = _T_1163 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@72186.4]
assign _T_1169 = _T_1167 | _T_1168; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@72187.4]
assign _T_1171 = _T_1169 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@72189.4]
assign _T_1172 = _T_1171 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@72190.4]
assign _T_1174 = _T_1163 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@72196.4]
assign _T_1177 = _T_963 | _T_1019; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@72200.4]
assign _GEN_19 = io_in_a_valid & _T_199; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@70825.10]
assign _GEN_35 = io_in_a_valid & _T_311; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@70966.10]
assign _GEN_53 = io_in_a_valid & _T_427; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71123.10]
assign _GEN_65 = io_in_a_valid & _T_489; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71213.10]
assign _GEN_75 = io_in_a_valid & _T_549; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@71295.10]
assign _GEN_85 = io_in_a_valid & _T_611; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71374.10]
assign _GEN_95 = io_in_a_valid & _T_666; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@71451.10]
assign _GEN_105 = io_in_a_valid & _T_721; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71528.10]
assign _GEN_115 = io_in_d_valid & _T_822; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71616.10]
assign _GEN_125 = io_in_d_valid & _T_842; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@71658.10]
assign _GEN_137 = io_in_d_valid & _T_870; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@71716.10]
assign _GEN_149 = io_in_d_valid & _T_899; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@71775.10]
assign _GEN_155 = io_in_d_valid & _T_916; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@71810.10]
assign _GEN_161 = io_in_d_valid & _T_934; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@71846.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_973 = _RAND_0[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_986 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_988 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_990 = _RAND_3[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_992 = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_994 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_1028 = _RAND_6[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_1041 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_1043 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1045 = _RAND_9[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1047 = _RAND_10[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_1049 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_1051 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_1081 = _RAND_13[24:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_1092 = _RAND_14[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_1113 = _RAND_15[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_1163 = _RAND_16[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_973 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_977) begin
if (_T_970) begin
_T_973 <= _T_968;
end else begin
_T_973 <= 9'h0;
end
end else begin
_T_973 <= _T_976;
end
end
end
if (_T_1018) begin
_T_986 <= io_in_a_bits_opcode;
end
if (_T_1018) begin
_T_988 <= io_in_a_bits_param;
end
if (_T_1018) begin
_T_990 <= io_in_a_bits_size;
end
if (_T_1018) begin
_T_992 <= io_in_a_bits_source;
end
if (_T_1018) begin
_T_994 <= io_in_a_bits_address;
end
if (reset) begin
_T_1028 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1032) begin
if (_T_1025) begin
_T_1028 <= _T_1024;
end else begin
_T_1028 <= 9'h0;
end
end else begin
_T_1028 <= _T_1031;
end
end
end
if (_T_1079) begin
_T_1041 <= io_in_d_bits_opcode;
end
if (_T_1079) begin
_T_1043 <= io_in_d_bits_param;
end
if (_T_1079) begin
_T_1045 <= io_in_d_bits_size;
end
if (_T_1079) begin
_T_1047 <= io_in_d_bits_source;
end
if (_T_1079) begin
_T_1049 <= io_in_d_bits_sink;
end
if (_T_1079) begin
_T_1051 <= io_in_d_bits_denied;
end
if (reset) begin
_T_1081 <= 25'h0;
end else begin
_T_1081 <= _T_1161;
end
if (reset) begin
_T_1092 <= 9'h0;
end else begin
if (_T_963) begin
if (_T_1096) begin
if (_T_970) begin
_T_1092 <= _T_968;
end else begin
_T_1092 <= 9'h0;
end
end else begin
_T_1092 <= _T_1095;
end
end
end
if (reset) begin
_T_1113 <= 9'h0;
end else begin
if (_T_1019) begin
if (_T_1117) begin
if (_T_1025) begin
_T_1113 <= _T_1024;
end else begin
_T_1113 <= 9'h0;
end
end else begin
_T_1113 <= _T_1116;
end
end
end
if (reset) begin
_T_1163 <= 32'h0;
end else begin
if (_T_1177) begin
_T_1163 <= 32'h0;
end else begin
_T_1163 <= _T_1174;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@70605.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@70606.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@70784.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@70785.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@70825.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_234) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@70826.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@70877.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_287) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@70878.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@70884.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_290) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@70885.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@70892.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_294) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@70893.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@70899.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_297) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@70900.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@70907.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_301) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@70908.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@70916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_306) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@70917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@70924.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_310) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@70925.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@70966.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_234) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@70967.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@71018.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_287) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@71019.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@71025.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_290) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@71026.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@71033.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_294) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@71034.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@71040.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_297) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@71041.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@71048.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_301) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@71049.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@71056.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_417) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@71057.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@71065.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_306) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@71066.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@71073.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_310) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@71074.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71123.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_470) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@71124.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@71130.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_290) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@71131.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@71137.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_297) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@71138.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@71145.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_480) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@71146.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@71153.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_484) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@71154.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@71161.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_310) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@71162.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71213.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_534) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@71214.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@71220.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_290) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@71221.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@71227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_297) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@71228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@71235.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_480) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@71236.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@71243.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_484) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@71244.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@71295.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_534) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@71296.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@71302.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_290) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@71303.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@71309.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_297) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@71310.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@71317.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_480) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@71318.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@71327.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_610) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@71328.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71374.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_651) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@71375.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@71381.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_290) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@71382.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@71388.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_297) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@71389.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@71396.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_661) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@71397.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@71404.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_484) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@71405.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@71451.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_651) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@71452.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@71458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_290) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@71459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@71465.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_297) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@71466.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@71473.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_716) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@71474.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@71481.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_484) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@71482.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71528.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_761) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@71529.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@71535.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_290) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@71536.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@71542.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_297) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@71543.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@71550.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_484) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@71551.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@71558.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_310) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@71559.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@71569.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_779) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@71570.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71616.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_825) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@71617.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@71624.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_829) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@71625.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@71632.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_833) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@71633.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@71640.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_837) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@71641.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@71648.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_841) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@71649.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@71658.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_825) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@71659.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@71665.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_234) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@71666.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@71673.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_829) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@71674.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@71681.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_856) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@71682.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@71689.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_860) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@71690.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@71697.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_837) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@71698.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@71706.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@71707.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@71716.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_825) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@71717.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@71723.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_234) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@71724.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@71731.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_829) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@71732.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@71739.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_856) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@71740.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@71747.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_860) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@71748.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@71756.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_137 & _T_893) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@71757.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@71765.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@71766.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@71775.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_825) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@71776.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@71783.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_833) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@71784.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@71791.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_149 & _T_837) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@71792.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@71800.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@71801.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@71810.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_825) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@71811.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@71818.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_833) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@71819.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@71827.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_155 & _T_893) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@71828.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@71836.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@71837.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@71846.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_825) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@71847.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@71854.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_833) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@71855.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@71862.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_161 & _T_837) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@71863.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@71871.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@71872.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@71881.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@71882.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@71889.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@71890.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@71897.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@71898.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@71937.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1000) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@71938.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@71945.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1004) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@71946.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@71953.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1008) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@71954.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@71961.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1012) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@71962.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@71969.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_996 & _T_1016) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@71970.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@72019.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1057) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@72020.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@72027.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1061) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@72028.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@72035.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1065) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@72036.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@72043.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1069) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@72044.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@72051.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1073) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@72052.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@72059.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1053 & _T_1077) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@72060.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@72137.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1128 & _T_1136) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@72138.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@72160.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1144 & _T_1151) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@72161.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1158) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 2 (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@72172.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1158) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@72173.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1172) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CrossingHelper.scala:17:44)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@72192.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1172) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@72193.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLBuffer_10( // @[:freechips.rocketchip.system.LowRiscConfig.fir@72205.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72206.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72207.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [3:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [4:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [1:0] auto_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [3:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [4:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [2:0] auto_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [3:0] auto_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [4:0] auto_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [27:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [7:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output [63:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [2:0] auto_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [1:0] auto_out_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [3:0] auto_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [4:0] auto_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_out_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input [63:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
input auto_out_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@72208.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [3:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [4:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [3:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire [4:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
TLMonitor_30 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@72215.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign auto_in_a_ready = auto_out_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_valid = auto_out_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_param = auto_out_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_size = auto_out_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_source = auto_out_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_sink = auto_out_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_denied = auto_out_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_data = auto_out_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72255.4]
assign auto_out_a_valid = auto_in_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_param = auto_in_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_size = auto_in_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_source = auto_in_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_a_bits_corrupt = auto_in_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign auto_out_d_ready = auto_in_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72254.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72217.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72218.4]
assign TLMonitor_io_in_a_ready = auto_out_a_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_valid = auto_out_d_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_opcode = auto_out_d_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_param = auto_out_d_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_size = auto_out_d_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_source = auto_out_d_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_sink = auto_out_d_bits_sink; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_denied = auto_out_d_bits_denied; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
assign TLMonitor_io_in_d_bits_corrupt = auto_out_d_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@72251.4]
endmodule
module PeripheryBus_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@72289.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72290.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72291.4]
input auto_coupler_to_bootrom_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_bootrom_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [1:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [8:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [16:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [7:0] auto_coupler_to_bootrom_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_bootrom_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_bootrom_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [1:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [8:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [63:0] auto_coupler_to_bootrom_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_debug_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_debug_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_debug_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_debug_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [1:0] auto_coupler_to_debug_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [8:0] auto_coupler_to_debug_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [11:0] auto_coupler_to_debug_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [7:0] auto_coupler_to_debug_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [63:0] auto_coupler_to_debug_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_debug_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_debug_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_debug_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [2:0] auto_coupler_to_debug_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [1:0] auto_coupler_to_debug_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [8:0] auto_coupler_to_debug_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [63:0] auto_coupler_to_debug_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_clint_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_clint_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_clint_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_clint_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [1:0] auto_coupler_to_clint_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [8:0] auto_coupler_to_clint_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [25:0] auto_coupler_to_clint_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [7:0] auto_coupler_to_clint_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [63:0] auto_coupler_to_clint_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_clint_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_clint_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_clint_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [2:0] auto_coupler_to_clint_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [1:0] auto_coupler_to_clint_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [8:0] auto_coupler_to_clint_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [63:0] auto_coupler_to_clint_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_plic_fragmenter_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_plic_fragmenter_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_plic_fragmenter_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_coupler_to_plic_fragmenter_out_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [1:0] auto_coupler_to_plic_fragmenter_out_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [8:0] auto_coupler_to_plic_fragmenter_out_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [27:0] auto_coupler_to_plic_fragmenter_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [7:0] auto_coupler_to_plic_fragmenter_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [63:0] auto_coupler_to_plic_fragmenter_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_plic_fragmenter_out_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_coupler_to_plic_fragmenter_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_coupler_to_plic_fragmenter_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [2:0] auto_coupler_to_plic_fragmenter_out_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [1:0] auto_coupler_to_plic_fragmenter_out_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [8:0] auto_coupler_to_plic_fragmenter_out_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [63:0] auto_coupler_to_plic_fragmenter_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_bus_xing_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_bus_xing_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [2:0] auto_bus_xing_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [2:0] auto_bus_xing_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [3:0] auto_bus_xing_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [4:0] auto_bus_xing_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [27:0] auto_bus_xing_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [7:0] auto_bus_xing_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input [63:0] auto_bus_xing_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_bus_xing_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
input auto_bus_xing_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_bus_xing_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [2:0] auto_bus_xing_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [1:0] auto_bus_xing_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [3:0] auto_bus_xing_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [4:0] auto_bus_xing_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_bus_xing_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_bus_xing_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output [63:0] auto_bus_xing_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
output auto_bus_xing_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@72292.4]
);
wire fixer_clock; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_reset; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_a_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_a_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [2:0] fixer_auto_in_a_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [2:0] fixer_auto_in_a_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [3:0] fixer_auto_in_a_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [4:0] fixer_auto_in_a_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [27:0] fixer_auto_in_a_bits_address; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [7:0] fixer_auto_in_a_bits_mask; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [63:0] fixer_auto_in_a_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_d_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_d_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [2:0] fixer_auto_in_d_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [1:0] fixer_auto_in_d_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [3:0] fixer_auto_in_d_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [4:0] fixer_auto_in_d_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_d_bits_sink; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_d_bits_denied; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [63:0] fixer_auto_in_d_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_a_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_a_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [2:0] fixer_auto_out_a_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [2:0] fixer_auto_out_a_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [3:0] fixer_auto_out_a_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [4:0] fixer_auto_out_a_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [27:0] fixer_auto_out_a_bits_address; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [7:0] fixer_auto_out_a_bits_mask; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [63:0] fixer_auto_out_a_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_d_ready; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_d_valid; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [2:0] fixer_auto_out_d_bits_opcode; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [1:0] fixer_auto_out_d_bits_param; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [3:0] fixer_auto_out_d_bits_size; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [4:0] fixer_auto_out_d_bits_source; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_d_bits_sink; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_d_bits_denied; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire [63:0] fixer_auto_out_d_bits_data; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire fixer_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
wire in_xbar_clock; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_reset; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_a_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_a_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [2:0] in_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [2:0] in_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [3:0] in_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [4:0] in_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [27:0] in_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [7:0] in_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [63:0] in_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_d_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_d_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [2:0] in_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [1:0] in_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [3:0] in_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [4:0] in_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [63:0] in_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_a_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_a_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [2:0] in_xbar_auto_out_a_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [2:0] in_xbar_auto_out_a_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [3:0] in_xbar_auto_out_a_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [4:0] in_xbar_auto_out_a_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [27:0] in_xbar_auto_out_a_bits_address; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [7:0] in_xbar_auto_out_a_bits_mask; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [63:0] in_xbar_auto_out_a_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_a_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_d_ready; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_d_valid; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [2:0] in_xbar_auto_out_d_bits_opcode; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [1:0] in_xbar_auto_out_d_bits_param; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [3:0] in_xbar_auto_out_d_bits_size; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [4:0] in_xbar_auto_out_d_bits_source; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_d_bits_sink; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_d_bits_denied; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire [63:0] in_xbar_auto_out_d_bits_data; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire in_xbar_auto_out_d_bits_corrupt; // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
wire out_xbar_clock; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_reset; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_in_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_in_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [3:0] out_xbar_auto_in_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_in_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [27:0] out_xbar_auto_in_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [7:0] out_xbar_auto_in_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_in_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_in_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [1:0] out_xbar_auto_in_d_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [3:0] out_xbar_auto_in_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_in_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_d_bits_sink; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_d_bits_denied; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_in_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_in_d_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_4_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_4_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_4_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_4_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_4_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_4_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [16:0] out_xbar_auto_out_4_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [7:0] out_xbar_auto_out_4_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_4_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_4_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_4_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_4_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_4_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_4_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_3_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_3_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_3_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_3_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_3_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_3_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [11:0] out_xbar_auto_out_3_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [7:0] out_xbar_auto_out_3_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_3_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_3_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_3_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_3_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_3_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_3_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_3_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_3_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_2_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_2_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_2_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_2_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_2_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_2_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [25:0] out_xbar_auto_out_2_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [7:0] out_xbar_auto_out_2_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_2_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_2_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_2_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_2_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_2_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_2_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_2_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_2_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_1_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_1_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_1_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_1_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_1_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_1_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [27:0] out_xbar_auto_out_1_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [7:0] out_xbar_auto_out_1_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_1_a_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_1_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_1_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_1_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_1_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_1_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_1_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_1_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_a_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_a_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_0_a_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_0_a_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [3:0] out_xbar_auto_out_0_a_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_0_a_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [13:0] out_xbar_auto_out_0_a_bits_address; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [7:0] out_xbar_auto_out_0_a_bits_mask; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_a_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_d_ready; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_d_valid; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [2:0] out_xbar_auto_out_0_d_bits_opcode; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [1:0] out_xbar_auto_out_0_d_bits_param; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [3:0] out_xbar_auto_out_0_d_bits_size; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [4:0] out_xbar_auto_out_0_d_bits_source; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_d_bits_sink; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_d_bits_denied; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire [63:0] out_xbar_auto_out_0_d_bits_data; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire out_xbar_auto_out_0_d_bits_corrupt; // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
wire buffer_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [4:0] buffer_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [27:0] buffer_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [7:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [63:0] buffer_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [4:0] buffer_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [63:0] buffer_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [4:0] buffer_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [27:0] buffer_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [7:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [63:0] buffer_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [2:0] buffer_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [1:0] buffer_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [3:0] buffer_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [4:0] buffer_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire [63:0] buffer_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire buffer_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
wire atomics_clock; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_reset; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_a_ready; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_a_valid; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [2:0] atomics_auto_in_a_bits_opcode; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [2:0] atomics_auto_in_a_bits_param; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [3:0] atomics_auto_in_a_bits_size; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [4:0] atomics_auto_in_a_bits_source; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [27:0] atomics_auto_in_a_bits_address; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [7:0] atomics_auto_in_a_bits_mask; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [63:0] atomics_auto_in_a_bits_data; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_a_bits_corrupt; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_d_ready; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_d_valid; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [2:0] atomics_auto_in_d_bits_opcode; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [1:0] atomics_auto_in_d_bits_param; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [3:0] atomics_auto_in_d_bits_size; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [4:0] atomics_auto_in_d_bits_source; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_d_bits_sink; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_d_bits_denied; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [63:0] atomics_auto_in_d_bits_data; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_in_d_bits_corrupt; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_a_ready; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_a_valid; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [2:0] atomics_auto_out_a_bits_opcode; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [2:0] atomics_auto_out_a_bits_param; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [3:0] atomics_auto_out_a_bits_size; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [4:0] atomics_auto_out_a_bits_source; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [27:0] atomics_auto_out_a_bits_address; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [7:0] atomics_auto_out_a_bits_mask; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [63:0] atomics_auto_out_a_bits_data; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_a_bits_corrupt; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_d_ready; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_d_valid; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [2:0] atomics_auto_out_d_bits_opcode; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [1:0] atomics_auto_out_d_bits_param; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [3:0] atomics_auto_out_d_bits_size; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [4:0] atomics_auto_out_d_bits_source; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_d_bits_sink; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_d_bits_denied; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire [63:0] atomics_auto_out_d_bits_data; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire atomics_auto_out_d_bits_corrupt; // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
wire wrapped_error_device_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [2:0] wrapped_error_device_auto_buffer_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [3:0] wrapped_error_device_auto_buffer_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [4:0] wrapped_error_device_auto_buffer_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [13:0] wrapped_error_device_auto_buffer_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [7:0] wrapped_error_device_auto_buffer_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [2:0] wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [1:0] wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [3:0] wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [4:0] wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire [63:0] wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
wire coupler_to_plic_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [4:0] coupler_to_plic_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [27:0] coupler_to_plic_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [7:0] coupler_to_plic_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [63:0] coupler_to_plic_auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [4:0] coupler_to_plic_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [63:0] coupler_to_plic_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [1:0] coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [8:0] coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [27:0] coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [7:0] coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [63:0] coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_plic_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [2:0] coupler_to_plic_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [1:0] coupler_to_plic_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [8:0] coupler_to_plic_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire [63:0] coupler_to_plic_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
wire coupler_to_clint_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [4:0] coupler_to_clint_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [25:0] coupler_to_clint_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [7:0] coupler_to_clint_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [63:0] coupler_to_clint_auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [4:0] coupler_to_clint_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [63:0] coupler_to_clint_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [1:0] coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [8:0] coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [25:0] coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [7:0] coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [63:0] coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_clint_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [2:0] coupler_to_clint_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [1:0] coupler_to_clint_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [8:0] coupler_to_clint_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire [63:0] coupler_to_clint_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
wire coupler_to_debug_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [4:0] coupler_to_debug_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [11:0] coupler_to_debug_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [7:0] coupler_to_debug_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [63:0] coupler_to_debug_auto_fragmenter_in_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [4:0] coupler_to_debug_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [63:0] coupler_to_debug_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [1:0] coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [8:0] coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [11:0] coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [7:0] coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [63:0] coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_debug_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [2:0] coupler_to_debug_auto_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [1:0] coupler_to_debug_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [8:0] coupler_to_debug_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire [63:0] coupler_to_debug_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
wire coupler_to_bootrom_clock; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_reset; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_in_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_in_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [2:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [2:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [2:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [4:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [16:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [7:0] coupler_to_bootrom_auto_fragmenter_in_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_in_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_in_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_in_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [2:0] coupler_to_bootrom_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [4:0] coupler_to_bootrom_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [63:0] coupler_to_bootrom_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_out_a_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [2:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [1:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [8:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [16:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [7:0] coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire coupler_to_bootrom_auto_fragmenter_out_d_valid; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [1:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_size; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [8:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_source; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire [63:0] coupler_to_bootrom_auto_fragmenter_out_d_bits_data; // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
wire buffer_1_clock; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_reset; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [2:0] buffer_1_auto_in_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [2:0] buffer_1_auto_in_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [3:0] buffer_1_auto_in_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [4:0] buffer_1_auto_in_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [27:0] buffer_1_auto_in_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [7:0] buffer_1_auto_in_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [63:0] buffer_1_auto_in_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [2:0] buffer_1_auto_in_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [1:0] buffer_1_auto_in_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [3:0] buffer_1_auto_in_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [4:0] buffer_1_auto_in_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [63:0] buffer_1_auto_in_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_in_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_a_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_a_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [2:0] buffer_1_auto_out_a_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [2:0] buffer_1_auto_out_a_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [3:0] buffer_1_auto_out_a_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [4:0] buffer_1_auto_out_a_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [27:0] buffer_1_auto_out_a_bits_address; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [7:0] buffer_1_auto_out_a_bits_mask; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [63:0] buffer_1_auto_out_a_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_a_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_d_ready; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_d_valid; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [2:0] buffer_1_auto_out_d_bits_opcode; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [1:0] buffer_1_auto_out_d_bits_param; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [3:0] buffer_1_auto_out_d_bits_size; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [4:0] buffer_1_auto_out_d_bits_source; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_d_bits_sink; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_d_bits_denied; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire [63:0] buffer_1_auto_out_d_bits_data; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
wire buffer_1_auto_out_d_bits_corrupt; // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
TLFIFOFixer_3 fixer ( // @[PeripheryBus.scala 34:33:freechips.rocketchip.system.LowRiscConfig.fir@72297.4]
.clock(fixer_clock),
.reset(fixer_reset),
.auto_in_a_ready(fixer_auto_in_a_ready),
.auto_in_a_valid(fixer_auto_in_a_valid),
.auto_in_a_bits_opcode(fixer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(fixer_auto_in_a_bits_param),
.auto_in_a_bits_size(fixer_auto_in_a_bits_size),
.auto_in_a_bits_source(fixer_auto_in_a_bits_source),
.auto_in_a_bits_address(fixer_auto_in_a_bits_address),
.auto_in_a_bits_mask(fixer_auto_in_a_bits_mask),
.auto_in_a_bits_data(fixer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(fixer_auto_in_a_bits_corrupt),
.auto_in_d_ready(fixer_auto_in_d_ready),
.auto_in_d_valid(fixer_auto_in_d_valid),
.auto_in_d_bits_opcode(fixer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(fixer_auto_in_d_bits_param),
.auto_in_d_bits_size(fixer_auto_in_d_bits_size),
.auto_in_d_bits_source(fixer_auto_in_d_bits_source),
.auto_in_d_bits_sink(fixer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(fixer_auto_in_d_bits_denied),
.auto_in_d_bits_data(fixer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(fixer_auto_in_d_bits_corrupt),
.auto_out_a_ready(fixer_auto_out_a_ready),
.auto_out_a_valid(fixer_auto_out_a_valid),
.auto_out_a_bits_opcode(fixer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(fixer_auto_out_a_bits_param),
.auto_out_a_bits_size(fixer_auto_out_a_bits_size),
.auto_out_a_bits_source(fixer_auto_out_a_bits_source),
.auto_out_a_bits_address(fixer_auto_out_a_bits_address),
.auto_out_a_bits_mask(fixer_auto_out_a_bits_mask),
.auto_out_a_bits_data(fixer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(fixer_auto_out_a_bits_corrupt),
.auto_out_d_ready(fixer_auto_out_d_ready),
.auto_out_d_valid(fixer_auto_out_d_valid),
.auto_out_d_bits_opcode(fixer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(fixer_auto_out_d_bits_param),
.auto_out_d_bits_size(fixer_auto_out_d_bits_size),
.auto_out_d_bits_source(fixer_auto_out_d_bits_source),
.auto_out_d_bits_sink(fixer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(fixer_auto_out_d_bits_denied),
.auto_out_d_bits_data(fixer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(fixer_auto_out_d_bits_corrupt)
);
TLXbar_5 in_xbar ( // @[PeripheryBus.scala 36:29:freechips.rocketchip.system.LowRiscConfig.fir@72303.4]
.clock(in_xbar_clock),
.reset(in_xbar_reset),
.auto_in_a_ready(in_xbar_auto_in_a_ready),
.auto_in_a_valid(in_xbar_auto_in_a_valid),
.auto_in_a_bits_opcode(in_xbar_auto_in_a_bits_opcode),
.auto_in_a_bits_param(in_xbar_auto_in_a_bits_param),
.auto_in_a_bits_size(in_xbar_auto_in_a_bits_size),
.auto_in_a_bits_source(in_xbar_auto_in_a_bits_source),
.auto_in_a_bits_address(in_xbar_auto_in_a_bits_address),
.auto_in_a_bits_mask(in_xbar_auto_in_a_bits_mask),
.auto_in_a_bits_data(in_xbar_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(in_xbar_auto_in_a_bits_corrupt),
.auto_in_d_ready(in_xbar_auto_in_d_ready),
.auto_in_d_valid(in_xbar_auto_in_d_valid),
.auto_in_d_bits_opcode(in_xbar_auto_in_d_bits_opcode),
.auto_in_d_bits_param(in_xbar_auto_in_d_bits_param),
.auto_in_d_bits_size(in_xbar_auto_in_d_bits_size),
.auto_in_d_bits_source(in_xbar_auto_in_d_bits_source),
.auto_in_d_bits_sink(in_xbar_auto_in_d_bits_sink),
.auto_in_d_bits_denied(in_xbar_auto_in_d_bits_denied),
.auto_in_d_bits_data(in_xbar_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(in_xbar_auto_in_d_bits_corrupt),
.auto_out_a_ready(in_xbar_auto_out_a_ready),
.auto_out_a_valid(in_xbar_auto_out_a_valid),
.auto_out_a_bits_opcode(in_xbar_auto_out_a_bits_opcode),
.auto_out_a_bits_param(in_xbar_auto_out_a_bits_param),
.auto_out_a_bits_size(in_xbar_auto_out_a_bits_size),
.auto_out_a_bits_source(in_xbar_auto_out_a_bits_source),
.auto_out_a_bits_address(in_xbar_auto_out_a_bits_address),
.auto_out_a_bits_mask(in_xbar_auto_out_a_bits_mask),
.auto_out_a_bits_data(in_xbar_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(in_xbar_auto_out_a_bits_corrupt),
.auto_out_d_ready(in_xbar_auto_out_d_ready),
.auto_out_d_valid(in_xbar_auto_out_d_valid),
.auto_out_d_bits_opcode(in_xbar_auto_out_d_bits_opcode),
.auto_out_d_bits_param(in_xbar_auto_out_d_bits_param),
.auto_out_d_bits_size(in_xbar_auto_out_d_bits_size),
.auto_out_d_bits_source(in_xbar_auto_out_d_bits_source),
.auto_out_d_bits_sink(in_xbar_auto_out_d_bits_sink),
.auto_out_d_bits_denied(in_xbar_auto_out_d_bits_denied),
.auto_out_d_bits_data(in_xbar_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(in_xbar_auto_out_d_bits_corrupt)
);
TLXbar_6 out_xbar ( // @[PeripheryBus.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@72309.4]
.clock(out_xbar_clock),
.reset(out_xbar_reset),
.auto_in_a_ready(out_xbar_auto_in_a_ready),
.auto_in_a_valid(out_xbar_auto_in_a_valid),
.auto_in_a_bits_opcode(out_xbar_auto_in_a_bits_opcode),
.auto_in_a_bits_param(out_xbar_auto_in_a_bits_param),
.auto_in_a_bits_size(out_xbar_auto_in_a_bits_size),
.auto_in_a_bits_source(out_xbar_auto_in_a_bits_source),
.auto_in_a_bits_address(out_xbar_auto_in_a_bits_address),
.auto_in_a_bits_mask(out_xbar_auto_in_a_bits_mask),
.auto_in_a_bits_data(out_xbar_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(out_xbar_auto_in_a_bits_corrupt),
.auto_in_d_ready(out_xbar_auto_in_d_ready),
.auto_in_d_valid(out_xbar_auto_in_d_valid),
.auto_in_d_bits_opcode(out_xbar_auto_in_d_bits_opcode),
.auto_in_d_bits_param(out_xbar_auto_in_d_bits_param),
.auto_in_d_bits_size(out_xbar_auto_in_d_bits_size),
.auto_in_d_bits_source(out_xbar_auto_in_d_bits_source),
.auto_in_d_bits_sink(out_xbar_auto_in_d_bits_sink),
.auto_in_d_bits_denied(out_xbar_auto_in_d_bits_denied),
.auto_in_d_bits_data(out_xbar_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(out_xbar_auto_in_d_bits_corrupt),
.auto_out_4_a_ready(out_xbar_auto_out_4_a_ready),
.auto_out_4_a_valid(out_xbar_auto_out_4_a_valid),
.auto_out_4_a_bits_opcode(out_xbar_auto_out_4_a_bits_opcode),
.auto_out_4_a_bits_param(out_xbar_auto_out_4_a_bits_param),
.auto_out_4_a_bits_size(out_xbar_auto_out_4_a_bits_size),
.auto_out_4_a_bits_source(out_xbar_auto_out_4_a_bits_source),
.auto_out_4_a_bits_address(out_xbar_auto_out_4_a_bits_address),
.auto_out_4_a_bits_mask(out_xbar_auto_out_4_a_bits_mask),
.auto_out_4_a_bits_corrupt(out_xbar_auto_out_4_a_bits_corrupt),
.auto_out_4_d_ready(out_xbar_auto_out_4_d_ready),
.auto_out_4_d_valid(out_xbar_auto_out_4_d_valid),
.auto_out_4_d_bits_size(out_xbar_auto_out_4_d_bits_size),
.auto_out_4_d_bits_source(out_xbar_auto_out_4_d_bits_source),
.auto_out_4_d_bits_data(out_xbar_auto_out_4_d_bits_data),
.auto_out_3_a_ready(out_xbar_auto_out_3_a_ready),
.auto_out_3_a_valid(out_xbar_auto_out_3_a_valid),
.auto_out_3_a_bits_opcode(out_xbar_auto_out_3_a_bits_opcode),
.auto_out_3_a_bits_param(out_xbar_auto_out_3_a_bits_param),
.auto_out_3_a_bits_size(out_xbar_auto_out_3_a_bits_size),
.auto_out_3_a_bits_source(out_xbar_auto_out_3_a_bits_source),
.auto_out_3_a_bits_address(out_xbar_auto_out_3_a_bits_address),
.auto_out_3_a_bits_mask(out_xbar_auto_out_3_a_bits_mask),
.auto_out_3_a_bits_data(out_xbar_auto_out_3_a_bits_data),
.auto_out_3_a_bits_corrupt(out_xbar_auto_out_3_a_bits_corrupt),
.auto_out_3_d_ready(out_xbar_auto_out_3_d_ready),
.auto_out_3_d_valid(out_xbar_auto_out_3_d_valid),
.auto_out_3_d_bits_opcode(out_xbar_auto_out_3_d_bits_opcode),
.auto_out_3_d_bits_size(out_xbar_auto_out_3_d_bits_size),
.auto_out_3_d_bits_source(out_xbar_auto_out_3_d_bits_source),
.auto_out_3_d_bits_data(out_xbar_auto_out_3_d_bits_data),
.auto_out_2_a_ready(out_xbar_auto_out_2_a_ready),
.auto_out_2_a_valid(out_xbar_auto_out_2_a_valid),
.auto_out_2_a_bits_opcode(out_xbar_auto_out_2_a_bits_opcode),
.auto_out_2_a_bits_param(out_xbar_auto_out_2_a_bits_param),
.auto_out_2_a_bits_size(out_xbar_auto_out_2_a_bits_size),
.auto_out_2_a_bits_source(out_xbar_auto_out_2_a_bits_source),
.auto_out_2_a_bits_address(out_xbar_auto_out_2_a_bits_address),
.auto_out_2_a_bits_mask(out_xbar_auto_out_2_a_bits_mask),
.auto_out_2_a_bits_data(out_xbar_auto_out_2_a_bits_data),
.auto_out_2_a_bits_corrupt(out_xbar_auto_out_2_a_bits_corrupt),
.auto_out_2_d_ready(out_xbar_auto_out_2_d_ready),
.auto_out_2_d_valid(out_xbar_auto_out_2_d_valid),
.auto_out_2_d_bits_opcode(out_xbar_auto_out_2_d_bits_opcode),
.auto_out_2_d_bits_size(out_xbar_auto_out_2_d_bits_size),
.auto_out_2_d_bits_source(out_xbar_auto_out_2_d_bits_source),
.auto_out_2_d_bits_data(out_xbar_auto_out_2_d_bits_data),
.auto_out_1_a_ready(out_xbar_auto_out_1_a_ready),
.auto_out_1_a_valid(out_xbar_auto_out_1_a_valid),
.auto_out_1_a_bits_opcode(out_xbar_auto_out_1_a_bits_opcode),
.auto_out_1_a_bits_param(out_xbar_auto_out_1_a_bits_param),
.auto_out_1_a_bits_size(out_xbar_auto_out_1_a_bits_size),
.auto_out_1_a_bits_source(out_xbar_auto_out_1_a_bits_source),
.auto_out_1_a_bits_address(out_xbar_auto_out_1_a_bits_address),
.auto_out_1_a_bits_mask(out_xbar_auto_out_1_a_bits_mask),
.auto_out_1_a_bits_data(out_xbar_auto_out_1_a_bits_data),
.auto_out_1_a_bits_corrupt(out_xbar_auto_out_1_a_bits_corrupt),
.auto_out_1_d_ready(out_xbar_auto_out_1_d_ready),
.auto_out_1_d_valid(out_xbar_auto_out_1_d_valid),
.auto_out_1_d_bits_opcode(out_xbar_auto_out_1_d_bits_opcode),
.auto_out_1_d_bits_size(out_xbar_auto_out_1_d_bits_size),
.auto_out_1_d_bits_source(out_xbar_auto_out_1_d_bits_source),
.auto_out_1_d_bits_data(out_xbar_auto_out_1_d_bits_data),
.auto_out_0_a_ready(out_xbar_auto_out_0_a_ready),
.auto_out_0_a_valid(out_xbar_auto_out_0_a_valid),
.auto_out_0_a_bits_opcode(out_xbar_auto_out_0_a_bits_opcode),
.auto_out_0_a_bits_param(out_xbar_auto_out_0_a_bits_param),
.auto_out_0_a_bits_size(out_xbar_auto_out_0_a_bits_size),
.auto_out_0_a_bits_source(out_xbar_auto_out_0_a_bits_source),
.auto_out_0_a_bits_address(out_xbar_auto_out_0_a_bits_address),
.auto_out_0_a_bits_mask(out_xbar_auto_out_0_a_bits_mask),
.auto_out_0_a_bits_corrupt(out_xbar_auto_out_0_a_bits_corrupt),
.auto_out_0_d_ready(out_xbar_auto_out_0_d_ready),
.auto_out_0_d_valid(out_xbar_auto_out_0_d_valid),
.auto_out_0_d_bits_opcode(out_xbar_auto_out_0_d_bits_opcode),
.auto_out_0_d_bits_param(out_xbar_auto_out_0_d_bits_param),
.auto_out_0_d_bits_size(out_xbar_auto_out_0_d_bits_size),
.auto_out_0_d_bits_source(out_xbar_auto_out_0_d_bits_source),
.auto_out_0_d_bits_sink(out_xbar_auto_out_0_d_bits_sink),
.auto_out_0_d_bits_denied(out_xbar_auto_out_0_d_bits_denied),
.auto_out_0_d_bits_data(out_xbar_auto_out_0_d_bits_data),
.auto_out_0_d_bits_corrupt(out_xbar_auto_out_0_d_bits_corrupt)
);
TLBuffer_7 buffer ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72315.4]
.clock(buffer_clock),
.reset(buffer_reset),
.auto_in_a_ready(buffer_auto_in_a_ready),
.auto_in_a_valid(buffer_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_auto_in_d_ready),
.auto_in_d_valid(buffer_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_auto_in_d_bits_opcode),
.auto_in_d_bits_param(buffer_auto_in_d_bits_param),
.auto_in_d_bits_size(buffer_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_auto_in_d_bits_source),
.auto_in_d_bits_sink(buffer_auto_in_d_bits_sink),
.auto_in_d_bits_denied(buffer_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_auto_out_a_ready),
.auto_out_a_valid(buffer_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_auto_out_d_ready),
.auto_out_d_valid(buffer_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_auto_out_d_bits_opcode),
.auto_out_d_bits_param(buffer_auto_out_d_bits_param),
.auto_out_d_bits_size(buffer_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_auto_out_d_bits_source),
.auto_out_d_bits_sink(buffer_auto_out_d_bits_sink),
.auto_out_d_bits_denied(buffer_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_auto_out_d_bits_corrupt)
);
TLAtomicAutomata_1 atomics ( // @[AtomicAutomata.scala 279:29:freechips.rocketchip.system.LowRiscConfig.fir@72321.4]
.clock(atomics_clock),
.reset(atomics_reset),
.auto_in_a_ready(atomics_auto_in_a_ready),
.auto_in_a_valid(atomics_auto_in_a_valid),
.auto_in_a_bits_opcode(atomics_auto_in_a_bits_opcode),
.auto_in_a_bits_param(atomics_auto_in_a_bits_param),
.auto_in_a_bits_size(atomics_auto_in_a_bits_size),
.auto_in_a_bits_source(atomics_auto_in_a_bits_source),
.auto_in_a_bits_address(atomics_auto_in_a_bits_address),
.auto_in_a_bits_mask(atomics_auto_in_a_bits_mask),
.auto_in_a_bits_data(atomics_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(atomics_auto_in_a_bits_corrupt),
.auto_in_d_ready(atomics_auto_in_d_ready),
.auto_in_d_valid(atomics_auto_in_d_valid),
.auto_in_d_bits_opcode(atomics_auto_in_d_bits_opcode),
.auto_in_d_bits_param(atomics_auto_in_d_bits_param),
.auto_in_d_bits_size(atomics_auto_in_d_bits_size),
.auto_in_d_bits_source(atomics_auto_in_d_bits_source),
.auto_in_d_bits_sink(atomics_auto_in_d_bits_sink),
.auto_in_d_bits_denied(atomics_auto_in_d_bits_denied),
.auto_in_d_bits_data(atomics_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(atomics_auto_in_d_bits_corrupt),
.auto_out_a_ready(atomics_auto_out_a_ready),
.auto_out_a_valid(atomics_auto_out_a_valid),
.auto_out_a_bits_opcode(atomics_auto_out_a_bits_opcode),
.auto_out_a_bits_param(atomics_auto_out_a_bits_param),
.auto_out_a_bits_size(atomics_auto_out_a_bits_size),
.auto_out_a_bits_source(atomics_auto_out_a_bits_source),
.auto_out_a_bits_address(atomics_auto_out_a_bits_address),
.auto_out_a_bits_mask(atomics_auto_out_a_bits_mask),
.auto_out_a_bits_data(atomics_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(atomics_auto_out_a_bits_corrupt),
.auto_out_d_ready(atomics_auto_out_d_ready),
.auto_out_d_valid(atomics_auto_out_d_valid),
.auto_out_d_bits_opcode(atomics_auto_out_d_bits_opcode),
.auto_out_d_bits_param(atomics_auto_out_d_bits_param),
.auto_out_d_bits_size(atomics_auto_out_d_bits_size),
.auto_out_d_bits_source(atomics_auto_out_d_bits_source),
.auto_out_d_bits_sink(atomics_auto_out_d_bits_sink),
.auto_out_d_bits_denied(atomics_auto_out_d_bits_denied),
.auto_out_d_bits_data(atomics_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(atomics_auto_out_d_bits_corrupt)
);
SimpleLazyModule_8 wrapped_error_device ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72327.4]
.clock(wrapped_error_device_clock),
.reset(wrapped_error_device_reset),
.auto_buffer_in_a_ready(wrapped_error_device_auto_buffer_in_a_ready),
.auto_buffer_in_a_valid(wrapped_error_device_auto_buffer_in_a_valid),
.auto_buffer_in_a_bits_opcode(wrapped_error_device_auto_buffer_in_a_bits_opcode),
.auto_buffer_in_a_bits_param(wrapped_error_device_auto_buffer_in_a_bits_param),
.auto_buffer_in_a_bits_size(wrapped_error_device_auto_buffer_in_a_bits_size),
.auto_buffer_in_a_bits_source(wrapped_error_device_auto_buffer_in_a_bits_source),
.auto_buffer_in_a_bits_address(wrapped_error_device_auto_buffer_in_a_bits_address),
.auto_buffer_in_a_bits_mask(wrapped_error_device_auto_buffer_in_a_bits_mask),
.auto_buffer_in_a_bits_corrupt(wrapped_error_device_auto_buffer_in_a_bits_corrupt),
.auto_buffer_in_d_ready(wrapped_error_device_auto_buffer_in_d_ready),
.auto_buffer_in_d_valid(wrapped_error_device_auto_buffer_in_d_valid),
.auto_buffer_in_d_bits_opcode(wrapped_error_device_auto_buffer_in_d_bits_opcode),
.auto_buffer_in_d_bits_param(wrapped_error_device_auto_buffer_in_d_bits_param),
.auto_buffer_in_d_bits_size(wrapped_error_device_auto_buffer_in_d_bits_size),
.auto_buffer_in_d_bits_source(wrapped_error_device_auto_buffer_in_d_bits_source),
.auto_buffer_in_d_bits_sink(wrapped_error_device_auto_buffer_in_d_bits_sink),
.auto_buffer_in_d_bits_denied(wrapped_error_device_auto_buffer_in_d_bits_denied),
.auto_buffer_in_d_bits_data(wrapped_error_device_auto_buffer_in_d_bits_data),
.auto_buffer_in_d_bits_corrupt(wrapped_error_device_auto_buffer_in_d_bits_corrupt)
);
SimpleLazyModule_9 coupler_to_plic ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72333.4]
.clock(coupler_to_plic_clock),
.reset(coupler_to_plic_reset),
.auto_fragmenter_in_a_ready(coupler_to_plic_auto_fragmenter_in_a_ready),
.auto_fragmenter_in_a_valid(coupler_to_plic_auto_fragmenter_in_a_valid),
.auto_fragmenter_in_a_bits_opcode(coupler_to_plic_auto_fragmenter_in_a_bits_opcode),
.auto_fragmenter_in_a_bits_param(coupler_to_plic_auto_fragmenter_in_a_bits_param),
.auto_fragmenter_in_a_bits_size(coupler_to_plic_auto_fragmenter_in_a_bits_size),
.auto_fragmenter_in_a_bits_source(coupler_to_plic_auto_fragmenter_in_a_bits_source),
.auto_fragmenter_in_a_bits_address(coupler_to_plic_auto_fragmenter_in_a_bits_address),
.auto_fragmenter_in_a_bits_mask(coupler_to_plic_auto_fragmenter_in_a_bits_mask),
.auto_fragmenter_in_a_bits_data(coupler_to_plic_auto_fragmenter_in_a_bits_data),
.auto_fragmenter_in_a_bits_corrupt(coupler_to_plic_auto_fragmenter_in_a_bits_corrupt),
.auto_fragmenter_in_d_ready(coupler_to_plic_auto_fragmenter_in_d_ready),
.auto_fragmenter_in_d_valid(coupler_to_plic_auto_fragmenter_in_d_valid),
.auto_fragmenter_in_d_bits_opcode(coupler_to_plic_auto_fragmenter_in_d_bits_opcode),
.auto_fragmenter_in_d_bits_size(coupler_to_plic_auto_fragmenter_in_d_bits_size),
.auto_fragmenter_in_d_bits_source(coupler_to_plic_auto_fragmenter_in_d_bits_source),
.auto_fragmenter_in_d_bits_data(coupler_to_plic_auto_fragmenter_in_d_bits_data),
.auto_fragmenter_out_a_ready(coupler_to_plic_auto_fragmenter_out_a_ready),
.auto_fragmenter_out_a_valid(coupler_to_plic_auto_fragmenter_out_a_valid),
.auto_fragmenter_out_a_bits_opcode(coupler_to_plic_auto_fragmenter_out_a_bits_opcode),
.auto_fragmenter_out_a_bits_param(coupler_to_plic_auto_fragmenter_out_a_bits_param),
.auto_fragmenter_out_a_bits_size(coupler_to_plic_auto_fragmenter_out_a_bits_size),
.auto_fragmenter_out_a_bits_source(coupler_to_plic_auto_fragmenter_out_a_bits_source),
.auto_fragmenter_out_a_bits_address(coupler_to_plic_auto_fragmenter_out_a_bits_address),
.auto_fragmenter_out_a_bits_mask(coupler_to_plic_auto_fragmenter_out_a_bits_mask),
.auto_fragmenter_out_a_bits_data(coupler_to_plic_auto_fragmenter_out_a_bits_data),
.auto_fragmenter_out_a_bits_corrupt(coupler_to_plic_auto_fragmenter_out_a_bits_corrupt),
.auto_fragmenter_out_d_ready(coupler_to_plic_auto_fragmenter_out_d_ready),
.auto_fragmenter_out_d_valid(coupler_to_plic_auto_fragmenter_out_d_valid),
.auto_fragmenter_out_d_bits_opcode(coupler_to_plic_auto_fragmenter_out_d_bits_opcode),
.auto_fragmenter_out_d_bits_size(coupler_to_plic_auto_fragmenter_out_d_bits_size),
.auto_fragmenter_out_d_bits_source(coupler_to_plic_auto_fragmenter_out_d_bits_source),
.auto_fragmenter_out_d_bits_data(coupler_to_plic_auto_fragmenter_out_d_bits_data)
);
SimpleLazyModule_10 coupler_to_clint ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72339.4]
.clock(coupler_to_clint_clock),
.reset(coupler_to_clint_reset),
.auto_fragmenter_in_a_ready(coupler_to_clint_auto_fragmenter_in_a_ready),
.auto_fragmenter_in_a_valid(coupler_to_clint_auto_fragmenter_in_a_valid),
.auto_fragmenter_in_a_bits_opcode(coupler_to_clint_auto_fragmenter_in_a_bits_opcode),
.auto_fragmenter_in_a_bits_param(coupler_to_clint_auto_fragmenter_in_a_bits_param),
.auto_fragmenter_in_a_bits_size(coupler_to_clint_auto_fragmenter_in_a_bits_size),
.auto_fragmenter_in_a_bits_source(coupler_to_clint_auto_fragmenter_in_a_bits_source),
.auto_fragmenter_in_a_bits_address(coupler_to_clint_auto_fragmenter_in_a_bits_address),
.auto_fragmenter_in_a_bits_mask(coupler_to_clint_auto_fragmenter_in_a_bits_mask),
.auto_fragmenter_in_a_bits_data(coupler_to_clint_auto_fragmenter_in_a_bits_data),
.auto_fragmenter_in_a_bits_corrupt(coupler_to_clint_auto_fragmenter_in_a_bits_corrupt),
.auto_fragmenter_in_d_ready(coupler_to_clint_auto_fragmenter_in_d_ready),
.auto_fragmenter_in_d_valid(coupler_to_clint_auto_fragmenter_in_d_valid),
.auto_fragmenter_in_d_bits_opcode(coupler_to_clint_auto_fragmenter_in_d_bits_opcode),
.auto_fragmenter_in_d_bits_size(coupler_to_clint_auto_fragmenter_in_d_bits_size),
.auto_fragmenter_in_d_bits_source(coupler_to_clint_auto_fragmenter_in_d_bits_source),
.auto_fragmenter_in_d_bits_data(coupler_to_clint_auto_fragmenter_in_d_bits_data),
.auto_fragmenter_out_a_ready(coupler_to_clint_auto_fragmenter_out_a_ready),
.auto_fragmenter_out_a_valid(coupler_to_clint_auto_fragmenter_out_a_valid),
.auto_fragmenter_out_a_bits_opcode(coupler_to_clint_auto_fragmenter_out_a_bits_opcode),
.auto_fragmenter_out_a_bits_param(coupler_to_clint_auto_fragmenter_out_a_bits_param),
.auto_fragmenter_out_a_bits_size(coupler_to_clint_auto_fragmenter_out_a_bits_size),
.auto_fragmenter_out_a_bits_source(coupler_to_clint_auto_fragmenter_out_a_bits_source),
.auto_fragmenter_out_a_bits_address(coupler_to_clint_auto_fragmenter_out_a_bits_address),
.auto_fragmenter_out_a_bits_mask(coupler_to_clint_auto_fragmenter_out_a_bits_mask),
.auto_fragmenter_out_a_bits_data(coupler_to_clint_auto_fragmenter_out_a_bits_data),
.auto_fragmenter_out_a_bits_corrupt(coupler_to_clint_auto_fragmenter_out_a_bits_corrupt),
.auto_fragmenter_out_d_ready(coupler_to_clint_auto_fragmenter_out_d_ready),
.auto_fragmenter_out_d_valid(coupler_to_clint_auto_fragmenter_out_d_valid),
.auto_fragmenter_out_d_bits_opcode(coupler_to_clint_auto_fragmenter_out_d_bits_opcode),
.auto_fragmenter_out_d_bits_size(coupler_to_clint_auto_fragmenter_out_d_bits_size),
.auto_fragmenter_out_d_bits_source(coupler_to_clint_auto_fragmenter_out_d_bits_source),
.auto_fragmenter_out_d_bits_data(coupler_to_clint_auto_fragmenter_out_d_bits_data)
);
SimpleLazyModule_11 coupler_to_debug ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72345.4]
.clock(coupler_to_debug_clock),
.reset(coupler_to_debug_reset),
.auto_fragmenter_in_a_ready(coupler_to_debug_auto_fragmenter_in_a_ready),
.auto_fragmenter_in_a_valid(coupler_to_debug_auto_fragmenter_in_a_valid),
.auto_fragmenter_in_a_bits_opcode(coupler_to_debug_auto_fragmenter_in_a_bits_opcode),
.auto_fragmenter_in_a_bits_param(coupler_to_debug_auto_fragmenter_in_a_bits_param),
.auto_fragmenter_in_a_bits_size(coupler_to_debug_auto_fragmenter_in_a_bits_size),
.auto_fragmenter_in_a_bits_source(coupler_to_debug_auto_fragmenter_in_a_bits_source),
.auto_fragmenter_in_a_bits_address(coupler_to_debug_auto_fragmenter_in_a_bits_address),
.auto_fragmenter_in_a_bits_mask(coupler_to_debug_auto_fragmenter_in_a_bits_mask),
.auto_fragmenter_in_a_bits_data(coupler_to_debug_auto_fragmenter_in_a_bits_data),
.auto_fragmenter_in_a_bits_corrupt(coupler_to_debug_auto_fragmenter_in_a_bits_corrupt),
.auto_fragmenter_in_d_ready(coupler_to_debug_auto_fragmenter_in_d_ready),
.auto_fragmenter_in_d_valid(coupler_to_debug_auto_fragmenter_in_d_valid),
.auto_fragmenter_in_d_bits_opcode(coupler_to_debug_auto_fragmenter_in_d_bits_opcode),
.auto_fragmenter_in_d_bits_size(coupler_to_debug_auto_fragmenter_in_d_bits_size),
.auto_fragmenter_in_d_bits_source(coupler_to_debug_auto_fragmenter_in_d_bits_source),
.auto_fragmenter_in_d_bits_data(coupler_to_debug_auto_fragmenter_in_d_bits_data),
.auto_fragmenter_out_a_ready(coupler_to_debug_auto_fragmenter_out_a_ready),
.auto_fragmenter_out_a_valid(coupler_to_debug_auto_fragmenter_out_a_valid),
.auto_fragmenter_out_a_bits_opcode(coupler_to_debug_auto_fragmenter_out_a_bits_opcode),
.auto_fragmenter_out_a_bits_param(coupler_to_debug_auto_fragmenter_out_a_bits_param),
.auto_fragmenter_out_a_bits_size(coupler_to_debug_auto_fragmenter_out_a_bits_size),
.auto_fragmenter_out_a_bits_source(coupler_to_debug_auto_fragmenter_out_a_bits_source),
.auto_fragmenter_out_a_bits_address(coupler_to_debug_auto_fragmenter_out_a_bits_address),
.auto_fragmenter_out_a_bits_mask(coupler_to_debug_auto_fragmenter_out_a_bits_mask),
.auto_fragmenter_out_a_bits_data(coupler_to_debug_auto_fragmenter_out_a_bits_data),
.auto_fragmenter_out_a_bits_corrupt(coupler_to_debug_auto_fragmenter_out_a_bits_corrupt),
.auto_fragmenter_out_d_ready(coupler_to_debug_auto_fragmenter_out_d_ready),
.auto_fragmenter_out_d_valid(coupler_to_debug_auto_fragmenter_out_d_valid),
.auto_fragmenter_out_d_bits_opcode(coupler_to_debug_auto_fragmenter_out_d_bits_opcode),
.auto_fragmenter_out_d_bits_size(coupler_to_debug_auto_fragmenter_out_d_bits_size),
.auto_fragmenter_out_d_bits_source(coupler_to_debug_auto_fragmenter_out_d_bits_source),
.auto_fragmenter_out_d_bits_data(coupler_to_debug_auto_fragmenter_out_d_bits_data)
);
SimpleLazyModule_13 coupler_to_bootrom ( // @[LazyModule.scala 225:27:freechips.rocketchip.system.LowRiscConfig.fir@72357.4]
.clock(coupler_to_bootrom_clock),
.reset(coupler_to_bootrom_reset),
.auto_fragmenter_in_a_ready(coupler_to_bootrom_auto_fragmenter_in_a_ready),
.auto_fragmenter_in_a_valid(coupler_to_bootrom_auto_fragmenter_in_a_valid),
.auto_fragmenter_in_a_bits_opcode(coupler_to_bootrom_auto_fragmenter_in_a_bits_opcode),
.auto_fragmenter_in_a_bits_param(coupler_to_bootrom_auto_fragmenter_in_a_bits_param),
.auto_fragmenter_in_a_bits_size(coupler_to_bootrom_auto_fragmenter_in_a_bits_size),
.auto_fragmenter_in_a_bits_source(coupler_to_bootrom_auto_fragmenter_in_a_bits_source),
.auto_fragmenter_in_a_bits_address(coupler_to_bootrom_auto_fragmenter_in_a_bits_address),
.auto_fragmenter_in_a_bits_mask(coupler_to_bootrom_auto_fragmenter_in_a_bits_mask),
.auto_fragmenter_in_a_bits_corrupt(coupler_to_bootrom_auto_fragmenter_in_a_bits_corrupt),
.auto_fragmenter_in_d_ready(coupler_to_bootrom_auto_fragmenter_in_d_ready),
.auto_fragmenter_in_d_valid(coupler_to_bootrom_auto_fragmenter_in_d_valid),
.auto_fragmenter_in_d_bits_size(coupler_to_bootrom_auto_fragmenter_in_d_bits_size),
.auto_fragmenter_in_d_bits_source(coupler_to_bootrom_auto_fragmenter_in_d_bits_source),
.auto_fragmenter_in_d_bits_data(coupler_to_bootrom_auto_fragmenter_in_d_bits_data),
.auto_fragmenter_out_a_ready(coupler_to_bootrom_auto_fragmenter_out_a_ready),
.auto_fragmenter_out_a_valid(coupler_to_bootrom_auto_fragmenter_out_a_valid),
.auto_fragmenter_out_a_bits_opcode(coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode),
.auto_fragmenter_out_a_bits_param(coupler_to_bootrom_auto_fragmenter_out_a_bits_param),
.auto_fragmenter_out_a_bits_size(coupler_to_bootrom_auto_fragmenter_out_a_bits_size),
.auto_fragmenter_out_a_bits_source(coupler_to_bootrom_auto_fragmenter_out_a_bits_source),
.auto_fragmenter_out_a_bits_address(coupler_to_bootrom_auto_fragmenter_out_a_bits_address),
.auto_fragmenter_out_a_bits_mask(coupler_to_bootrom_auto_fragmenter_out_a_bits_mask),
.auto_fragmenter_out_a_bits_corrupt(coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt),
.auto_fragmenter_out_d_ready(coupler_to_bootrom_auto_fragmenter_out_d_ready),
.auto_fragmenter_out_d_valid(coupler_to_bootrom_auto_fragmenter_out_d_valid),
.auto_fragmenter_out_d_bits_size(coupler_to_bootrom_auto_fragmenter_out_d_bits_size),
.auto_fragmenter_out_d_bits_source(coupler_to_bootrom_auto_fragmenter_out_d_bits_source),
.auto_fragmenter_out_d_bits_data(coupler_to_bootrom_auto_fragmenter_out_d_bits_data)
);
TLBuffer_10 buffer_1 ( // @[Buffer.scala 69:28:freechips.rocketchip.system.LowRiscConfig.fir@72363.4]
.clock(buffer_1_clock),
.reset(buffer_1_reset),
.auto_in_a_ready(buffer_1_auto_in_a_ready),
.auto_in_a_valid(buffer_1_auto_in_a_valid),
.auto_in_a_bits_opcode(buffer_1_auto_in_a_bits_opcode),
.auto_in_a_bits_param(buffer_1_auto_in_a_bits_param),
.auto_in_a_bits_size(buffer_1_auto_in_a_bits_size),
.auto_in_a_bits_source(buffer_1_auto_in_a_bits_source),
.auto_in_a_bits_address(buffer_1_auto_in_a_bits_address),
.auto_in_a_bits_mask(buffer_1_auto_in_a_bits_mask),
.auto_in_a_bits_data(buffer_1_auto_in_a_bits_data),
.auto_in_a_bits_corrupt(buffer_1_auto_in_a_bits_corrupt),
.auto_in_d_ready(buffer_1_auto_in_d_ready),
.auto_in_d_valid(buffer_1_auto_in_d_valid),
.auto_in_d_bits_opcode(buffer_1_auto_in_d_bits_opcode),
.auto_in_d_bits_param(buffer_1_auto_in_d_bits_param),
.auto_in_d_bits_size(buffer_1_auto_in_d_bits_size),
.auto_in_d_bits_source(buffer_1_auto_in_d_bits_source),
.auto_in_d_bits_sink(buffer_1_auto_in_d_bits_sink),
.auto_in_d_bits_denied(buffer_1_auto_in_d_bits_denied),
.auto_in_d_bits_data(buffer_1_auto_in_d_bits_data),
.auto_in_d_bits_corrupt(buffer_1_auto_in_d_bits_corrupt),
.auto_out_a_ready(buffer_1_auto_out_a_ready),
.auto_out_a_valid(buffer_1_auto_out_a_valid),
.auto_out_a_bits_opcode(buffer_1_auto_out_a_bits_opcode),
.auto_out_a_bits_param(buffer_1_auto_out_a_bits_param),
.auto_out_a_bits_size(buffer_1_auto_out_a_bits_size),
.auto_out_a_bits_source(buffer_1_auto_out_a_bits_source),
.auto_out_a_bits_address(buffer_1_auto_out_a_bits_address),
.auto_out_a_bits_mask(buffer_1_auto_out_a_bits_mask),
.auto_out_a_bits_data(buffer_1_auto_out_a_bits_data),
.auto_out_a_bits_corrupt(buffer_1_auto_out_a_bits_corrupt),
.auto_out_d_ready(buffer_1_auto_out_d_ready),
.auto_out_d_valid(buffer_1_auto_out_d_valid),
.auto_out_d_bits_opcode(buffer_1_auto_out_d_bits_opcode),
.auto_out_d_bits_param(buffer_1_auto_out_d_bits_param),
.auto_out_d_bits_size(buffer_1_auto_out_d_bits_size),
.auto_out_d_bits_source(buffer_1_auto_out_d_bits_source),
.auto_out_d_bits_sink(buffer_1_auto_out_d_bits_sink),
.auto_out_d_bits_denied(buffer_1_auto_out_d_bits_denied),
.auto_out_d_bits_data(buffer_1_auto_out_d_bits_data),
.auto_out_d_bits_corrupt(buffer_1_auto_out_d_bits_corrupt)
);
assign auto_coupler_to_bootrom_fragmenter_out_a_valid = coupler_to_bootrom_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_opcode = coupler_to_bootrom_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_param = coupler_to_bootrom_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_size = coupler_to_bootrom_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_source = coupler_to_bootrom_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_address = coupler_to_bootrom_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_mask = coupler_to_bootrom_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_a_bits_corrupt = coupler_to_bootrom_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_bootrom_fragmenter_out_d_ready = coupler_to_bootrom_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign auto_coupler_to_debug_fragmenter_out_a_valid = coupler_to_debug_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_opcode = coupler_to_debug_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_param = coupler_to_debug_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_size = coupler_to_debug_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_source = coupler_to_debug_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_address = coupler_to_debug_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_mask = coupler_to_debug_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_data = coupler_to_debug_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_a_bits_corrupt = coupler_to_debug_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_debug_fragmenter_out_d_ready = coupler_to_debug_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign auto_coupler_to_clint_fragmenter_out_a_valid = coupler_to_clint_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_opcode = coupler_to_clint_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_param = coupler_to_clint_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_size = coupler_to_clint_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_source = coupler_to_clint_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_address = coupler_to_clint_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_mask = coupler_to_clint_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_data = coupler_to_clint_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_a_bits_corrupt = coupler_to_clint_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_clint_fragmenter_out_d_ready = coupler_to_clint_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign auto_coupler_to_plic_fragmenter_out_a_valid = coupler_to_plic_auto_fragmenter_out_a_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_opcode = coupler_to_plic_auto_fragmenter_out_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_param = coupler_to_plic_auto_fragmenter_out_a_bits_param; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_size = coupler_to_plic_auto_fragmenter_out_a_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_source = coupler_to_plic_auto_fragmenter_out_a_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_address = coupler_to_plic_auto_fragmenter_out_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_mask = coupler_to_plic_auto_fragmenter_out_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_data = coupler_to_plic_auto_fragmenter_out_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_a_bits_corrupt = coupler_to_plic_auto_fragmenter_out_a_bits_corrupt; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_coupler_to_plic_fragmenter_out_d_ready = coupler_to_plic_auto_fragmenter_out_d_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign auto_bus_xing_in_a_ready = buffer_1_auto_in_a_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_valid = buffer_1_auto_in_d_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_opcode = buffer_1_auto_in_d_bits_opcode; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_param = buffer_1_auto_in_d_bits_param; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_size = buffer_1_auto_in_d_bits_size; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_source = buffer_1_auto_in_d_bits_source; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_sink = buffer_1_auto_in_d_bits_sink; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_denied = buffer_1_auto_in_d_bits_denied; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_data = buffer_1_auto_in_d_bits_data; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign auto_bus_xing_in_d_bits_corrupt = buffer_1_auto_in_d_bits_corrupt; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@72391.4]
assign fixer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72301.4]
assign fixer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72302.4]
assign fixer_auto_in_a_valid = buffer_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_opcode = buffer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_param = buffer_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_size = buffer_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_source = buffer_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_address = buffer_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_mask = buffer_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_data = buffer_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_a_bits_corrupt = buffer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_in_d_ready = buffer_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign fixer_auto_out_a_ready = out_xbar_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_valid = out_xbar_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_opcode = out_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_param = out_xbar_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_size = out_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_source = out_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_sink = out_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_denied = out_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_data = out_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign fixer_auto_out_d_bits_corrupt = out_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign in_xbar_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72307.4]
assign in_xbar_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72308.4]
assign in_xbar_auto_in_a_valid = buffer_1_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_opcode = buffer_1_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_param = buffer_1_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_size = buffer_1_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_source = buffer_1_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_address = buffer_1_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_mask = buffer_1_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_data = buffer_1_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_a_bits_corrupt = buffer_1_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_in_d_ready = buffer_1_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign in_xbar_auto_out_a_ready = atomics_auto_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_valid = atomics_auto_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_opcode = atomics_auto_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_param = atomics_auto_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_size = atomics_auto_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_source = atomics_auto_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_sink = atomics_auto_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_denied = atomics_auto_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_data = atomics_auto_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign in_xbar_auto_out_d_bits_corrupt = atomics_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign out_xbar_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72313.4]
assign out_xbar_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72314.4]
assign out_xbar_auto_in_a_valid = fixer_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_opcode = fixer_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_param = fixer_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_size = fixer_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_source = fixer_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_address = fixer_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_mask = fixer_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_data = fixer_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_a_bits_corrupt = fixer_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_in_d_ready = fixer_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72380.4]
assign out_xbar_auto_out_4_a_ready = coupler_to_bootrom_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign out_xbar_auto_out_4_d_valid = coupler_to_bootrom_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign out_xbar_auto_out_4_d_bits_size = coupler_to_bootrom_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign out_xbar_auto_out_4_d_bits_source = coupler_to_bootrom_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign out_xbar_auto_out_4_d_bits_data = coupler_to_bootrom_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign out_xbar_auto_out_3_a_ready = coupler_to_debug_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign out_xbar_auto_out_3_d_valid = coupler_to_debug_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign out_xbar_auto_out_3_d_bits_opcode = coupler_to_debug_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign out_xbar_auto_out_3_d_bits_size = coupler_to_debug_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign out_xbar_auto_out_3_d_bits_source = coupler_to_debug_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign out_xbar_auto_out_3_d_bits_data = coupler_to_debug_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign out_xbar_auto_out_2_a_ready = coupler_to_clint_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign out_xbar_auto_out_2_d_valid = coupler_to_clint_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign out_xbar_auto_out_2_d_bits_opcode = coupler_to_clint_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign out_xbar_auto_out_2_d_bits_size = coupler_to_clint_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign out_xbar_auto_out_2_d_bits_source = coupler_to_clint_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign out_xbar_auto_out_2_d_bits_data = coupler_to_clint_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign out_xbar_auto_out_1_a_ready = coupler_to_plic_auto_fragmenter_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign out_xbar_auto_out_1_d_valid = coupler_to_plic_auto_fragmenter_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign out_xbar_auto_out_1_d_bits_opcode = coupler_to_plic_auto_fragmenter_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign out_xbar_auto_out_1_d_bits_size = coupler_to_plic_auto_fragmenter_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign out_xbar_auto_out_1_d_bits_source = coupler_to_plic_auto_fragmenter_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign out_xbar_auto_out_1_d_bits_data = coupler_to_plic_auto_fragmenter_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign out_xbar_auto_out_0_a_ready = wrapped_error_device_auto_buffer_in_a_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_valid = wrapped_error_device_auto_buffer_in_d_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_opcode = wrapped_error_device_auto_buffer_in_d_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_param = wrapped_error_device_auto_buffer_in_d_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_size = wrapped_error_device_auto_buffer_in_d_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_source = wrapped_error_device_auto_buffer_in_d_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_sink = wrapped_error_device_auto_buffer_in_d_bits_sink; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_denied = wrapped_error_device_auto_buffer_in_d_bits_denied; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_data = wrapped_error_device_auto_buffer_in_d_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign out_xbar_auto_out_0_d_bits_corrupt = wrapped_error_device_auto_buffer_in_d_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign buffer_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72319.4]
assign buffer_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72320.4]
assign buffer_auto_in_a_valid = atomics_auto_out_a_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_opcode = atomics_auto_out_a_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_param = atomics_auto_out_a_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_size = atomics_auto_out_a_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_source = atomics_auto_out_a_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_address = atomics_auto_out_a_bits_address; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_mask = atomics_auto_out_a_bits_mask; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_data = atomics_auto_out_a_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_a_bits_corrupt = atomics_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_in_d_ready = atomics_auto_out_d_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign buffer_auto_out_a_ready = fixer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_valid = fixer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_opcode = fixer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_param = fixer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_size = fixer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_source = fixer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_sink = fixer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_denied = fixer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_data = fixer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign buffer_auto_out_d_bits_corrupt = fixer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72387.4]
assign atomics_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72325.4]
assign atomics_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72326.4]
assign atomics_auto_in_a_valid = in_xbar_auto_out_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_opcode = in_xbar_auto_out_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_param = in_xbar_auto_out_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_size = in_xbar_auto_out_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_source = in_xbar_auto_out_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_address = in_xbar_auto_out_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_mask = in_xbar_auto_out_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_data = in_xbar_auto_out_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_a_bits_corrupt = in_xbar_auto_out_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_in_d_ready = in_xbar_auto_out_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72381.4]
assign atomics_auto_out_a_ready = buffer_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_valid = buffer_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_param = buffer_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_size = buffer_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_source = buffer_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_sink = buffer_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_denied = buffer_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_data = buffer_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign atomics_auto_out_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72388.4]
assign wrapped_error_device_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72331.4]
assign wrapped_error_device_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72332.4]
assign wrapped_error_device_auto_buffer_in_a_valid = out_xbar_auto_out_0_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_opcode = out_xbar_auto_out_0_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_param = out_xbar_auto_out_0_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_size = out_xbar_auto_out_0_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_source = out_xbar_auto_out_0_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_address = out_xbar_auto_out_0_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_mask = out_xbar_auto_out_0_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_a_bits_corrupt = out_xbar_auto_out_0_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign wrapped_error_device_auto_buffer_in_d_ready = out_xbar_auto_out_0_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72382.4]
assign coupler_to_plic_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72337.4]
assign coupler_to_plic_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72338.4]
assign coupler_to_plic_auto_fragmenter_in_a_valid = out_xbar_auto_out_1_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_1_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_1_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_1_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_1_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_1_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_1_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_data = out_xbar_auto_out_1_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_1_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_in_d_ready = out_xbar_auto_out_1_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72383.4]
assign coupler_to_plic_auto_fragmenter_out_a_ready = auto_coupler_to_plic_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign coupler_to_plic_auto_fragmenter_out_d_valid = auto_coupler_to_plic_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign coupler_to_plic_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_plic_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign coupler_to_plic_auto_fragmenter_out_d_bits_size = auto_coupler_to_plic_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign coupler_to_plic_auto_fragmenter_out_d_bits_source = auto_coupler_to_plic_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign coupler_to_plic_auto_fragmenter_out_d_bits_data = auto_coupler_to_plic_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72392.4]
assign coupler_to_clint_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72343.4]
assign coupler_to_clint_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72344.4]
assign coupler_to_clint_auto_fragmenter_in_a_valid = out_xbar_auto_out_2_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_2_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_2_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_2_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_2_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_2_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_2_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_data = out_xbar_auto_out_2_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_2_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_in_d_ready = out_xbar_auto_out_2_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72384.4]
assign coupler_to_clint_auto_fragmenter_out_a_ready = auto_coupler_to_clint_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign coupler_to_clint_auto_fragmenter_out_d_valid = auto_coupler_to_clint_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign coupler_to_clint_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_clint_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign coupler_to_clint_auto_fragmenter_out_d_bits_size = auto_coupler_to_clint_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign coupler_to_clint_auto_fragmenter_out_d_bits_source = auto_coupler_to_clint_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign coupler_to_clint_auto_fragmenter_out_d_bits_data = auto_coupler_to_clint_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72393.4]
assign coupler_to_debug_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72349.4]
assign coupler_to_debug_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72350.4]
assign coupler_to_debug_auto_fragmenter_in_a_valid = out_xbar_auto_out_3_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_3_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_3_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_3_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_3_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_3_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_3_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_data = out_xbar_auto_out_3_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_3_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_in_d_ready = out_xbar_auto_out_3_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72385.4]
assign coupler_to_debug_auto_fragmenter_out_a_ready = auto_coupler_to_debug_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign coupler_to_debug_auto_fragmenter_out_d_valid = auto_coupler_to_debug_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign coupler_to_debug_auto_fragmenter_out_d_bits_opcode = auto_coupler_to_debug_fragmenter_out_d_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign coupler_to_debug_auto_fragmenter_out_d_bits_size = auto_coupler_to_debug_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign coupler_to_debug_auto_fragmenter_out_d_bits_source = auto_coupler_to_debug_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign coupler_to_debug_auto_fragmenter_out_d_bits_data = auto_coupler_to_debug_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72394.4]
assign coupler_to_bootrom_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72361.4]
assign coupler_to_bootrom_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72362.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_valid = out_xbar_auto_out_4_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_opcode = out_xbar_auto_out_4_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_param = out_xbar_auto_out_4_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_size = out_xbar_auto_out_4_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_source = out_xbar_auto_out_4_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_address = out_xbar_auto_out_4_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_mask = out_xbar_auto_out_4_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_a_bits_corrupt = out_xbar_auto_out_4_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_in_d_ready = out_xbar_auto_out_4_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72386.4]
assign coupler_to_bootrom_auto_fragmenter_out_a_ready = auto_coupler_to_bootrom_fragmenter_out_a_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign coupler_to_bootrom_auto_fragmenter_out_d_valid = auto_coupler_to_bootrom_fragmenter_out_d_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign coupler_to_bootrom_auto_fragmenter_out_d_bits_size = auto_coupler_to_bootrom_fragmenter_out_d_bits_size; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign coupler_to_bootrom_auto_fragmenter_out_d_bits_source = auto_coupler_to_bootrom_fragmenter_out_d_bits_source; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign coupler_to_bootrom_auto_fragmenter_out_d_bits_data = auto_coupler_to_bootrom_fragmenter_out_d_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@72395.4]
assign buffer_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72367.4]
assign buffer_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@72368.4]
assign buffer_1_auto_in_a_valid = auto_bus_xing_in_a_valid; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_opcode = auto_bus_xing_in_a_bits_opcode; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_param = auto_bus_xing_in_a_bits_param; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_size = auto_bus_xing_in_a_bits_size; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_source = auto_bus_xing_in_a_bits_source; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_address = auto_bus_xing_in_a_bits_address; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_mask = auto_bus_xing_in_a_bits_mask; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_data = auto_bus_xing_in_a_bits_data; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_a_bits_corrupt = auto_bus_xing_in_a_bits_corrupt; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_in_d_ready = auto_bus_xing_in_d_ready; // @[LazyModule.scala 167:57:freechips.rocketchip.system.LowRiscConfig.fir@72390.4]
assign buffer_1_auto_out_a_ready = in_xbar_auto_in_a_ready; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_valid = in_xbar_auto_in_d_valid; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_opcode = in_xbar_auto_in_d_bits_opcode; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_param = in_xbar_auto_in_d_bits_param; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_size = in_xbar_auto_in_d_bits_size; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_source = in_xbar_auto_in_d_bits_source; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_sink = in_xbar_auto_in_d_bits_sink; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_denied = in_xbar_auto_in_d_bits_denied; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_data = in_xbar_auto_in_d_bits_data; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
assign buffer_1_auto_out_d_bits_corrupt = in_xbar_auto_in_d_bits_corrupt; // @[LazyModule.scala 167:31:freechips.rocketchip.system.LowRiscConfig.fir@72389.4]
endmodule
module TLMonitor_31( // @[:freechips.rocketchip.system.LowRiscConfig.fir@72452.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72453.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72454.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [8:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [27:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
input [8:0] io_in_d_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@72455.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@73624.4]
wire _T_26; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@72476.6]
wire [5:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@72482.6]
wire [2:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@72483.6]
wire [2:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@72484.6]
wire [27:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@72485.6]
wire [27:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@72485.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@72486.6]
wire [2:0] _T_41; // @[Misc.scala 200:34:freechips.rocketchip.system.LowRiscConfig.fir@72487.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@72488.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@72489.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@72490.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@72491.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@72492.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@72493.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@72494.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@72495.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72497.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72498.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72500.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72501.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@72502.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@72503.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@72504.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72505.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72506.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72507.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72508.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72509.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72510.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72511.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72512.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72513.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72514.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72515.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72516.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@72517.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@72518.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@72519.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72520.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72521.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72522.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72523.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72524.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72525.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72526.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72527.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72528.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72529.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72530.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72531.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72532.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72533.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72534.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72535.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72536.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72537.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72538.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72539.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72540.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72541.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72542.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72543.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@72550.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@72573.6]
wire [27:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@72576.8]
wire [28:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@72577.8]
wire [28:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@72578.8]
wire [28:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@72579.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@72580.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@72585.8]
wire _T_139; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@72598.8]
wire _T_140; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@72599.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@72606.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@72607.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@72613.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@72614.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@72619.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@72621.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@72622.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@72627.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@72628.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@72630.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@72631.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@72636.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@72638.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@72639.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@72645.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@72699.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@72701.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@72702.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@72725.6]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72739.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72740.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@72759.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@72761.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@72762.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@72767.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@72769.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@72770.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@72784.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@72835.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@72877.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@72878.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@72879.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@72881.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@72882.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@72888.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@72919.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@72921.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@72922.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@72936.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@72967.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@72969.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@72970.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@72984.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@73034.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@73036.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@73037.6]
wire _T_384; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@73048.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@73054.6]
wire _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73057.8]
wire _T_397; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73058.8]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@73063.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@73065.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@73066.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@73096.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@73154.6]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@73213.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@73248.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@73284.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@73344.4]
reg _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@73353.4]
reg [31:0] _RAND_0;
wire [1:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73354.4]
wire [1:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73355.4]
wire _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73356.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73357.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@73368.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@73369.4]
reg [31:0] _RAND_2;
reg [1:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@73370.4]
reg [31:0] _RAND_3;
reg [8:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@73371.4]
reg [31:0] _RAND_4;
reg [27:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@73372.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@73373.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@73374.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@73376.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@73378.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@73379.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@73384.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@73386.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@73387.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@73392.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@73394.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@73395.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@73400.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@73402.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@73403.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@73408.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@73410.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@73411.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@73418.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@73426.4]
reg _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@73434.4]
reg [31:0] _RAND_6;
wire [1:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73435.4]
wire [1:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73436.4]
wire _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73437.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73438.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@73449.4]
reg [31:0] _RAND_7;
reg [1:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@73451.4]
reg [31:0] _RAND_8;
reg [8:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@73452.4]
reg [31:0] _RAND_9;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@73455.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@73456.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@73458.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@73460.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@73461.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@73474.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@73476.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@73477.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@73482.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@73484.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@73485.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@73508.4]
reg [399:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@73517.4]
reg [415:0] _RAND_10;
reg _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@73527.4]
reg [31:0] _RAND_11;
wire [1:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73528.4]
wire [1:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73529.4]
wire _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73530.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73531.4]
reg _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@73550.4]
reg [31:0] _RAND_12;
wire [1:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73551.4]
wire [1:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73552.4]
wire _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73553.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73554.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@73569.4]
wire [511:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@73572.6]
wire [399:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@73574.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@73575.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@73576.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@73578.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@73579.6]
wire [511:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@73571.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@73590.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@73592.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@73593.4]
wire [511:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@73595.6]
wire [399:0] _T_698; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73565.4 :freechips.rocketchip.system.LowRiscConfig.fir@73567.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@73573.6]
wire [399:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@73597.6]
wire [399:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@73598.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@73599.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@73601.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@73602.6]
wire [511:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@73594.4]
wire [399:0] _T_710; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73585.4 :freechips.rocketchip.system.LowRiscConfig.fir@73587.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@73596.6]
wire _T_724; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@73608.4]
wire _T_725; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@73609.4]
wire _T_726; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@73610.4]
wire _T_727; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@73611.4]
wire _T_729; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@73613.4]
wire _T_730; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@73614.4]
wire [399:0] _T_731; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@73619.4]
wire [399:0] _T_732; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@73620.4]
wire [399:0] _T_733; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@73621.4]
reg [31:0] _T_735; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@73623.4]
reg [31:0] _RAND_13;
wire _T_736; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@73626.4]
wire _T_737; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@73627.4]
wire _T_738; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@73628.4]
wire _T_739; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@73629.4]
wire _T_740; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@73630.4]
wire _T_741; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@73631.4]
wire _T_743; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@73633.4]
wire _T_744; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@73634.4]
wire [31:0] _T_746; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@73640.4]
wire _T_749; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@73644.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@72587.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@72659.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72742.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@72801.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@72852.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@72902.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@72950.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@72998.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73060.10]
wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@73102.10]
wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@73160.10]
wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@73219.10]
wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@73254.10]
wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@73290.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@73624.4]
.out(plusarg_reader_out)
);
assign _T_26 = io_in_a_bits_source <= 9'h18f; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@72476.6]
assign _T_36 = 6'h7 << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@72482.6]
assign _T_37 = _T_36[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@72483.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@72484.6]
assign _GEN_18 = {{25'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@72485.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@72485.6]
assign _T_40 = _T_39 == 28'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@72486.6]
assign _T_41 = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 200:34:freechips.rocketchip.system.LowRiscConfig.fir@72487.6]
assign _T_42 = _T_41[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@72488.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@72489.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@72490.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@72491.6]
assign _T_46 = io_in_a_bits_size >= 2'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@72492.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@72493.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@72494.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@72495.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72497.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72498.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72500.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72501.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@72502.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@72503.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@72504.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72505.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72506.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72507.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72508.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72509.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72510.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72511.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72512.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72513.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72514.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72515.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72516.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@72517.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@72518.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@72519.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72520.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72521.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72522.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72523.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72524.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72525.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72526.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72527.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72528.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72529.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72530.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72531.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72532.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72533.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72534.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72535.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72536.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72537.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72538.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72539.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72540.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@72541.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@72542.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@72543.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@72550.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@72573.6]
assign _T_125 = io_in_a_bits_address ^ 28'hc000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@72576.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@72577.8]
assign _T_127 = $signed(_T_126) & $signed(-29'sh4000000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@72578.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@72579.8]
assign _T_129 = $signed(_T_128) == $signed(29'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@72580.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@72585.8]
assign _T_139 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@72598.8]
assign _T_140 = _T_139 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@72599.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@72606.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@72607.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@72613.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@72614.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@72619.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@72621.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@72622.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@72627.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@72628.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@72630.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@72631.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@72636.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@72638.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@72639.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@72645.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@72699.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@72701.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@72702.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@72725.6]
assign _T_216 = _T_129 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72739.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72740.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@72759.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@72761.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@72762.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@72767.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@72769.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@72770.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@72784.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@72835.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@72877.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@72878.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@72879.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@72881.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@72882.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@72888.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@72919.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@72921.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@72922.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@72936.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@72967.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@72969.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@72970.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@72984.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@73034.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@73036.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@73037.6]
assign _T_384 = io_in_d_bits_source <= 9'h18f; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@73048.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@73054.6]
assign _T_396 = _T_384 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73057.8]
assign _T_397 = _T_396 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73058.8]
assign _T_398 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@73063.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@73065.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@73066.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@73096.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@73154.6]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@73213.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@73248.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@73284.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@73344.4]
assign _T_546 = _T_545 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73354.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73355.4]
assign _T_548 = _T_547[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73356.4]
assign _T_549 = _T_545 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73357.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@73373.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@73374.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@73376.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@73378.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@73379.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@73384.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@73386.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@73387.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@73392.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@73394.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@73395.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@73400.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@73402.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@73403.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@73408.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@73410.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@73411.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@73418.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@73426.4]
assign _T_601 = _T_600 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73435.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73436.4]
assign _T_603 = _T_602[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73437.4]
assign _T_604 = _T_600 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73438.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@73455.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@73456.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@73458.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@73460.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@73461.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@73474.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@73476.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@73477.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@73482.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@73484.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@73485.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@73508.4]
assign _T_665 = _T_664 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73528.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73529.4]
assign _T_667 = _T_666[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73530.4]
assign _T_668 = _T_664 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73531.4]
assign _T_686 = _T_685 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73551.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73552.4]
assign _T_688 = _T_687[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@73553.4]
assign _T_689 = _T_685 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@73554.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@73569.4]
assign _T_702 = 512'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@73572.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@73574.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@73575.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@73576.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@73578.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@73579.6]
assign _GEN_15 = _T_700 ? _T_702 : 512'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@73571.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@73590.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@73592.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@73593.4]
assign _T_717 = 512'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@73595.6]
assign _T_698 = _GEN_15[399:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73565.4 :freechips.rocketchip.system.LowRiscConfig.fir@73567.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@73573.6]
assign _T_718 = _T_698 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@73597.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@73598.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@73599.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@73601.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@73602.6]
assign _GEN_16 = _T_716 ? _T_717 : 512'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@73594.4]
assign _T_710 = _GEN_16[399:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73585.4 :freechips.rocketchip.system.LowRiscConfig.fir@73587.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@73596.6]
assign _T_724 = _T_698 != _T_710; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@73608.4]
assign _T_725 = _T_698 != 400'h0; // @[Monitor.scala 471:40:freechips.rocketchip.system.LowRiscConfig.fir@73609.4]
assign _T_726 = _T_725 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@73610.4]
assign _T_727 = _T_724 | _T_726; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@73611.4]
assign _T_729 = _T_727 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@73613.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@73614.4]
assign _T_731 = _T_653 | _T_698; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@73619.4]
assign _T_732 = ~ _T_710; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@73620.4]
assign _T_733 = _T_731 & _T_732; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@73621.4]
assign _T_736 = _T_653 != 400'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@73626.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@73627.4]
assign _T_738 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@73628.4]
assign _T_739 = _T_737 | _T_738; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@73629.4]
assign _T_740 = _T_735 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@73630.4]
assign _T_741 = _T_739 | _T_740; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@73631.4]
assign _T_743 = _T_741 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@73633.4]
assign _T_744 = _T_743 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@73634.4]
assign _T_746 = _T_735 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@73640.4]
assign _T_749 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@73644.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@72587.10]
assign _GEN_35 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@72659.10]
assign _GEN_53 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72742.10]
assign _GEN_65 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@72801.10]
assign _GEN_75 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@72852.10]
assign _GEN_85 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@72902.10]
assign _GEN_95 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@72950.10]
assign _GEN_105 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@72998.10]
assign _GEN_115 = io_in_d_valid & _T_394; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73060.10]
assign _GEN_119 = io_in_d_valid & _T_414; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@73102.10]
assign _GEN_125 = io_in_d_valid & _T_442; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@73160.10]
assign _GEN_131 = io_in_d_valid & _T_471; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@73219.10]
assign _GEN_133 = io_in_d_valid & _T_488; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@73254.10]
assign _GEN_135 = io_in_d_valid & _T_506; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@73290.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[27:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {13{`RANDOM}};
_T_653 = _RAND_10[399:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_664 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_685 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_735 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 1'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
_T_545 <= 1'h0;
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 1'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
_T_600 <= 1'h0;
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (reset) begin
_T_653 <= 400'h0;
end else begin
_T_653 <= _T_733;
end
if (reset) begin
_T_664 <= 1'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
_T_664 <= 1'h0;
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 1'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
_T_685 <= 1'h0;
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_735 <= 32'h0;
end else begin
if (_T_749) begin
_T_735 <= 32'h0;
end else begin
_T_735 <= _T_746;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Plic.scala:366:15)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@72467.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@72468.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@72570.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@72571.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@72587.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@72588.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Plic.scala:366:15)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@72594.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@72595.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@72601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_140) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@72602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Plic.scala:366:15)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@72609.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@72610.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@72616.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@72617.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Plic.scala:366:15)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@72624.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@72625.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@72633.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@72634.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@72641.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@72642.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@72659.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@72660.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Plic.scala:366:15)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@72666.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@72667.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@72673.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_140) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@72674.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Plic.scala:366:15)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@72681.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@72682.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@72688.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@72689.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Plic.scala:366:15)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@72696.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@72697.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Plic.scala:366:15)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@72704.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@72705.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@72713.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@72714.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@72721.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@72722.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72742.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@72743.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@72749.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_140) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@72750.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@72756.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@72757.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@72764.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@72765.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@72772.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@72773.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@72780.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@72781.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@72801.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@72802.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@72808.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_140) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@72809.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@72815.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@72816.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@72823.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@72824.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@72831.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@72832.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@72852.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@72853.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@72859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_140) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@72860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@72866.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@72867.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@72874.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@72875.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@72884.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@72885.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@72902.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@72903.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@72909.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_140) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@72910.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@72916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@72917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Plic.scala:366:15)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@72924.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@72925.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@72932.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@72933.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@72950.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@72951.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@72957.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_140) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@72958.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@72964.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@72965.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Plic.scala:366:15)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@72972.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@72973.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@72980.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@72981.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Plic.scala:366:15)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@72998.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@72999.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@73005.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_140) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@73006.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Plic.scala:366:15)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@73012.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@73013.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Plic.scala:366:15)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@73020.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@73021.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@73028.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@73029.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Plic.scala:366:15)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@73039.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@73040.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73060.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_397) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@73061.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Plic.scala:366:15)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@73068.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@73069.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@73076.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@73077.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@73084.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@73085.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Plic.scala:366:15)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@73092.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@73093.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@73102.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_397) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@73103.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Plic.scala:366:15)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@73109.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@73110.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Plic.scala:366:15)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@73117.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@73118.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Plic.scala:366:15)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@73125.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@73126.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Plic.scala:366:15)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@73133.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@73134.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@73141.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@73142.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Plic.scala:366:15)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@73150.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@73151.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@73160.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_397) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@73161.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Plic.scala:366:15)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@73167.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@73168.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Plic.scala:366:15)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@73175.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@73176.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Plic.scala:366:15)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@73183.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@73184.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Plic.scala:366:15)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@73191.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@73192.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@73200.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@73201.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Plic.scala:366:15)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@73209.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@73210.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@73219.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_397) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@73220.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@73227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@73228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@73235.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@73236.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Plic.scala:366:15)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@73244.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@73245.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_133 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@73254.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_133 & _T_397) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@73255.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@73262.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@73263.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@73271.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@73272.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Plic.scala:366:15)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@73280.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@73281.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Plic.scala:366:15)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@73290.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_397) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@73291.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Plic.scala:366:15)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@73298.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@73299.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Plic.scala:366:15)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@73306.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@73307.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Plic.scala:366:15)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@73315.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@73316.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Plic.scala:366:15)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@73325.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@73326.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Plic.scala:366:15)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@73333.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@73334.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Plic.scala:366:15)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@73341.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@73342.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@73381.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@73382.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@73389.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@73390.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@73397.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@73398.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@73405.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@73406.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@73413.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@73414.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@73463.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@73464.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@73471.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@73472.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@73479.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@73480.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@73487.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@73488.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@73495.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@73496.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Plic.scala:366:15)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@73503.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@73504.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Plic.scala:366:15)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@73581.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@73582.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Plic.scala:366:15)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@73604.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@73605.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_730) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 1 (connected at Plic.scala:366:15)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@73616.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_730) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@73617.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_744) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Plic.scala:366:15)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@73636.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_744) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@73637.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module LevelGateway( // @[:freechips.rocketchip.system.LowRiscConfig.fir@73649.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73650.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73651.4]
input io_interrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73652.4]
output io_plic_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73652.4]
input io_plic_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73652.4]
input io_plic_complete // @[:freechips.rocketchip.system.LowRiscConfig.fir@73652.4]
);
reg inFlight; // @[Plic.scala 34:21:freechips.rocketchip.system.LowRiscConfig.fir@73657.4]
reg [31:0] _RAND_0;
wire _T_9; // @[Plic.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@73658.4]
wire _T_10; // @[Plic.scala 37:36:freechips.rocketchip.system.LowRiscConfig.fir@73665.4]
assign _T_9 = io_interrupt & io_plic_ready; // @[Plic.scala 35:22:freechips.rocketchip.system.LowRiscConfig.fir@73658.4]
assign _T_10 = inFlight == 1'h0; // @[Plic.scala 37:36:freechips.rocketchip.system.LowRiscConfig.fir@73665.4]
assign io_plic_valid = io_interrupt & _T_10; // @[Plic.scala 37:17:freechips.rocketchip.system.LowRiscConfig.fir@73667.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
inFlight = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
inFlight <= 1'h0;
end else begin
if (io_plic_complete) begin
inFlight <= 1'h0;
end else begin
if (_T_9) begin
inFlight <= 1'h1;
end
end
end
end
endmodule
module PLICFanIn( // @[:freechips.rocketchip.system.LowRiscConfig.fir@73729.2]
input [2:0] io_prio_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
input [2:0] io_prio_1, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
input [2:0] io_prio_2, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
input [2:0] io_prio_3, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
input [3:0] io_ip, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
output [2:0] io_dev, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
output [2:0] io_max // @[:freechips.rocketchip.system.LowRiscConfig.fir@73732.4]
);
wire _T_14; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73738.4]
wire _T_15; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73739.4]
wire _T_16; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73740.4]
wire _T_17; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73741.4]
wire [3:0] effectivePriority_1; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73742.4]
wire [3:0] effectivePriority_2; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73743.4]
wire [3:0] effectivePriority_3; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73744.4]
wire [3:0] effectivePriority_4; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73745.4]
wire _T_18; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73746.4]
wire [3:0] _T_20; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73748.4]
wire _T_21; // @[Misc.scala 33:36:freechips.rocketchip.system.LowRiscConfig.fir@73749.4]
wire _T_22; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73750.4]
wire [3:0] _T_24; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73752.4]
wire _T_25; // @[Misc.scala 33:36:freechips.rocketchip.system.LowRiscConfig.fir@73753.4]
wire _T_26; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73754.4]
wire [1:0] _GEN_0; // @[Plic.scala 352:61:freechips.rocketchip.system.LowRiscConfig.fir@73755.4]
wire [1:0] _T_27; // @[Plic.scala 352:61:freechips.rocketchip.system.LowRiscConfig.fir@73755.4]
wire [3:0] _T_28; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73756.4]
wire [1:0] _T_29; // @[Misc.scala 33:36:freechips.rocketchip.system.LowRiscConfig.fir@73757.4]
wire _T_30; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73758.4]
wire [3:0] maxPri; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73760.4]
assign _T_14 = io_ip[0]; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73738.4]
assign _T_15 = io_ip[1]; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73739.4]
assign _T_16 = io_ip[2]; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73740.4]
assign _T_17 = io_ip[3]; // @[Plic.scala 356:59:freechips.rocketchip.system.LowRiscConfig.fir@73741.4]
assign effectivePriority_1 = {_T_14,io_prio_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73742.4]
assign effectivePriority_2 = {_T_15,io_prio_1}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73743.4]
assign effectivePriority_3 = {_T_16,io_prio_2}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73744.4]
assign effectivePriority_4 = {_T_17,io_prio_3}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73745.4]
assign _T_18 = 4'h8 >= effectivePriority_1; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73746.4]
assign _T_20 = _T_18 ? 4'h8 : effectivePriority_1; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73748.4]
assign _T_21 = _T_18 ? 1'h0 : 1'h1; // @[Misc.scala 33:36:freechips.rocketchip.system.LowRiscConfig.fir@73749.4]
assign _T_22 = effectivePriority_2 >= effectivePriority_3; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73750.4]
assign _T_24 = _T_22 ? effectivePriority_2 : effectivePriority_3; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73752.4]
assign _T_25 = _T_22 ? 1'h0 : 1'h1; // @[Misc.scala 33:36:freechips.rocketchip.system.LowRiscConfig.fir@73753.4]
assign _T_26 = _T_20 >= _T_24; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73754.4]
assign _GEN_0 = {{1'd0}, _T_25}; // @[Plic.scala 352:61:freechips.rocketchip.system.LowRiscConfig.fir@73755.4]
assign _T_27 = 2'h2 | _GEN_0; // @[Plic.scala 352:61:freechips.rocketchip.system.LowRiscConfig.fir@73755.4]
assign _T_28 = _T_26 ? _T_20 : _T_24; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73756.4]
assign _T_29 = _T_26 ? {{1'd0}, _T_21} : _T_27; // @[Misc.scala 33:36:freechips.rocketchip.system.LowRiscConfig.fir@73757.4]
assign _T_30 = _T_28 >= effectivePriority_4; // @[Plic.scala 352:20:freechips.rocketchip.system.LowRiscConfig.fir@73758.4]
assign maxPri = _T_30 ? _T_28 : effectivePriority_4; // @[Misc.scala 33:9:freechips.rocketchip.system.LowRiscConfig.fir@73760.4]
assign io_dev = _T_30 ? {{1'd0}, _T_29} : 3'h4; // @[Plic.scala 359:10:freechips.rocketchip.system.LowRiscConfig.fir@73763.4]
assign io_max = maxPri[2:0]; // @[Plic.scala 358:10:freechips.rocketchip.system.LowRiscConfig.fir@73762.4]
endmodule
module Queue_83( // @[:freechips.rocketchip.system.LowRiscConfig.fir@73801.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73802.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73803.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input io_enq_bits_read, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input [22:0] io_enq_bits_index, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input [63:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input [7:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input [10:0] io_enq_bits_extra, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
input io_deq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
output io_deq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
output io_deq_bits_read, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
output [22:0] io_deq_bits_index, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
output [63:0] io_deq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
output [7:0] io_deq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
output [10:0] io_deq_bits_extra // @[:freechips.rocketchip.system.LowRiscConfig.fir@73804.4]
);
reg _T_35_read [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [31:0] _RAND_0;
wire _T_35_read__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_read__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_read__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_read__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_read__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_read__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [22:0] _T_35_index [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [31:0] _RAND_1;
wire [22:0] _T_35_index__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_index__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire [22:0] _T_35_index__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_index__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_index__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_index__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [63:0] _T_35_data [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [63:0] _RAND_2;
wire [63:0] _T_35_data__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_data__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire [63:0] _T_35_data__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_data__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_data__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_data__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [7:0] _T_35_mask [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [31:0] _RAND_3;
wire [7:0] _T_35_mask__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_mask__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire [7:0] _T_35_mask__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_mask__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_mask__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_mask__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [10:0] _T_35_extra [0:0]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg [31:0] _RAND_4;
wire [10:0] _T_35_extra__T_52_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_extra__T_52_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire [10:0] _T_35_extra__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_extra__T_48_addr; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_extra__T_48_mask; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
wire _T_35_extra__T_48_en; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
reg _T_37; // @[Decoupled.scala 217:35:freechips.rocketchip.system.LowRiscConfig.fir@73807.4]
reg [31:0] _RAND_5;
wire _T_39; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@73809.4]
wire _T_42; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@73812.4]
wire _T_45; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@73815.4]
wire _T_49; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@73828.4]
assign _T_35_read__T_52_addr = 1'h0;
assign _T_35_read__T_52_data = _T_35_read[_T_35_read__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
assign _T_35_read__T_48_data = io_enq_bits_read;
assign _T_35_read__T_48_addr = 1'h0;
assign _T_35_read__T_48_mask = 1'h1;
assign _T_35_read__T_48_en = io_enq_ready & io_enq_valid;
assign _T_35_index__T_52_addr = 1'h0;
assign _T_35_index__T_52_data = _T_35_index[_T_35_index__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
assign _T_35_index__T_48_data = io_enq_bits_index;
assign _T_35_index__T_48_addr = 1'h0;
assign _T_35_index__T_48_mask = 1'h1;
assign _T_35_index__T_48_en = io_enq_ready & io_enq_valid;
assign _T_35_data__T_52_addr = 1'h0;
assign _T_35_data__T_52_data = _T_35_data[_T_35_data__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
assign _T_35_data__T_48_data = io_enq_bits_data;
assign _T_35_data__T_48_addr = 1'h0;
assign _T_35_data__T_48_mask = 1'h1;
assign _T_35_data__T_48_en = io_enq_ready & io_enq_valid;
assign _T_35_mask__T_52_addr = 1'h0;
assign _T_35_mask__T_52_data = _T_35_mask[_T_35_mask__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
assign _T_35_mask__T_48_data = io_enq_bits_mask;
assign _T_35_mask__T_48_addr = 1'h0;
assign _T_35_mask__T_48_mask = 1'h1;
assign _T_35_mask__T_48_en = io_enq_ready & io_enq_valid;
assign _T_35_extra__T_52_addr = 1'h0;
assign _T_35_extra__T_52_data = _T_35_extra[_T_35_extra__T_52_addr]; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
assign _T_35_extra__T_48_data = io_enq_bits_extra;
assign _T_35_extra__T_48_addr = 1'h0;
assign _T_35_extra__T_48_mask = 1'h1;
assign _T_35_extra__T_48_en = io_enq_ready & io_enq_valid;
assign _T_39 = _T_37 == 1'h0; // @[Decoupled.scala 220:36:freechips.rocketchip.system.LowRiscConfig.fir@73809.4]
assign _T_42 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@73812.4]
assign _T_45 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@73815.4]
assign _T_49 = _T_42 != _T_45; // @[Decoupled.scala 232:16:freechips.rocketchip.system.LowRiscConfig.fir@73828.4]
assign io_enq_ready = _T_37 == 1'h0; // @[Decoupled.scala 237:16:freechips.rocketchip.system.LowRiscConfig.fir@73835.4]
assign io_deq_valid = _T_39 == 1'h0; // @[Decoupled.scala 236:16:freechips.rocketchip.system.LowRiscConfig.fir@73833.4]
assign io_deq_bits_read = _T_35_read__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@73841.4]
assign io_deq_bits_index = _T_35_index__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@73840.4]
assign io_deq_bits_data = _T_35_data__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@73839.4]
assign io_deq_bits_mask = _T_35_mask__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@73838.4]
assign io_deq_bits_extra = _T_35_extra__T_52_data; // @[Decoupled.scala 238:15:freechips.rocketchip.system.LowRiscConfig.fir@73837.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_read[initvar] = _RAND_0[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_index[initvar] = _RAND_1[22:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {2{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_data[initvar] = _RAND_2[63:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_mask[initvar] = _RAND_3[7:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 1; initvar = initvar+1)
_T_35_extra[initvar] = _RAND_4[10:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_37 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if(_T_35_read__T_48_en & _T_35_read__T_48_mask) begin
_T_35_read[_T_35_read__T_48_addr] <= _T_35_read__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
end
if(_T_35_index__T_48_en & _T_35_index__T_48_mask) begin
_T_35_index[_T_35_index__T_48_addr] <= _T_35_index__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
end
if(_T_35_data__T_48_en & _T_35_data__T_48_mask) begin
_T_35_data[_T_35_data__T_48_addr] <= _T_35_data__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
end
if(_T_35_mask__T_48_en & _T_35_mask__T_48_mask) begin
_T_35_mask[_T_35_mask__T_48_addr] <= _T_35_mask__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
end
if(_T_35_extra__T_48_en & _T_35_extra__T_48_mask) begin
_T_35_extra[_T_35_extra__T_48_addr] <= _T_35_extra__T_48_data; // @[Decoupled.scala 214:24:freechips.rocketchip.system.LowRiscConfig.fir@73806.4]
end
if (reset) begin
_T_37 <= 1'h0;
end else begin
if (_T_49) begin
_T_37 <= _T_42;
end
end
end
endmodule
module TLPLIC( // @[:freechips.rocketchip.system.LowRiscConfig.fir@73849.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73850.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73851.4]
input auto_int_in_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input auto_int_in_1, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input auto_int_in_2, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input auto_int_in_3, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output auto_int_out_1_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output auto_int_out_0_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [1:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [8:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [27:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output [8:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
output [63:0] auto_in_d_bits_data // @[:freechips.rocketchip.system.LowRiscConfig.fir@73852.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [1:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [8:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [27:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire [8:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
wire LevelGateway_clock; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
wire LevelGateway_reset; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
wire LevelGateway_io_interrupt; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
wire LevelGateway_io_plic_valid; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
wire LevelGateway_io_plic_ready; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
wire LevelGateway_io_plic_complete; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
wire LevelGateway_1_clock; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
wire LevelGateway_1_reset; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
wire LevelGateway_1_io_interrupt; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
wire LevelGateway_1_io_plic_valid; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
wire LevelGateway_1_io_plic_ready; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
wire LevelGateway_1_io_plic_complete; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
wire LevelGateway_2_clock; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
wire LevelGateway_2_reset; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
wire LevelGateway_2_io_interrupt; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
wire LevelGateway_2_io_plic_valid; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
wire LevelGateway_2_io_plic_ready; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
wire LevelGateway_2_io_plic_complete; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
wire LevelGateway_3_clock; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
wire LevelGateway_3_reset; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
wire LevelGateway_3_io_interrupt; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
wire LevelGateway_3_io_plic_valid; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
wire LevelGateway_3_io_plic_ready; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
wire LevelGateway_3_io_plic_complete; // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
wire [2:0] PLICFanIn_io_prio_0; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [2:0] PLICFanIn_io_prio_1; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [2:0] PLICFanIn_io_prio_2; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [2:0] PLICFanIn_io_prio_3; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [3:0] PLICFanIn_io_ip; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [2:0] PLICFanIn_io_dev; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [2:0] PLICFanIn_io_max; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
wire [2:0] PLICFanIn_1_io_prio_0; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire [2:0] PLICFanIn_1_io_prio_1; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire [2:0] PLICFanIn_1_io_prio_2; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire [2:0] PLICFanIn_1_io_prio_3; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire [3:0] PLICFanIn_1_io_ip; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire [2:0] PLICFanIn_1_io_dev; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire [2:0] PLICFanIn_1_io_max; // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
wire Queue_clock; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_reset; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_io_enq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_io_enq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_io_enq_bits_read; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [22:0] Queue_io_enq_bits_index; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [63:0] Queue_io_enq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [7:0] Queue_io_enq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [10:0] Queue_io_enq_bits_extra; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_io_deq_ready; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_io_deq_valid; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire Queue_io_deq_bits_read; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [22:0] Queue_io_deq_bits_index; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [63:0] Queue_io_deq_bits_data; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [7:0] Queue_io_deq_bits_mask; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
wire [10:0] Queue_io_deq_bits_extra; // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
reg [2:0] priority_0; // @[Plic.scala 176:31:freechips.rocketchip.system.LowRiscConfig.fir@73926.4]
reg [31:0] _RAND_0;
reg [2:0] priority_1; // @[Plic.scala 176:31:freechips.rocketchip.system.LowRiscConfig.fir@73926.4]
reg [31:0] _RAND_1;
reg [2:0] priority_2; // @[Plic.scala 176:31:freechips.rocketchip.system.LowRiscConfig.fir@73926.4]
reg [31:0] _RAND_2;
reg [2:0] priority_3; // @[Plic.scala 176:31:freechips.rocketchip.system.LowRiscConfig.fir@73926.4]
reg [31:0] _RAND_3;
reg [2:0] threshold_0; // @[Plic.scala 179:31:freechips.rocketchip.system.LowRiscConfig.fir@73927.4]
reg [31:0] _RAND_4;
reg [2:0] threshold_1; // @[Plic.scala 179:31:freechips.rocketchip.system.LowRiscConfig.fir@73927.4]
reg [31:0] _RAND_5;
reg pending_0; // @[Plic.scala 181:22:freechips.rocketchip.system.LowRiscConfig.fir@73934.4]
reg [31:0] _RAND_6;
reg pending_1; // @[Plic.scala 181:22:freechips.rocketchip.system.LowRiscConfig.fir@73934.4]
reg [31:0] _RAND_7;
reg pending_2; // @[Plic.scala 181:22:freechips.rocketchip.system.LowRiscConfig.fir@73934.4]
reg [31:0] _RAND_8;
reg pending_3; // @[Plic.scala 181:22:freechips.rocketchip.system.LowRiscConfig.fir@73934.4]
reg [31:0] _RAND_9;
reg [3:0] enables_0_0; // @[Plic.scala 187:26:freechips.rocketchip.system.LowRiscConfig.fir@73935.4]
reg [31:0] _RAND_10;
reg [3:0] enables_1_0; // @[Plic.scala 187:26:freechips.rocketchip.system.LowRiscConfig.fir@73936.4]
reg [31:0] _RAND_11;
wire [4:0] enableVec0_0; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73941.4]
wire [4:0] enableVec0_1; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73942.4]
reg [2:0] maxDevs_0; // @[Plic.scala 194:22:freechips.rocketchip.system.LowRiscConfig.fir@73947.4]
reg [31:0] _RAND_12;
reg [2:0] maxDevs_1; // @[Plic.scala 194:22:freechips.rocketchip.system.LowRiscConfig.fir@73947.4]
reg [31:0] _RAND_13;
wire [3:0] pendingUInt; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73950.4]
reg [2:0] _T_337; // @[Plic.scala 201:41:freechips.rocketchip.system.LowRiscConfig.fir@73959.4]
reg [31:0] _RAND_14;
reg [2:0] _T_341; // @[Plic.scala 201:41:freechips.rocketchip.system.LowRiscConfig.fir@73971.4]
reg [31:0] _RAND_15;
wire _T_2246; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@75999.4]
wire _T_2247; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76000.4]
wire _T_1187; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74784.4]
wire _T_1179; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74776.4]
wire _T_1178; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74775.4]
wire _T_1173; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74770.4]
wire _T_1170; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74767.4]
wire _T_1169; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74766.4]
wire [5:0] _T_1196; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74793.4]
wire [63:0] _T_1262; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@74859.4]
wire _T_1303; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74900.4]
wire _T_2490; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76299.4]
wire [22:0] _T_445; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74096.4]
wire _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74110.4]
wire _T_2491; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76300.4]
wire _T_600; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74159.4]
wire [7:0] _T_616; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74175.4]
wire _T_599; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74158.4]
wire [7:0] _T_614; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74173.4]
wire _T_598; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74157.4]
wire [7:0] _T_612; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74171.4]
wire _T_597; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74156.4]
wire [7:0] _T_610; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74169.4]
wire _T_596; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74155.4]
wire [7:0] _T_608; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74167.4]
wire _T_595; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74154.4]
wire [7:0] _T_606; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74165.4]
wire _T_594; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74153.4]
wire [7:0] _T_604; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74163.4]
wire _T_593; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74152.4]
wire [7:0] _T_602; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74161.4]
wire [63:0] _T_623; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74182.4]
wire [31:0] _T_1022; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74602.4]
wire _T_1023; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74603.4]
wire claimer_1; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74608.4]
wire _T_1295; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74892.4]
wire _T_2442; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76240.4]
wire _T_2443; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76241.4]
wire claimer_0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74706.4]
wire [1:0] _T_350; // @[Plic.scala 252:21:freechips.rocketchip.system.LowRiscConfig.fir@73977.4]
wire [2:0] _T_352; // @[Plic.scala 252:46:freechips.rocketchip.system.LowRiscConfig.fir@73979.4]
wire [2:0] _T_353; // @[Plic.scala 252:46:freechips.rocketchip.system.LowRiscConfig.fir@73980.4]
wire [1:0] _T_354; // @[Plic.scala 252:46:freechips.rocketchip.system.LowRiscConfig.fir@73981.4]
wire [1:0] _T_355; // @[Plic.scala 252:28:freechips.rocketchip.system.LowRiscConfig.fir@73982.4]
wire _T_356; // @[Plic.scala 252:58:freechips.rocketchip.system.LowRiscConfig.fir@73983.4]
wire _T_358; // @[Plic.scala 252:11:freechips.rocketchip.system.LowRiscConfig.fir@73985.4]
wire _T_359; // @[Plic.scala 252:11:freechips.rocketchip.system.LowRiscConfig.fir@73986.4]
wire [2:0] _T_360; // @[Plic.scala 253:49:freechips.rocketchip.system.LowRiscConfig.fir@73991.4]
wire [2:0] _T_361; // @[Plic.scala 253:49:freechips.rocketchip.system.LowRiscConfig.fir@73992.4]
wire [2:0] claiming; // @[Plic.scala 253:96:freechips.rocketchip.system.LowRiscConfig.fir@73993.4]
wire [7:0] _T_363; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@73995.4]
wire [4:0] _T_364; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@73996.4]
wire claimedDevs_1; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@73998.4]
wire claimedDevs_2; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@73999.4]
wire claimedDevs_3; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@74000.4]
wire claimedDevs_4; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@74001.4]
wire _T_381; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74011.4]
wire _T_382; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74013.6]
wire _T_384; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74018.4]
wire _T_385; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74020.6]
wire _T_387; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74025.4]
wire _T_388; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74027.6]
wire _T_390; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74032.4]
wire _T_391; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74034.6]
wire _T_2706; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76537.4]
wire _T_2707; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76538.4]
wire _T_2950; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76837.4]
wire _T_2951; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76838.4]
wire [31:0] _T_1025; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74605.4]
wire _T_1026; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74606.4]
wire _T_1030; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74610.4]
wire [31:0] _T_1119; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74710.4]
wire [2:0] completerDev; // @[package.scala 119:13:freechips.rocketchip.system.LowRiscConfig.fir@74720.4]
wire [4:0] _T_1038; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74624.4]
wire _T_1039; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74625.4]
wire completer_1; // @[Plic.scala 302:35:freechips.rocketchip.system.LowRiscConfig.fir@74626.4]
wire _T_2902; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76778.4]
wire _T_2903; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76779.4]
wire _T_1118; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74708.4]
wire [4:0] _T_1126; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74722.4]
wire _T_1127; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74723.4]
wire completer_0; // @[Plic.scala 302:35:freechips.rocketchip.system.LowRiscConfig.fir@74724.4]
wire [1:0] _T_399; // @[Plic.scala 269:23:freechips.rocketchip.system.LowRiscConfig.fir@74039.4]
wire [2:0] _T_401; // @[Plic.scala 269:50:freechips.rocketchip.system.LowRiscConfig.fir@74041.4]
wire [2:0] _T_402; // @[Plic.scala 269:50:freechips.rocketchip.system.LowRiscConfig.fir@74042.4]
wire [1:0] _T_403; // @[Plic.scala 269:50:freechips.rocketchip.system.LowRiscConfig.fir@74043.4]
wire [1:0] _T_404; // @[Plic.scala 269:30:freechips.rocketchip.system.LowRiscConfig.fir@74044.4]
wire _T_405; // @[Plic.scala 269:62:freechips.rocketchip.system.LowRiscConfig.fir@74045.4]
wire _T_407; // @[Plic.scala 269:11:freechips.rocketchip.system.LowRiscConfig.fir@74047.4]
wire _T_408; // @[Plic.scala 269:11:freechips.rocketchip.system.LowRiscConfig.fir@74048.4]
wire _T_410; // @[Plic.scala 271:48:freechips.rocketchip.system.LowRiscConfig.fir@74055.4]
wire [7:0] _T_412; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@74057.4]
wire [4:0] _T_413; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@74058.4]
wire [4:0] completedDevs; // @[Plic.scala 271:28:freechips.rocketchip.system.LowRiscConfig.fir@74059.4]
wire [24:0] _T_427; // @[Edges.scala 192:34:freechips.rocketchip.system.LowRiscConfig.fir@74073.4]
wire _T_1279; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74876.4]
wire _T_2806; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76662.4]
wire _T_2807; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76663.4]
wire [3:0] _T_654; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74213.4]
wire [3:0] _T_657; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74216.4]
wire _T_658; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74217.4]
wire _T_662; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74221.4]
wire [3:0] _T_663; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74222.4]
wire [2:0] _T_681; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74243.4]
wire [2:0] _T_684; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74246.4]
wire _T_685; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74247.4]
wire _T_1263; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74860.4]
wire _T_2710; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76541.4]
wire _T_2711; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76542.4]
wire _T_689; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74251.4]
wire [2:0] _T_690; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74252.4]
wire [34:0] _T_700; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74265.4]
wire _T_1283; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74880.4]
wire _T_2830; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76692.4]
wire _T_2831; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76693.4]
wire _T_741; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74306.4]
wire [2:0] _T_760; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74328.4]
wire [2:0] _T_763; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74331.4]
wire _T_764; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74332.4]
wire _T_1264; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74861.4]
wire _T_2716; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76549.4]
wire _T_2717; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76550.4]
wire _T_768; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74336.4]
wire [2:0] _T_769; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74337.4]
wire _T_793; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74364.4]
wire [31:0] _T_803; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74377.4]
wire [34:0] _T_804; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74378.4]
wire [4:0] _T_937; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74511.4]
wire _T_1265; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74862.4]
wire _T_2722; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76558.4]
wire _T_2723; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76559.4]
wire _T_953; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74527.4]
wire _T_978; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74555.4]
wire [3:0] _T_1014; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74594.4]
wire [31:0] _T_1015; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74595.4]
wire _T_1033; // @[Plic.scala 299:33:freechips.rocketchip.system.LowRiscConfig.fir@74614.4]
wire _T_1035; // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74616.4]
wire _T_1036; // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74617.4]
wire [34:0] _T_1050; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74637.4]
wire [63:0] _T_1051; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74638.4]
wire _T_1066; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74653.4]
wire [3:0] _T_1102; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74692.4]
wire [31:0] _T_1103; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74693.4]
wire [34:0] _T_1138; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74735.4]
wire [63:0] _T_1139; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74736.4]
wire _T_3173; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77088.4]
wire _T_3174; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77093.6]
wire _T_3175; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77098.8]
wire _T_3176; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77103.10]
wire _T_3177; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77108.12]
wire _T_3178; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77113.14]
wire _T_3179; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77118.16]
wire _T_3180; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77123.18]
wire _GEN_268; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77124.18]
wire _GEN_269; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77119.16]
wire _GEN_270; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77114.14]
wire _GEN_271; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77109.12]
wire _GEN_272; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77104.10]
wire _GEN_273; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77099.8]
wire _GEN_274; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77094.6]
wire _GEN_275; // @[Conditional.scala 40:58:freechips.rocketchip.system.LowRiscConfig.fir@77089.4]
wire [63:0] _GEN_276; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77166.18]
wire [63:0] _GEN_277; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77161.16]
wire [63:0] _GEN_278; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77156.14]
wire [63:0] _GEN_279; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77151.12]
wire [63:0] _GEN_280; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77146.10]
wire [63:0] _GEN_281; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77141.8]
wire [63:0] _GEN_282; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77136.6]
wire [63:0] _GEN_283; // @[Conditional.scala 40:58:freechips.rocketchip.system.LowRiscConfig.fir@77131.4]
wire [10:0] _T_433_bits_extra; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74079.4 RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@77171.4]
wire _T_433_bits_read; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74079.4 RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@77084.4]
TLMonitor_31 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@73859.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source)
);
LevelGateway LevelGateway ( // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73906.4]
.clock(LevelGateway_clock),
.reset(LevelGateway_reset),
.io_interrupt(LevelGateway_io_interrupt),
.io_plic_valid(LevelGateway_io_plic_valid),
.io_plic_ready(LevelGateway_io_plic_ready),
.io_plic_complete(LevelGateway_io_plic_complete)
);
LevelGateway LevelGateway_1 ( // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73911.4]
.clock(LevelGateway_1_clock),
.reset(LevelGateway_1_reset),
.io_interrupt(LevelGateway_1_io_interrupt),
.io_plic_valid(LevelGateway_1_io_plic_valid),
.io_plic_ready(LevelGateway_1_io_plic_ready),
.io_plic_complete(LevelGateway_1_io_plic_complete)
);
LevelGateway LevelGateway_2 ( // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73916.4]
.clock(LevelGateway_2_clock),
.reset(LevelGateway_2_reset),
.io_interrupt(LevelGateway_2_io_interrupt),
.io_plic_valid(LevelGateway_2_io_plic_valid),
.io_plic_ready(LevelGateway_2_io_plic_ready),
.io_plic_complete(LevelGateway_2_io_plic_complete)
);
LevelGateway LevelGateway_3 ( // @[Plic.scala 169:27:freechips.rocketchip.system.LowRiscConfig.fir@73921.4]
.clock(LevelGateway_3_clock),
.reset(LevelGateway_3_reset),
.io_interrupt(LevelGateway_3_io_interrupt),
.io_plic_valid(LevelGateway_3_io_plic_valid),
.io_plic_ready(LevelGateway_3_io_plic_ready),
.io_plic_complete(LevelGateway_3_io_plic_complete)
);
PLICFanIn PLICFanIn ( // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73951.4]
.io_prio_0(PLICFanIn_io_prio_0),
.io_prio_1(PLICFanIn_io_prio_1),
.io_prio_2(PLICFanIn_io_prio_2),
.io_prio_3(PLICFanIn_io_prio_3),
.io_ip(PLICFanIn_io_ip),
.io_dev(PLICFanIn_io_dev),
.io_max(PLICFanIn_io_max)
);
PLICFanIn PLICFanIn_1 ( // @[Plic.scala 197:25:freechips.rocketchip.system.LowRiscConfig.fir@73963.4]
.io_prio_0(PLICFanIn_1_io_prio_0),
.io_prio_1(PLICFanIn_1_io_prio_1),
.io_prio_2(PLICFanIn_1_io_prio_2),
.io_prio_3(PLICFanIn_1_io_prio_3),
.io_ip(PLICFanIn_1_io_ip),
.io_dev(PLICFanIn_1_io_dev),
.io_max(PLICFanIn_1_io_max)
);
Queue_83 Queue ( // @[Decoupled.scala 293:21:freechips.rocketchip.system.LowRiscConfig.fir@74084.4]
.clock(Queue_clock),
.reset(Queue_reset),
.io_enq_ready(Queue_io_enq_ready),
.io_enq_valid(Queue_io_enq_valid),
.io_enq_bits_read(Queue_io_enq_bits_read),
.io_enq_bits_index(Queue_io_enq_bits_index),
.io_enq_bits_data(Queue_io_enq_bits_data),
.io_enq_bits_mask(Queue_io_enq_bits_mask),
.io_enq_bits_extra(Queue_io_enq_bits_extra),
.io_deq_ready(Queue_io_deq_ready),
.io_deq_valid(Queue_io_deq_valid),
.io_deq_bits_read(Queue_io_deq_bits_read),
.io_deq_bits_index(Queue_io_deq_bits_index),
.io_deq_bits_data(Queue_io_deq_bits_data),
.io_deq_bits_mask(Queue_io_deq_bits_mask),
.io_deq_bits_extra(Queue_io_deq_bits_extra)
);
assign enableVec0_0 = {enables_0_0,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73941.4]
assign enableVec0_1 = {enables_1_0,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73942.4]
assign pendingUInt = {pending_3,pending_2,pending_1,pending_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@73950.4]
assign _T_2246 = Queue_io_deq_valid & auto_in_d_ready; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@75999.4]
assign _T_2247 = _T_2246 & Queue_io_deq_bits_read; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76000.4]
assign _T_1187 = Queue_io_deq_bits_index[18]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74784.4]
assign _T_1179 = Queue_io_deq_bits_index[10]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74776.4]
assign _T_1178 = Queue_io_deq_bits_index[9]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74775.4]
assign _T_1173 = Queue_io_deq_bits_index[4]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74770.4]
assign _T_1170 = Queue_io_deq_bits_index[1]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74767.4]
assign _T_1169 = Queue_io_deq_bits_index[0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74766.4]
assign _T_1196 = {_T_1187,_T_1179,_T_1178,_T_1173,_T_1170,_T_1169}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74793.4]
assign _T_1262 = 64'h1 << _T_1196; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@74859.4]
assign _T_1303 = _T_1262[40]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74900.4]
assign _T_2490 = _T_2247 & _T_1303; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76299.4]
assign _T_445 = Queue_io_deq_bits_index & 23'h7bf9ec; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74096.4]
assign _T_459 = _T_445 == 23'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74110.4]
assign _T_2491 = _T_2490 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76300.4]
assign _T_600 = Queue_io_deq_bits_mask[7]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74159.4]
assign _T_616 = _T_600 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74175.4]
assign _T_599 = Queue_io_deq_bits_mask[6]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74158.4]
assign _T_614 = _T_599 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74173.4]
assign _T_598 = Queue_io_deq_bits_mask[5]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74157.4]
assign _T_612 = _T_598 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74171.4]
assign _T_597 = Queue_io_deq_bits_mask[4]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74156.4]
assign _T_610 = _T_597 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74169.4]
assign _T_596 = Queue_io_deq_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74155.4]
assign _T_608 = _T_596 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74167.4]
assign _T_595 = Queue_io_deq_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74154.4]
assign _T_606 = _T_595 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74165.4]
assign _T_594 = Queue_io_deq_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74153.4]
assign _T_604 = _T_594 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74163.4]
assign _T_593 = Queue_io_deq_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@74152.4]
assign _T_602 = _T_593 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@74161.4]
assign _T_623 = {_T_616,_T_614,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74182.4]
assign _T_1022 = _T_623[63:32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74602.4]
assign _T_1023 = _T_1022 != 32'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74603.4]
assign claimer_1 = _T_2491 & _T_1023; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74608.4]
assign _T_1295 = _T_1262[32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74892.4]
assign _T_2442 = _T_2247 & _T_1295; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76240.4]
assign _T_2443 = _T_2442 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76241.4]
assign claimer_0 = _T_2443 & _T_1023; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74706.4]
assign _T_350 = {claimer_1,claimer_0}; // @[Plic.scala 252:21:freechips.rocketchip.system.LowRiscConfig.fir@73977.4]
assign _T_352 = _T_350 - 2'h1; // @[Plic.scala 252:46:freechips.rocketchip.system.LowRiscConfig.fir@73979.4]
assign _T_353 = $unsigned(_T_352); // @[Plic.scala 252:46:freechips.rocketchip.system.LowRiscConfig.fir@73980.4]
assign _T_354 = _T_353[1:0]; // @[Plic.scala 252:46:freechips.rocketchip.system.LowRiscConfig.fir@73981.4]
assign _T_355 = _T_350 & _T_354; // @[Plic.scala 252:28:freechips.rocketchip.system.LowRiscConfig.fir@73982.4]
assign _T_356 = _T_355 == 2'h0; // @[Plic.scala 252:58:freechips.rocketchip.system.LowRiscConfig.fir@73983.4]
assign _T_358 = _T_356 | reset; // @[Plic.scala 252:11:freechips.rocketchip.system.LowRiscConfig.fir@73985.4]
assign _T_359 = _T_358 == 1'h0; // @[Plic.scala 252:11:freechips.rocketchip.system.LowRiscConfig.fir@73986.4]
assign _T_360 = claimer_0 ? maxDevs_0 : 3'h0; // @[Plic.scala 253:49:freechips.rocketchip.system.LowRiscConfig.fir@73991.4]
assign _T_361 = claimer_1 ? maxDevs_1 : 3'h0; // @[Plic.scala 253:49:freechips.rocketchip.system.LowRiscConfig.fir@73992.4]
assign claiming = _T_360 | _T_361; // @[Plic.scala 253:96:freechips.rocketchip.system.LowRiscConfig.fir@73993.4]
assign _T_363 = 8'h1 << claiming; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@73995.4]
assign _T_364 = _T_363[4:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@73996.4]
assign claimedDevs_1 = _T_364[1]; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@73998.4]
assign claimedDevs_2 = _T_364[2]; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@73999.4]
assign claimedDevs_3 = _T_364[3]; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@74000.4]
assign claimedDevs_4 = _T_364[4]; // @[Plic.scala 254:58:freechips.rocketchip.system.LowRiscConfig.fir@74001.4]
assign _T_381 = claimedDevs_1 | LevelGateway_io_plic_valid; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74011.4]
assign _T_382 = claimedDevs_1 == 1'h0; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74013.6]
assign _T_384 = claimedDevs_2 | LevelGateway_1_io_plic_valid; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74018.4]
assign _T_385 = claimedDevs_2 == 1'h0; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74020.6]
assign _T_387 = claimedDevs_3 | LevelGateway_2_io_plic_valid; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74025.4]
assign _T_388 = claimedDevs_3 == 1'h0; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74027.6]
assign _T_390 = claimedDevs_4 | LevelGateway_3_io_plic_valid; // @[Plic.scala 258:15:freechips.rocketchip.system.LowRiscConfig.fir@74032.4]
assign _T_391 = claimedDevs_4 == 1'h0; // @[Plic.scala 258:34:freechips.rocketchip.system.LowRiscConfig.fir@74034.6]
assign _T_2706 = Queue_io_deq_bits_read == 1'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76537.4]
assign _T_2707 = _T_2246 & _T_2706; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76538.4]
assign _T_2950 = _T_2707 & _T_1303; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76837.4]
assign _T_2951 = _T_2950 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76838.4]
assign _T_1025 = ~ _T_1022; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74605.4]
assign _T_1026 = _T_1025 == 32'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74606.4]
assign _T_1030 = _T_2951 & _T_1026; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74610.4]
assign _T_1119 = Queue_io_deq_bits_data[63:32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74710.4]
assign completerDev = _T_1119[2:0]; // @[package.scala 119:13:freechips.rocketchip.system.LowRiscConfig.fir@74720.4]
assign _T_1038 = enableVec0_1 >> completerDev; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74624.4]
assign _T_1039 = _T_1038[0]; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74625.4]
assign completer_1 = _T_1030 & _T_1039; // @[Plic.scala 302:35:freechips.rocketchip.system.LowRiscConfig.fir@74626.4]
assign _T_2902 = _T_2707 & _T_1295; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76778.4]
assign _T_2903 = _T_2902 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76779.4]
assign _T_1118 = _T_2903 & _T_1026; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74708.4]
assign _T_1126 = enableVec0_0 >> completerDev; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74722.4]
assign _T_1127 = _T_1126[0]; // @[Plic.scala 302:51:freechips.rocketchip.system.LowRiscConfig.fir@74723.4]
assign completer_0 = _T_1118 & _T_1127; // @[Plic.scala 302:35:freechips.rocketchip.system.LowRiscConfig.fir@74724.4]
assign _T_399 = {completer_1,completer_0}; // @[Plic.scala 269:23:freechips.rocketchip.system.LowRiscConfig.fir@74039.4]
assign _T_401 = _T_399 - 2'h1; // @[Plic.scala 269:50:freechips.rocketchip.system.LowRiscConfig.fir@74041.4]
assign _T_402 = $unsigned(_T_401); // @[Plic.scala 269:50:freechips.rocketchip.system.LowRiscConfig.fir@74042.4]
assign _T_403 = _T_402[1:0]; // @[Plic.scala 269:50:freechips.rocketchip.system.LowRiscConfig.fir@74043.4]
assign _T_404 = _T_399 & _T_403; // @[Plic.scala 269:30:freechips.rocketchip.system.LowRiscConfig.fir@74044.4]
assign _T_405 = _T_404 == 2'h0; // @[Plic.scala 269:62:freechips.rocketchip.system.LowRiscConfig.fir@74045.4]
assign _T_407 = _T_405 | reset; // @[Plic.scala 269:11:freechips.rocketchip.system.LowRiscConfig.fir@74047.4]
assign _T_408 = _T_407 == 1'h0; // @[Plic.scala 269:11:freechips.rocketchip.system.LowRiscConfig.fir@74048.4]
assign _T_410 = completer_0 | completer_1; // @[Plic.scala 271:48:freechips.rocketchip.system.LowRiscConfig.fir@74055.4]
assign _T_412 = 8'h1 << completerDev; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@74057.4]
assign _T_413 = _T_412[4:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@74058.4]
assign completedDevs = _T_410 ? _T_413 : 5'h0; // @[Plic.scala 271:28:freechips.rocketchip.system.LowRiscConfig.fir@74059.4]
assign _T_427 = auto_in_a_bits_address[27:3]; // @[Edges.scala 192:34:freechips.rocketchip.system.LowRiscConfig.fir@74073.4]
assign _T_1279 = _T_1262[16]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74876.4]
assign _T_2806 = _T_2707 & _T_1279; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76662.4]
assign _T_2807 = _T_2806 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76663.4]
assign _T_654 = _T_623[4:1]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74213.4]
assign _T_657 = ~ _T_654; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74216.4]
assign _T_658 = _T_657 == 4'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74217.4]
assign _T_662 = _T_2807 & _T_658; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74221.4]
assign _T_663 = Queue_io_deq_bits_data[4:1]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74222.4]
assign _T_681 = _T_623[34:32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74243.4]
assign _T_684 = ~ _T_681; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74246.4]
assign _T_685 = _T_684 == 3'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74247.4]
assign _T_1263 = _T_1262[0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74860.4]
assign _T_2710 = _T_2707 & _T_1263; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76541.4]
assign _T_2711 = _T_2710 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76542.4]
assign _T_689 = _T_2711 & _T_685; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74251.4]
assign _T_690 = Queue_io_deq_bits_data[34:32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74252.4]
assign _T_700 = {priority_0,32'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74265.4]
assign _T_1283 = _T_1262[20]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74880.4]
assign _T_2830 = _T_2707 & _T_1283; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76692.4]
assign _T_2831 = _T_2830 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76693.4]
assign _T_741 = _T_2831 & _T_658; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74306.4]
assign _T_760 = _T_623[2:0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74328.4]
assign _T_763 = ~ _T_760; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74331.4]
assign _T_764 = _T_763 == 3'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74332.4]
assign _T_1264 = _T_1262[1]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74861.4]
assign _T_2716 = _T_2707 & _T_1264; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76549.4]
assign _T_2717 = _T_2716 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76550.4]
assign _T_768 = _T_2717 & _T_764; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74336.4]
assign _T_769 = Queue_io_deq_bits_data[2:0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74337.4]
assign _T_793 = _T_2717 & _T_685; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74364.4]
assign _T_803 = {{29'd0}, priority_1}; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74377.4]
assign _T_804 = {priority_2,_T_803}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74378.4]
assign _T_937 = {pending_3,pending_2,pending_1,pending_0,1'h0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74511.4]
assign _T_1265 = _T_1262[2]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74862.4]
assign _T_2722 = _T_2707 & _T_1265; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76558.4]
assign _T_2723 = _T_2722 & _T_459; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@76559.4]
assign _T_953 = _T_2723 & _T_764; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74527.4]
assign _T_978 = _T_2951 & _T_764; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74555.4]
assign _T_1014 = {1'h0,threshold_1}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74594.4]
assign _T_1015 = {{28'd0}, _T_1014}; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74595.4]
assign _T_1033 = completerDev == completerDev; // @[Plic.scala 299:33:freechips.rocketchip.system.LowRiscConfig.fir@74614.4]
assign _T_1035 = _T_1033 | reset; // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74616.4]
assign _T_1036 = _T_1035 == 1'h0; // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74617.4]
assign _T_1050 = {maxDevs_1,_T_1015}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74637.4]
assign _T_1051 = {{29'd0}, _T_1050}; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74638.4]
assign _T_1066 = _T_2903 & _T_764; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74653.4]
assign _T_1102 = {1'h0,threshold_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74692.4]
assign _T_1103 = {{28'd0}, _T_1102}; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74693.4]
assign _T_1138 = {maxDevs_0,_T_1103}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@74735.4]
assign _T_1139 = {{29'd0}, _T_1138}; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74736.4]
assign _T_3173 = 6'h0 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77088.4]
assign _T_3174 = 6'h1 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77093.6]
assign _T_3175 = 6'h2 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77098.8]
assign _T_3176 = 6'h8 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77103.10]
assign _T_3177 = 6'h10 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77108.12]
assign _T_3178 = 6'h14 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77113.14]
assign _T_3179 = 6'h20 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77118.16]
assign _T_3180 = 6'h28 == _T_1196; // @[Conditional.scala 37:30:freechips.rocketchip.system.LowRiscConfig.fir@77123.18]
assign _GEN_268 = _T_3180 ? _T_459 : 1'h1; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77124.18]
assign _GEN_269 = _T_3179 ? _T_459 : _GEN_268; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77119.16]
assign _GEN_270 = _T_3178 ? _T_459 : _GEN_269; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77114.14]
assign _GEN_271 = _T_3177 ? _T_459 : _GEN_270; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77109.12]
assign _GEN_272 = _T_3176 ? _T_459 : _GEN_271; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77104.10]
assign _GEN_273 = _T_3175 ? _T_459 : _GEN_272; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77099.8]
assign _GEN_274 = _T_3174 ? _T_459 : _GEN_273; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77094.6]
assign _GEN_275 = _T_3173 ? _T_459 : _GEN_274; // @[Conditional.scala 40:58:freechips.rocketchip.system.LowRiscConfig.fir@77089.4]
assign _GEN_276 = _T_3180 ? _T_1051 : 64'h0; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77166.18]
assign _GEN_277 = _T_3179 ? _T_1139 : _GEN_276; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77161.16]
assign _GEN_278 = _T_3178 ? {{59'd0}, enableVec0_1} : _GEN_277; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77156.14]
assign _GEN_279 = _T_3177 ? {{59'd0}, enableVec0_0} : _GEN_278; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77151.12]
assign _GEN_280 = _T_3176 ? {{59'd0}, _T_937} : _GEN_279; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77146.10]
assign _GEN_281 = _T_3175 ? {{61'd0}, priority_3} : _GEN_280; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77141.8]
assign _GEN_282 = _T_3174 ? {{29'd0}, _T_804} : _GEN_281; // @[Conditional.scala 39:67:freechips.rocketchip.system.LowRiscConfig.fir@77136.6]
assign _GEN_283 = _T_3173 ? {{29'd0}, _T_700} : _GEN_282; // @[Conditional.scala 40:58:freechips.rocketchip.system.LowRiscConfig.fir@77131.4]
assign _T_433_bits_extra = Queue_io_deq_bits_extra; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74079.4 RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@77171.4]
assign _T_433_bits_read = Queue_io_deq_bits_read; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@74079.4 RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@77084.4]
assign auto_int_out_1_0 = _T_341 > threshold_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@73904.4]
assign auto_int_out_0_0 = _T_337 > threshold_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@73903.4]
assign auto_in_a_ready = Queue_io_enq_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@73902.4]
assign auto_in_d_valid = Queue_io_deq_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@73902.4]
assign auto_in_d_bits_opcode = {{2'd0}, _T_433_bits_read}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@73902.4]
assign auto_in_d_bits_size = _T_433_bits_extra[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@73902.4]
assign auto_in_d_bits_source = _T_433_bits_extra[10:2]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@73902.4]
assign auto_in_d_bits_data = _GEN_275 ? _GEN_283 : 64'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@73902.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73861.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73862.4]
assign TLMonitor_io_in_a_ready = Queue_io_enq_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_d_valid = Queue_io_deq_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_433_bits_read}; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_d_bits_size = _T_433_bits_extra[1:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign TLMonitor_io_in_d_bits_source = _T_433_bits_extra[10:2]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@73895.4]
assign LevelGateway_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73908.4]
assign LevelGateway_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73909.4]
assign LevelGateway_io_interrupt = auto_int_in_0; // @[Plic.scala 170:28:freechips.rocketchip.system.LowRiscConfig.fir@73910.4]
assign LevelGateway_io_plic_ready = pending_0 == 1'h0; // @[Plic.scala 257:15:freechips.rocketchip.system.LowRiscConfig.fir@74010.4]
assign LevelGateway_io_plic_complete = completedDevs[1]; // @[Plic.scala 273:19:freechips.rocketchip.system.LowRiscConfig.fir@74065.4]
assign LevelGateway_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73913.4]
assign LevelGateway_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73914.4]
assign LevelGateway_1_io_interrupt = auto_int_in_1; // @[Plic.scala 170:28:freechips.rocketchip.system.LowRiscConfig.fir@73915.4]
assign LevelGateway_1_io_plic_ready = pending_1 == 1'h0; // @[Plic.scala 257:15:freechips.rocketchip.system.LowRiscConfig.fir@74017.4]
assign LevelGateway_1_io_plic_complete = completedDevs[2]; // @[Plic.scala 273:19:freechips.rocketchip.system.LowRiscConfig.fir@74066.4]
assign LevelGateway_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73918.4]
assign LevelGateway_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73919.4]
assign LevelGateway_2_io_interrupt = auto_int_in_2; // @[Plic.scala 170:28:freechips.rocketchip.system.LowRiscConfig.fir@73920.4]
assign LevelGateway_2_io_plic_ready = pending_2 == 1'h0; // @[Plic.scala 257:15:freechips.rocketchip.system.LowRiscConfig.fir@74024.4]
assign LevelGateway_2_io_plic_complete = completedDevs[3]; // @[Plic.scala 273:19:freechips.rocketchip.system.LowRiscConfig.fir@74067.4]
assign LevelGateway_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73923.4]
assign LevelGateway_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@73924.4]
assign LevelGateway_3_io_interrupt = auto_int_in_3; // @[Plic.scala 170:28:freechips.rocketchip.system.LowRiscConfig.fir@73925.4]
assign LevelGateway_3_io_plic_ready = pending_3 == 1'h0; // @[Plic.scala 257:15:freechips.rocketchip.system.LowRiscConfig.fir@74031.4]
assign LevelGateway_3_io_plic_complete = completedDevs[4]; // @[Plic.scala 273:19:freechips.rocketchip.system.LowRiscConfig.fir@74068.4]
assign PLICFanIn_io_prio_0 = priority_0; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73955.4]
assign PLICFanIn_io_prio_1 = priority_1; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73955.4]
assign PLICFanIn_io_prio_2 = priority_2; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73955.4]
assign PLICFanIn_io_prio_3 = priority_3; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73955.4]
assign PLICFanIn_io_ip = enables_0_0 & pendingUInt; // @[Plic.scala 199:21:freechips.rocketchip.system.LowRiscConfig.fir@73957.4]
assign PLICFanIn_1_io_prio_0 = priority_0; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73967.4]
assign PLICFanIn_1_io_prio_1 = priority_1; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73967.4]
assign PLICFanIn_1_io_prio_2 = priority_2; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73967.4]
assign PLICFanIn_1_io_prio_3 = priority_3; // @[Plic.scala 198:21:freechips.rocketchip.system.LowRiscConfig.fir@73967.4]
assign PLICFanIn_1_io_ip = enables_1_0 & pendingUInt; // @[Plic.scala 199:21:freechips.rocketchip.system.LowRiscConfig.fir@73969.4]
assign Queue_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@74085.4]
assign Queue_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@74086.4]
assign Queue_io_enq_valid = auto_in_a_valid; // @[Decoupled.scala 294:22:freechips.rocketchip.system.LowRiscConfig.fir@74087.4]
assign Queue_io_enq_bits_read = auto_in_a_bits_opcode == 3'h4; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@74092.4]
assign Queue_io_enq_bits_index = _T_427[22:0]; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@74091.4]
assign Queue_io_enq_bits_data = auto_in_a_bits_data; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@74090.4]
assign Queue_io_enq_bits_mask = auto_in_a_bits_mask; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@74089.4]
assign Queue_io_enq_bits_extra = {auto_in_a_bits_source,auto_in_a_bits_size}; // @[Decoupled.scala 295:21:freechips.rocketchip.system.LowRiscConfig.fir@74088.4]
assign Queue_io_deq_ready = auto_in_d_ready; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@77081.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
priority_0 = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
priority_1 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
priority_2 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
priority_3 = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
threshold_0 = _RAND_4[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
threshold_1 = _RAND_5[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
pending_0 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
pending_1 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
pending_2 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
pending_3 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
enables_0_0 = _RAND_10[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
enables_1_0 = _RAND_11[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
maxDevs_0 = _RAND_12[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
maxDevs_1 = _RAND_13[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_337 = _RAND_14[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_341 = _RAND_15[2:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (_T_689) begin
priority_0 <= _T_690;
end
if (_T_768) begin
priority_1 <= _T_769;
end
if (_T_793) begin
priority_2 <= _T_690;
end
if (_T_953) begin
priority_3 <= _T_769;
end
if (_T_1066) begin
threshold_0 <= _T_769;
end
if (_T_978) begin
threshold_1 <= _T_769;
end
if (reset) begin
pending_0 <= 1'h0;
end else begin
if (_T_381) begin
pending_0 <= _T_382;
end
end
if (reset) begin
pending_1 <= 1'h0;
end else begin
if (_T_384) begin
pending_1 <= _T_385;
end
end
if (reset) begin
pending_2 <= 1'h0;
end else begin
if (_T_387) begin
pending_2 <= _T_388;
end
end
if (reset) begin
pending_3 <= 1'h0;
end else begin
if (_T_390) begin
pending_3 <= _T_391;
end
end
if (_T_662) begin
enables_0_0 <= _T_663;
end
if (_T_741) begin
enables_1_0 <= _T_663;
end
maxDevs_0 <= PLICFanIn_io_dev;
maxDevs_1 <= PLICFanIn_1_io_dev;
_T_337 <= PLICFanIn_io_max;
_T_341 <= PLICFanIn_1_io_max;
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_359) begin
$fwrite(32'h80000002,"Assertion failed\n at Plic.scala:252 assert((claimer.asUInt & (claimer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"); // @[Plic.scala 252:11:freechips.rocketchip.system.LowRiscConfig.fir@73988.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_359) begin
$fatal; // @[Plic.scala 252:11:freechips.rocketchip.system.LowRiscConfig.fir@73989.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_408) begin
$fwrite(32'h80000002,"Assertion failed\n at Plic.scala:269 assert((completer.asUInt & (completer.asUInt - UInt(1))) === UInt(0)) // One-Hot\n"); // @[Plic.scala 269:11:freechips.rocketchip.system.LowRiscConfig.fir@74050.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_408) begin
$fatal; // @[Plic.scala 269:11:freechips.rocketchip.system.LowRiscConfig.fir@74051.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1036) begin
$fwrite(32'h80000002,"Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:299 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n"); // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74619.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1036) begin
$fatal; // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74620.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1036) begin
$fwrite(32'h80000002,"Assertion failed: completerDev should be consistent for all harts\n at Plic.scala:299 assert(completerDev === data.extract(log2Ceil(nDevices+1)-1, 0),\n"); // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74717.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1036) begin
$fatal; // @[Plic.scala 299:19:freechips.rocketchip.system.LowRiscConfig.fir@74718.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_32( // @[:freechips.rocketchip.system.LowRiscConfig.fir@77235.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77236.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77237.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [2:0] io_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [1:0] io_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [8:0] io_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [25:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [7:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input io_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
input [8:0] io_in_d_bits_source // @[:freechips.rocketchip.system.LowRiscConfig.fir@77238.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@78396.4]
wire _T_26; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@77259.6]
wire [5:0] _T_36; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@77265.6]
wire [2:0] _T_37; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@77266.6]
wire [2:0] _T_38; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@77267.6]
wire [25:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@77268.6]
wire [25:0] _T_39; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@77268.6]
wire _T_40; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@77269.6]
wire [2:0] _T_41; // @[Misc.scala 200:34:freechips.rocketchip.system.LowRiscConfig.fir@77270.6]
wire [1:0] _T_42; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@77271.6]
wire [3:0] _T_43; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@77272.6]
wire [2:0] _T_44; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@77273.6]
wire [2:0] _T_45; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@77274.6]
wire _T_46; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@77275.6]
wire _T_47; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@77276.6]
wire _T_48; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77277.6]
wire _T_49; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@77278.6]
wire _T_51; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77280.6]
wire _T_52; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77281.6]
wire _T_54; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77283.6]
wire _T_55; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77284.6]
wire _T_56; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@77285.6]
wire _T_57; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77286.6]
wire _T_58; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@77287.6]
wire _T_59; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77288.6]
wire _T_60; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77289.6]
wire _T_61; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77290.6]
wire _T_62; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77291.6]
wire _T_63; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77292.6]
wire _T_64; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77293.6]
wire _T_65; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77294.6]
wire _T_66; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77295.6]
wire _T_67; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77296.6]
wire _T_68; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77297.6]
wire _T_69; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77298.6]
wire _T_70; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77299.6]
wire _T_71; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@77300.6]
wire _T_72; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77301.6]
wire _T_73; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@77302.6]
wire _T_74; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77303.6]
wire _T_75; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77304.6]
wire _T_76; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77305.6]
wire _T_77; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77306.6]
wire _T_78; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77307.6]
wire _T_79; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77308.6]
wire _T_80; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77309.6]
wire _T_81; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77310.6]
wire _T_82; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77311.6]
wire _T_83; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77312.6]
wire _T_84; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77313.6]
wire _T_85; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77314.6]
wire _T_86; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77315.6]
wire _T_87; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77316.6]
wire _T_88; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77317.6]
wire _T_89; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77318.6]
wire _T_90; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77319.6]
wire _T_91; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77320.6]
wire _T_92; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77321.6]
wire _T_93; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77322.6]
wire _T_94; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77323.6]
wire _T_95; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77324.6]
wire _T_96; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77325.6]
wire _T_97; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77326.6]
wire [7:0] _T_104; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@77333.6]
wire _T_123; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@77356.6]
wire [25:0] _T_125; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@77359.8]
wire [26:0] _T_126; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@77360.8]
wire [26:0] _T_127; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@77361.8]
wire [26:0] _T_128; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@77362.8]
wire _T_129; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@77363.8]
wire _T_134; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@77368.8]
wire _T_139; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@77381.8]
wire _T_140; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@77382.8]
wire _T_143; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@77389.8]
wire _T_144; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@77390.8]
wire _T_146; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@77396.8]
wire _T_147; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@77397.8]
wire _T_148; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@77402.8]
wire _T_150; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@77404.8]
wire _T_151; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@77405.8]
wire [7:0] _T_152; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@77410.8]
wire _T_153; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@77411.8]
wire _T_155; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@77413.8]
wire _T_156; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@77414.8]
wire _T_157; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@77419.8]
wire _T_159; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@77421.8]
wire _T_160; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@77422.8]
wire _T_161; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@77428.6]
wire _T_190; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@77482.8]
wire _T_192; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@77484.8]
wire _T_193; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@77485.8]
wire _T_203; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@77508.6]
wire _T_216; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77522.8]
wire _T_217; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77523.8]
wire _T_224; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@77542.8]
wire _T_226; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@77544.8]
wire _T_227; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@77545.8]
wire _T_228; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@77550.8]
wire _T_230; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@77552.8]
wire _T_231; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@77553.8]
wire _T_236; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@77567.6]
wire _T_265; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@77618.6]
wire [7:0] _T_290; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@77660.8]
wire [7:0] _T_291; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@77661.8]
wire _T_292; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@77662.8]
wire _T_294; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@77664.8]
wire _T_295; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@77665.8]
wire _T_296; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@77671.6]
wire _T_314; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@77702.8]
wire _T_316; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@77704.8]
wire _T_317; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@77705.8]
wire _T_322; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@77719.6]
wire _T_340; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@77750.8]
wire _T_342; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@77752.8]
wire _T_343; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@77753.8]
wire _T_348; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@77767.6]
wire _T_374; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@77817.6]
wire _T_376; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@77819.6]
wire _T_377; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@77820.6]
wire _T_384; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@77831.6]
wire _T_394; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@77837.6]
wire _T_396; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77840.8]
wire _T_397; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77841.8]
wire _T_398; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@77846.8]
wire _T_400; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@77848.8]
wire _T_401; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@77849.8]
wire _T_414; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@77879.6]
wire _T_442; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@77937.6]
wire _T_471; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@77996.6]
wire _T_488; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@78031.6]
wire _T_506; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@78067.6]
wire _T_535; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@78127.4]
reg _T_545; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@78136.4]
reg [31:0] _RAND_0;
wire [1:0] _T_546; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78137.4]
wire [1:0] _T_547; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78138.4]
wire _T_548; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78139.4]
wire _T_549; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78140.4]
reg [2:0] _T_558; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@78151.4]
reg [31:0] _RAND_1;
reg [2:0] _T_560; // @[Monitor.scala 350:22:freechips.rocketchip.system.LowRiscConfig.fir@78152.4]
reg [31:0] _RAND_2;
reg [1:0] _T_562; // @[Monitor.scala 351:22:freechips.rocketchip.system.LowRiscConfig.fir@78153.4]
reg [31:0] _RAND_3;
reg [8:0] _T_564; // @[Monitor.scala 352:22:freechips.rocketchip.system.LowRiscConfig.fir@78154.4]
reg [31:0] _RAND_4;
reg [25:0] _T_566; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@78155.4]
reg [31:0] _RAND_5;
wire _T_567; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@78156.4]
wire _T_568; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@78157.4]
wire _T_569; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@78159.6]
wire _T_571; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@78161.6]
wire _T_572; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@78162.6]
wire _T_573; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@78167.6]
wire _T_575; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@78169.6]
wire _T_576; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@78170.6]
wire _T_577; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@78175.6]
wire _T_579; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@78177.6]
wire _T_580; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@78178.6]
wire _T_581; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@78183.6]
wire _T_583; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@78185.6]
wire _T_584; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@78186.6]
wire _T_585; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@78191.6]
wire _T_587; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@78193.6]
wire _T_588; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@78194.6]
wire _T_590; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@78201.4]
wire _T_591; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@78209.4]
reg _T_600; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@78217.4]
reg [31:0] _RAND_6;
wire [1:0] _T_601; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78218.4]
wire [1:0] _T_602; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78219.4]
wire _T_603; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78220.4]
wire _T_604; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78221.4]
reg [2:0] _T_613; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@78232.4]
reg [31:0] _RAND_7;
reg [1:0] _T_617; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@78234.4]
reg [31:0] _RAND_8;
reg [8:0] _T_619; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@78235.4]
reg [31:0] _RAND_9;
wire _T_624; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@78238.4]
wire _T_625; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@78239.4]
wire _T_626; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@78241.6]
wire _T_628; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@78243.6]
wire _T_629; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@78244.6]
wire _T_634; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@78257.6]
wire _T_636; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@78259.6]
wire _T_637; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@78260.6]
wire _T_638; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@78265.6]
wire _T_640; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@78267.6]
wire _T_641; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@78268.6]
wire _T_651; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@78291.4]
reg [399:0] _T_653; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@78300.4]
reg [415:0] _RAND_10;
reg _T_664; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@78310.4]
reg [31:0] _RAND_11;
wire [1:0] _T_665; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78311.4]
wire [1:0] _T_666; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78312.4]
wire _T_667; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78313.4]
wire _T_668; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78314.4]
reg _T_685; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@78333.4]
reg [31:0] _RAND_12;
wire [1:0] _T_686; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78334.4]
wire [1:0] _T_687; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78335.4]
wire _T_688; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78336.4]
wire _T_689; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78337.4]
wire _T_700; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@78352.4]
wire [511:0] _T_702; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@78355.6]
wire [399:0] _T_703; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@78357.6]
wire _T_704; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@78358.6]
wire _T_705; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@78359.6]
wire _T_707; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@78361.6]
wire _T_708; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@78362.6]
wire [511:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@78354.4]
wire _T_713; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@78373.4]
wire _T_715; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@78375.4]
wire _T_716; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@78376.4]
wire [511:0] _T_717; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@78378.6]
wire [399:0] _T_698; // @[:freechips.rocketchip.system.LowRiscConfig.fir@78348.4 :freechips.rocketchip.system.LowRiscConfig.fir@78350.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@78356.6]
wire [399:0] _T_718; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@78380.6]
wire [399:0] _T_719; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@78381.6]
wire _T_720; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@78382.6]
wire _T_722; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@78384.6]
wire _T_723; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@78385.6]
wire [511:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@78377.4]
wire [399:0] _T_724; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@78391.4]
wire [399:0] _T_710; // @[:freechips.rocketchip.system.LowRiscConfig.fir@78368.4 :freechips.rocketchip.system.LowRiscConfig.fir@78370.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@78379.6]
wire [399:0] _T_725; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@78392.4]
wire [399:0] _T_726; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@78393.4]
reg [31:0] _T_728; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@78395.4]
reg [31:0] _RAND_13;
wire _T_729; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@78398.4]
wire _T_730; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@78399.4]
wire _T_731; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@78400.4]
wire _T_732; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@78401.4]
wire _T_733; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@78402.4]
wire _T_734; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@78403.4]
wire _T_736; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@78405.4]
wire _T_737; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@78406.4]
wire [31:0] _T_739; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@78412.4]
wire _T_742; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@78416.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@77370.10]
wire _GEN_35; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@77442.10]
wire _GEN_53; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77525.10]
wire _GEN_65; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@77584.10]
wire _GEN_75; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@77635.10]
wire _GEN_85; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@77685.10]
wire _GEN_95; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@77733.10]
wire _GEN_105; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@77781.10]
wire _GEN_115; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77843.10]
wire _GEN_119; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@77885.10]
wire _GEN_125; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@77943.10]
wire _GEN_131; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@78002.10]
wire _GEN_133; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@78037.10]
wire _GEN_135; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@78073.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@78396.4]
.out(plusarg_reader_out)
);
assign _T_26 = io_in_a_bits_source <= 9'h18f; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@77259.6]
assign _T_36 = 6'h7 << io_in_a_bits_size; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@77265.6]
assign _T_37 = _T_36[2:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@77266.6]
assign _T_38 = ~ _T_37; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@77267.6]
assign _GEN_18 = {{23'd0}, _T_38}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@77268.6]
assign _T_39 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@77268.6]
assign _T_40 = _T_39 == 26'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@77269.6]
assign _T_41 = {{1'd0}, io_in_a_bits_size}; // @[Misc.scala 200:34:freechips.rocketchip.system.LowRiscConfig.fir@77270.6]
assign _T_42 = _T_41[1:0]; // @[OneHot.scala 51:49:freechips.rocketchip.system.LowRiscConfig.fir@77271.6]
assign _T_43 = 4'h1 << _T_42; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@77272.6]
assign _T_44 = _T_43[2:0]; // @[OneHot.scala 52:27:freechips.rocketchip.system.LowRiscConfig.fir@77273.6]
assign _T_45 = _T_44 | 3'h1; // @[Misc.scala 200:81:freechips.rocketchip.system.LowRiscConfig.fir@77274.6]
assign _T_46 = io_in_a_bits_size >= 2'h3; // @[Misc.scala 204:21:freechips.rocketchip.system.LowRiscConfig.fir@77275.6]
assign _T_47 = _T_45[2]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@77276.6]
assign _T_48 = io_in_a_bits_address[2]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77277.6]
assign _T_49 = _T_48 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@77278.6]
assign _T_51 = _T_47 & _T_49; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77280.6]
assign _T_52 = _T_46 | _T_51; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77281.6]
assign _T_54 = _T_47 & _T_48; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77283.6]
assign _T_55 = _T_46 | _T_54; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77284.6]
assign _T_56 = _T_45[1]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@77285.6]
assign _T_57 = io_in_a_bits_address[1]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77286.6]
assign _T_58 = _T_57 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@77287.6]
assign _T_59 = _T_49 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77288.6]
assign _T_60 = _T_56 & _T_59; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77289.6]
assign _T_61 = _T_52 | _T_60; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77290.6]
assign _T_62 = _T_49 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77291.6]
assign _T_63 = _T_56 & _T_62; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77292.6]
assign _T_64 = _T_52 | _T_63; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77293.6]
assign _T_65 = _T_48 & _T_58; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77294.6]
assign _T_66 = _T_56 & _T_65; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77295.6]
assign _T_67 = _T_55 | _T_66; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77296.6]
assign _T_68 = _T_48 & _T_57; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77297.6]
assign _T_69 = _T_56 & _T_68; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77298.6]
assign _T_70 = _T_55 | _T_69; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77299.6]
assign _T_71 = _T_45[0]; // @[Misc.scala 207:26:freechips.rocketchip.system.LowRiscConfig.fir@77300.6]
assign _T_72 = io_in_a_bits_address[0]; // @[Misc.scala 208:26:freechips.rocketchip.system.LowRiscConfig.fir@77301.6]
assign _T_73 = _T_72 == 1'h0; // @[Misc.scala 209:20:freechips.rocketchip.system.LowRiscConfig.fir@77302.6]
assign _T_74 = _T_59 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77303.6]
assign _T_75 = _T_71 & _T_74; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77304.6]
assign _T_76 = _T_61 | _T_75; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77305.6]
assign _T_77 = _T_59 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77306.6]
assign _T_78 = _T_71 & _T_77; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77307.6]
assign _T_79 = _T_61 | _T_78; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77308.6]
assign _T_80 = _T_62 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77309.6]
assign _T_81 = _T_71 & _T_80; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77310.6]
assign _T_82 = _T_64 | _T_81; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77311.6]
assign _T_83 = _T_62 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77312.6]
assign _T_84 = _T_71 & _T_83; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77313.6]
assign _T_85 = _T_64 | _T_84; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77314.6]
assign _T_86 = _T_65 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77315.6]
assign _T_87 = _T_71 & _T_86; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77316.6]
assign _T_88 = _T_67 | _T_87; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77317.6]
assign _T_89 = _T_65 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77318.6]
assign _T_90 = _T_71 & _T_89; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77319.6]
assign _T_91 = _T_67 | _T_90; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77320.6]
assign _T_92 = _T_68 & _T_73; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77321.6]
assign _T_93 = _T_71 & _T_92; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77322.6]
assign _T_94 = _T_70 | _T_93; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77323.6]
assign _T_95 = _T_68 & _T_72; // @[Misc.scala 212:27:freechips.rocketchip.system.LowRiscConfig.fir@77324.6]
assign _T_96 = _T_71 & _T_95; // @[Misc.scala 213:38:freechips.rocketchip.system.LowRiscConfig.fir@77325.6]
assign _T_97 = _T_70 | _T_96; // @[Misc.scala 213:29:freechips.rocketchip.system.LowRiscConfig.fir@77326.6]
assign _T_104 = {_T_97,_T_94,_T_91,_T_88,_T_85,_T_82,_T_79,_T_76}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@77333.6]
assign _T_123 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@77356.6]
assign _T_125 = io_in_a_bits_address ^ 26'h2000000; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@77359.8]
assign _T_126 = {1'b0,$signed(_T_125)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@77360.8]
assign _T_127 = $signed(_T_126) & $signed(-27'sh10000); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@77361.8]
assign _T_128 = $signed(_T_127); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@77362.8]
assign _T_129 = $signed(_T_128) == $signed(27'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@77363.8]
assign _T_134 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@77368.8]
assign _T_139 = _T_26 | reset; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@77381.8]
assign _T_140 = _T_139 == 1'h0; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@77382.8]
assign _T_143 = _T_46 | reset; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@77389.8]
assign _T_144 = _T_143 == 1'h0; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@77390.8]
assign _T_146 = _T_40 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@77396.8]
assign _T_147 = _T_146 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@77397.8]
assign _T_148 = io_in_a_bits_param <= 3'h2; // @[Bundles.scala 109:27:freechips.rocketchip.system.LowRiscConfig.fir@77402.8]
assign _T_150 = _T_148 | reset; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@77404.8]
assign _T_151 = _T_150 == 1'h0; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@77405.8]
assign _T_152 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@77410.8]
assign _T_153 = _T_152 == 8'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@77411.8]
assign _T_155 = _T_153 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@77413.8]
assign _T_156 = _T_155 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@77414.8]
assign _T_157 = io_in_a_bits_corrupt == 1'h0; // @[Monitor.scala 56:15:freechips.rocketchip.system.LowRiscConfig.fir@77419.8]
assign _T_159 = _T_157 | reset; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@77421.8]
assign _T_160 = _T_159 == 1'h0; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@77422.8]
assign _T_161 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@77428.6]
assign _T_190 = io_in_a_bits_param != 3'h0; // @[Monitor.scala 66:28:freechips.rocketchip.system.LowRiscConfig.fir@77482.8]
assign _T_192 = _T_190 | reset; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@77484.8]
assign _T_193 = _T_192 == 1'h0; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@77485.8]
assign _T_203 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@77508.6]
assign _T_216 = _T_129 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77522.8]
assign _T_217 = _T_216 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77523.8]
assign _T_224 = io_in_a_bits_param == 3'h0; // @[Monitor.scala 75:28:freechips.rocketchip.system.LowRiscConfig.fir@77542.8]
assign _T_226 = _T_224 | reset; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@77544.8]
assign _T_227 = _T_226 == 1'h0; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@77545.8]
assign _T_228 = io_in_a_bits_mask == _T_104; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@77550.8]
assign _T_230 = _T_228 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@77552.8]
assign _T_231 = _T_230 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@77553.8]
assign _T_236 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@77567.6]
assign _T_265 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@77618.6]
assign _T_290 = ~ _T_104; // @[Monitor.scala 93:30:freechips.rocketchip.system.LowRiscConfig.fir@77660.8]
assign _T_291 = io_in_a_bits_mask & _T_290; // @[Monitor.scala 93:28:freechips.rocketchip.system.LowRiscConfig.fir@77661.8]
assign _T_292 = _T_291 == 8'h0; // @[Monitor.scala 93:37:freechips.rocketchip.system.LowRiscConfig.fir@77662.8]
assign _T_294 = _T_292 | reset; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@77664.8]
assign _T_295 = _T_294 == 1'h0; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@77665.8]
assign _T_296 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@77671.6]
assign _T_314 = io_in_a_bits_param <= 3'h4; // @[Bundles.scala 139:33:freechips.rocketchip.system.LowRiscConfig.fir@77702.8]
assign _T_316 = _T_314 | reset; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@77704.8]
assign _T_317 = _T_316 == 1'h0; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@77705.8]
assign _T_322 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@77719.6]
assign _T_340 = io_in_a_bits_param <= 3'h3; // @[Bundles.scala 146:30:freechips.rocketchip.system.LowRiscConfig.fir@77750.8]
assign _T_342 = _T_340 | reset; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@77752.8]
assign _T_343 = _T_342 == 1'h0; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@77753.8]
assign _T_348 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@77767.6]
assign _T_374 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@77817.6]
assign _T_376 = _T_374 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@77819.6]
assign _T_377 = _T_376 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@77820.6]
assign _T_384 = io_in_d_bits_source <= 9'h18f; // @[Parameters.scala 55:20:freechips.rocketchip.system.LowRiscConfig.fir@77831.6]
assign _T_394 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@77837.6]
assign _T_396 = _T_384 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77840.8]
assign _T_397 = _T_396 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77841.8]
assign _T_398 = io_in_d_bits_size >= 2'h3; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@77846.8]
assign _T_400 = _T_398 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@77848.8]
assign _T_401 = _T_400 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@77849.8]
assign _T_414 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@77879.6]
assign _T_442 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@77937.6]
assign _T_471 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@77996.6]
assign _T_488 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@78031.6]
assign _T_506 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@78067.6]
assign _T_535 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@78127.4]
assign _T_546 = _T_545 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78137.4]
assign _T_547 = $unsigned(_T_546); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78138.4]
assign _T_548 = _T_547[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78139.4]
assign _T_549 = _T_545 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78140.4]
assign _T_567 = _T_549 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@78156.4]
assign _T_568 = io_in_a_valid & _T_567; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@78157.4]
assign _T_569 = io_in_a_bits_opcode == _T_558; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@78159.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@78161.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@78162.6]
assign _T_573 = io_in_a_bits_param == _T_560; // @[Monitor.scala 356:29:freechips.rocketchip.system.LowRiscConfig.fir@78167.6]
assign _T_575 = _T_573 | reset; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@78169.6]
assign _T_576 = _T_575 == 1'h0; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@78170.6]
assign _T_577 = io_in_a_bits_size == _T_562; // @[Monitor.scala 357:29:freechips.rocketchip.system.LowRiscConfig.fir@78175.6]
assign _T_579 = _T_577 | reset; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@78177.6]
assign _T_580 = _T_579 == 1'h0; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@78178.6]
assign _T_581 = io_in_a_bits_source == _T_564; // @[Monitor.scala 358:29:freechips.rocketchip.system.LowRiscConfig.fir@78183.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@78185.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@78186.6]
assign _T_585 = io_in_a_bits_address == _T_566; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@78191.6]
assign _T_587 = _T_585 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@78193.6]
assign _T_588 = _T_587 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@78194.6]
assign _T_590 = _T_535 & _T_549; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@78201.4]
assign _T_591 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@78209.4]
assign _T_601 = _T_600 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78218.4]
assign _T_602 = $unsigned(_T_601); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78219.4]
assign _T_603 = _T_602[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78220.4]
assign _T_604 = _T_600 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78221.4]
assign _T_624 = _T_604 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@78238.4]
assign _T_625 = io_in_d_valid & _T_624; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@78239.4]
assign _T_626 = io_in_d_bits_opcode == _T_613; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@78241.6]
assign _T_628 = _T_626 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@78243.6]
assign _T_629 = _T_628 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@78244.6]
assign _T_634 = io_in_d_bits_size == _T_617; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@78257.6]
assign _T_636 = _T_634 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@78259.6]
assign _T_637 = _T_636 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@78260.6]
assign _T_638 = io_in_d_bits_source == _T_619; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@78265.6]
assign _T_640 = _T_638 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@78267.6]
assign _T_641 = _T_640 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@78268.6]
assign _T_651 = _T_591 & _T_604; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@78291.4]
assign _T_665 = _T_664 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78311.4]
assign _T_666 = $unsigned(_T_665); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78312.4]
assign _T_667 = _T_666[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78313.4]
assign _T_668 = _T_664 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78314.4]
assign _T_686 = _T_685 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78334.4]
assign _T_687 = $unsigned(_T_686); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78335.4]
assign _T_688 = _T_687[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@78336.4]
assign _T_689 = _T_685 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@78337.4]
assign _T_700 = _T_535 & _T_668; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@78352.4]
assign _T_702 = 512'h1 << io_in_a_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@78355.6]
assign _T_703 = _T_653 >> io_in_a_bits_source; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@78357.6]
assign _T_704 = _T_703[0]; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@78358.6]
assign _T_705 = _T_704 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@78359.6]
assign _T_707 = _T_705 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@78361.6]
assign _T_708 = _T_707 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@78362.6]
assign _GEN_15 = _T_700 ? _T_702 : 512'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@78354.4]
assign _T_713 = _T_591 & _T_689; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@78373.4]
assign _T_715 = _T_394 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@78375.4]
assign _T_716 = _T_713 & _T_715; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@78376.4]
assign _T_717 = 512'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@78378.6]
assign _T_698 = _GEN_15[399:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@78348.4 :freechips.rocketchip.system.LowRiscConfig.fir@78350.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@78356.6]
assign _T_718 = _T_698 | _T_653; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@78380.6]
assign _T_719 = _T_718 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@78381.6]
assign _T_720 = _T_719[0]; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@78382.6]
assign _T_722 = _T_720 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@78384.6]
assign _T_723 = _T_722 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@78385.6]
assign _GEN_16 = _T_716 ? _T_717 : 512'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@78377.4]
assign _T_724 = _T_653 | _T_698; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@78391.4]
assign _T_710 = _GEN_16[399:0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@78368.4 :freechips.rocketchip.system.LowRiscConfig.fir@78370.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@78379.6]
assign _T_725 = ~ _T_710; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@78392.4]
assign _T_726 = _T_724 & _T_725; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@78393.4]
assign _T_729 = _T_653 != 400'h0; // @[Monitor.scala 479:23:freechips.rocketchip.system.LowRiscConfig.fir@78398.4]
assign _T_730 = _T_729 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@78399.4]
assign _T_731 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@78400.4]
assign _T_732 = _T_730 | _T_731; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@78401.4]
assign _T_733 = _T_728 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@78402.4]
assign _T_734 = _T_732 | _T_733; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@78403.4]
assign _T_736 = _T_734 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@78405.4]
assign _T_737 = _T_736 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@78406.4]
assign _T_739 = _T_728 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@78412.4]
assign _T_742 = _T_535 | _T_591; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@78416.4]
assign _GEN_19 = io_in_a_valid & _T_123; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@77370.10]
assign _GEN_35 = io_in_a_valid & _T_161; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@77442.10]
assign _GEN_53 = io_in_a_valid & _T_203; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77525.10]
assign _GEN_65 = io_in_a_valid & _T_236; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@77584.10]
assign _GEN_75 = io_in_a_valid & _T_265; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@77635.10]
assign _GEN_85 = io_in_a_valid & _T_296; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@77685.10]
assign _GEN_95 = io_in_a_valid & _T_322; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@77733.10]
assign _GEN_105 = io_in_a_valid & _T_348; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@77781.10]
assign _GEN_115 = io_in_d_valid & _T_394; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77843.10]
assign _GEN_119 = io_in_d_valid & _T_414; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@77885.10]
assign _GEN_125 = io_in_d_valid & _T_442; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@77943.10]
assign _GEN_131 = io_in_d_valid & _T_471; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@78002.10]
assign _GEN_133 = io_in_d_valid & _T_488; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@78037.10]
assign _GEN_135 = io_in_d_valid & _T_506; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@78073.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_545 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_558 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_560 = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_562 = _RAND_3[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_564 = _RAND_4[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_566 = _RAND_5[25:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_600 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_613 = _RAND_7[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_617 = _RAND_8[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_619 = _RAND_9[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {13{`RANDOM}};
_T_653 = _RAND_10[399:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_664 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_685 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_728 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_545 <= 1'h0;
end else begin
if (_T_535) begin
if (_T_549) begin
_T_545 <= 1'h0;
end else begin
_T_545 <= _T_548;
end
end
end
if (_T_590) begin
_T_558 <= io_in_a_bits_opcode;
end
if (_T_590) begin
_T_560 <= io_in_a_bits_param;
end
if (_T_590) begin
_T_562 <= io_in_a_bits_size;
end
if (_T_590) begin
_T_564 <= io_in_a_bits_source;
end
if (_T_590) begin
_T_566 <= io_in_a_bits_address;
end
if (reset) begin
_T_600 <= 1'h0;
end else begin
if (_T_591) begin
if (_T_604) begin
_T_600 <= 1'h0;
end else begin
_T_600 <= _T_603;
end
end
end
if (_T_651) begin
_T_613 <= io_in_d_bits_opcode;
end
if (_T_651) begin
_T_617 <= io_in_d_bits_size;
end
if (_T_651) begin
_T_619 <= io_in_d_bits_source;
end
if (reset) begin
_T_653 <= 400'h0;
end else begin
_T_653 <= _T_726;
end
if (reset) begin
_T_664 <= 1'h0;
end else begin
if (_T_535) begin
if (_T_668) begin
_T_664 <= 1'h0;
end else begin
_T_664 <= _T_667;
end
end
end
if (reset) begin
_T_685 <= 1'h0;
end else begin
if (_T_591) begin
if (_T_689) begin
_T_685 <= 1'h0;
end else begin
_T_685 <= _T_688;
end
end
end
if (reset) begin
_T_728 <= 32'h0;
end else begin
if (_T_742) begin
_T_728 <= 32'h0;
end else begin
_T_728 <= _T_739;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at CLINT.scala:122:16)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@77250.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@77251.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@77353.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@77354.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@77370.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@77371.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at CLINT.scala:122:16)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@77377.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_134) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@77378.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@77384.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_140) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@77385.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at CLINT.scala:122:16)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@77392.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_144) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@77393.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@77399.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_147) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@77400.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at CLINT.scala:122:16)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@77407.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_151) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@77408.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@77416.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_156) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@77417.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@77424.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_160) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@77425.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@77442.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@77443.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at CLINT.scala:122:16)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@77449.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_134) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@77450.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@77456.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_140) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@77457.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_144) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at CLINT.scala:122:16)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@77464.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_144) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@77465.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@77471.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_147) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@77472.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_151) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at CLINT.scala:122:16)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@77479.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_151) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@77480.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_193) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at CLINT.scala:122:16)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@77487.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_193) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@77488.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_156) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@77496.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_156) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@77497.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_35 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@77504.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_35 & _T_160) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@77505.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77525.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_217) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@77526.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@77532.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_140) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@77533.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@77539.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_147) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@77540.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@77547.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_227) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@77548.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@77555.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_231) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@77556.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@77563.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_160) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@77564.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@77584.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_217) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@77585.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@77591.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_140) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@77592.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@77598.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_147) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@77599.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@77606.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_227) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@77607.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@77614.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_231) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@77615.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_217) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@77635.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_217) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@77636.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@77642.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_140) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@77643.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@77649.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_147) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@77650.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_227) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@77657.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_227) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@77658.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_75 & _T_295) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@77667.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_75 & _T_295) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@77668.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@77685.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_134) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@77686.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@77692.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_140) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@77693.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@77699.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_147) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@77700.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_317) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at CLINT.scala:122:16)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@77707.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_317) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@77708.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_85 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@77715.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_85 & _T_231) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@77716.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@77733.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_134) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@77734.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@77740.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_140) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@77741.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@77747.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_147) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@77748.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_343) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at CLINT.scala:122:16)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@77755.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_343) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@77756.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@77763.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_231) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@77764.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at CLINT.scala:122:16)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@77781.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_134) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@77782.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_140) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@77788.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_140) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@77789.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_147) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at CLINT.scala:122:16)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@77795.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_147) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@77796.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_231) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at CLINT.scala:122:16)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@77803.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_231) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@77804.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_105 & _T_160) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@77811.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_105 & _T_160) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@77812.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at CLINT.scala:122:16)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@77822.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_377) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@77823.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77843.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_397) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@77844.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at CLINT.scala:122:16)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@77851.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_401) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@77852.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@77859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@77860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@77867.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@77868.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at CLINT.scala:122:16)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@77875.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@77876.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@77885.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_397) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@77886.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at CLINT.scala:122:16)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@77892.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_134) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@77893.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_119 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at CLINT.scala:122:16)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@77900.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_119 & _T_401) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@77901.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at CLINT.scala:122:16)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@77908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@77909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at CLINT.scala:122:16)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@77916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@77917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@77924.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@77925.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at CLINT.scala:122:16)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@77933.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@77934.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@77943.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_397) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@77944.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_134) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at CLINT.scala:122:16)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@77950.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_134) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@77951.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_401) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at CLINT.scala:122:16)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@77958.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_401) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@77959.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at CLINT.scala:122:16)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@77966.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@77967.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at CLINT.scala:122:16)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@77974.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@77975.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@77983.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@77984.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at CLINT.scala:122:16)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@77992.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@77993.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_131 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@78002.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_131 & _T_397) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@78003.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@78010.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@78011.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@78018.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@78019.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at CLINT.scala:122:16)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@78027.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@78028.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_133 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@78037.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_133 & _T_397) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@78038.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@78045.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@78046.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@78054.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@78055.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at CLINT.scala:122:16)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@78063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@78064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_135 & _T_397) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@78073.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_135 & _T_397) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@78074.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at CLINT.scala:122:16)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@78081.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@78082.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at CLINT.scala:122:16)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@78089.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@78090.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at CLINT.scala:122:16)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@78098.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@78099.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at CLINT.scala:122:16)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@78108.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@78109.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at CLINT.scala:122:16)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@78116.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@78117.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at CLINT.scala:122:16)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@78124.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@78125.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@78164.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_572) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@78165.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_576) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@78172.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_576) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@78173.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_580) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@78180.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_580) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@78181.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@78188.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_584) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@78189.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_568 & _T_588) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@78196.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_568 & _T_588) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@78197.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_629) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@78246.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_629) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@78247.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@78254.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@78255.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_637) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@78262.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_637) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@78263.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_625 & _T_641) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@78270.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_625 & _T_641) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@78271.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@78278.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@78279.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at CLINT.scala:122:16)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@78286.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@78287.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_700 & _T_708) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at CLINT.scala:122:16)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@78364.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_700 & _T_708) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@78365.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_716 & _T_723) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at CLINT.scala:122:16)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@78387.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_716 & _T_723) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@78388.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_737) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at CLINT.scala:122:16)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@78408.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_737) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@78409.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module CLINT( // @[:freechips.rocketchip.system.LowRiscConfig.fir@78421.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78422.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78423.4]
output auto_int_out_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output auto_int_out_1, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [2:0] auto_in_a_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [1:0] auto_in_a_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [8:0] auto_in_a_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [25:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [7:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input [63:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input auto_in_a_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output [2:0] auto_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output [1:0] auto_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output [8:0] auto_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
output [63:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@78424.4]
input io_rtcTick // @[:freechips.rocketchip.system.LowRiscConfig.fir@78425.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [2:0] TLMonitor_io_in_a_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [1:0] TLMonitor_io_in_a_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [8:0] TLMonitor_io_in_a_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [25:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [7:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire TLMonitor_io_in_a_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
wire [8:0] TLMonitor_io_in_d_bits_source; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
reg [63:0] time_; // @[CLINT.scala 84:23:freechips.rocketchip.system.LowRiscConfig.fir@78474.4]
reg [63:0] _RAND_0;
wire [63:0] _T_183; // @[CLINT.scala 85:38:freechips.rocketchip.system.LowRiscConfig.fir@78477.6]
reg [63:0] timecmp_0; // @[CLINT.scala 88:41:freechips.rocketchip.system.LowRiscConfig.fir@78480.4]
reg [63:0] _RAND_1;
reg ipi_0; // @[CLINT.scala 89:41:freechips.rocketchip.system.LowRiscConfig.fir@78481.4]
reg [31:0] _RAND_2;
wire [7:0] _T_189; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78487.4]
wire [7:0] _T_190; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78488.4]
wire [7:0] _T_191; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78489.4]
wire [7:0] _T_192; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78490.4]
wire [7:0] _T_193; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78491.4]
wire [7:0] _T_194; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78492.4]
wire [7:0] _T_195; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78493.4]
wire [7:0] _T_196; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78494.4]
wire _T_493; // @[RegisterRouter.scala 58:36:freechips.rocketchip.system.LowRiscConfig.fir@78592.4]
wire [22:0] _T_494; // @[Edges.scala 192:34:freechips.rocketchip.system.LowRiscConfig.fir@78594.4]
wire [12:0] _T_490_bits_index; // @[RegisterRouter.scala 57:18:freechips.rocketchip.system.LowRiscConfig.fir@78590.4 RegisterRouter.scala 59:19:freechips.rocketchip.system.LowRiscConfig.fir@78595.4]
wire _T_1169; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79243.4]
wire _T_1168; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79242.4]
wire [1:0] _T_1170; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@79244.4]
wire [12:0] _T_511; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78606.4]
wire _T_515; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78610.4]
wire _T_513; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78608.4]
wire _T_1313; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79438.4]
wire _T_1314; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79439.4]
wire _T_1315; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79440.4]
wire [3:0] _T_1190; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@79264.4]
wire _T_1192; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79266.4]
wire _T_1324; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79452.4]
wire _T_1325; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79453.4]
wire _T_653; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78660.4]
wire [7:0] _T_669; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78676.4]
wire _T_652; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78659.4]
wire [7:0] _T_667; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78674.4]
wire _T_651; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78658.4]
wire [7:0] _T_665; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78672.4]
wire _T_650; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78657.4]
wire [7:0] _T_663; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78670.4]
wire _T_649; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78656.4]
wire [7:0] _T_661; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78668.4]
wire _T_648; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78655.4]
wire [7:0] _T_659; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78666.4]
wire _T_647; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78654.4]
wire [7:0] _T_657; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78664.4]
wire _T_646; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78653.4]
wire [7:0] _T_655; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78662.4]
wire [63:0] _T_676; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@78683.4]
wire [7:0] _T_684; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78691.4]
wire [7:0] _T_685; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78692.4]
wire _T_686; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78693.4]
wire _T_690; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78697.4]
wire [7:0] _T_709; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78720.4]
wire [7:0] _T_710; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78721.4]
wire _T_711; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78722.4]
wire _T_715; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78726.4]
wire _T_323; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78521.4]
wire [7:0] _T_736; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78751.4]
wire [7:0] _T_737; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78752.4]
wire _T_738; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78753.4]
wire _T_742; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78757.4]
wire _T_324; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78522.4]
wire [7:0] _T_763; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78782.4]
wire [7:0] _T_764; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78783.4]
wire _T_765; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78784.4]
wire _T_769; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78788.4]
wire _T_325; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78523.4]
wire [7:0] _T_790; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78813.4]
wire [7:0] _T_791; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78814.4]
wire _T_792; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78815.4]
wire _T_796; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78819.4]
wire _T_326; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78524.4]
wire [7:0] _T_817; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78844.4]
wire [7:0] _T_818; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78845.4]
wire _T_819; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78846.4]
wire _T_823; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78850.4]
wire _T_327; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78525.4]
wire [7:0] _T_844; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78875.4]
wire [7:0] _T_845; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78876.4]
wire _T_846; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78877.4]
wire _T_850; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78881.4]
wire _T_328; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78526.4]
wire [7:0] _T_871; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78906.4]
wire [7:0] _T_872; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78907.4]
wire _T_873; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78908.4]
wire _T_877; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78912.4]
wire _T_329; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78527.4]
wire [7:0] _T_716; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78727.4]
wire [7:0] _GEN_4; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78729.4]
wire [7:0] _T_691; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78698.4]
wire [7:0] _GEN_3; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78700.4]
wire [7:0] _T_770; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78789.4]
wire [7:0] _GEN_6; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78791.4]
wire [7:0] _T_743; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78758.4]
wire [7:0] _GEN_5; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78760.4]
wire [7:0] _T_824; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78851.4]
wire [7:0] _GEN_8; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78853.4]
wire [7:0] _T_797; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78820.4]
wire [7:0] _GEN_7; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78822.4]
wire [7:0] _T_878; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78913.4]
wire [7:0] _GEN_10; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78915.4]
wire [7:0] _T_851; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78882.4]
wire [7:0] _GEN_9; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78884.4]
wire [63:0] _T_336; // @[RegField.scala 213:52:freechips.rocketchip.system.LowRiscConfig.fir@78535.6]
wire [7:0] _T_338; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78539.4]
wire [7:0] _T_339; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78540.4]
wire [7:0] _T_340; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78541.4]
wire [7:0] _T_341; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78542.4]
wire [7:0] _T_342; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78543.4]
wire [7:0] _T_343; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78544.4]
wire [7:0] _T_344; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78545.4]
wire [7:0] _T_345; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78546.4]
wire _T_1193; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79267.4]
wire _T_1330; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79467.4]
wire _T_1331; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79468.4]
wire _T_904; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78943.4]
wire _T_929; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78972.4]
wire _T_472; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78573.4]
wire _T_956; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79003.4]
wire _T_473; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78574.4]
wire _T_983; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79034.4]
wire _T_474; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78575.4]
wire _T_1010; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79065.4]
wire _T_475; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78576.4]
wire _T_1037; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79096.4]
wire _T_476; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78577.4]
wire _T_1064; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79127.4]
wire _T_477; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78578.4]
wire _T_1091; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79158.4]
wire _T_478; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78579.4]
wire [7:0] _GEN_12; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78975.4]
wire [7:0] _GEN_11; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78946.4]
wire [7:0] _GEN_14; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79037.4]
wire [7:0] _GEN_13; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79006.4]
wire [7:0] _GEN_16; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79099.4]
wire [7:0] _GEN_15; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79068.4]
wire [7:0] _GEN_18; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79161.4]
wire [7:0] _GEN_17; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79130.4]
wire [63:0] _T_485; // @[RegField.scala 213:52:freechips.rocketchip.system.LowRiscConfig.fir@78587.6]
wire [10:0] _T_495; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@78598.4]
wire [63:0] _T_888; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@78927.4]
wire [63:0] _T_1102; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@79173.4]
wire _T_1105; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79176.4]
wire _T_1108; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79179.4]
wire _T_1109; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79180.4]
wire _T_1186; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79260.4]
wire _T_1239; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79330.4]
wire _T_1240; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79331.4]
wire _T_1117; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79188.4]
wire _T_1119; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79190.4]
wire [1:0] _T_1154; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@79228.4]
wire [31:0] _T_1155; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79229.4]
wire _GEN_37; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79513.4]
wire _GEN_38; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79513.4]
wire _GEN_39; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79513.4]
wire [63:0] _T_1376_0; // @[MuxLiteral.scala 48:48:freechips.rocketchip.system.LowRiscConfig.fir@79515.4 MuxLiteral.scala 48:48:freechips.rocketchip.system.LowRiscConfig.fir@79517.4]
wire [63:0] _GEN_41; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79521.4]
wire [63:0] _GEN_42; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79521.4]
wire [63:0] _GEN_43; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79521.4]
TLMonitor_32 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@78433.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_param(TLMonitor_io_in_a_bits_param),
.io_in_a_bits_size(TLMonitor_io_in_a_bits_size),
.io_in_a_bits_source(TLMonitor_io_in_a_bits_source),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_a_bits_corrupt(TLMonitor_io_in_a_bits_corrupt),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_source(TLMonitor_io_in_d_bits_source)
);
assign _T_183 = time_ + 64'h1; // @[CLINT.scala 85:38:freechips.rocketchip.system.LowRiscConfig.fir@78477.6]
assign _T_189 = timecmp_0[7:0]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78487.4]
assign _T_190 = timecmp_0[15:8]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78488.4]
assign _T_191 = timecmp_0[23:16]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78489.4]
assign _T_192 = timecmp_0[31:24]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78490.4]
assign _T_193 = timecmp_0[39:32]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78491.4]
assign _T_194 = timecmp_0[47:40]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78492.4]
assign _T_195 = timecmp_0[55:48]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78493.4]
assign _T_196 = timecmp_0[63:56]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78494.4]
assign _T_493 = auto_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 58:36:freechips.rocketchip.system.LowRiscConfig.fir@78592.4]
assign _T_494 = auto_in_a_bits_address[25:3]; // @[Edges.scala 192:34:freechips.rocketchip.system.LowRiscConfig.fir@78594.4]
assign _T_490_bits_index = _T_494[12:0]; // @[RegisterRouter.scala 57:18:freechips.rocketchip.system.LowRiscConfig.fir@78590.4 RegisterRouter.scala 59:19:freechips.rocketchip.system.LowRiscConfig.fir@78595.4]
assign _T_1169 = _T_490_bits_index[12]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79243.4]
assign _T_1168 = _T_490_bits_index[11]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79242.4]
assign _T_1170 = {_T_1169,_T_1168}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@79244.4]
assign _T_511 = _T_490_bits_index & 13'h7ff; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78606.4]
assign _T_515 = _T_511 == 13'h7ff; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78610.4]
assign _T_513 = _T_511 == 13'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78608.4]
assign _T_1313 = auto_in_a_valid & auto_in_d_ready; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79438.4]
assign _T_1314 = _T_493 == 1'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79439.4]
assign _T_1315 = _T_1313 & _T_1314; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79440.4]
assign _T_1190 = 4'h1 << _T_1170; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@79264.4]
assign _T_1192 = _T_1190[1]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79266.4]
assign _T_1324 = _T_1315 & _T_1192; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79452.4]
assign _T_1325 = _T_1324 & _T_513; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79453.4]
assign _T_653 = auto_in_a_bits_mask[7]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78660.4]
assign _T_669 = _T_653 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78676.4]
assign _T_652 = auto_in_a_bits_mask[6]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78659.4]
assign _T_667 = _T_652 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78674.4]
assign _T_651 = auto_in_a_bits_mask[5]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78658.4]
assign _T_665 = _T_651 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78672.4]
assign _T_650 = auto_in_a_bits_mask[4]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78657.4]
assign _T_663 = _T_650 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78670.4]
assign _T_649 = auto_in_a_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78656.4]
assign _T_661 = _T_649 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78668.4]
assign _T_648 = auto_in_a_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78655.4]
assign _T_659 = _T_648 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78666.4]
assign _T_647 = auto_in_a_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78654.4]
assign _T_657 = _T_647 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78664.4]
assign _T_646 = auto_in_a_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@78653.4]
assign _T_655 = _T_646 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@78662.4]
assign _T_676 = {_T_669,_T_667,_T_665,_T_663,_T_661,_T_659,_T_657,_T_655}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@78683.4]
assign _T_684 = _T_676[7:0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78691.4]
assign _T_685 = ~ _T_684; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78692.4]
assign _T_686 = _T_685 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78693.4]
assign _T_690 = _T_1325 & _T_686; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78697.4]
assign _T_709 = _T_676[15:8]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78720.4]
assign _T_710 = ~ _T_709; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78721.4]
assign _T_711 = _T_710 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78722.4]
assign _T_715 = _T_1325 & _T_711; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78726.4]
assign _T_323 = _T_690 | _T_715; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78521.4]
assign _T_736 = _T_676[23:16]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78751.4]
assign _T_737 = ~ _T_736; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78752.4]
assign _T_738 = _T_737 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78753.4]
assign _T_742 = _T_1325 & _T_738; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78757.4]
assign _T_324 = _T_323 | _T_742; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78522.4]
assign _T_763 = _T_676[31:24]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78782.4]
assign _T_764 = ~ _T_763; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78783.4]
assign _T_765 = _T_764 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78784.4]
assign _T_769 = _T_1325 & _T_765; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78788.4]
assign _T_325 = _T_324 | _T_769; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78523.4]
assign _T_790 = _T_676[39:32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78813.4]
assign _T_791 = ~ _T_790; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78814.4]
assign _T_792 = _T_791 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78815.4]
assign _T_796 = _T_1325 & _T_792; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78819.4]
assign _T_326 = _T_325 | _T_796; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78524.4]
assign _T_817 = _T_676[47:40]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78844.4]
assign _T_818 = ~ _T_817; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78845.4]
assign _T_819 = _T_818 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78846.4]
assign _T_823 = _T_1325 & _T_819; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78850.4]
assign _T_327 = _T_326 | _T_823; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78525.4]
assign _T_844 = _T_676[55:48]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78875.4]
assign _T_845 = ~ _T_844; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78876.4]
assign _T_846 = _T_845 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78877.4]
assign _T_850 = _T_1325 & _T_846; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78881.4]
assign _T_328 = _T_327 | _T_850; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78526.4]
assign _T_871 = _T_676[63:56]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78906.4]
assign _T_872 = ~ _T_871; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78907.4]
assign _T_873 = _T_872 == 8'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78908.4]
assign _T_877 = _T_1325 & _T_873; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78912.4]
assign _T_329 = _T_328 | _T_877; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78527.4]
assign _T_716 = auto_in_a_bits_data[15:8]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78727.4]
assign _GEN_4 = _T_715 ? _T_716 : _T_190; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78729.4]
assign _T_691 = auto_in_a_bits_data[7:0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78698.4]
assign _GEN_3 = _T_690 ? _T_691 : _T_189; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78700.4]
assign _T_770 = auto_in_a_bits_data[31:24]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78789.4]
assign _GEN_6 = _T_769 ? _T_770 : _T_192; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78791.4]
assign _T_743 = auto_in_a_bits_data[23:16]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78758.4]
assign _GEN_5 = _T_742 ? _T_743 : _T_191; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78760.4]
assign _T_824 = auto_in_a_bits_data[47:40]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78851.4]
assign _GEN_8 = _T_823 ? _T_824 : _T_194; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78853.4]
assign _T_797 = auto_in_a_bits_data[39:32]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78820.4]
assign _GEN_7 = _T_796 ? _T_797 : _T_193; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78822.4]
assign _T_878 = auto_in_a_bits_data[63:56]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78913.4]
assign _GEN_10 = _T_877 ? _T_878 : _T_196; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78915.4]
assign _T_851 = auto_in_a_bits_data[55:48]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78882.4]
assign _GEN_9 = _T_850 ? _T_851 : _T_195; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78884.4]
assign _T_336 = {_GEN_10,_GEN_9,_GEN_8,_GEN_7,_GEN_6,_GEN_5,_GEN_4,_GEN_3}; // @[RegField.scala 213:52:freechips.rocketchip.system.LowRiscConfig.fir@78535.6]
assign _T_338 = time_[7:0]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78539.4]
assign _T_339 = time_[15:8]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78540.4]
assign _T_340 = time_[23:16]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78541.4]
assign _T_341 = time_[31:24]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78542.4]
assign _T_342 = time_[39:32]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78543.4]
assign _T_343 = time_[47:40]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78544.4]
assign _T_344 = time_[55:48]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78545.4]
assign _T_345 = time_[63:56]; // @[RegField.scala 210:53:freechips.rocketchip.system.LowRiscConfig.fir@78546.4]
assign _T_1193 = _T_1190[2]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79267.4]
assign _T_1330 = _T_1315 & _T_1193; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79467.4]
assign _T_1331 = _T_1330 & _T_515; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79468.4]
assign _T_904 = _T_1331 & _T_686; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78943.4]
assign _T_929 = _T_1331 & _T_711; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@78972.4]
assign _T_472 = _T_904 | _T_929; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78573.4]
assign _T_956 = _T_1331 & _T_738; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79003.4]
assign _T_473 = _T_472 | _T_956; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78574.4]
assign _T_983 = _T_1331 & _T_765; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79034.4]
assign _T_474 = _T_473 | _T_983; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78575.4]
assign _T_1010 = _T_1331 & _T_792; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79065.4]
assign _T_475 = _T_474 | _T_1010; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78576.4]
assign _T_1037 = _T_1331 & _T_819; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79096.4]
assign _T_476 = _T_475 | _T_1037; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78577.4]
assign _T_1064 = _T_1331 & _T_846; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79127.4]
assign _T_477 = _T_476 | _T_1064; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78578.4]
assign _T_1091 = _T_1331 & _T_873; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79158.4]
assign _T_478 = _T_477 | _T_1091; // @[RegField.scala 213:27:freechips.rocketchip.system.LowRiscConfig.fir@78579.4]
assign _GEN_12 = _T_929 ? _T_716 : _T_339; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78975.4]
assign _GEN_11 = _T_904 ? _T_691 : _T_338; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@78946.4]
assign _GEN_14 = _T_983 ? _T_770 : _T_341; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79037.4]
assign _GEN_13 = _T_956 ? _T_743 : _T_340; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79006.4]
assign _GEN_16 = _T_1037 ? _T_824 : _T_343; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79099.4]
assign _GEN_15 = _T_1010 ? _T_797 : _T_342; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79068.4]
assign _GEN_18 = _T_1091 ? _T_878 : _T_345; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79161.4]
assign _GEN_17 = _T_1064 ? _T_851 : _T_344; // @[RegField.scala 217:20:freechips.rocketchip.system.LowRiscConfig.fir@79130.4]
assign _T_485 = {_GEN_18,_GEN_17,_GEN_16,_GEN_15,_GEN_14,_GEN_13,_GEN_12,_GEN_11}; // @[RegField.scala 213:52:freechips.rocketchip.system.LowRiscConfig.fir@78587.6]
assign _T_495 = {auto_in_a_bits_source,auto_in_a_bits_size}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@78598.4]
assign _T_888 = {_T_196,_T_195,_T_194,_T_193,_T_192,_T_191,_T_190,_T_189}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@78927.4]
assign _T_1102 = {_T_345,_T_344,_T_343,_T_342,_T_341,_T_340,_T_339,_T_338}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@79173.4]
assign _T_1105 = _T_676[0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79176.4]
assign _T_1108 = ~ _T_1105; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79179.4]
assign _T_1109 = _T_1108 == 1'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79180.4]
assign _T_1186 = _T_1190[0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79260.4]
assign _T_1239 = _T_1315 & _T_1186; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79330.4]
assign _T_1240 = _T_1239 & _T_513; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79331.4]
assign _T_1117 = _T_1240 & _T_1109; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79188.4]
assign _T_1119 = auto_in_a_bits_data[0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79190.4]
assign _T_1154 = {1'h0,ipi_0}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@79228.4]
assign _T_1155 = {{30'd0}, _T_1154}; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@79229.4]
assign _GEN_37 = 2'h1 == _T_1170 ? _T_513 : _T_513; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79513.4]
assign _GEN_38 = 2'h2 == _T_1170 ? _T_515 : _GEN_37; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79513.4]
assign _GEN_39 = 2'h3 == _T_1170 ? 1'h1 : _GEN_38; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79513.4]
assign _T_1376_0 = {{32'd0}, _T_1155}; // @[MuxLiteral.scala 48:48:freechips.rocketchip.system.LowRiscConfig.fir@79515.4 MuxLiteral.scala 48:48:freechips.rocketchip.system.LowRiscConfig.fir@79517.4]
assign _GEN_41 = 2'h1 == _T_1170 ? _T_888 : _T_1376_0; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79521.4]
assign _GEN_42 = 2'h2 == _T_1170 ? _T_1102 : _GEN_41; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79521.4]
assign _GEN_43 = 2'h3 == _T_1170 ? 64'h0 : _GEN_42; // @[MuxLiteral.scala 48:10:freechips.rocketchip.system.LowRiscConfig.fir@79521.4]
assign auto_int_out_0 = ipi_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@78473.4]
assign auto_int_out_1 = time_ >= timecmp_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@78473.4]
assign auto_in_a_ready = auto_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@78472.4]
assign auto_in_d_valid = auto_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@78472.4]
assign auto_in_d_bits_opcode = {{2'd0}, _T_493}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@78472.4]
assign auto_in_d_bits_size = _T_495[1:0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@78472.4]
assign auto_in_d_bits_source = _T_495[10:2]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@78472.4]
assign auto_in_d_bits_data = _GEN_39 ? _GEN_43 : 64'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@78472.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@78435.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@78436.4]
assign TLMonitor_io_in_a_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_param = auto_in_a_bits_param; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_size = auto_in_a_bits_size; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_source = auto_in_a_bits_source; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_a_bits_corrupt = auto_in_a_bits_corrupt; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_d_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_493}; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_d_bits_size = _T_495[1:0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
assign TLMonitor_io_in_d_bits_source = _T_495[10:2]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@78469.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
time_ = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {2{`RANDOM}};
timecmp_0 = _RAND_1[63:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
ipi_0 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
time_ <= 64'h0;
end else begin
if (_T_478) begin
time_ <= _T_485;
end else begin
if (io_rtcTick) begin
time_ <= _T_183;
end
end
end
if (_T_329) begin
timecmp_0 <= _T_336;
end
if (reset) begin
ipi_0 <= 1'h0;
end else begin
if (_T_1117) begin
ipi_0 <= _T_1119;
end
end
end
endmodule
module DMIToTL( // @[:freechips.rocketchip.system.LowRiscConfig.fir@79549.2]
input auto_out_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output auto_out_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output [2:0] auto_out_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output [8:0] auto_out_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output [3:0] auto_out_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output [31:0] auto_out_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output auto_out_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
input auto_out_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
input auto_out_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
input [31:0] auto_out_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
input auto_out_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79552.4]
output io_dmi_req_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
input io_dmi_req_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
input [6:0] io_dmi_req_bits_addr, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
input [31:0] io_dmi_req_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
input [1:0] io_dmi_req_bits_op, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
input io_dmi_resp_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
output io_dmi_resp_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
output [31:0] io_dmi_resp_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
output [1:0] io_dmi_resp_bits_resp // @[:freechips.rocketchip.system.LowRiscConfig.fir@79553.4]
);
wire [8:0] _GEN_16; // @[DMI.scala 92:50:freechips.rocketchip.system.LowRiscConfig.fir@79565.4]
wire [8:0] addr; // @[DMI.scala 92:50:freechips.rocketchip.system.LowRiscConfig.fir@79565.4]
wire _T_234; // @[DMI.scala 106:30:freechips.rocketchip.system.LowRiscConfig.fir@79698.4]
wire _T_235; // @[DMI.scala 107:37:freechips.rocketchip.system.LowRiscConfig.fir@79703.6]
wire [2:0] _GEN_0; // @[DMI.scala 107:64:freechips.rocketchip.system.LowRiscConfig.fir@79704.6]
wire [8:0] _GEN_4; // @[DMI.scala 107:64:freechips.rocketchip.system.LowRiscConfig.fir@79704.6]
wire [3:0] _GEN_5; // @[DMI.scala 107:64:freechips.rocketchip.system.LowRiscConfig.fir@79704.6]
wire _T_236; // @[DMI.scala 116:53:freechips.rocketchip.system.LowRiscConfig.fir@79714.4]
assign _GEN_16 = {{2'd0}, io_dmi_req_bits_addr}; // @[DMI.scala 92:50:freechips.rocketchip.system.LowRiscConfig.fir@79565.4]
assign addr = _GEN_16 << 2; // @[DMI.scala 92:50:freechips.rocketchip.system.LowRiscConfig.fir@79565.4]
assign _T_234 = io_dmi_req_bits_op == 2'h2; // @[DMI.scala 106:30:freechips.rocketchip.system.LowRiscConfig.fir@79698.4]
assign _T_235 = io_dmi_req_bits_op == 2'h1; // @[DMI.scala 107:37:freechips.rocketchip.system.LowRiscConfig.fir@79703.6]
assign _GEN_0 = _T_235 ? 3'h4 : 3'h1; // @[DMI.scala 107:64:freechips.rocketchip.system.LowRiscConfig.fir@79704.6]
assign _GEN_4 = _T_235 ? addr : 9'h40; // @[DMI.scala 107:64:freechips.rocketchip.system.LowRiscConfig.fir@79704.6]
assign _GEN_5 = _T_235 ? 4'hf : 4'h0; // @[DMI.scala 107:64:freechips.rocketchip.system.LowRiscConfig.fir@79704.6]
assign _T_236 = auto_out_d_bits_corrupt | auto_out_d_bits_denied; // @[DMI.scala 116:53:freechips.rocketchip.system.LowRiscConfig.fir@79714.4]
assign auto_out_a_valid = io_dmi_req_valid; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@79561.4]
assign auto_out_a_bits_opcode = _T_234 ? 3'h0 : _GEN_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@79561.4]
assign auto_out_a_bits_address = _T_234 ? addr : _GEN_4; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@79561.4]
assign auto_out_a_bits_mask = _T_234 ? 4'hf : _GEN_5; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@79561.4]
assign auto_out_a_bits_data = _T_234 ? io_dmi_req_bits_data : 32'h0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@79561.4]
assign auto_out_d_ready = io_dmi_resp_ready; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@79561.4]
assign io_dmi_req_ready = auto_out_a_ready; // @[DMI.scala 112:22:freechips.rocketchip.system.LowRiscConfig.fir@79711.4]
assign io_dmi_resp_valid = auto_out_d_valid; // @[DMI.scala 114:28:freechips.rocketchip.system.LowRiscConfig.fir@79712.4]
assign io_dmi_resp_bits_data = auto_out_d_bits_data; // @[DMI.scala 117:28:freechips.rocketchip.system.LowRiscConfig.fir@79717.4]
assign io_dmi_resp_bits_resp = {{1'd0}, _T_236}; // @[DMI.scala 116:28:freechips.rocketchip.system.LowRiscConfig.fir@79716.4]
endmodule
module TLMonitor_33( // @[:freechips.rocketchip.system.LowRiscConfig.fir@79729.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79730.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79731.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input [8:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@79732.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@80838.4]
wire [4:0] _T_29; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@79752.6]
wire [1:0] _T_30; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@79753.6]
wire [1:0] _T_31; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@79754.6]
wire [8:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@79755.6]
wire [8:0] _T_32; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@79755.6]
wire _T_33; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@79756.6]
wire [1:0] _T_36; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@79759.6]
wire [9:0] _T_70; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@79793.6]
wire _T_78; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@79805.6]
wire [9:0] _T_82; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@79810.8]
wire [9:0] _T_83; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@79811.8]
wire _T_84; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@79812.8]
wire _T_89; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@79817.8]
wire _T_101; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@79845.8]
wire _T_102; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@79846.8]
wire [3:0] _T_107; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@79859.8]
wire _T_108; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@79860.8]
wire _T_110; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@79862.8]
wire _T_111; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@79863.8]
wire _T_116; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@79877.6]
wire _T_158; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@79957.6]
wire _T_171; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79971.8]
wire _T_172; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79972.8]
wire _T_183; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@79999.8]
wire _T_185; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@80001.8]
wire _T_186; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@80002.8]
wire _T_191; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@80016.6]
wire _T_220; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@80067.6]
wire _T_251; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@80120.6]
wire _T_277; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@80168.6]
wire _T_303; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@80216.6]
wire _T_329; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@80266.6]
wire _T_331; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@80268.6]
wire _T_332; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@80269.6]
wire _T_342; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@80279.6]
wire _T_346; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@80288.8]
wire _T_348; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80290.8]
wire _T_349; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80291.8]
wire _T_350; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@80296.8]
wire _T_352; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@80298.8]
wire _T_353; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@80299.8]
wire _T_354; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@80304.8]
wire _T_356; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@80306.8]
wire _T_357; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@80307.8]
wire _T_358; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@80312.8]
wire _T_360; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@80314.8]
wire _T_361; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@80315.8]
wire _T_362; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@80321.6]
wire _T_373; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@80345.8]
wire _T_375; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@80347.8]
wire _T_376; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@80348.8]
wire _T_377; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@80353.8]
wire _T_379; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@80355.8]
wire _T_380; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@80356.8]
wire _T_390; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@80379.6]
wire _T_410; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@80420.8]
wire _T_412; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@80422.8]
wire _T_413; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@80423.8]
wire _T_419; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@80438.6]
wire _T_436; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@80473.6]
wire _T_454; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@80509.6]
wire _T_483; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@80569.4]
reg _T_493; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@80578.4]
reg [31:0] _RAND_0;
wire [1:0] _T_494; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80579.4]
wire [1:0] _T_495; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80580.4]
wire _T_496; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80581.4]
wire _T_497; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80582.4]
reg [2:0] _T_506; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@80593.4]
reg [31:0] _RAND_1;
reg [8:0] _T_514; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@80597.4]
reg [31:0] _RAND_2;
wire _T_515; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@80598.4]
wire _T_516; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@80599.4]
wire _T_517; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@80601.6]
wire _T_519; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@80603.6]
wire _T_520; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@80604.6]
wire _T_533; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@80633.6]
wire _T_535; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@80635.6]
wire _T_536; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@80636.6]
wire _T_538; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@80643.4]
wire _T_539; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@80651.4]
reg _T_548; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@80659.4]
reg [31:0] _RAND_3;
wire [1:0] _T_549; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80660.4]
wire [1:0] _T_550; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80661.4]
wire _T_551; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80662.4]
wire _T_552; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80663.4]
reg [2:0] _T_561; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@80674.4]
reg [31:0] _RAND_4;
reg [1:0] _T_563; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@80675.4]
reg [31:0] _RAND_5;
reg [1:0] _T_565; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@80676.4]
reg [31:0] _RAND_6;
reg _T_569; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@80678.4]
reg [31:0] _RAND_7;
reg _T_571; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@80679.4]
reg [31:0] _RAND_8;
wire _T_572; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@80680.4]
wire _T_573; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@80681.4]
wire _T_574; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@80683.6]
wire _T_576; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@80685.6]
wire _T_577; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@80686.6]
wire _T_578; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@80691.6]
wire _T_580; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@80693.6]
wire _T_581; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@80694.6]
wire _T_582; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@80699.6]
wire _T_584; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@80701.6]
wire _T_585; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@80702.6]
wire _T_590; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@80715.6]
wire _T_592; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@80717.6]
wire _T_593; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@80718.6]
wire _T_594; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@80723.6]
wire _T_596; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@80725.6]
wire _T_597; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@80726.6]
wire _T_599; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@80733.4]
reg _T_601; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@80742.4]
reg [31:0] _RAND_9;
reg _T_612; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@80752.4]
reg [31:0] _RAND_10;
wire [1:0] _T_613; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80753.4]
wire [1:0] _T_614; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80754.4]
wire _T_615; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80755.4]
wire _T_616; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80756.4]
reg _T_633; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@80775.4]
reg [31:0] _RAND_11;
wire [1:0] _T_634; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80776.4]
wire [1:0] _T_635; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80777.4]
wire _T_636; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80778.4]
wire _T_637; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80779.4]
wire _T_648; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@80794.4]
wire _T_651; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@80799.6]
wire _T_653; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@80801.6]
wire _T_655; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@80803.6]
wire _T_656; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@80804.6]
wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@80796.4]
wire _T_661; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@80815.4]
wire _T_663; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@80817.4]
wire _T_664; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@80818.4]
wire _T_646; // @[:freechips.rocketchip.system.LowRiscConfig.fir@80790.4 :freechips.rocketchip.system.LowRiscConfig.fir@80792.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@80798.6]
wire _T_666; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@80822.6]
wire _T_667; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@80823.6]
wire _T_670; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@80826.6]
wire _T_671; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@80827.6]
wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@80819.4]
wire _T_672; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@80833.4]
wire _T_658; // @[:freechips.rocketchip.system.LowRiscConfig.fir@80810.4 :freechips.rocketchip.system.LowRiscConfig.fir@80812.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@80821.6]
wire _T_673; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@80834.4]
wire _T_674; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@80835.4]
reg [31:0] _T_676; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@80837.4]
reg [31:0] _RAND_12;
wire _T_678; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@80841.4]
wire _T_679; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@80842.4]
wire _T_680; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@80843.4]
wire _T_681; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@80844.4]
wire _T_682; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@80845.4]
wire _T_684; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@80847.4]
wire _T_685; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@80848.4]
wire [31:0] _T_687; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@80854.4]
wire _T_690; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@80858.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@79819.10]
wire _GEN_27; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@79891.10]
wire _GEN_37; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79974.10]
wire _GEN_43; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@80033.10]
wire _GEN_49; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@80084.10]
wire _GEN_53; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@80134.10]
wire _GEN_59; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@80182.10]
wire _GEN_65; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@80230.10]
wire _GEN_71; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80293.10]
wire _GEN_79; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@80334.10]
wire _GEN_91; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@80392.10]
wire _GEN_103; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@80452.10]
wire _GEN_109; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@80487.10]
wire _GEN_115; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@80523.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@80838.4]
.out(plusarg_reader_out)
);
assign _T_29 = 5'h3 << 2'h2; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@79752.6]
assign _T_30 = _T_29[1:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@79753.6]
assign _T_31 = ~ _T_30; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@79754.6]
assign _GEN_18 = {{7'd0}, _T_31}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@79755.6]
assign _T_32 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@79755.6]
assign _T_33 = _T_32 == 9'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@79756.6]
assign _T_36 = 2'h1 << 1'h0; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@79759.6]
assign _T_70 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@79793.6]
assign _T_78 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@79805.6]
assign _T_82 = $signed(_T_70) & $signed(-10'sh200); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@79810.8]
assign _T_83 = $signed(_T_82); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@79811.8]
assign _T_84 = $signed(_T_83) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@79812.8]
assign _T_89 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@79817.8]
assign _T_101 = _T_33 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@79845.8]
assign _T_102 = _T_101 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@79846.8]
assign _T_107 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@79859.8]
assign _T_108 = _T_107 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@79860.8]
assign _T_110 = _T_108 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@79862.8]
assign _T_111 = _T_110 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@79863.8]
assign _T_116 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@79877.6]
assign _T_158 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@79957.6]
assign _T_171 = _T_84 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79971.8]
assign _T_172 = _T_171 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79972.8]
assign _T_183 = io_in_a_bits_mask == 4'hf; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@79999.8]
assign _T_185 = _T_183 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@80001.8]
assign _T_186 = _T_185 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@80002.8]
assign _T_191 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@80016.6]
assign _T_220 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@80067.6]
assign _T_251 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@80120.6]
assign _T_277 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@80168.6]
assign _T_303 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@80216.6]
assign _T_329 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@80266.6]
assign _T_331 = _T_329 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@80268.6]
assign _T_332 = _T_331 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@80269.6]
assign _T_342 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@80279.6]
assign _T_346 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@80288.8]
assign _T_348 = _T_346 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80290.8]
assign _T_349 = _T_348 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80291.8]
assign _T_350 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@80296.8]
assign _T_352 = _T_350 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@80298.8]
assign _T_353 = _T_352 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@80299.8]
assign _T_354 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@80304.8]
assign _T_356 = _T_354 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@80306.8]
assign _T_357 = _T_356 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@80307.8]
assign _T_358 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@80312.8]
assign _T_360 = _T_358 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@80314.8]
assign _T_361 = _T_360 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@80315.8]
assign _T_362 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@80321.6]
assign _T_373 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@80345.8]
assign _T_375 = _T_373 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@80347.8]
assign _T_376 = _T_375 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@80348.8]
assign _T_377 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@80353.8]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@80355.8]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@80356.8]
assign _T_390 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@80379.6]
assign _T_410 = _T_358 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@80420.8]
assign _T_412 = _T_410 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@80422.8]
assign _T_413 = _T_412 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@80423.8]
assign _T_419 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@80438.6]
assign _T_436 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@80473.6]
assign _T_454 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@80509.6]
assign _T_483 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@80569.4]
assign _T_494 = _T_493 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80579.4]
assign _T_495 = $unsigned(_T_494); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80580.4]
assign _T_496 = _T_495[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80581.4]
assign _T_497 = _T_493 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80582.4]
assign _T_515 = _T_497 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@80598.4]
assign _T_516 = io_in_a_valid & _T_515; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@80599.4]
assign _T_517 = io_in_a_bits_opcode == _T_506; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@80601.6]
assign _T_519 = _T_517 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@80603.6]
assign _T_520 = _T_519 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@80604.6]
assign _T_533 = io_in_a_bits_address == _T_514; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@80633.6]
assign _T_535 = _T_533 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@80635.6]
assign _T_536 = _T_535 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@80636.6]
assign _T_538 = _T_483 & _T_497; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@80643.4]
assign _T_539 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@80651.4]
assign _T_549 = _T_548 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80660.4]
assign _T_550 = $unsigned(_T_549); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80661.4]
assign _T_551 = _T_550[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80662.4]
assign _T_552 = _T_548 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80663.4]
assign _T_572 = _T_552 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@80680.4]
assign _T_573 = io_in_d_valid & _T_572; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@80681.4]
assign _T_574 = io_in_d_bits_opcode == _T_561; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@80683.6]
assign _T_576 = _T_574 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@80685.6]
assign _T_577 = _T_576 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@80686.6]
assign _T_578 = io_in_d_bits_param == _T_563; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@80691.6]
assign _T_580 = _T_578 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@80693.6]
assign _T_581 = _T_580 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@80694.6]
assign _T_582 = io_in_d_bits_size == _T_565; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@80699.6]
assign _T_584 = _T_582 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@80701.6]
assign _T_585 = _T_584 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@80702.6]
assign _T_590 = io_in_d_bits_sink == _T_569; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@80715.6]
assign _T_592 = _T_590 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@80717.6]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@80718.6]
assign _T_594 = io_in_d_bits_denied == _T_571; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@80723.6]
assign _T_596 = _T_594 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@80725.6]
assign _T_597 = _T_596 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@80726.6]
assign _T_599 = _T_539 & _T_552; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@80733.4]
assign _T_613 = _T_612 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80753.4]
assign _T_614 = $unsigned(_T_613); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80754.4]
assign _T_615 = _T_614[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80755.4]
assign _T_616 = _T_612 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80756.4]
assign _T_634 = _T_633 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80776.4]
assign _T_635 = $unsigned(_T_634); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80777.4]
assign _T_636 = _T_635[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@80778.4]
assign _T_637 = _T_633 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@80779.4]
assign _T_648 = _T_483 & _T_616; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@80794.4]
assign _T_651 = _T_601 >> 1'h0; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@80799.6]
assign _T_653 = _T_651 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@80801.6]
assign _T_655 = _T_653 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@80803.6]
assign _T_656 = _T_655 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@80804.6]
assign _GEN_15 = _T_648 ? _T_36 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@80796.4]
assign _T_661 = _T_539 & _T_637; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@80815.4]
assign _T_663 = _T_342 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@80817.4]
assign _T_664 = _T_661 & _T_663; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@80818.4]
assign _T_646 = _GEN_15[0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@80790.4 :freechips.rocketchip.system.LowRiscConfig.fir@80792.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@80798.6]
assign _T_666 = _T_646 | _T_601; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@80822.6]
assign _T_667 = _T_666 >> 1'h0; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@80823.6]
assign _T_670 = _T_667 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@80826.6]
assign _T_671 = _T_670 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@80827.6]
assign _GEN_16 = _T_664 ? _T_36 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@80819.4]
assign _T_672 = _T_601 | _T_646; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@80833.4]
assign _T_658 = _GEN_16[0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@80810.4 :freechips.rocketchip.system.LowRiscConfig.fir@80812.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@80821.6]
assign _T_673 = ~ _T_658; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@80834.4]
assign _T_674 = _T_672 & _T_673; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@80835.4]
assign _T_678 = _T_601 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@80841.4]
assign _T_679 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@80842.4]
assign _T_680 = _T_678 | _T_679; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@80843.4]
assign _T_681 = _T_676 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@80844.4]
assign _T_682 = _T_680 | _T_681; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@80845.4]
assign _T_684 = _T_682 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@80847.4]
assign _T_685 = _T_684 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@80848.4]
assign _T_687 = _T_676 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@80854.4]
assign _T_690 = _T_483 | _T_539; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@80858.4]
assign _GEN_19 = io_in_a_valid & _T_78; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@79819.10]
assign _GEN_27 = io_in_a_valid & _T_116; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@79891.10]
assign _GEN_37 = io_in_a_valid & _T_158; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79974.10]
assign _GEN_43 = io_in_a_valid & _T_191; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@80033.10]
assign _GEN_49 = io_in_a_valid & _T_220; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@80084.10]
assign _GEN_53 = io_in_a_valid & _T_251; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@80134.10]
assign _GEN_59 = io_in_a_valid & _T_277; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@80182.10]
assign _GEN_65 = io_in_a_valid & _T_303; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@80230.10]
assign _GEN_71 = io_in_d_valid & _T_342; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80293.10]
assign _GEN_79 = io_in_d_valid & _T_362; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@80334.10]
assign _GEN_91 = io_in_d_valid & _T_390; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@80392.10]
assign _GEN_103 = io_in_d_valid & _T_419; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@80452.10]
assign _GEN_109 = io_in_d_valid & _T_436; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@80487.10]
assign _GEN_115 = io_in_d_valid & _T_454; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@80523.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_493 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_506 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_514 = _RAND_2[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_548 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_561 = _RAND_4[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_563 = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_565 = _RAND_6[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_569 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_571 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_601 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_612 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_633 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_676 = _RAND_12[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_493 <= 1'h0;
end else begin
if (_T_483) begin
if (_T_497) begin
_T_493 <= 1'h0;
end else begin
_T_493 <= _T_496;
end
end
end
if (_T_538) begin
_T_506 <= io_in_a_bits_opcode;
end
if (_T_538) begin
_T_514 <= io_in_a_bits_address;
end
if (reset) begin
_T_548 <= 1'h0;
end else begin
if (_T_539) begin
if (_T_552) begin
_T_548 <= 1'h0;
end else begin
_T_548 <= _T_551;
end
end
end
if (_T_599) begin
_T_561 <= io_in_d_bits_opcode;
end
if (_T_599) begin
_T_563 <= io_in_d_bits_param;
end
if (_T_599) begin
_T_565 <= io_in_d_bits_size;
end
if (_T_599) begin
_T_569 <= io_in_d_bits_sink;
end
if (_T_599) begin
_T_571 <= io_in_d_bits_denied;
end
if (reset) begin
_T_601 <= 1'h0;
end else begin
_T_601 <= _T_674;
end
if (reset) begin
_T_612 <= 1'h0;
end else begin
if (_T_483) begin
if (_T_616) begin
_T_612 <= 1'h0;
end else begin
_T_612 <= _T_615;
end
end
end
if (reset) begin
_T_633 <= 1'h0;
end else begin
if (_T_539) begin
if (_T_637) begin
_T_633 <= 1'h0;
end else begin
_T_633 <= _T_636;
end
end
end
if (reset) begin
_T_676 <= 32'h0;
end else begin
if (_T_690) begin
_T_676 <= 32'h0;
end else begin
_T_676 <= _T_687;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Debug.scala:466:16)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@79744.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@79745.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@79802.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@79803.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@79819.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_89) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@79820.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:466:16)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@79826.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_89) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@79827.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@79833.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@79834.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Debug.scala:466:16)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@79841.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@79842.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@79848.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_102) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@79849.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Debug.scala:466:16)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@79856.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@79857.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_111) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@79865.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_111) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@79866.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@79873.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@79874.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@79891.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_89) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@79892.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:466:16)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@79898.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_89) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@79899.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@79905.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@79906.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Debug.scala:466:16)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@79913.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@79914.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@79920.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_102) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@79921.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Debug.scala:466:16)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@79928.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@79929.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:466:16)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@79936.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_89) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@79937.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_111) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@79945.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_111) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@79946.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@79953.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@79954.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_172) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79974.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_172) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@79975.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@79981.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@79982.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@79988.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_102) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@79989.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@79996.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@79997.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_186) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@80004.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_186) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@80005.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@80012.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@80013.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_172) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@80033.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_172) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@80034.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@80040.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@80041.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@80047.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_102) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@80048.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@80055.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@80056.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_186) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@80063.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_186) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@80064.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_172) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@80084.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_172) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@80085.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@80091.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@80092.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@80098.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_102) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@80099.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@80106.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@80107.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@80116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@80117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@80134.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_89) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@80135.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@80141.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@80142.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@80148.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_102) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@80149.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Debug.scala:466:16)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@80156.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@80157.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_186) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@80164.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_186) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@80165.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@80182.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_89) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@80183.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@80189.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@80190.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@80196.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_102) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@80197.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Debug.scala:466:16)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@80204.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@80205.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_186) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@80212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_186) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@80213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:466:16)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@80230.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_89) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@80231.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@80237.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@80238.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_102) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:466:16)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@80244.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_102) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@80245.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_186) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:466:16)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@80252.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_186) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@80253.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@80260.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@80261.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_332) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:466:16)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@80271.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_332) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@80272.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@80285.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@80286.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_349) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:466:16)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80293.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_349) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@80294.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_353) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@80301.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_353) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@80302.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_357) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@80309.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_357) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@80310.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_361) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:466:16)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@80317.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_361) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@80318.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@80327.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@80328.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_79 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:466:16)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@80334.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_79 & _T_89) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@80335.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_79 & _T_349) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:466:16)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@80342.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_79 & _T_349) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@80343.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_79 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:466:16)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@80350.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_79 & _T_376) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@80351.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_79 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:466:16)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@80358.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_79 & _T_380) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@80359.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_79 & _T_357) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@80366.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_79 & _T_357) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@80367.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_79 & _T_361) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:466:16)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@80375.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_79 & _T_361) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@80376.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@80385.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@80386.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_89) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:466:16)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@80392.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_89) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@80393.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_349) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:466:16)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@80400.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_349) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@80401.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_376) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:466:16)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@80408.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_376) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@80409.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:466:16)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@80416.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_380) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@80417.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@80425.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_413) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@80426.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_91 & _T_361) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:466:16)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@80434.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_91 & _T_361) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@80435.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@80444.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@80445.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_103 & _T_353) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@80452.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_103 & _T_353) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@80453.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_103 & _T_357) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@80460.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_103 & _T_357) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@80461.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_103 & _T_361) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:466:16)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@80469.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_103 & _T_361) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@80470.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@80479.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@80480.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_353) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@80487.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_353) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@80488.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_413) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@80496.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_413) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@80497.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_361) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:466:16)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@80505.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_361) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@80506.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:466:16)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@80515.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@80516.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_353) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:466:16)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@80523.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_353) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@80524.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_357) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:466:16)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@80531.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_357) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@80532.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_115 & _T_361) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:466:16)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@80540.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_115 & _T_361) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@80541.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Debug.scala:466:16)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@80550.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@80551.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Debug.scala:466:16)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@80558.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@80559.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Debug.scala:466:16)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@80566.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@80567.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_516 & _T_520) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@80606.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_516 & _T_520) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@80607.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@80614.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@80615.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@80622.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@80623.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@80630.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@80631.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_516 & _T_536) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@80638.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_516 & _T_536) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@80639.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_573 & _T_577) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@80688.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_573 & _T_577) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@80689.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_573 & _T_581) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@80696.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_573 & _T_581) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@80697.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_573 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@80704.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_573 & _T_585) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@80705.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@80712.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@80713.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_573 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@80720.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_573 & _T_593) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@80721.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_573 & _T_597) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:466:16)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@80728.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_573 & _T_597) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@80729.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_648 & _T_656) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:466:16)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@80806.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_648 & _T_656) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@80807.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_664 & _T_671) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:466:16)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@80829.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_664 & _T_671) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@80830.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_685) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:466:16)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@80850.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_685) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@80851.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLXbar_7( // @[:freechips.rocketchip.system.LowRiscConfig.fir@80863.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80864.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80865.4]
output auto_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [2:0] auto_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [8:0] auto_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [3:0] auto_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [31:0] auto_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [31:0] auto_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_in_d_bits_corrupt, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_1_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_out_1_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [2:0] auto_out_1_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [6:0] auto_out_1_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [3:0] auto_out_1_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [31:0] auto_out_1_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_out_1_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_1_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [2:0] auto_out_1_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [31:0] auto_out_1_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_0_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_out_0_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [2:0] auto_out_0_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [8:0] auto_out_0_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [3:0] auto_out_0_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output [31:0] auto_out_0_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
output auto_out_0_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_0_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [2:0] auto_out_0_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [1:0] auto_out_0_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [1:0] auto_out_0_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_0_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_0_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_0_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input [31:0] auto_out_0_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
input auto_out_0_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@80866.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [8:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [1:0] TLMonitor_io_in_d_bits_param; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [1:0] TLMonitor_io_in_d_bits_size; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_d_bits_sink; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_d_bits_denied; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire TLMonitor_io_in_d_bits_corrupt; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
wire [9:0] _T_700; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80953.4]
wire [9:0] _T_701; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80954.4]
wire [9:0] _T_702; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80955.4]
wire _T_703; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80956.4]
wire [8:0] _T_704; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80957.4]
wire [9:0] _T_705; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80958.4]
wire [9:0] _T_706; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80959.4]
wire [9:0] _T_707; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80960.4]
wire _T_708; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80961.4]
wire [8:0] _T_709; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80962.4]
wire [9:0] _T_710; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80963.4]
wire [9:0] _T_711; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80964.4]
wire [9:0] _T_712; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80965.4]
wire _T_713; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80966.4]
wire [8:0] _T_714; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80967.4]
wire [9:0] _T_715; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80968.4]
wire [9:0] _T_716; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80969.4]
wire [9:0] _T_717; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80970.4]
wire _T_718; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80971.4]
wire [8:0] _T_719; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80972.4]
wire [9:0] _T_720; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80973.4]
wire [9:0] _T_721; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80974.4]
wire [9:0] _T_722; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80975.4]
wire _T_723; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80976.4]
wire [8:0] _T_724; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80977.4]
wire [9:0] _T_725; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80978.4]
wire [9:0] _T_726; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80979.4]
wire [9:0] _T_727; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80980.4]
wire _T_728; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80981.4]
wire _T_729; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80982.4]
wire _T_730; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80983.4]
wire _T_731; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80984.4]
wire _T_732; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80985.4]
wire requestAIO_0_0; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80986.4]
wire [8:0] _T_734; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80988.4]
wire [9:0] _T_735; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80989.4]
wire [9:0] _T_736; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80990.4]
wire [9:0] _T_737; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80991.4]
wire _T_738; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80992.4]
wire [8:0] _T_739; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80993.4]
wire [9:0] _T_740; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80994.4]
wire [9:0] _T_741; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80995.4]
wire [9:0] _T_742; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80996.4]
wire _T_743; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80997.4]
wire requestAIO_0_1; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80998.4]
wire _T_824; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81071.4]
wire _T_825; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81072.4]
reg _T_980; // @[Arbiter.scala 53:30:freechips.rocketchip.system.LowRiscConfig.fir@81144.4]
reg [31:0] _RAND_0;
wire _T_981; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@81145.4]
wire _T_982; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@81146.4]
wire [1:0] _T_983; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@81147.4]
wire _T_985; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@81149.4]
wire _T_987; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@81151.4]
wire _T_988; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@81152.4]
reg [1:0] _T_991; // @[Arbiter.scala 20:23:freechips.rocketchip.system.LowRiscConfig.fir@81158.4]
reg [31:0] _RAND_1;
wire [1:0] _T_992; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@81159.4]
wire [1:0] _T_993; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@81160.4]
wire [3:0] _T_994; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@81161.4]
wire [2:0] _T_995; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@81162.4]
wire [3:0] _GEN_1; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@81163.4]
wire [3:0] _T_996; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@81163.4]
wire [2:0] _T_998; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@81165.4]
wire [3:0] _GEN_2; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@81166.4]
wire [3:0] _T_999; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@81166.4]
wire [3:0] _GEN_3; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@81167.4]
wire [3:0] _T_1000; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@81167.4]
wire [1:0] _T_1001; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@81168.4]
wire [1:0] _T_1002; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@81169.4]
wire [1:0] _T_1003; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@81170.4]
wire [1:0] _T_1004; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@81171.4]
wire _T_1005; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@81172.4]
wire _T_1006; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@81173.4]
wire [1:0] _T_1007; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@81175.6]
wire [2:0] _GEN_4; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@81176.6]
wire [2:0] _T_1008; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@81176.6]
wire [1:0] _T_1009; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@81177.6]
wire [1:0] _T_1010; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@81178.6]
wire _T_1013; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@81183.4]
wire _T_1014; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@81184.4]
wire _T_1023; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@81189.4]
wire _T_1024; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@81190.4]
wire _T_1034; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@81196.4]
wire _T_1036; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@81198.4]
wire _T_1039; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@81201.4]
wire _T_1040; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@81202.4]
wire _T_1043; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@81205.4]
wire _T_1044; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@81206.4]
wire _T_1045; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@81211.4]
wire _T_1046; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@81212.4]
wire _T_1048; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@81214.4]
wire _T_1050; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@81216.4]
wire _T_1051; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@81217.4]
reg _T_1076_0; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@81235.4]
reg [31:0] _RAND_2;
wire _T_1107; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81244.4]
reg _T_1076_1; // @[Arbiter.scala 78:26:freechips.rocketchip.system.LowRiscConfig.fir@81235.4]
reg [31:0] _RAND_3;
wire _T_1108; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81245.4]
wire _T_1109; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81246.4]
wire in_0_d_valid; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@81249.4]
wire _T_1055; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@81225.4]
wire [1:0] _T_1056; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@81226.4]
wire [1:0] _T_1057; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@81227.4]
wire _T_1058; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@81228.4]
wire _T_1087_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@81236.4]
wire _T_1087_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@81236.4]
wire _T_1095_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@81238.4]
wire _T_1095_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@81238.4]
wire [42:0] _T_1120; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81257.4]
wire [42:0] _T_1121; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81258.4]
wire [42:0] _T_1128; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81265.4]
wire [42:0] _T_1129; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81266.4]
wire [42:0] _T_1130; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81267.4]
TLMonitor_33 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@80873.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode),
.io_in_d_bits_param(TLMonitor_io_in_d_bits_param),
.io_in_d_bits_size(TLMonitor_io_in_d_bits_size),
.io_in_d_bits_sink(TLMonitor_io_in_d_bits_sink),
.io_in_d_bits_denied(TLMonitor_io_in_d_bits_denied),
.io_in_d_bits_corrupt(TLMonitor_io_in_d_bits_corrupt)
);
assign _T_700 = {1'b0,$signed(auto_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80953.4]
assign _T_701 = $signed(_T_700) & $signed(10'sh1c0); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80954.4]
assign _T_702 = $signed(_T_701); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80955.4]
assign _T_703 = $signed(_T_702) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80956.4]
assign _T_704 = auto_in_a_bits_address ^ 9'h44; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80957.4]
assign _T_705 = {1'b0,$signed(_T_704)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80958.4]
assign _T_706 = $signed(_T_705) & $signed(10'sh1fc); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80959.4]
assign _T_707 = $signed(_T_706); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80960.4]
assign _T_708 = $signed(_T_707) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80961.4]
assign _T_709 = auto_in_a_bits_address ^ 9'h48; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80962.4]
assign _T_710 = {1'b0,$signed(_T_709)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80963.4]
assign _T_711 = $signed(_T_710) & $signed(10'sh1e8); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80964.4]
assign _T_712 = $signed(_T_711); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80965.4]
assign _T_713 = $signed(_T_712) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80966.4]
assign _T_714 = auto_in_a_bits_address ^ 9'h60; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80967.4]
assign _T_715 = {1'b0,$signed(_T_714)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80968.4]
assign _T_716 = $signed(_T_715) & $signed(10'sh1e0); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80969.4]
assign _T_717 = $signed(_T_716); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80970.4]
assign _T_718 = $signed(_T_717) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80971.4]
assign _T_719 = auto_in_a_bits_address ^ 9'h80; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80972.4]
assign _T_720 = {1'b0,$signed(_T_719)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80973.4]
assign _T_721 = $signed(_T_720) & $signed(10'sh180); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80974.4]
assign _T_722 = $signed(_T_721); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80975.4]
assign _T_723 = $signed(_T_722) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80976.4]
assign _T_724 = auto_in_a_bits_address ^ 9'h100; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80977.4]
assign _T_725 = {1'b0,$signed(_T_724)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80978.4]
assign _T_726 = $signed(_T_725) & $signed(10'sh100); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80979.4]
assign _T_727 = $signed(_T_726); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80980.4]
assign _T_728 = $signed(_T_727) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80981.4]
assign _T_729 = _T_703 | _T_708; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80982.4]
assign _T_730 = _T_729 | _T_713; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80983.4]
assign _T_731 = _T_730 | _T_718; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80984.4]
assign _T_732 = _T_731 | _T_723; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80985.4]
assign requestAIO_0_0 = _T_732 | _T_728; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80986.4]
assign _T_734 = auto_in_a_bits_address ^ 9'h40; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80988.4]
assign _T_735 = {1'b0,$signed(_T_734)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80989.4]
assign _T_736 = $signed(_T_735) & $signed(10'sh1ec); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80990.4]
assign _T_737 = $signed(_T_736); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80991.4]
assign _T_738 = $signed(_T_737) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80992.4]
assign _T_739 = auto_in_a_bits_address ^ 9'h54; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@80993.4]
assign _T_740 = {1'b0,$signed(_T_739)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@80994.4]
assign _T_741 = $signed(_T_740) & $signed(10'sh1fc); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80995.4]
assign _T_742 = $signed(_T_741); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@80996.4]
assign _T_743 = $signed(_T_742) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@80997.4]
assign requestAIO_0_1 = _T_738 | _T_743; // @[Xbar.scala 217:92:freechips.rocketchip.system.LowRiscConfig.fir@80998.4]
assign _T_824 = requestAIO_0_0 ? auto_out_0_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81071.4]
assign _T_825 = requestAIO_0_1 ? auto_out_1_a_ready : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81072.4]
assign _T_981 = _T_980 == 1'h0; // @[Arbiter.scala 54:28:freechips.rocketchip.system.LowRiscConfig.fir@81145.4]
assign _T_982 = _T_981 & auto_in_d_ready; // @[Arbiter.scala 55:24:freechips.rocketchip.system.LowRiscConfig.fir@81146.4]
assign _T_983 = {auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@81147.4]
assign _T_985 = _T_983 == _T_983; // @[Arbiter.scala 19:19:freechips.rocketchip.system.LowRiscConfig.fir@81149.4]
assign _T_987 = _T_985 | reset; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@81151.4]
assign _T_988 = _T_987 == 1'h0; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@81152.4]
assign _T_992 = ~ _T_991; // @[Arbiter.scala 21:30:freechips.rocketchip.system.LowRiscConfig.fir@81159.4]
assign _T_993 = _T_983 & _T_992; // @[Arbiter.scala 21:28:freechips.rocketchip.system.LowRiscConfig.fir@81160.4]
assign _T_994 = {_T_993,auto_out_1_d_valid,auto_out_0_d_valid}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@81161.4]
assign _T_995 = _T_994[3:1]; // @[package.scala 203:48:freechips.rocketchip.system.LowRiscConfig.fir@81162.4]
assign _GEN_1 = {{1'd0}, _T_995}; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@81163.4]
assign _T_996 = _T_994 | _GEN_1; // @[package.scala 203:43:freechips.rocketchip.system.LowRiscConfig.fir@81163.4]
assign _T_998 = _T_996[3:1]; // @[Arbiter.scala 22:52:freechips.rocketchip.system.LowRiscConfig.fir@81165.4]
assign _GEN_2 = {{2'd0}, _T_991}; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@81166.4]
assign _T_999 = _GEN_2 << 2; // @[Arbiter.scala 22:66:freechips.rocketchip.system.LowRiscConfig.fir@81166.4]
assign _GEN_3 = {{1'd0}, _T_998}; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@81167.4]
assign _T_1000 = _GEN_3 | _T_999; // @[Arbiter.scala 22:58:freechips.rocketchip.system.LowRiscConfig.fir@81167.4]
assign _T_1001 = _T_1000[3:2]; // @[Arbiter.scala 23:29:freechips.rocketchip.system.LowRiscConfig.fir@81168.4]
assign _T_1002 = _T_1000[1:0]; // @[Arbiter.scala 23:48:freechips.rocketchip.system.LowRiscConfig.fir@81169.4]
assign _T_1003 = _T_1001 & _T_1002; // @[Arbiter.scala 23:39:freechips.rocketchip.system.LowRiscConfig.fir@81170.4]
assign _T_1004 = ~ _T_1003; // @[Arbiter.scala 23:18:freechips.rocketchip.system.LowRiscConfig.fir@81171.4]
assign _T_1005 = _T_983 != 2'h0; // @[Arbiter.scala 24:27:freechips.rocketchip.system.LowRiscConfig.fir@81172.4]
assign _T_1006 = _T_982 & _T_1005; // @[Arbiter.scala 24:18:freechips.rocketchip.system.LowRiscConfig.fir@81173.4]
assign _T_1007 = _T_1004 & _T_983; // @[Arbiter.scala 25:29:freechips.rocketchip.system.LowRiscConfig.fir@81175.6]
assign _GEN_4 = {{1'd0}, _T_1007}; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@81176.6]
assign _T_1008 = _GEN_4 << 1; // @[package.scala 194:48:freechips.rocketchip.system.LowRiscConfig.fir@81176.6]
assign _T_1009 = _T_1008[1:0]; // @[package.scala 194:53:freechips.rocketchip.system.LowRiscConfig.fir@81177.6]
assign _T_1010 = _T_1007 | _T_1009; // @[package.scala 194:43:freechips.rocketchip.system.LowRiscConfig.fir@81178.6]
assign _T_1013 = _T_1004[0]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@81183.4]
assign _T_1014 = _T_1004[1]; // @[Arbiter.scala 60:72:freechips.rocketchip.system.LowRiscConfig.fir@81184.4]
assign _T_1023 = _T_1013 & auto_out_0_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@81189.4]
assign _T_1024 = _T_1014 & auto_out_1_d_valid; // @[Arbiter.scala 62:65:freechips.rocketchip.system.LowRiscConfig.fir@81190.4]
assign _T_1034 = _T_1023 | _T_1024; // @[Arbiter.scala 67:52:freechips.rocketchip.system.LowRiscConfig.fir@81196.4]
assign _T_1036 = _T_1023 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@81198.4]
assign _T_1039 = _T_1024 == 1'h0; // @[Arbiter.scala 68:62:freechips.rocketchip.system.LowRiscConfig.fir@81201.4]
assign _T_1040 = _T_1036 | _T_1039; // @[Arbiter.scala 68:59:freechips.rocketchip.system.LowRiscConfig.fir@81202.4]
assign _T_1043 = _T_1040 | reset; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@81205.4]
assign _T_1044 = _T_1043 == 1'h0; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@81206.4]
assign _T_1045 = auto_out_0_d_valid | auto_out_1_d_valid; // @[Arbiter.scala 70:31:freechips.rocketchip.system.LowRiscConfig.fir@81211.4]
assign _T_1046 = _T_1045 == 1'h0; // @[Arbiter.scala 70:15:freechips.rocketchip.system.LowRiscConfig.fir@81212.4]
assign _T_1048 = _T_1046 | _T_1034; // @[Arbiter.scala 70:36:freechips.rocketchip.system.LowRiscConfig.fir@81214.4]
assign _T_1050 = _T_1048 | reset; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@81216.4]
assign _T_1051 = _T_1050 == 1'h0; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@81217.4]
assign _T_1107 = _T_1076_0 ? auto_out_0_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81244.4]
assign _T_1108 = _T_1076_1 ? auto_out_1_d_valid : 1'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81245.4]
assign _T_1109 = _T_1107 | _T_1108; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81246.4]
assign in_0_d_valid = _T_981 ? _T_1045 : _T_1109; // @[Arbiter.scala 86:24:freechips.rocketchip.system.LowRiscConfig.fir@81249.4]
assign _T_1055 = auto_in_d_ready & in_0_d_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@81225.4]
assign _T_1056 = _T_980 - _T_1055; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@81226.4]
assign _T_1057 = $unsigned(_T_1056); // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@81227.4]
assign _T_1058 = _T_1057[0:0]; // @[Arbiter.scala 75:52:freechips.rocketchip.system.LowRiscConfig.fir@81228.4]
assign _T_1087_0 = _T_981 ? _T_1023 : _T_1076_0; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@81236.4]
assign _T_1087_1 = _T_981 ? _T_1024 : _T_1076_1; // @[Arbiter.scala 79:25:freechips.rocketchip.system.LowRiscConfig.fir@81236.4]
assign _T_1095_0 = _T_981 ? _T_1013 : _T_1076_0; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@81238.4]
assign _T_1095_1 = _T_981 ? _T_1014 : _T_1076_1; // @[Arbiter.scala 82:24:freechips.rocketchip.system.LowRiscConfig.fir@81238.4]
assign _T_1120 = {auto_out_0_d_bits_opcode,auto_out_0_d_bits_param,auto_out_0_d_bits_size,auto_out_0_d_bits_source,auto_out_0_d_bits_sink,auto_out_0_d_bits_denied,auto_out_0_d_bits_data,auto_out_0_d_bits_corrupt}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81257.4]
assign _T_1121 = _T_1087_0 ? _T_1120 : 43'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81258.4]
assign _T_1128 = {auto_out_1_d_bits_opcode,2'h0,3'h4,2'h0,auto_out_1_d_bits_data,1'h0}; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81265.4]
assign _T_1129 = _T_1087_1 ? _T_1128 : 43'h0; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81266.4]
assign _T_1130 = _T_1121 | _T_1129; // @[Mux.scala 19:72:freechips.rocketchip.system.LowRiscConfig.fir@81267.4]
assign auto_in_a_ready = _T_824 | _T_825; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@80916.4]
assign auto_in_d_valid = _T_981 ? _T_1045 : _T_1109; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@80916.4]
assign auto_in_d_bits_denied = _T_1130[33]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@80916.4]
assign auto_in_d_bits_data = _T_1130[32:1]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@80916.4]
assign auto_in_d_bits_corrupt = _T_1130[0]; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@80916.4]
assign auto_out_1_a_valid = auto_in_a_valid & requestAIO_0_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80915.4]
assign auto_out_1_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80915.4]
assign auto_out_1_a_bits_address = auto_in_a_bits_address[6:0]; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80915.4]
assign auto_out_1_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80915.4]
assign auto_out_1_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80915.4]
assign auto_out_1_d_ready = auto_in_d_ready & _T_1095_1; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80915.4]
assign auto_out_0_a_valid = auto_in_a_valid & requestAIO_0_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80914.4]
assign auto_out_0_a_bits_opcode = auto_in_a_bits_opcode; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80914.4]
assign auto_out_0_a_bits_address = auto_in_a_bits_address; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80914.4]
assign auto_out_0_a_bits_mask = auto_in_a_bits_mask; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80914.4]
assign auto_out_0_a_bits_data = auto_in_a_bits_data; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80914.4]
assign auto_out_0_d_ready = auto_in_d_ready & _T_1095_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@80914.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@80875.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@80876.4]
assign TLMonitor_io_in_a_ready = _T_824 | _T_825; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_a_valid = auto_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_a_bits_opcode = auto_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_a_bits_address = auto_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_a_bits_mask = auto_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_ready = auto_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_valid = _T_981 ? _T_1045 : _T_1109; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_bits_opcode = _T_1130[42:40]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_bits_param = _T_1130[39:38]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_bits_size = _T_1130[37:36]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_bits_sink = _T_1130[34]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_bits_denied = _T_1130[33]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
assign TLMonitor_io_in_d_bits_corrupt = _T_1130[0]; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@80909.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_980 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_991 = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1076_0 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1076_1 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_980 <= 1'h0;
end else begin
if (_T_982) begin
_T_980 <= 1'h0;
end else begin
_T_980 <= _T_1058;
end
end
if (reset) begin
_T_991 <= 2'h3;
end else begin
if (_T_1006) begin
_T_991 <= _T_1010;
end
end
if (reset) begin
_T_1076_0 <= 1'h0;
end else begin
if (_T_981) begin
_T_1076_0 <= _T_1023;
end
end
if (reset) begin
_T_1076_1 <= 1'h0;
end else begin
if (_T_981) begin
_T_1076_1 <= _T_1024;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_988) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:19 assert (valid === valids)\n"); // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@81154.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_988) begin
$fatal; // @[Arbiter.scala 19:12:freechips.rocketchip.system.LowRiscConfig.fir@81155.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1044) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:68 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n"); // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@81208.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1044) begin
$fatal; // @[Arbiter.scala 68:13:freechips.rocketchip.system.LowRiscConfig.fir@81209.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_1051) begin
$fwrite(32'h80000002,"Assertion failed\n at Arbiter.scala:70 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n"); // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@81219.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_1051) begin
$fatal; // @[Arbiter.scala 70:14:freechips.rocketchip.system.LowRiscConfig.fir@81220.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module TLMonitor_34( // @[:freechips.rocketchip.system.LowRiscConfig.fir@81296.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81297.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81298.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input [6:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
input [2:0] io_in_d_bits_opcode // @[:freechips.rocketchip.system.LowRiscConfig.fir@81299.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@82453.4]
wire [4:0] _T_29; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@81319.6]
wire [1:0] _T_30; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@81320.6]
wire [1:0] _T_31; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@81321.6]
wire [6:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@81322.6]
wire [6:0] _T_32; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@81322.6]
wire _T_33; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@81323.6]
wire [1:0] _T_36; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@81326.6]
wire _T_78; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@81372.6]
wire [6:0] _T_80; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@81375.8]
wire [7:0] _T_81; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@81376.8]
wire [7:0] _T_82; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81377.8]
wire [7:0] _T_83; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81378.8]
wire _T_84; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@81379.8]
wire [6:0] _T_85; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@81380.8]
wire [7:0] _T_86; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@81381.8]
wire [7:0] _T_87; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81382.8]
wire [7:0] _T_88; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81383.8]
wire _T_89; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@81384.8]
wire _T_90; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@81385.8]
wire _T_95; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@81390.8]
wire _T_107; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@81418.8]
wire _T_108; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@81419.8]
wire [3:0] _T_113; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@81432.8]
wire _T_114; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@81433.8]
wire _T_116; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@81435.8]
wire _T_117; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@81436.8]
wire _T_122; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@81450.6]
wire _T_170; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@81536.6]
wire _T_189; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81556.8]
wire _T_190; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81557.8]
wire _T_201; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@81584.8]
wire _T_203; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@81586.8]
wire _T_204; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@81587.8]
wire _T_209; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@81601.6]
wire _T_244; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@81658.6]
wire _T_281; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@81717.6]
wire _T_313; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@81771.6]
wire _T_345; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@81825.6]
wire _T_377; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@81881.6]
wire _T_379; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@81883.6]
wire _T_380; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@81884.6]
wire _T_390; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@81894.6]
wire _T_410; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@81936.6]
wire _T_438; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@81994.6]
wire _T_531; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@82184.4]
reg _T_541; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@82193.4]
reg [31:0] _RAND_0;
wire [1:0] _T_542; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82194.4]
wire [1:0] _T_543; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82195.4]
wire _T_544; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82196.4]
wire _T_545; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82197.4]
reg [2:0] _T_554; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@82208.4]
reg [31:0] _RAND_1;
reg [6:0] _T_562; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@82212.4]
reg [31:0] _RAND_2;
wire _T_563; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@82213.4]
wire _T_564; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@82214.4]
wire _T_565; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@82216.6]
wire _T_567; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@82218.6]
wire _T_568; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@82219.6]
wire _T_581; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@82248.6]
wire _T_583; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@82250.6]
wire _T_584; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@82251.6]
wire _T_586; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@82258.4]
wire _T_587; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@82266.4]
reg _T_596; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@82274.4]
reg [31:0] _RAND_3;
wire [1:0] _T_597; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82275.4]
wire [1:0] _T_598; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82276.4]
wire _T_599; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82277.4]
wire _T_600; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82278.4]
reg [2:0] _T_609; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@82289.4]
reg [31:0] _RAND_4;
wire _T_620; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@82295.4]
wire _T_621; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@82296.4]
wire _T_622; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@82298.6]
wire _T_624; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@82300.6]
wire _T_625; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@82301.6]
wire _T_647; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@82348.4]
reg _T_649; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@82357.4]
reg [31:0] _RAND_5;
reg _T_660; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@82367.4]
reg [31:0] _RAND_6;
wire [1:0] _T_661; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82368.4]
wire [1:0] _T_662; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82369.4]
wire _T_663; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82370.4]
wire _T_664; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82371.4]
reg _T_681; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@82390.4]
reg [31:0] _RAND_7;
wire [1:0] _T_682; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82391.4]
wire [1:0] _T_683; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82392.4]
wire _T_684; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82393.4]
wire _T_685; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82394.4]
wire _T_696; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@82409.4]
wire _T_699; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@82414.6]
wire _T_701; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@82416.6]
wire _T_703; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@82418.6]
wire _T_704; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@82419.6]
wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@82411.4]
wire _T_709; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@82430.4]
wire _T_711; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@82432.4]
wire _T_712; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@82433.4]
wire _T_694; // @[:freechips.rocketchip.system.LowRiscConfig.fir@82405.4 :freechips.rocketchip.system.LowRiscConfig.fir@82407.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@82413.6]
wire _T_714; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@82437.6]
wire _T_715; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@82438.6]
wire _T_718; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@82441.6]
wire _T_719; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@82442.6]
wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@82434.4]
wire _T_720; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@82448.4]
wire _T_706; // @[:freechips.rocketchip.system.LowRiscConfig.fir@82425.4 :freechips.rocketchip.system.LowRiscConfig.fir@82427.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@82436.6]
wire _T_721; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@82449.4]
wire _T_722; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@82450.4]
reg [31:0] _T_724; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@82452.4]
reg [31:0] _RAND_8;
wire _T_726; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@82456.4]
wire _T_727; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@82457.4]
wire _T_728; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@82458.4]
wire _T_729; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@82459.4]
wire _T_730; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@82460.4]
wire _T_732; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@82462.4]
wire _T_733; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@82463.4]
wire [31:0] _T_735; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@82469.4]
wire _T_738; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@82473.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@81392.10]
wire _GEN_27; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@81470.10]
wire _GEN_37; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81559.10]
wire _GEN_43; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@81624.10]
wire _GEN_49; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@81681.10]
wire _GEN_53; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@81737.10]
wire _GEN_59; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@81791.10]
wire _GEN_65; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@81845.10]
wire _GEN_71; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@81949.10]
wire _GEN_73; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@82007.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@82453.4]
.out(plusarg_reader_out)
);
assign _T_29 = 5'h3 << 2'h2; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@81319.6]
assign _T_30 = _T_29[1:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@81320.6]
assign _T_31 = ~ _T_30; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@81321.6]
assign _GEN_18 = {{5'd0}, _T_31}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@81322.6]
assign _T_32 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@81322.6]
assign _T_33 = _T_32 == 7'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@81323.6]
assign _T_36 = 2'h1 << 1'h0; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@81326.6]
assign _T_78 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@81372.6]
assign _T_80 = io_in_a_bits_address ^ 7'h40; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@81375.8]
assign _T_81 = {1'b0,$signed(_T_80)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@81376.8]
assign _T_82 = $signed(_T_81) & $signed(-8'sh14); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81377.8]
assign _T_83 = $signed(_T_82); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81378.8]
assign _T_84 = $signed(_T_83) == $signed(8'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@81379.8]
assign _T_85 = io_in_a_bits_address ^ 7'h54; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@81380.8]
assign _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@81381.8]
assign _T_87 = $signed(_T_86) & $signed(-8'sh4); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81382.8]
assign _T_88 = $signed(_T_87); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@81383.8]
assign _T_89 = $signed(_T_88) == $signed(8'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@81384.8]
assign _T_90 = _T_84 | _T_89; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@81385.8]
assign _T_95 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@81390.8]
assign _T_107 = _T_33 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@81418.8]
assign _T_108 = _T_107 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@81419.8]
assign _T_113 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@81432.8]
assign _T_114 = _T_113 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@81433.8]
assign _T_116 = _T_114 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@81435.8]
assign _T_117 = _T_116 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@81436.8]
assign _T_122 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@81450.6]
assign _T_170 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@81536.6]
assign _T_189 = _T_90 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81556.8]
assign _T_190 = _T_189 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81557.8]
assign _T_201 = io_in_a_bits_mask == 4'hf; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@81584.8]
assign _T_203 = _T_201 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@81586.8]
assign _T_204 = _T_203 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@81587.8]
assign _T_209 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@81601.6]
assign _T_244 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@81658.6]
assign _T_281 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@81717.6]
assign _T_313 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@81771.6]
assign _T_345 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@81825.6]
assign _T_377 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@81881.6]
assign _T_379 = _T_377 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@81883.6]
assign _T_380 = _T_379 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@81884.6]
assign _T_390 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@81894.6]
assign _T_410 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@81936.6]
assign _T_438 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@81994.6]
assign _T_531 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@82184.4]
assign _T_542 = _T_541 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82194.4]
assign _T_543 = $unsigned(_T_542); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82195.4]
assign _T_544 = _T_543[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82196.4]
assign _T_545 = _T_541 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82197.4]
assign _T_563 = _T_545 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@82213.4]
assign _T_564 = io_in_a_valid & _T_563; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@82214.4]
assign _T_565 = io_in_a_bits_opcode == _T_554; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@82216.6]
assign _T_567 = _T_565 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@82218.6]
assign _T_568 = _T_567 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@82219.6]
assign _T_581 = io_in_a_bits_address == _T_562; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@82248.6]
assign _T_583 = _T_581 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@82250.6]
assign _T_584 = _T_583 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@82251.6]
assign _T_586 = _T_531 & _T_545; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@82258.4]
assign _T_587 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@82266.4]
assign _T_597 = _T_596 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82275.4]
assign _T_598 = $unsigned(_T_597); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82276.4]
assign _T_599 = _T_598[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82277.4]
assign _T_600 = _T_596 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82278.4]
assign _T_620 = _T_600 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@82295.4]
assign _T_621 = io_in_d_valid & _T_620; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@82296.4]
assign _T_622 = io_in_d_bits_opcode == _T_609; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@82298.6]
assign _T_624 = _T_622 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@82300.6]
assign _T_625 = _T_624 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@82301.6]
assign _T_647 = _T_587 & _T_600; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@82348.4]
assign _T_661 = _T_660 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82368.4]
assign _T_662 = $unsigned(_T_661); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82369.4]
assign _T_663 = _T_662[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82370.4]
assign _T_664 = _T_660 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82371.4]
assign _T_682 = _T_681 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82391.4]
assign _T_683 = $unsigned(_T_682); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82392.4]
assign _T_684 = _T_683[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@82393.4]
assign _T_685 = _T_681 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@82394.4]
assign _T_696 = _T_531 & _T_664; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@82409.4]
assign _T_699 = _T_649 >> 1'h0; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@82414.6]
assign _T_701 = _T_699 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@82416.6]
assign _T_703 = _T_701 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@82418.6]
assign _T_704 = _T_703 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@82419.6]
assign _GEN_15 = _T_696 ? _T_36 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@82411.4]
assign _T_709 = _T_587 & _T_685; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@82430.4]
assign _T_711 = _T_390 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@82432.4]
assign _T_712 = _T_709 & _T_711; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@82433.4]
assign _T_694 = _GEN_15[0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@82405.4 :freechips.rocketchip.system.LowRiscConfig.fir@82407.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@82413.6]
assign _T_714 = _T_694 | _T_649; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@82437.6]
assign _T_715 = _T_714 >> 1'h0; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@82438.6]
assign _T_718 = _T_715 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@82441.6]
assign _T_719 = _T_718 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@82442.6]
assign _GEN_16 = _T_712 ? _T_36 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@82434.4]
assign _T_720 = _T_649 | _T_694; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@82448.4]
assign _T_706 = _GEN_16[0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@82425.4 :freechips.rocketchip.system.LowRiscConfig.fir@82427.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@82436.6]
assign _T_721 = ~ _T_706; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@82449.4]
assign _T_722 = _T_720 & _T_721; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@82450.4]
assign _T_726 = _T_649 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@82456.4]
assign _T_727 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@82457.4]
assign _T_728 = _T_726 | _T_727; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@82458.4]
assign _T_729 = _T_724 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@82459.4]
assign _T_730 = _T_728 | _T_729; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@82460.4]
assign _T_732 = _T_730 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@82462.4]
assign _T_733 = _T_732 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@82463.4]
assign _T_735 = _T_724 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@82469.4]
assign _T_738 = _T_531 | _T_587; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@82473.4]
assign _GEN_19 = io_in_a_valid & _T_78; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@81392.10]
assign _GEN_27 = io_in_a_valid & _T_122; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@81470.10]
assign _GEN_37 = io_in_a_valid & _T_170; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81559.10]
assign _GEN_43 = io_in_a_valid & _T_209; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@81624.10]
assign _GEN_49 = io_in_a_valid & _T_244; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@81681.10]
assign _GEN_53 = io_in_a_valid & _T_281; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@81737.10]
assign _GEN_59 = io_in_a_valid & _T_313; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@81791.10]
assign _GEN_65 = io_in_a_valid & _T_345; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@81845.10]
assign _GEN_71 = io_in_d_valid & _T_410; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@81949.10]
assign _GEN_73 = io_in_d_valid & _T_438; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@82007.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_541 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_554 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_562 = _RAND_2[6:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_596 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_609 = _RAND_4[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_649 = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_660 = _RAND_6[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_681 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_724 = _RAND_8[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_541 <= 1'h0;
end else begin
if (_T_531) begin
if (_T_545) begin
_T_541 <= 1'h0;
end else begin
_T_541 <= _T_544;
end
end
end
if (_T_586) begin
_T_554 <= io_in_a_bits_opcode;
end
if (_T_586) begin
_T_562 <= io_in_a_bits_address;
end
if (reset) begin
_T_596 <= 1'h0;
end else begin
if (_T_587) begin
if (_T_600) begin
_T_596 <= 1'h0;
end else begin
_T_596 <= _T_599;
end
end
end
if (_T_647) begin
_T_609 <= io_in_d_bits_opcode;
end
if (reset) begin
_T_649 <= 1'h0;
end else begin
_T_649 <= _T_722;
end
if (reset) begin
_T_660 <= 1'h0;
end else begin
if (_T_531) begin
if (_T_664) begin
_T_660 <= 1'h0;
end else begin
_T_660 <= _T_663;
end
end
end
if (reset) begin
_T_681 <= 1'h0;
end else begin
if (_T_587) begin
if (_T_685) begin
_T_681 <= 1'h0;
end else begin
_T_681 <= _T_684;
end
end
end
if (reset) begin
_T_724 <= 32'h0;
end else begin
if (_T_738) begin
_T_724 <= 32'h0;
end else begin
_T_724 <= _T_735;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Debug.scala:467:19)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@81311.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@81312.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@81369.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@81370.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@81392.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_95) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@81393.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:467:19)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@81399.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_95) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@81400.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@81406.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@81407.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Debug.scala:467:19)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@81414.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@81415.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@81421.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_108) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@81422.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Debug.scala:467:19)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@81429.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@81430.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_117) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@81438.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_117) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@81439.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@81446.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@81447.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@81470.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_95) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@81471.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:467:19)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@81477.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_95) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@81478.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@81484.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@81485.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Debug.scala:467:19)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@81492.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@81493.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@81499.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_108) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@81500.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Debug.scala:467:19)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@81507.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@81508.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:467:19)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@81515.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_95) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@81516.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_117) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@81524.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_117) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@81525.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@81532.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@81533.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_190) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81559.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_190) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@81560.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@81566.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@81567.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@81573.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_108) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@81574.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@81581.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@81582.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@81589.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_204) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@81590.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@81597.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@81598.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_190) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@81624.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_190) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@81625.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@81631.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@81632.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@81638.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_108) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@81639.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@81646.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@81647.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@81654.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_204) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@81655.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_190) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@81681.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_190) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@81682.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@81688.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@81689.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@81695.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_108) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@81696.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@81703.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@81704.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@81713.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@81714.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@81737.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_95) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@81738.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@81744.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@81745.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@81751.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_108) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@81752.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Debug.scala:467:19)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@81759.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@81760.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@81767.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_204) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@81768.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@81791.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_95) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@81792.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@81798.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@81799.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@81805.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_108) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@81806.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Debug.scala:467:19)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@81813.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@81814.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@81821.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_204) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@81822.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:467:19)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@81845.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_95) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@81846.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@81852.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@81853.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_108) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:467:19)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@81859.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_108) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@81860.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_204) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:467:19)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@81867.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_204) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@81868.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@81875.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@81876.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_380) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:467:19)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@81886.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_380) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@81887.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@81900.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@81901.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:467:19)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@81908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@81909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@81916.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@81917.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@81924.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@81925.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:467:19)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@81932.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@81933.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@81942.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@81943.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:467:19)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@81949.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_95) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@81950.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:467:19)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@81957.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@81958.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:467:19)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@81965.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@81966.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:467:19)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@81973.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@81974.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@81981.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@81982.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:467:19)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@81990.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@81991.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@82000.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@82001.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_73 & _T_95) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:467:19)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@82007.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_73 & _T_95) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@82008.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:467:19)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@82015.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@82016.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:467:19)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@82023.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@82024.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:467:19)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@82031.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@82032.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@82040.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@82041.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:467:19)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@82049.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@82050.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@82059.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@82060.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@82067.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@82068.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@82075.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@82076.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:467:19)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@82084.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@82085.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@82094.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@82095.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@82102.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@82103.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@82111.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@82112.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:467:19)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@82120.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@82121.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:467:19)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@82130.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@82131.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:467:19)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@82138.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@82139.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:467:19)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@82146.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@82147.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:467:19)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@82155.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@82156.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Debug.scala:467:19)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@82165.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@82166.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Debug.scala:467:19)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@82173.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@82174.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Debug.scala:467:19)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@82181.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@82182.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_564 & _T_568) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@82221.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_564 & _T_568) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@82222.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@82229.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@82230.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@82237.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@82238.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@82245.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@82246.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_564 & _T_584) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@82253.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_564 & _T_584) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@82254.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_621 & _T_625) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@82303.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_621 & _T_625) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@82304.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@82311.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@82312.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@82319.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@82320.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@82327.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@82328.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@82335.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@82336.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:467:19)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@82343.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@82344.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_696 & _T_704) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:467:19)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@82421.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_696 & _T_704) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@82422.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_712 & _T_719) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:467:19)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@82444.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_712 & _T_719) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@82445.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_733) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:467:19)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@82465.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_733) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@82466.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module AsyncResetRegVec_w32_i0( // @[:freechips.rocketchip.system.LowRiscConfig.fir@82798.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@82799.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@82800.4]
input [31:0] io_d, // @[:freechips.rocketchip.system.LowRiscConfig.fir@82801.4]
output [31:0] io_q // @[:freechips.rocketchip.system.LowRiscConfig.fir@82801.4]
);
wire reg_0_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82806.4]
wire reg_0_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82806.4]
wire reg_0_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82806.4]
wire reg_0_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82806.4]
wire reg_0_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82806.4]
wire reg_1_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82812.4]
wire reg_1_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82812.4]
wire reg_1_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82812.4]
wire reg_1_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82812.4]
wire reg_1_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82812.4]
wire reg_2_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82818.4]
wire reg_2_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82818.4]
wire reg_2_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82818.4]
wire reg_2_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82818.4]
wire reg_2_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82818.4]
wire reg_3_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82824.4]
wire reg_3_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82824.4]
wire reg_3_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82824.4]
wire reg_3_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82824.4]
wire reg_3_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82824.4]
wire reg_4_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82830.4]
wire reg_4_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82830.4]
wire reg_4_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82830.4]
wire reg_4_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82830.4]
wire reg_4_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82830.4]
wire reg_5_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82836.4]
wire reg_5_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82836.4]
wire reg_5_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82836.4]
wire reg_5_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82836.4]
wire reg_5_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82836.4]
wire reg_6_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82842.4]
wire reg_6_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82842.4]
wire reg_6_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82842.4]
wire reg_6_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82842.4]
wire reg_6_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82842.4]
wire reg_7_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82848.4]
wire reg_7_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82848.4]
wire reg_7_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82848.4]
wire reg_7_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82848.4]
wire reg_7_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82848.4]
wire reg_8_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82854.4]
wire reg_8_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82854.4]
wire reg_8_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82854.4]
wire reg_8_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82854.4]
wire reg_8_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82854.4]
wire reg_9_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82860.4]
wire reg_9_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82860.4]
wire reg_9_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82860.4]
wire reg_9_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82860.4]
wire reg_9_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82860.4]
wire reg_10_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82866.4]
wire reg_10_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82866.4]
wire reg_10_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82866.4]
wire reg_10_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82866.4]
wire reg_10_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82866.4]
wire reg_11_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82872.4]
wire reg_11_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82872.4]
wire reg_11_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82872.4]
wire reg_11_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82872.4]
wire reg_11_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82872.4]
wire reg_12_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82878.4]
wire reg_12_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82878.4]
wire reg_12_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82878.4]
wire reg_12_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82878.4]
wire reg_12_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82878.4]
wire reg_13_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82884.4]
wire reg_13_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82884.4]
wire reg_13_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82884.4]
wire reg_13_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82884.4]
wire reg_13_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82884.4]
wire reg_14_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82890.4]
wire reg_14_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82890.4]
wire reg_14_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82890.4]
wire reg_14_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82890.4]
wire reg_14_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82890.4]
wire reg_15_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82896.4]
wire reg_15_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82896.4]
wire reg_15_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82896.4]
wire reg_15_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82896.4]
wire reg_15_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82896.4]
wire reg_16_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82902.4]
wire reg_16_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82902.4]
wire reg_16_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82902.4]
wire reg_16_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82902.4]
wire reg_16_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82902.4]
wire reg_17_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82908.4]
wire reg_17_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82908.4]
wire reg_17_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82908.4]
wire reg_17_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82908.4]
wire reg_17_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82908.4]
wire reg_18_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82914.4]
wire reg_18_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82914.4]
wire reg_18_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82914.4]
wire reg_18_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82914.4]
wire reg_18_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82914.4]
wire reg_19_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82920.4]
wire reg_19_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82920.4]
wire reg_19_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82920.4]
wire reg_19_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82920.4]
wire reg_19_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82920.4]
wire reg_20_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82926.4]
wire reg_20_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82926.4]
wire reg_20_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82926.4]
wire reg_20_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82926.4]
wire reg_20_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82926.4]
wire reg_21_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82932.4]
wire reg_21_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82932.4]
wire reg_21_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82932.4]
wire reg_21_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82932.4]
wire reg_21_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82932.4]
wire reg_22_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82938.4]
wire reg_22_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82938.4]
wire reg_22_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82938.4]
wire reg_22_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82938.4]
wire reg_22_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82938.4]
wire reg_23_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82944.4]
wire reg_23_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82944.4]
wire reg_23_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82944.4]
wire reg_23_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82944.4]
wire reg_23_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82944.4]
wire reg_24_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82950.4]
wire reg_24_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82950.4]
wire reg_24_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82950.4]
wire reg_24_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82950.4]
wire reg_24_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82950.4]
wire reg_25_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82956.4]
wire reg_25_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82956.4]
wire reg_25_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82956.4]
wire reg_25_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82956.4]
wire reg_25_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82956.4]
wire reg_26_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82962.4]
wire reg_26_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82962.4]
wire reg_26_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82962.4]
wire reg_26_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82962.4]
wire reg_26_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82962.4]
wire reg_27_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82968.4]
wire reg_27_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82968.4]
wire reg_27_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82968.4]
wire reg_27_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82968.4]
wire reg_27_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82968.4]
wire reg_28_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82974.4]
wire reg_28_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82974.4]
wire reg_28_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82974.4]
wire reg_28_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82974.4]
wire reg_28_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82974.4]
wire reg_29_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82980.4]
wire reg_29_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82980.4]
wire reg_29_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82980.4]
wire reg_29_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82980.4]
wire reg_29_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82980.4]
wire reg_30_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82986.4]
wire reg_30_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82986.4]
wire reg_30_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82986.4]
wire reg_30_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82986.4]
wire reg_30_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82986.4]
wire reg_31_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82992.4]
wire reg_31_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82992.4]
wire reg_31_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82992.4]
wire reg_31_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82992.4]
wire reg_31_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82992.4]
wire [7:0] _T_45; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83164.4]
wire [15:0] _T_53; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83172.4]
wire [7:0] _T_60; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83179.4]
wire [15:0] _T_68; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83187.4]
AsyncResetReg #(.RESET_VALUE(0)) reg_0 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82806.4]
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_1 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82812.4]
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_2 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82818.4]
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_3 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82824.4]
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_4 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82830.4]
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_5 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82836.4]
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_6 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82842.4]
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_7 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82848.4]
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_8 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82854.4]
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_9 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82860.4]
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_10 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82866.4]
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_11 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82872.4]
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_12 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82878.4]
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_13 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82884.4]
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_14 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82890.4]
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_15 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82896.4]
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_16 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82902.4]
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_17 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82908.4]
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_18 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82914.4]
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_19 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82920.4]
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_20 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82926.4]
.rst(reg_20_rst),
.clk(reg_20_clk),
.en(reg_20_en),
.q(reg_20_q),
.d(reg_20_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_21 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82932.4]
.rst(reg_21_rst),
.clk(reg_21_clk),
.en(reg_21_en),
.q(reg_21_q),
.d(reg_21_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_22 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82938.4]
.rst(reg_22_rst),
.clk(reg_22_clk),
.en(reg_22_en),
.q(reg_22_q),
.d(reg_22_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_23 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82944.4]
.rst(reg_23_rst),
.clk(reg_23_clk),
.en(reg_23_en),
.q(reg_23_q),
.d(reg_23_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_24 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82950.4]
.rst(reg_24_rst),
.clk(reg_24_clk),
.en(reg_24_en),
.q(reg_24_q),
.d(reg_24_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_25 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82956.4]
.rst(reg_25_rst),
.clk(reg_25_clk),
.en(reg_25_en),
.q(reg_25_q),
.d(reg_25_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_26 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82962.4]
.rst(reg_26_rst),
.clk(reg_26_clk),
.en(reg_26_en),
.q(reg_26_q),
.d(reg_26_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_27 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82968.4]
.rst(reg_27_rst),
.clk(reg_27_clk),
.en(reg_27_en),
.q(reg_27_q),
.d(reg_27_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_28 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82974.4]
.rst(reg_28_rst),
.clk(reg_28_clk),
.en(reg_28_en),
.q(reg_28_q),
.d(reg_28_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_29 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82980.4]
.rst(reg_29_rst),
.clk(reg_29_clk),
.en(reg_29_en),
.q(reg_29_q),
.d(reg_29_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_30 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82986.4]
.rst(reg_30_rst),
.clk(reg_30_clk),
.en(reg_30_en),
.q(reg_30_q),
.d(reg_30_d)
);
AsyncResetReg #(.RESET_VALUE(0)) reg_31 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@82992.4]
.rst(reg_31_rst),
.clk(reg_31_clk),
.en(reg_31_en),
.q(reg_31_q),
.d(reg_31_d)
);
assign _T_45 = {reg_7_q,reg_6_q,reg_5_q,reg_4_q,reg_3_q,reg_2_q,reg_1_q,reg_0_q}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83164.4]
assign _T_53 = {reg_15_q,reg_14_q,reg_13_q,reg_12_q,reg_11_q,reg_10_q,reg_9_q,reg_8_q,_T_45}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83172.4]
assign _T_60 = {reg_23_q,reg_22_q,reg_21_q,reg_20_q,reg_19_q,reg_18_q,reg_17_q,reg_16_q}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83179.4]
assign _T_68 = {reg_31_q,reg_30_q,reg_29_q,reg_28_q,reg_27_q,reg_26_q,reg_25_q,reg_24_q,_T_60}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83187.4]
assign io_q = {_T_68,_T_53}; // @[AsyncResetReg.scala 73:8:freechips.rocketchip.system.LowRiscConfig.fir@83189.4]
assign reg_0_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@82999.4]
assign reg_0_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@82998.4]
assign reg_0_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83002.4]
assign reg_0_d = io_d[0]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83001.4]
assign reg_1_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83004.4]
assign reg_1_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83003.4]
assign reg_1_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83007.4]
assign reg_1_d = io_d[1]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83006.4]
assign reg_2_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83009.4]
assign reg_2_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83008.4]
assign reg_2_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83012.4]
assign reg_2_d = io_d[2]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83011.4]
assign reg_3_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83014.4]
assign reg_3_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83013.4]
assign reg_3_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83017.4]
assign reg_3_d = io_d[3]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83016.4]
assign reg_4_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83019.4]
assign reg_4_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83018.4]
assign reg_4_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83022.4]
assign reg_4_d = io_d[4]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83021.4]
assign reg_5_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83024.4]
assign reg_5_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83023.4]
assign reg_5_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83027.4]
assign reg_5_d = io_d[5]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83026.4]
assign reg_6_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83029.4]
assign reg_6_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83028.4]
assign reg_6_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83032.4]
assign reg_6_d = io_d[6]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83031.4]
assign reg_7_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83034.4]
assign reg_7_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83033.4]
assign reg_7_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83037.4]
assign reg_7_d = io_d[7]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83036.4]
assign reg_8_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83039.4]
assign reg_8_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83038.4]
assign reg_8_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83042.4]
assign reg_8_d = io_d[8]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83041.4]
assign reg_9_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83044.4]
assign reg_9_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83043.4]
assign reg_9_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83047.4]
assign reg_9_d = io_d[9]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83046.4]
assign reg_10_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83049.4]
assign reg_10_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83048.4]
assign reg_10_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83052.4]
assign reg_10_d = io_d[10]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83051.4]
assign reg_11_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83054.4]
assign reg_11_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83053.4]
assign reg_11_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83057.4]
assign reg_11_d = io_d[11]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83056.4]
assign reg_12_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83059.4]
assign reg_12_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83058.4]
assign reg_12_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83062.4]
assign reg_12_d = io_d[12]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83061.4]
assign reg_13_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83064.4]
assign reg_13_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83063.4]
assign reg_13_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83067.4]
assign reg_13_d = io_d[13]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83066.4]
assign reg_14_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83069.4]
assign reg_14_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83068.4]
assign reg_14_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83072.4]
assign reg_14_d = io_d[14]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83071.4]
assign reg_15_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83074.4]
assign reg_15_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83073.4]
assign reg_15_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83077.4]
assign reg_15_d = io_d[15]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83076.4]
assign reg_16_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83079.4]
assign reg_16_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83078.4]
assign reg_16_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83082.4]
assign reg_16_d = io_d[16]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83081.4]
assign reg_17_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83084.4]
assign reg_17_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83083.4]
assign reg_17_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83087.4]
assign reg_17_d = io_d[17]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83086.4]
assign reg_18_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83089.4]
assign reg_18_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83088.4]
assign reg_18_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83092.4]
assign reg_18_d = io_d[18]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83091.4]
assign reg_19_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83094.4]
assign reg_19_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83093.4]
assign reg_19_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83097.4]
assign reg_19_d = io_d[19]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83096.4]
assign reg_20_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83099.4]
assign reg_20_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83098.4]
assign reg_20_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83102.4]
assign reg_20_d = io_d[20]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83101.4]
assign reg_21_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83104.4]
assign reg_21_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83103.4]
assign reg_21_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83107.4]
assign reg_21_d = io_d[21]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83106.4]
assign reg_22_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83109.4]
assign reg_22_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83108.4]
assign reg_22_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83112.4]
assign reg_22_d = io_d[22]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83111.4]
assign reg_23_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83114.4]
assign reg_23_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83113.4]
assign reg_23_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83117.4]
assign reg_23_d = io_d[23]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83116.4]
assign reg_24_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83119.4]
assign reg_24_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83118.4]
assign reg_24_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83122.4]
assign reg_24_d = io_d[24]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83121.4]
assign reg_25_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83124.4]
assign reg_25_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83123.4]
assign reg_25_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83127.4]
assign reg_25_d = io_d[25]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83126.4]
assign reg_26_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83129.4]
assign reg_26_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83128.4]
assign reg_26_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83132.4]
assign reg_26_d = io_d[26]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83131.4]
assign reg_27_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83134.4]
assign reg_27_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83133.4]
assign reg_27_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83137.4]
assign reg_27_d = io_d[27]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83136.4]
assign reg_28_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83139.4]
assign reg_28_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83138.4]
assign reg_28_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83142.4]
assign reg_28_d = io_d[28]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83141.4]
assign reg_29_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83144.4]
assign reg_29_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83143.4]
assign reg_29_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83147.4]
assign reg_29_d = io_d[29]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83146.4]
assign reg_30_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83149.4]
assign reg_30_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83148.4]
assign reg_30_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83152.4]
assign reg_30_d = io_d[30]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83151.4]
assign reg_31_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83154.4]
assign reg_31_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83153.4]
assign reg_31_en = 1'h1; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83157.4]
assign reg_31_d = io_d[31]; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83156.4]
endmodule
module AsyncResetRegVec_w1_i0( // @[:freechips.rocketchip.system.LowRiscConfig.fir@83201.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83202.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83203.4]
input io_d, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83204.4]
output io_q, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83204.4]
input io_en // @[:freechips.rocketchip.system.LowRiscConfig.fir@83204.4]
);
wire reg_0_rst; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@83209.4]
wire reg_0_clk; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@83209.4]
wire reg_0_en; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@83209.4]
wire reg_0_q; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@83209.4]
wire reg_0_d; // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@83209.4]
AsyncResetReg #(.RESET_VALUE(0)) reg_0 ( // @[AsyncResetReg.scala 61:11:freechips.rocketchip.system.LowRiscConfig.fir@83209.4]
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
assign io_q = reg_0_q; // @[AsyncResetReg.scala 73:8:freechips.rocketchip.system.LowRiscConfig.fir@83220.4]
assign reg_0_rst = reset; // @[AsyncResetReg.scala 66:16:freechips.rocketchip.system.LowRiscConfig.fir@83216.4]
assign reg_0_clk = clock; // @[AsyncResetReg.scala 65:16:freechips.rocketchip.system.LowRiscConfig.fir@83215.4]
assign reg_0_en = io_en; // @[AsyncResetReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@83219.4]
assign reg_0_d = io_d; // @[AsyncResetReg.scala 67:16:freechips.rocketchip.system.LowRiscConfig.fir@83218.4]
endmodule
module TLDebugModuleOuter( // @[:freechips.rocketchip.system.LowRiscConfig.fir@83222.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83223.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83224.4]
output auto_dmi_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
input auto_dmi_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
input [2:0] auto_dmi_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
input [6:0] auto_dmi_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
input [3:0] auto_dmi_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
input [31:0] auto_dmi_in_a_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
input auto_dmi_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
output auto_dmi_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
output [2:0] auto_dmi_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
output [31:0] auto_dmi_in_d_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
output auto_int_out_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83225.4]
output io_ctrl_ndreset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83226.4]
output io_ctrl_dmactive, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83226.4]
output io_innerCtrl_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83226.4]
output io_innerCtrl_bits_resumereq, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83226.4]
output [9:0] io_innerCtrl_bits_hartsel, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83226.4]
output io_innerCtrl_bits_ackhavereset // @[:freechips.rocketchip.system.LowRiscConfig.fir@83226.4]
);
wire TLMonitor_clock; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire TLMonitor_reset; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire TLMonitor_io_in_a_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire TLMonitor_io_in_a_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire [2:0] TLMonitor_io_in_a_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire [6:0] TLMonitor_io_in_a_bits_address; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire [3:0] TLMonitor_io_in_a_bits_mask; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire TLMonitor_io_in_d_ready; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire TLMonitor_io_in_d_valid; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire [2:0] TLMonitor_io_in_d_bits_opcode; // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
wire DMCONTROL_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83345.4]
wire DMCONTROL_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83345.4]
wire [31:0] DMCONTROL_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83345.4]
wire [31:0] DMCONTROL_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83345.4]
wire debugInterrupts_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83719.4]
wire debugInterrupts_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83719.4]
wire debugInterrupts_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83719.4]
wire debugInterrupts_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83719.4]
wire debugInterrupts_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83719.4]
wire [31:0] _T_252; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83353.4 :freechips.rocketchip.system.LowRiscConfig.fir@83355.4]
wire DMCONTROLReg_dmactive; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83356.4]
wire _T_284; // @[Debug.scala 284:11:freechips.rocketchip.system.LowRiscConfig.fir@83421.4]
wire _T_354; // @[RegisterRouter.scala 58:36:freechips.rocketchip.system.LowRiscConfig.fir@83512.4]
wire [4:0] _T_355; // @[Edges.scala 192:34:freechips.rocketchip.system.LowRiscConfig.fir@83514.4]
wire [2:0] _T_351_bits_index; // @[RegisterRouter.scala 57:18:freechips.rocketchip.system.LowRiscConfig.fir@83510.4 RegisterRouter.scala 59:19:freechips.rocketchip.system.LowRiscConfig.fir@83515.4]
wire _T_374; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83528.4]
wire _T_520; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83650.4]
wire _T_521; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83651.4]
wire _T_522; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83652.4]
wire [1:0] _T_462; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@83601.4]
wire _T_463; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83602.4]
wire _T_525; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83655.4]
wire _T_526; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83656.4]
wire _T_422; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83556.4]
wire [7:0] _T_430; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83564.4]
wire _T_421; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83555.4]
wire [7:0] _T_428; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83562.4]
wire _T_420; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83554.4]
wire [7:0] _T_426; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83560.4]
wire _T_419; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83553.4]
wire [7:0] _T_424; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83558.4]
wire [31:0] _T_433; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83567.4]
wire [31:0] _T_442; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83576.4]
wire _T_443; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83577.4]
wire DMCONTROLWrEn; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83581.4]
wire [31:0] DMCONTROLWrDataVal; // @[Debug.scala 221:24:freechips.rocketchip.system.LowRiscConfig.fir@83585.4]
wire DMCONTROLWrData_ndmreset; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83394.4]
wire DMCONTROLReg_ndmreset; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83358.4]
wire _GEN_0; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
wire DMCONTROLNxt_ndmreset; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLWrData_dmactive; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83392.4]
wire _GEN_16; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLNxt_dmactive; // @[Debug.scala 298:26:freechips.rocketchip.system.LowRiscConfig.fir@83435.4]
wire [9:0] DMCONTROLWrData_hartsello; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83400.4]
wire [9:0] DMCONTROLReg_hartsello; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83364.4]
wire [9:0] _GEN_1; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
wire [9:0] DMCONTROLNxt_hartsello; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire [9:0] DMCONTROLReg_hartselhi; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83362.4]
wire [9:0] DMCONTROLNxt_hartselhi; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire [3:0] DMCONTROLReg_reserved1; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83360.4]
wire [3:0] DMCONTROLNxt_reserved1; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire [25:0] _T_242; // @[Debug.scala 268:107:freechips.rocketchip.system.LowRiscConfig.fir@83338.4]
wire DMCONTROLWrData_ackhavereset; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83406.4]
wire DMCONTROLReg_ackhavereset; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83370.4]
wire _GEN_4; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
wire DMCONTROLNxt_ackhavereset; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLReg_reserved0; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83368.4]
wire DMCONTROLNxt_reserved0; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLReg_hasel; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83366.4]
wire _GEN_5; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
wire DMCONTROLNxt_hasel; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLWrData_haltreq; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83412.4]
wire DMCONTROLReg_haltreq; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83376.4]
wire _GEN_2; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
wire DMCONTROLNxt_haltreq; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLWrData_resumereq; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83410.4]
wire DMCONTROLReg_resumereq; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83374.4]
wire _GEN_3; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
wire DMCONTROLNxt_resumereq; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire DMCONTROLReg_hartreset; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83372.4]
wire DMCONTROLNxt_hartreset; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
wire [5:0] _T_247; // @[Debug.scala 268:107:freechips.rocketchip.system.LowRiscConfig.fir@83343.4]
wire [25:0] _T_340; // @[Debug.scala 397:72:freechips.rocketchip.system.LowRiscConfig.fir@83503.4]
wire [31:0] _T_346; // @[Debug.scala 397:72:freechips.rocketchip.system.LowRiscConfig.fir@83509.4]
wire debugIntRegs_0; // @[Debug.scala 413:33:freechips.rocketchip.system.LowRiscConfig.fir@83725.4]
wire _T_613; // @[Debug.scala 434:60:freechips.rocketchip.system.LowRiscConfig.fir@83739.6]
wire _T_615; // @[Debug.scala 434:29:freechips.rocketchip.system.LowRiscConfig.fir@83741.6]
wire _GEN_19; // @[Debug.scala 435:98:freechips.rocketchip.system.LowRiscConfig.fir@83742.6]
TLMonitor_34 TLMonitor ( // @[Nodes.scala 25:25:freechips.rocketchip.system.LowRiscConfig.fir@83236.4]
.clock(TLMonitor_clock),
.reset(TLMonitor_reset),
.io_in_a_ready(TLMonitor_io_in_a_ready),
.io_in_a_valid(TLMonitor_io_in_a_valid),
.io_in_a_bits_opcode(TLMonitor_io_in_a_bits_opcode),
.io_in_a_bits_address(TLMonitor_io_in_a_bits_address),
.io_in_a_bits_mask(TLMonitor_io_in_a_bits_mask),
.io_in_d_ready(TLMonitor_io_in_d_ready),
.io_in_d_valid(TLMonitor_io_in_d_valid),
.io_in_d_bits_opcode(TLMonitor_io_in_d_bits_opcode)
);
AsyncResetRegVec_w32_i0 DMCONTROL ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83345.4]
.clock(DMCONTROL_clock),
.reset(DMCONTROL_reset),
.io_d(DMCONTROL_io_d),
.io_q(DMCONTROL_io_q)
);
AsyncResetRegVec_w1_i0 debugInterrupts ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@83719.4]
.clock(debugInterrupts_clock),
.reset(debugInterrupts_reset),
.io_d(debugInterrupts_io_d),
.io_q(debugInterrupts_io_q),
.io_en(debugInterrupts_io_en)
);
assign _T_252 = DMCONTROL_io_q; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83353.4 :freechips.rocketchip.system.LowRiscConfig.fir@83355.4]
assign DMCONTROLReg_dmactive = _T_252[0]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83356.4]
assign _T_284 = ~ DMCONTROLReg_dmactive; // @[Debug.scala 284:11:freechips.rocketchip.system.LowRiscConfig.fir@83421.4]
assign _T_354 = auto_dmi_in_a_bits_opcode == 3'h4; // @[RegisterRouter.scala 58:36:freechips.rocketchip.system.LowRiscConfig.fir@83512.4]
assign _T_355 = auto_dmi_in_a_bits_address[6:2]; // @[Edges.scala 192:34:freechips.rocketchip.system.LowRiscConfig.fir@83514.4]
assign _T_351_bits_index = _T_355[2:0]; // @[RegisterRouter.scala 57:18:freechips.rocketchip.system.LowRiscConfig.fir@83510.4 RegisterRouter.scala 59:19:freechips.rocketchip.system.LowRiscConfig.fir@83515.4]
assign _T_374 = _T_351_bits_index == 3'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83528.4]
assign _T_520 = auto_dmi_in_a_valid & auto_dmi_in_d_ready; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83650.4]
assign _T_521 = _T_354 == 1'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83651.4]
assign _T_522 = _T_520 & _T_521; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83652.4]
assign _T_462 = 2'h1 << 1'h0; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@83601.4]
assign _T_463 = _T_462[0]; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83602.4]
assign _T_525 = _T_522 & _T_463; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83655.4]
assign _T_526 = _T_525 & _T_374; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83656.4]
assign _T_422 = auto_dmi_in_a_bits_mask[3]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83556.4]
assign _T_430 = _T_422 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83564.4]
assign _T_421 = auto_dmi_in_a_bits_mask[2]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83555.4]
assign _T_428 = _T_421 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83562.4]
assign _T_420 = auto_dmi_in_a_bits_mask[1]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83554.4]
assign _T_426 = _T_420 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83560.4]
assign _T_419 = auto_dmi_in_a_bits_mask[0]; // @[Bitwise.scala 27:51:freechips.rocketchip.system.LowRiscConfig.fir@83553.4]
assign _T_424 = _T_419 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12:freechips.rocketchip.system.LowRiscConfig.fir@83558.4]
assign _T_433 = {_T_430,_T_428,_T_426,_T_424}; // @[Cat.scala 30:58:freechips.rocketchip.system.LowRiscConfig.fir@83567.4]
assign _T_442 = ~ _T_433; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83576.4]
assign _T_443 = _T_442 == 32'h0; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83577.4]
assign DMCONTROLWrEn = _T_526 & _T_443; // @[RegisterRouter.scala 65:24:freechips.rocketchip.system.LowRiscConfig.fir@83581.4]
assign DMCONTROLWrDataVal = DMCONTROLWrEn ? auto_dmi_in_a_bits_data : 32'h0; // @[Debug.scala 221:24:freechips.rocketchip.system.LowRiscConfig.fir@83585.4]
assign DMCONTROLWrData_ndmreset = DMCONTROLWrDataVal[1]; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83394.4]
assign DMCONTROLReg_ndmreset = _T_252[1]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83358.4]
assign _GEN_0 = DMCONTROLWrEn ? DMCONTROLWrData_ndmreset : DMCONTROLReg_ndmreset; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
assign DMCONTROLNxt_ndmreset = _T_284 ? 1'h0 : _GEN_0; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLWrData_dmactive = DMCONTROLWrDataVal[0]; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83392.4]
assign _GEN_16 = _T_284 ? 1'h0 : DMCONTROLReg_dmactive; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLNxt_dmactive = DMCONTROLWrEn ? DMCONTROLWrData_dmactive : _GEN_16; // @[Debug.scala 298:26:freechips.rocketchip.system.LowRiscConfig.fir@83435.4]
assign DMCONTROLWrData_hartsello = DMCONTROLWrDataVal[25:16]; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83400.4]
assign DMCONTROLReg_hartsello = _T_252[25:16]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83364.4]
assign _GEN_1 = DMCONTROLWrEn ? DMCONTROLWrData_hartsello : DMCONTROLReg_hartsello; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
assign DMCONTROLNxt_hartsello = _T_284 ? 10'h0 : _GEN_1; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLReg_hartselhi = _T_252[15:6]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83362.4]
assign DMCONTROLNxt_hartselhi = _T_284 ? 10'h0 : DMCONTROLReg_hartselhi; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLReg_reserved1 = _T_252[5:2]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83360.4]
assign DMCONTROLNxt_reserved1 = _T_284 ? 4'h0 : DMCONTROLReg_reserved1; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign _T_242 = {DMCONTROLNxt_hartsello,DMCONTROLNxt_hartselhi,DMCONTROLNxt_reserved1,DMCONTROLNxt_ndmreset,DMCONTROLNxt_dmactive}; // @[Debug.scala 268:107:freechips.rocketchip.system.LowRiscConfig.fir@83338.4]
assign DMCONTROLWrData_ackhavereset = DMCONTROLWrDataVal[28]; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83406.4]
assign DMCONTROLReg_ackhavereset = _T_252[28]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83370.4]
assign _GEN_4 = DMCONTROLWrEn ? DMCONTROLWrData_ackhavereset : DMCONTROLReg_ackhavereset; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
assign DMCONTROLNxt_ackhavereset = _T_284 ? 1'h0 : _GEN_4; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLReg_reserved0 = _T_252[27]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83368.4]
assign DMCONTROLNxt_reserved0 = _T_284 ? 1'h0 : DMCONTROLReg_reserved0; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLReg_hasel = _T_252[26]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83366.4]
assign _GEN_5 = DMCONTROLWrEn ? 1'h0 : DMCONTROLReg_hasel; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
assign DMCONTROLNxt_hasel = _T_284 ? 1'h0 : _GEN_5; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLWrData_haltreq = DMCONTROLWrDataVal[31]; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83412.4]
assign DMCONTROLReg_haltreq = _T_252[31]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83376.4]
assign _GEN_2 = DMCONTROLWrEn ? DMCONTROLWrData_haltreq : DMCONTROLReg_haltreq; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
assign DMCONTROLNxt_haltreq = _T_284 ? 1'h0 : _GEN_2; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLWrData_resumereq = DMCONTROLWrDataVal[30]; // @[Debug.scala 277:59:freechips.rocketchip.system.LowRiscConfig.fir@83410.4]
assign DMCONTROLReg_resumereq = _T_252[30]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83374.4]
assign _GEN_3 = DMCONTROLWrEn ? DMCONTROLWrData_resumereq : DMCONTROLReg_resumereq; // @[Debug.scala 287:28:freechips.rocketchip.system.LowRiscConfig.fir@83426.6]
assign DMCONTROLNxt_resumereq = _T_284 ? 1'h0 : _GEN_3; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign DMCONTROLReg_hartreset = _T_252[29]; // @[Debug.scala 268:66:freechips.rocketchip.system.LowRiscConfig.fir@83372.4]
assign DMCONTROLNxt_hartreset = _T_284 ? 1'h0 : DMCONTROLReg_hartreset; // @[Debug.scala 284:22:freechips.rocketchip.system.LowRiscConfig.fir@83422.4]
assign _T_247 = {DMCONTROLNxt_haltreq,DMCONTROLNxt_resumereq,DMCONTROLNxt_hartreset,DMCONTROLNxt_ackhavereset,DMCONTROLNxt_reserved0,DMCONTROLNxt_hasel}; // @[Debug.scala 268:107:freechips.rocketchip.system.LowRiscConfig.fir@83343.4]
assign _T_340 = {DMCONTROLReg_hartsello,DMCONTROLReg_hartselhi,DMCONTROLReg_reserved1,DMCONTROLReg_ndmreset,DMCONTROLReg_dmactive}; // @[Debug.scala 397:72:freechips.rocketchip.system.LowRiscConfig.fir@83503.4]
assign _T_346 = {DMCONTROLReg_haltreq,DMCONTROLReg_resumereq,DMCONTROLReg_hartreset,DMCONTROLReg_ackhavereset,DMCONTROLReg_reserved0,DMCONTROLReg_hasel,_T_340}; // @[Debug.scala 397:72:freechips.rocketchip.system.LowRiscConfig.fir@83509.4]
assign debugIntRegs_0 = debugInterrupts_io_q; // @[Debug.scala 413:33:freechips.rocketchip.system.LowRiscConfig.fir@83725.4]
assign _T_613 = DMCONTROLWrData_hartsello == 10'h0; // @[Debug.scala 434:60:freechips.rocketchip.system.LowRiscConfig.fir@83739.6]
assign _T_615 = DMCONTROLWrEn & _T_613; // @[Debug.scala 434:29:freechips.rocketchip.system.LowRiscConfig.fir@83741.6]
assign _GEN_19 = _T_615 ? DMCONTROLWrData_haltreq : debugIntRegs_0; // @[Debug.scala 435:98:freechips.rocketchip.system.LowRiscConfig.fir@83742.6]
assign auto_dmi_in_a_ready = auto_dmi_in_d_ready; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@83274.4]
assign auto_dmi_in_d_valid = auto_dmi_in_a_valid; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@83274.4]
assign auto_dmi_in_d_bits_opcode = {{2'd0}, _T_354}; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@83274.4]
assign auto_dmi_in_d_bits_data = _T_374 ? _T_346 : 32'h0; // @[LazyModule.scala 173:31:freechips.rocketchip.system.LowRiscConfig.fir@83274.4]
assign auto_int_out_0 = debugInterrupts_io_q; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@83273.4]
assign io_ctrl_ndreset = _T_252[1]; // @[Debug.scala 450:21:freechips.rocketchip.system.LowRiscConfig.fir@83755.4]
assign io_ctrl_dmactive = _T_252[0]; // @[Debug.scala 451:22:freechips.rocketchip.system.LowRiscConfig.fir@83756.4]
assign io_innerCtrl_valid = _T_526 & _T_443; // @[Debug.scala 441:24:freechips.rocketchip.system.LowRiscConfig.fir@83748.4]
assign io_innerCtrl_bits_resumereq = DMCONTROLWrEn & DMCONTROLWrData_resumereq; // @[Debug.scala 443:36:freechips.rocketchip.system.LowRiscConfig.fir@83752.4]
assign io_innerCtrl_bits_hartsel = DMCONTROLWrEn ? DMCONTROLWrData_hartsello : DMCONTROLReg_hartsello; // @[Debug.scala 442:36:freechips.rocketchip.system.LowRiscConfig.fir@83750.4]
assign io_innerCtrl_bits_ackhavereset = DMCONTROLWrEn & DMCONTROLWrData_ackhavereset; // @[Debug.scala 444:36:freechips.rocketchip.system.LowRiscConfig.fir@83754.4]
assign TLMonitor_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83238.4]
assign TLMonitor_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83239.4]
assign TLMonitor_io_in_a_ready = auto_dmi_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_a_valid = auto_dmi_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_a_bits_opcode = auto_dmi_in_a_bits_opcode; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_a_bits_address = auto_dmi_in_a_bits_address; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_a_bits_mask = auto_dmi_in_a_bits_mask; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_d_ready = auto_dmi_in_d_ready; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_d_valid = auto_dmi_in_a_valid; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign TLMonitor_io_in_d_bits_opcode = {{2'd0}, _T_354}; // @[Nodes.scala 26:19:freechips.rocketchip.system.LowRiscConfig.fir@83272.4]
assign DMCONTROL_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83347.4]
assign DMCONTROL_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83348.4]
assign DMCONTROL_io_d = {_T_247,_T_242}; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@83349.4]
assign debugInterrupts_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83721.4]
assign debugInterrupts_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@83722.4]
assign debugInterrupts_io_d = _T_284 ? 1'h0 : _GEN_19; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@83723.4]
assign debugInterrupts_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.LowRiscConfig.fir@83724.4]
endmodule
module IntSyncCrossingSource( // @[:freechips.rocketchip.system.LowRiscConfig.fir@83758.2]
input auto_in_0, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83761.4]
output auto_out_sync_0 // @[:freechips.rocketchip.system.LowRiscConfig.fir@83761.4]
);
assign auto_out_sync_0 = auto_in_0; // @[LazyModule.scala 173:49:freechips.rocketchip.system.LowRiscConfig.fir@83770.4]
endmodule
module TLMonitor_35( // @[:freechips.rocketchip.system.LowRiscConfig.fir@83781.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83782.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83783.4]
input io_in_a_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_a_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input [2:0] io_in_a_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input [8:0] io_in_a_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input [3:0] io_in_a_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_d_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_d_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input [2:0] io_in_d_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input [1:0] io_in_d_bits_param, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input [1:0] io_in_d_bits_size, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_d_bits_source, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_d_bits_sink, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_d_bits_denied, // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
input io_in_d_bits_corrupt // @[:freechips.rocketchip.system.LowRiscConfig.fir@83784.4]
);
wire [31:0] plusarg_reader_out; // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@85141.4]
wire [4:0] _T_29; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@83804.6]
wire [1:0] _T_30; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@83805.6]
wire [1:0] _T_31; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@83806.6]
wire [8:0] _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@83807.6]
wire [8:0] _T_32; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@83807.6]
wire _T_33; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@83808.6]
wire [1:0] _T_36; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@83811.6]
wire [9:0] _T_70; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83845.6]
wire _T_78; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@83857.6]
wire [9:0] _T_82; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83862.8]
wire [9:0] _T_83; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83863.8]
wire _T_84; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83864.8]
wire [8:0] _T_85; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83865.8]
wire [9:0] _T_86; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83866.8]
wire [9:0] _T_87; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83867.8]
wire [9:0] _T_88; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83868.8]
wire _T_89; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83869.8]
wire [8:0] _T_90; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83870.8]
wire [9:0] _T_91; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83871.8]
wire [9:0] _T_92; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83872.8]
wire [9:0] _T_93; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83873.8]
wire _T_94; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83874.8]
wire [8:0] _T_95; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83875.8]
wire [9:0] _T_96; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83876.8]
wire [9:0] _T_97; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83877.8]
wire [9:0] _T_98; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83878.8]
wire _T_99; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83879.8]
wire [8:0] _T_100; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83880.8]
wire [9:0] _T_101; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83881.8]
wire [9:0] _T_102; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83882.8]
wire [9:0] _T_103; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83883.8]
wire _T_104; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83884.8]
wire [8:0] _T_105; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83885.8]
wire [9:0] _T_106; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83886.8]
wire [9:0] _T_107; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83887.8]
wire [9:0] _T_108; // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83888.8]
wire _T_109; // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83889.8]
wire _T_110; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83890.8]
wire _T_111; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83891.8]
wire _T_112; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83892.8]
wire _T_113; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83893.8]
wire _T_114; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83894.8]
wire _T_119; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@83899.8]
wire _T_131; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@83927.8]
wire _T_132; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@83928.8]
wire [3:0] _T_137; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@83941.8]
wire _T_138; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@83942.8]
wire _T_140; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@83944.8]
wire _T_141; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@83945.8]
wire _T_146; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@83959.6]
wire _T_218; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@84069.6]
wire _T_261; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84113.8]
wire _T_262; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84114.8]
wire _T_273; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@84141.8]
wire _T_275; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@84143.8]
wire _T_276; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@84144.8]
wire _T_281; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@84158.6]
wire _T_340; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@84239.6]
wire _T_401; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@84322.6]
wire _T_457; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@84400.6]
wire _T_513; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@84478.6]
wire _T_569; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@84558.6]
wire _T_571; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@84560.6]
wire _T_572; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@84561.6]
wire _T_573; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@84566.6]
wire _T_582; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@84571.6]
wire _T_584; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84574.8]
wire _T_585; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84575.8]
wire _T_586; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@84580.8]
wire _T_588; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@84582.8]
wire _T_589; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@84583.8]
wire _T_590; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@84588.8]
wire _T_592; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@84590.8]
wire _T_593; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@84591.8]
wire _T_594; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@84596.8]
wire _T_596; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@84598.8]
wire _T_597; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@84599.8]
wire _T_598; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@84604.8]
wire _T_600; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@84606.8]
wire _T_601; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@84607.8]
wire _T_602; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@84613.6]
wire _T_613; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@84637.8]
wire _T_615; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@84639.8]
wire _T_616; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@84640.8]
wire _T_617; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@84645.8]
wire _T_619; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@84647.8]
wire _T_620; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@84648.8]
wire _T_630; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@84671.6]
wire _T_650; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@84712.8]
wire _T_652; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@84714.8]
wire _T_653; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@84715.8]
wire _T_659; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@84730.6]
wire _T_676; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@84765.6]
wire _T_694; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@84801.6]
wire _T_723; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@84861.4]
reg _T_733; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@84870.4]
reg [31:0] _RAND_0;
wire [1:0] _T_734; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84871.4]
wire [1:0] _T_735; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84872.4]
wire _T_736; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84873.4]
wire _T_737; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@84874.4]
reg [2:0] _T_746; // @[Monitor.scala 349:22:freechips.rocketchip.system.LowRiscConfig.fir@84885.4]
reg [31:0] _RAND_1;
reg [8:0] _T_754; // @[Monitor.scala 353:22:freechips.rocketchip.system.LowRiscConfig.fir@84889.4]
reg [31:0] _RAND_2;
wire _T_755; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@84890.4]
wire _T_756; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@84891.4]
wire _T_757; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@84893.6]
wire _T_759; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@84895.6]
wire _T_760; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@84896.6]
wire _T_773; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@84925.6]
wire _T_775; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@84927.6]
wire _T_776; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@84928.6]
wire _T_778; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@84935.4]
wire _T_779; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@84943.4]
reg _T_788; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@84951.4]
reg [31:0] _RAND_3;
wire [1:0] _T_789; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84952.4]
wire [1:0] _T_790; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84953.4]
wire _T_791; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84954.4]
wire _T_792; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@84955.4]
reg [2:0] _T_801; // @[Monitor.scala 418:22:freechips.rocketchip.system.LowRiscConfig.fir@84966.4]
reg [31:0] _RAND_4;
reg [1:0] _T_803; // @[Monitor.scala 419:22:freechips.rocketchip.system.LowRiscConfig.fir@84967.4]
reg [31:0] _RAND_5;
reg [1:0] _T_805; // @[Monitor.scala 420:22:freechips.rocketchip.system.LowRiscConfig.fir@84968.4]
reg [31:0] _RAND_6;
reg _T_807; // @[Monitor.scala 421:22:freechips.rocketchip.system.LowRiscConfig.fir@84969.4]
reg [31:0] _RAND_7;
reg _T_809; // @[Monitor.scala 422:22:freechips.rocketchip.system.LowRiscConfig.fir@84970.4]
reg [31:0] _RAND_8;
reg _T_811; // @[Monitor.scala 423:22:freechips.rocketchip.system.LowRiscConfig.fir@84971.4]
reg [31:0] _RAND_9;
wire _T_812; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@84972.4]
wire _T_813; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@84973.4]
wire _T_814; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@84975.6]
wire _T_816; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@84977.6]
wire _T_817; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@84978.6]
wire _T_818; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@84983.6]
wire _T_820; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@84985.6]
wire _T_821; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@84986.6]
wire _T_822; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@84991.6]
wire _T_824; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@84993.6]
wire _T_825; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@84994.6]
wire _T_826; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@84999.6]
wire _T_828; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@85001.6]
wire _T_829; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@85002.6]
wire _T_830; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@85007.6]
wire _T_832; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@85009.6]
wire _T_833; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@85010.6]
wire _T_834; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@85015.6]
wire _T_836; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@85017.6]
wire _T_837; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@85018.6]
wire _T_839; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@85025.4]
reg _T_841; // @[Monitor.scala 452:27:freechips.rocketchip.system.LowRiscConfig.fir@85034.4]
reg [31:0] _RAND_10;
reg _T_852; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@85044.4]
reg [31:0] _RAND_11;
wire [1:0] _T_853; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85045.4]
wire [1:0] _T_854; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85046.4]
wire _T_855; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85047.4]
wire _T_856; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@85048.4]
reg _T_873; // @[Edges.scala 229:27:freechips.rocketchip.system.LowRiscConfig.fir@85067.4]
reg [31:0] _RAND_12;
wire [1:0] _T_874; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85068.4]
wire [1:0] _T_875; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85069.4]
wire _T_876; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85070.4]
wire _T_877; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@85071.4]
wire _T_888; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@85086.4]
wire _T_891; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@85091.6]
wire _T_893; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@85093.6]
wire _T_895; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@85095.6]
wire _T_896; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@85096.6]
wire [1:0] _GEN_15; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@85088.4]
wire _T_901; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@85107.4]
wire _T_903; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@85109.4]
wire _T_904; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@85110.4]
wire [1:0] _T_905; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@85112.6]
wire _T_886; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85082.4 :freechips.rocketchip.system.LowRiscConfig.fir@85084.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@85090.6]
wire _T_906; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@85114.6]
wire _T_907; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@85115.6]
wire _T_910; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@85118.6]
wire _T_911; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@85119.6]
wire [1:0] _GEN_16; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@85111.4]
wire _T_898; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85102.4 :freechips.rocketchip.system.LowRiscConfig.fir@85104.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@85113.6]
wire _T_912; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@85125.4]
wire _T_914; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@85127.4]
wire _T_915; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@85128.4]
wire _T_917; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@85130.4]
wire _T_918; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@85131.4]
wire _T_919; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@85136.4]
wire _T_920; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@85137.4]
wire _T_921; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@85138.4]
reg [31:0] _T_923; // @[Monitor.scala 476:27:freechips.rocketchip.system.LowRiscConfig.fir@85140.4]
reg [31:0] _RAND_13;
wire _T_925; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@85144.4]
wire _T_926; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@85145.4]
wire _T_927; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@85146.4]
wire _T_928; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@85147.4]
wire _T_929; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@85148.4]
wire _T_931; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@85150.4]
wire _T_932; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@85151.4]
wire [31:0] _T_934; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@85157.4]
wire _T_937; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@85161.4]
wire _GEN_19; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@83901.10]
wire _GEN_27; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@84003.10]
wire _GEN_37; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84116.10]
wire _GEN_43; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@84205.10]
wire _GEN_49; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@84286.10]
wire _GEN_53; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@84366.10]
wire _GEN_59; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@84444.10]
wire _GEN_65; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@84522.10]
wire _GEN_71; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84577.10]
wire _GEN_81; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@84619.10]
wire _GEN_95; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@84677.10]
wire _GEN_109; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@84736.10]
wire _GEN_117; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@84771.10]
wire _GEN_125; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@84807.10]
plusarg_reader #(.FORMAT("tilelink_timeout=%d"), .DEFAULT(0)) plusarg_reader ( // @[PlusArg.scala 42:11:freechips.rocketchip.system.LowRiscConfig.fir@85141.4]
.out(plusarg_reader_out)
);
assign _T_29 = 5'h3 << 2'h2; // @[package.scala 185:77:freechips.rocketchip.system.LowRiscConfig.fir@83804.6]
assign _T_30 = _T_29[1:0]; // @[package.scala 185:82:freechips.rocketchip.system.LowRiscConfig.fir@83805.6]
assign _T_31 = ~ _T_30; // @[package.scala 185:46:freechips.rocketchip.system.LowRiscConfig.fir@83806.6]
assign _GEN_18 = {{7'd0}, _T_31}; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@83807.6]
assign _T_32 = io_in_a_bits_address & _GEN_18; // @[Edges.scala 21:16:freechips.rocketchip.system.LowRiscConfig.fir@83807.6]
assign _T_33 = _T_32 == 9'h0; // @[Edges.scala 21:24:freechips.rocketchip.system.LowRiscConfig.fir@83808.6]
assign _T_36 = 2'h1 << 1'h0; // @[OneHot.scala 52:12:freechips.rocketchip.system.LowRiscConfig.fir@83811.6]
assign _T_70 = {1'b0,$signed(io_in_a_bits_address)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83845.6]
assign _T_78 = io_in_a_bits_opcode == 3'h6; // @[Monitor.scala 48:25:freechips.rocketchip.system.LowRiscConfig.fir@83857.6]
assign _T_82 = $signed(_T_70) & $signed(-10'sh40); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83862.8]
assign _T_83 = $signed(_T_82); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83863.8]
assign _T_84 = $signed(_T_83) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83864.8]
assign _T_85 = io_in_a_bits_address ^ 9'h44; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83865.8]
assign _T_86 = {1'b0,$signed(_T_85)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83866.8]
assign _T_87 = $signed(_T_86) & $signed(-10'sh4); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83867.8]
assign _T_88 = $signed(_T_87); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83868.8]
assign _T_89 = $signed(_T_88) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83869.8]
assign _T_90 = io_in_a_bits_address ^ 9'h48; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83870.8]
assign _T_91 = {1'b0,$signed(_T_90)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83871.8]
assign _T_92 = $signed(_T_91) & $signed(-10'sh18); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83872.8]
assign _T_93 = $signed(_T_92); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83873.8]
assign _T_94 = $signed(_T_93) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83874.8]
assign _T_95 = io_in_a_bits_address ^ 9'h60; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83875.8]
assign _T_96 = {1'b0,$signed(_T_95)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83876.8]
assign _T_97 = $signed(_T_96) & $signed(-10'sh20); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83877.8]
assign _T_98 = $signed(_T_97); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83878.8]
assign _T_99 = $signed(_T_98) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83879.8]
assign _T_100 = io_in_a_bits_address ^ 9'h80; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83880.8]
assign _T_101 = {1'b0,$signed(_T_100)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83881.8]
assign _T_102 = $signed(_T_101) & $signed(-10'sh80); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83882.8]
assign _T_103 = $signed(_T_102); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83883.8]
assign _T_104 = $signed(_T_103) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83884.8]
assign _T_105 = io_in_a_bits_address ^ 9'h100; // @[Parameters.scala 121:31:freechips.rocketchip.system.LowRiscConfig.fir@83885.8]
assign _T_106 = {1'b0,$signed(_T_105)}; // @[Parameters.scala 121:49:freechips.rocketchip.system.LowRiscConfig.fir@83886.8]
assign _T_107 = $signed(_T_106) & $signed(-10'sh100); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83887.8]
assign _T_108 = $signed(_T_107); // @[Parameters.scala 121:52:freechips.rocketchip.system.LowRiscConfig.fir@83888.8]
assign _T_109 = $signed(_T_108) == $signed(10'sh0); // @[Parameters.scala 121:67:freechips.rocketchip.system.LowRiscConfig.fir@83889.8]
assign _T_110 = _T_84 | _T_89; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83890.8]
assign _T_111 = _T_110 | _T_94; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83891.8]
assign _T_112 = _T_111 | _T_99; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83892.8]
assign _T_113 = _T_112 | _T_104; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83893.8]
assign _T_114 = _T_113 | _T_109; // @[Parameters.scala 172:42:freechips.rocketchip.system.LowRiscConfig.fir@83894.8]
assign _T_119 = reset == 1'h0; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@83899.8]
assign _T_131 = _T_33 | reset; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@83927.8]
assign _T_132 = _T_131 == 1'h0; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@83928.8]
assign _T_137 = ~ io_in_a_bits_mask; // @[Monitor.scala 55:15:freechips.rocketchip.system.LowRiscConfig.fir@83941.8]
assign _T_138 = _T_137 == 4'h0; // @[Monitor.scala 55:28:freechips.rocketchip.system.LowRiscConfig.fir@83942.8]
assign _T_140 = _T_138 | reset; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@83944.8]
assign _T_141 = _T_140 == 1'h0; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@83945.8]
assign _T_146 = io_in_a_bits_opcode == 3'h7; // @[Monitor.scala 59:25:freechips.rocketchip.system.LowRiscConfig.fir@83959.6]
assign _T_218 = io_in_a_bits_opcode == 3'h4; // @[Monitor.scala 71:25:freechips.rocketchip.system.LowRiscConfig.fir@84069.6]
assign _T_261 = _T_114 | reset; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84113.8]
assign _T_262 = _T_261 == 1'h0; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84114.8]
assign _T_273 = io_in_a_bits_mask == 4'hf; // @[Monitor.scala 76:27:freechips.rocketchip.system.LowRiscConfig.fir@84141.8]
assign _T_275 = _T_273 | reset; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@84143.8]
assign _T_276 = _T_275 == 1'h0; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@84144.8]
assign _T_281 = io_in_a_bits_opcode == 3'h0; // @[Monitor.scala 80:25:freechips.rocketchip.system.LowRiscConfig.fir@84158.6]
assign _T_340 = io_in_a_bits_opcode == 3'h1; // @[Monitor.scala 88:25:freechips.rocketchip.system.LowRiscConfig.fir@84239.6]
assign _T_401 = io_in_a_bits_opcode == 3'h2; // @[Monitor.scala 96:25:freechips.rocketchip.system.LowRiscConfig.fir@84322.6]
assign _T_457 = io_in_a_bits_opcode == 3'h3; // @[Monitor.scala 104:25:freechips.rocketchip.system.LowRiscConfig.fir@84400.6]
assign _T_513 = io_in_a_bits_opcode == 3'h5; // @[Monitor.scala 112:25:freechips.rocketchip.system.LowRiscConfig.fir@84478.6]
assign _T_569 = io_in_d_bits_opcode <= 3'h6; // @[Bundles.scala 43:24:freechips.rocketchip.system.LowRiscConfig.fir@84558.6]
assign _T_571 = _T_569 | reset; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@84560.6]
assign _T_572 = _T_571 == 1'h0; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@84561.6]
assign _T_573 = io_in_d_bits_source == 1'h0; // @[Parameters.scala 44:9:freechips.rocketchip.system.LowRiscConfig.fir@84566.6]
assign _T_582 = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala 275:25:freechips.rocketchip.system.LowRiscConfig.fir@84571.6]
assign _T_584 = _T_573 | reset; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84574.8]
assign _T_585 = _T_584 == 1'h0; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84575.8]
assign _T_586 = io_in_d_bits_size >= 2'h2; // @[Monitor.scala 277:27:freechips.rocketchip.system.LowRiscConfig.fir@84580.8]
assign _T_588 = _T_586 | reset; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@84582.8]
assign _T_589 = _T_588 == 1'h0; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@84583.8]
assign _T_590 = io_in_d_bits_param == 2'h0; // @[Monitor.scala 278:28:freechips.rocketchip.system.LowRiscConfig.fir@84588.8]
assign _T_592 = _T_590 | reset; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@84590.8]
assign _T_593 = _T_592 == 1'h0; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@84591.8]
assign _T_594 = io_in_d_bits_corrupt == 1'h0; // @[Monitor.scala 279:15:freechips.rocketchip.system.LowRiscConfig.fir@84596.8]
assign _T_596 = _T_594 | reset; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@84598.8]
assign _T_597 = _T_596 == 1'h0; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@84599.8]
assign _T_598 = io_in_d_bits_denied == 1'h0; // @[Monitor.scala 280:15:freechips.rocketchip.system.LowRiscConfig.fir@84604.8]
assign _T_600 = _T_598 | reset; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@84606.8]
assign _T_601 = _T_600 == 1'h0; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@84607.8]
assign _T_602 = io_in_d_bits_opcode == 3'h4; // @[Monitor.scala 283:25:freechips.rocketchip.system.LowRiscConfig.fir@84613.6]
assign _T_613 = io_in_d_bits_param <= 2'h2; // @[Bundles.scala 103:26:freechips.rocketchip.system.LowRiscConfig.fir@84637.8]
assign _T_615 = _T_613 | reset; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@84639.8]
assign _T_616 = _T_615 == 1'h0; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@84640.8]
assign _T_617 = io_in_d_bits_param != 2'h2; // @[Monitor.scala 288:28:freechips.rocketchip.system.LowRiscConfig.fir@84645.8]
assign _T_619 = _T_617 | reset; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@84647.8]
assign _T_620 = _T_619 == 1'h0; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@84648.8]
assign _T_630 = io_in_d_bits_opcode == 3'h5; // @[Monitor.scala 293:25:freechips.rocketchip.system.LowRiscConfig.fir@84671.6]
assign _T_650 = _T_598 | io_in_d_bits_corrupt; // @[Monitor.scala 299:30:freechips.rocketchip.system.LowRiscConfig.fir@84712.8]
assign _T_652 = _T_650 | reset; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@84714.8]
assign _T_653 = _T_652 == 1'h0; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@84715.8]
assign _T_659 = io_in_d_bits_opcode == 3'h0; // @[Monitor.scala 303:25:freechips.rocketchip.system.LowRiscConfig.fir@84730.6]
assign _T_676 = io_in_d_bits_opcode == 3'h1; // @[Monitor.scala 311:25:freechips.rocketchip.system.LowRiscConfig.fir@84765.6]
assign _T_694 = io_in_d_bits_opcode == 3'h2; // @[Monitor.scala 319:25:freechips.rocketchip.system.LowRiscConfig.fir@84801.6]
assign _T_723 = io_in_a_ready & io_in_a_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@84861.4]
assign _T_734 = _T_733 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84871.4]
assign _T_735 = $unsigned(_T_734); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84872.4]
assign _T_736 = _T_735[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84873.4]
assign _T_737 = _T_733 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@84874.4]
assign _T_755 = _T_737 == 1'h0; // @[Monitor.scala 354:22:freechips.rocketchip.system.LowRiscConfig.fir@84890.4]
assign _T_756 = io_in_a_valid & _T_755; // @[Monitor.scala 354:19:freechips.rocketchip.system.LowRiscConfig.fir@84891.4]
assign _T_757 = io_in_a_bits_opcode == _T_746; // @[Monitor.scala 355:29:freechips.rocketchip.system.LowRiscConfig.fir@84893.6]
assign _T_759 = _T_757 | reset; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@84895.6]
assign _T_760 = _T_759 == 1'h0; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@84896.6]
assign _T_773 = io_in_a_bits_address == _T_754; // @[Monitor.scala 359:29:freechips.rocketchip.system.LowRiscConfig.fir@84925.6]
assign _T_775 = _T_773 | reset; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@84927.6]
assign _T_776 = _T_775 == 1'h0; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@84928.6]
assign _T_778 = _T_723 & _T_737; // @[Monitor.scala 361:20:freechips.rocketchip.system.LowRiscConfig.fir@84935.4]
assign _T_779 = io_in_d_ready & io_in_d_valid; // @[Bundles.scala 277:22:freechips.rocketchip.system.LowRiscConfig.fir@84943.4]
assign _T_789 = _T_788 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84952.4]
assign _T_790 = $unsigned(_T_789); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84953.4]
assign _T_791 = _T_790[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@84954.4]
assign _T_792 = _T_788 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@84955.4]
assign _T_812 = _T_792 == 1'h0; // @[Monitor.scala 424:22:freechips.rocketchip.system.LowRiscConfig.fir@84972.4]
assign _T_813 = io_in_d_valid & _T_812; // @[Monitor.scala 424:19:freechips.rocketchip.system.LowRiscConfig.fir@84973.4]
assign _T_814 = io_in_d_bits_opcode == _T_801; // @[Monitor.scala 425:29:freechips.rocketchip.system.LowRiscConfig.fir@84975.6]
assign _T_816 = _T_814 | reset; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@84977.6]
assign _T_817 = _T_816 == 1'h0; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@84978.6]
assign _T_818 = io_in_d_bits_param == _T_803; // @[Monitor.scala 426:29:freechips.rocketchip.system.LowRiscConfig.fir@84983.6]
assign _T_820 = _T_818 | reset; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@84985.6]
assign _T_821 = _T_820 == 1'h0; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@84986.6]
assign _T_822 = io_in_d_bits_size == _T_805; // @[Monitor.scala 427:29:freechips.rocketchip.system.LowRiscConfig.fir@84991.6]
assign _T_824 = _T_822 | reset; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@84993.6]
assign _T_825 = _T_824 == 1'h0; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@84994.6]
assign _T_826 = io_in_d_bits_source == _T_807; // @[Monitor.scala 428:29:freechips.rocketchip.system.LowRiscConfig.fir@84999.6]
assign _T_828 = _T_826 | reset; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@85001.6]
assign _T_829 = _T_828 == 1'h0; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@85002.6]
assign _T_830 = io_in_d_bits_sink == _T_809; // @[Monitor.scala 429:29:freechips.rocketchip.system.LowRiscConfig.fir@85007.6]
assign _T_832 = _T_830 | reset; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@85009.6]
assign _T_833 = _T_832 == 1'h0; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@85010.6]
assign _T_834 = io_in_d_bits_denied == _T_811; // @[Monitor.scala 430:29:freechips.rocketchip.system.LowRiscConfig.fir@85015.6]
assign _T_836 = _T_834 | reset; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@85017.6]
assign _T_837 = _T_836 == 1'h0; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@85018.6]
assign _T_839 = _T_779 & _T_792; // @[Monitor.scala 432:20:freechips.rocketchip.system.LowRiscConfig.fir@85025.4]
assign _T_853 = _T_852 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85045.4]
assign _T_854 = $unsigned(_T_853); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85046.4]
assign _T_855 = _T_854[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85047.4]
assign _T_856 = _T_852 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@85048.4]
assign _T_874 = _T_873 - 1'h1; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85068.4]
assign _T_875 = $unsigned(_T_874); // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85069.4]
assign _T_876 = _T_875[0:0]; // @[Edges.scala 230:28:freechips.rocketchip.system.LowRiscConfig.fir@85070.4]
assign _T_877 = _T_873 == 1'h0; // @[Edges.scala 231:25:freechips.rocketchip.system.LowRiscConfig.fir@85071.4]
assign _T_888 = _T_723 & _T_856; // @[Monitor.scala 458:27:freechips.rocketchip.system.LowRiscConfig.fir@85086.4]
assign _T_891 = _T_841 >> 1'h0; // @[Monitor.scala 460:23:freechips.rocketchip.system.LowRiscConfig.fir@85091.6]
assign _T_893 = _T_891 == 1'h0; // @[Monitor.scala 460:14:freechips.rocketchip.system.LowRiscConfig.fir@85093.6]
assign _T_895 = _T_893 | reset; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@85095.6]
assign _T_896 = _T_895 == 1'h0; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@85096.6]
assign _GEN_15 = _T_888 ? _T_36 : 2'h0; // @[Monitor.scala 458:72:freechips.rocketchip.system.LowRiscConfig.fir@85088.4]
assign _T_901 = _T_779 & _T_877; // @[Monitor.scala 465:27:freechips.rocketchip.system.LowRiscConfig.fir@85107.4]
assign _T_903 = _T_582 == 1'h0; // @[Monitor.scala 465:75:freechips.rocketchip.system.LowRiscConfig.fir@85109.4]
assign _T_904 = _T_901 & _T_903; // @[Monitor.scala 465:72:freechips.rocketchip.system.LowRiscConfig.fir@85110.4]
assign _T_905 = 2'h1 << io_in_d_bits_source; // @[OneHot.scala 45:35:freechips.rocketchip.system.LowRiscConfig.fir@85112.6]
assign _T_886 = _GEN_15[0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85082.4 :freechips.rocketchip.system.LowRiscConfig.fir@85084.4 Monitor.scala 459:13:freechips.rocketchip.system.LowRiscConfig.fir@85090.6]
assign _T_906 = _T_886 | _T_841; // @[Monitor.scala 467:21:freechips.rocketchip.system.LowRiscConfig.fir@85114.6]
assign _T_907 = _T_906 >> io_in_d_bits_source; // @[Monitor.scala 467:32:freechips.rocketchip.system.LowRiscConfig.fir@85115.6]
assign _T_910 = _T_907 | reset; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@85118.6]
assign _T_911 = _T_910 == 1'h0; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@85119.6]
assign _GEN_16 = _T_904 ? _T_905 : 2'h0; // @[Monitor.scala 465:91:freechips.rocketchip.system.LowRiscConfig.fir@85111.4]
assign _T_898 = _GEN_16[0]; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85102.4 :freechips.rocketchip.system.LowRiscConfig.fir@85104.4 Monitor.scala 466:13:freechips.rocketchip.system.LowRiscConfig.fir@85113.6]
assign _T_912 = _T_886 != _T_898; // @[Monitor.scala 471:20:freechips.rocketchip.system.LowRiscConfig.fir@85125.4]
assign _T_914 = _T_886 == 1'h0; // @[Monitor.scala 471:33:freechips.rocketchip.system.LowRiscConfig.fir@85127.4]
assign _T_915 = _T_912 | _T_914; // @[Monitor.scala 471:30:freechips.rocketchip.system.LowRiscConfig.fir@85128.4]
assign _T_917 = _T_915 | reset; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@85130.4]
assign _T_918 = _T_917 == 1'h0; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@85131.4]
assign _T_919 = _T_841 | _T_886; // @[Monitor.scala 474:27:freechips.rocketchip.system.LowRiscConfig.fir@85136.4]
assign _T_920 = ~ _T_898; // @[Monitor.scala 474:38:freechips.rocketchip.system.LowRiscConfig.fir@85137.4]
assign _T_921 = _T_919 & _T_920; // @[Monitor.scala 474:36:freechips.rocketchip.system.LowRiscConfig.fir@85138.4]
assign _T_925 = _T_841 == 1'h0; // @[Monitor.scala 479:13:freechips.rocketchip.system.LowRiscConfig.fir@85144.4]
assign _T_926 = plusarg_reader_out == 32'h0; // @[Monitor.scala 479:36:freechips.rocketchip.system.LowRiscConfig.fir@85145.4]
assign _T_927 = _T_925 | _T_926; // @[Monitor.scala 479:27:freechips.rocketchip.system.LowRiscConfig.fir@85146.4]
assign _T_928 = _T_923 < plusarg_reader_out; // @[Monitor.scala 479:60:freechips.rocketchip.system.LowRiscConfig.fir@85147.4]
assign _T_929 = _T_927 | _T_928; // @[Monitor.scala 479:48:freechips.rocketchip.system.LowRiscConfig.fir@85148.4]
assign _T_931 = _T_929 | reset; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@85150.4]
assign _T_932 = _T_931 == 1'h0; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@85151.4]
assign _T_934 = _T_923 + 32'h1; // @[Monitor.scala 481:26:freechips.rocketchip.system.LowRiscConfig.fir@85157.4]
assign _T_937 = _T_723 | _T_779; // @[Monitor.scala 482:27:freechips.rocketchip.system.LowRiscConfig.fir@85161.4]
assign _GEN_19 = io_in_a_valid & _T_78; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@83901.10]
assign _GEN_27 = io_in_a_valid & _T_146; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@84003.10]
assign _GEN_37 = io_in_a_valid & _T_218; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84116.10]
assign _GEN_43 = io_in_a_valid & _T_281; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@84205.10]
assign _GEN_49 = io_in_a_valid & _T_340; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@84286.10]
assign _GEN_53 = io_in_a_valid & _T_401; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@84366.10]
assign _GEN_59 = io_in_a_valid & _T_457; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@84444.10]
assign _GEN_65 = io_in_a_valid & _T_513; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@84522.10]
assign _GEN_71 = io_in_d_valid & _T_582; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84577.10]
assign _GEN_81 = io_in_d_valid & _T_602; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@84619.10]
assign _GEN_95 = io_in_d_valid & _T_630; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@84677.10]
assign _GEN_109 = io_in_d_valid & _T_659; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@84736.10]
assign _GEN_117 = io_in_d_valid & _T_676; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@84771.10]
assign _GEN_125 = io_in_d_valid & _T_694; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@84807.10]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_733 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_746 = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_754 = _RAND_2[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_788 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_801 = _RAND_4[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_803 = _RAND_5[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_805 = _RAND_6[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_807 = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_809 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_811 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_841 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_852 = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_873 = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_923 = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (reset) begin
_T_733 <= 1'h0;
end else begin
if (_T_723) begin
if (_T_737) begin
_T_733 <= 1'h0;
end else begin
_T_733 <= _T_736;
end
end
end
if (_T_778) begin
_T_746 <= io_in_a_bits_opcode;
end
if (_T_778) begin
_T_754 <= io_in_a_bits_address;
end
if (reset) begin
_T_788 <= 1'h0;
end else begin
if (_T_779) begin
if (_T_792) begin
_T_788 <= 1'h0;
end else begin
_T_788 <= _T_791;
end
end
end
if (_T_839) begin
_T_801 <= io_in_d_bits_opcode;
end
if (_T_839) begin
_T_803 <= io_in_d_bits_param;
end
if (_T_839) begin
_T_805 <= io_in_d_bits_size;
end
if (_T_839) begin
_T_807 <= io_in_d_bits_source;
end
if (_T_839) begin
_T_809 <= io_in_d_bits_sink;
end
if (_T_839) begin
_T_811 <= io_in_d_bits_denied;
end
if (reset) begin
_T_841 <= 1'h0;
end else begin
_T_841 <= _T_921;
end
if (reset) begin
_T_852 <= 1'h0;
end else begin
if (_T_723) begin
if (_T_856) begin
_T_852 <= 1'h0;
end else begin
_T_852 <= _T_855;
end
end
end
if (reset) begin
_T_873 <= 1'h0;
end else begin
if (_T_779) begin
if (_T_877) begin
_T_873 <= 1'h0;
end else begin
_T_873 <= _T_876;
end
end
end
if (reset) begin
_T_923 <= 32'h0;
end else begin
if (_T_937) begin
_T_923 <= 32'h0;
end else begin
_T_923 <= _T_934;
end
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel has invalid opcode (connected at Debug.scala:464:46)\n at Monitor.scala:39 assert (TLMessages.isA(bundle.opcode), \"'A' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@83796.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 39:12:freechips.rocketchip.system.LowRiscConfig.fir@83797.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:46 assert (visible(edge.address(bundle), bundle.source, edge), \"'A' channel carries an address illegal for the specified bank visibility\")\n"); // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@83854.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 46:12:freechips.rocketchip.system.LowRiscConfig.fir@83855.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:49 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquireBlock type unsupported by manager\" + extra)\n"); // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@83901.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_119) begin
$fatal; // @[Monitor.scala 49:14:freechips.rocketchip.system.LowRiscConfig.fir@83902.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at Debug.scala:464:46)\n at Monitor.scala:50 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquireBlock from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@83908.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_119) begin
$fatal; // @[Monitor.scala 50:14:freechips.rocketchip.system.LowRiscConfig.fir@83909.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:51 assert (source_ok, \"'A' channel AcquireBlock carries invalid source ID\" + extra)\n"); // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@83915.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 51:14:freechips.rocketchip.system.LowRiscConfig.fir@83916.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at Debug.scala:464:46)\n at Monitor.scala:52 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquireBlock smaller than a beat\" + extra)\n"); // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@83923.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 52:14:freechips.rocketchip.system.LowRiscConfig.fir@83924.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:53 assert (is_aligned, \"'A' channel AcquireBlock address not aligned to size\" + extra)\n"); // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@83930.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_132) begin
$fatal; // @[Monitor.scala 53:14:freechips.rocketchip.system.LowRiscConfig.fir@83931.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at Debug.scala:464:46)\n at Monitor.scala:54 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquireBlock carries invalid grow param\" + extra)\n"); // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@83938.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 54:14:freechips.rocketchip.system.LowRiscConfig.fir@83939.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_19 & _T_141) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:55 assert (~bundle.mask === UInt(0), \"'A' channel AcquireBlock contains invalid mask\" + extra)\n"); // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@83947.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_19 & _T_141) begin
$fatal; // @[Monitor.scala 55:14:freechips.rocketchip.system.LowRiscConfig.fir@83948.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:56 assert (!bundle.corrupt, \"'A' channel AcquireBlock is corrupt\" + extra)\n"); // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@83955.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 56:14:freechips.rocketchip.system.LowRiscConfig.fir@83956.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:60 assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), \"'A' channel carries AcquirePerm type unsupported by manager\" + extra)\n"); // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@84003.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_119) begin
$fatal; // @[Monitor.scala 60:14:freechips.rocketchip.system.LowRiscConfig.fir@84004.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at Debug.scala:464:46)\n at Monitor.scala:61 assert (edge.client.supportsProbe(edge.source(bundle), bundle.size), \"'A' channel carries AcquirePerm from a client which does not support Probe\" + extra)\n"); // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@84010.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_119) begin
$fatal; // @[Monitor.scala 61:14:freechips.rocketchip.system.LowRiscConfig.fir@84011.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:62 assert (source_ok, \"'A' channel AcquirePerm carries invalid source ID\" + extra)\n"); // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@84017.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 62:14:freechips.rocketchip.system.LowRiscConfig.fir@84018.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at Debug.scala:464:46)\n at Monitor.scala:63 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'A' channel AcquirePerm smaller than a beat\" + extra)\n"); // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@84025.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 63:14:freechips.rocketchip.system.LowRiscConfig.fir@84026.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:64 assert (is_aligned, \"'A' channel AcquirePerm address not aligned to size\" + extra)\n"); // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@84032.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_132) begin
$fatal; // @[Monitor.scala 64:14:freechips.rocketchip.system.LowRiscConfig.fir@84033.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at Debug.scala:464:46)\n at Monitor.scala:65 assert (TLPermissions.isGrow(bundle.param), \"'A' channel AcquirePerm carries invalid grow param\" + extra)\n"); // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@84040.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 65:14:freechips.rocketchip.system.LowRiscConfig.fir@84041.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at Debug.scala:464:46)\n at Monitor.scala:66 assert (bundle.param =/= TLPermissions.NtoB, \"'A' channel AcquirePerm requests NtoB\" + extra)\n"); // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@84048.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_119) begin
$fatal; // @[Monitor.scala 66:14:freechips.rocketchip.system.LowRiscConfig.fir@84049.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_27 & _T_141) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:67 assert (~bundle.mask === UInt(0), \"'A' channel AcquirePerm contains invalid mask\" + extra)\n"); // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@84057.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_27 & _T_141) begin
$fatal; // @[Monitor.scala 67:14:freechips.rocketchip.system.LowRiscConfig.fir@84058.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:68 assert (!bundle.corrupt, \"'A' channel AcquirePerm is corrupt\" + extra)\n"); // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@84065.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 68:14:freechips.rocketchip.system.LowRiscConfig.fir@84066.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_262) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Get type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:72 assert (edge.manager.supportsGetSafe(edge.address(bundle), bundle.size), \"'A' channel carries Get type unsupported by manager\" + extra)\n"); // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84116.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_262) begin
$fatal; // @[Monitor.scala 72:14:freechips.rocketchip.system.LowRiscConfig.fir@84117.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:73 assert (source_ok, \"'A' channel Get carries invalid source ID\" + extra)\n"); // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@84123.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 73:14:freechips.rocketchip.system.LowRiscConfig.fir@84124.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:74 assert (is_aligned, \"'A' channel Get address not aligned to size\" + extra)\n"); // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@84130.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_132) begin
$fatal; // @[Monitor.scala 74:14:freechips.rocketchip.system.LowRiscConfig.fir@84131.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:75 assert (bundle.param === UInt(0), \"'A' channel Get carries invalid param\" + extra)\n"); // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@84138.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 75:14:freechips.rocketchip.system.LowRiscConfig.fir@84139.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_37 & _T_276) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:76 assert (bundle.mask === mask, \"'A' channel Get contains invalid mask\" + extra)\n"); // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@84146.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_37 & _T_276) begin
$fatal; // @[Monitor.scala 76:14:freechips.rocketchip.system.LowRiscConfig.fir@84147.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Get is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:77 assert (!bundle.corrupt, \"'A' channel Get is corrupt\" + extra)\n"); // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@84154.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 77:14:freechips.rocketchip.system.LowRiscConfig.fir@84155.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_262) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutFull type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:81 assert (edge.manager.supportsPutFullSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutFull type unsupported by manager\" + extra)\n"); // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@84205.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_262) begin
$fatal; // @[Monitor.scala 81:14:freechips.rocketchip.system.LowRiscConfig.fir@84206.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:82 assert (source_ok, \"'A' channel PutFull carries invalid source ID\" + extra)\n"); // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@84212.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 82:14:freechips.rocketchip.system.LowRiscConfig.fir@84213.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:83 assert (is_aligned, \"'A' channel PutFull address not aligned to size\" + extra)\n"); // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@84219.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_132) begin
$fatal; // @[Monitor.scala 83:14:freechips.rocketchip.system.LowRiscConfig.fir@84220.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:84 assert (bundle.param === UInt(0), \"'A' channel PutFull carries invalid param\" + extra)\n"); // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@84227.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 84:14:freechips.rocketchip.system.LowRiscConfig.fir@84228.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_43 & _T_276) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutFull contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:85 assert (bundle.mask === mask, \"'A' channel PutFull contains invalid mask\" + extra)\n"); // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@84235.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_43 & _T_276) begin
$fatal; // @[Monitor.scala 85:14:freechips.rocketchip.system.LowRiscConfig.fir@84236.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_262) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries PutPartial type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:89 assert (edge.manager.supportsPutPartialSafe(edge.address(bundle), bundle.size), \"'A' channel carries PutPartial type unsupported by manager\" + extra)\n"); // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@84286.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_262) begin
$fatal; // @[Monitor.scala 89:14:freechips.rocketchip.system.LowRiscConfig.fir@84287.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:90 assert (source_ok, \"'A' channel PutPartial carries invalid source ID\" + extra)\n"); // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@84293.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 90:14:freechips.rocketchip.system.LowRiscConfig.fir@84294.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_49 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:91 assert (is_aligned, \"'A' channel PutPartial address not aligned to size\" + extra)\n"); // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@84300.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_49 & _T_132) begin
$fatal; // @[Monitor.scala 91:14:freechips.rocketchip.system.LowRiscConfig.fir@84301.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:92 assert (bundle.param === UInt(0), \"'A' channel PutPartial carries invalid param\" + extra)\n"); // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@84308.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 92:14:freechips.rocketchip.system.LowRiscConfig.fir@84309.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:93 assert ((bundle.mask & ~mask) === UInt(0), \"'A' channel PutPartial contains invalid mask\" + extra)\n"); // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@84318.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 93:14:freechips.rocketchip.system.LowRiscConfig.fir@84319.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Arithmetic type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:97 assert (edge.manager.supportsArithmeticSafe(edge.address(bundle), bundle.size), \"'A' channel carries Arithmetic type unsupported by manager\" + extra)\n"); // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@84366.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_119) begin
$fatal; // @[Monitor.scala 97:14:freechips.rocketchip.system.LowRiscConfig.fir@84367.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:98 assert (source_ok, \"'A' channel Arithmetic carries invalid source ID\" + extra)\n"); // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@84373.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 98:14:freechips.rocketchip.system.LowRiscConfig.fir@84374.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:99 assert (is_aligned, \"'A' channel Arithmetic address not aligned to size\" + extra)\n"); // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@84380.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_132) begin
$fatal; // @[Monitor.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@84381.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at Debug.scala:464:46)\n at Monitor.scala:100 assert (TLAtomics.isArithmetic(bundle.param), \"'A' channel Arithmetic carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@84388.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 100:14:freechips.rocketchip.system.LowRiscConfig.fir@84389.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_53 & _T_276) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:101 assert (bundle.mask === mask, \"'A' channel Arithmetic contains invalid mask\" + extra)\n"); // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@84396.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_53 & _T_276) begin
$fatal; // @[Monitor.scala 101:14:freechips.rocketchip.system.LowRiscConfig.fir@84397.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Logical type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:105 assert (edge.manager.supportsLogicalSafe(edge.address(bundle), bundle.size), \"'A' channel carries Logical type unsupported by manager\" + extra)\n"); // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@84444.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_119) begin
$fatal; // @[Monitor.scala 105:14:freechips.rocketchip.system.LowRiscConfig.fir@84445.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:106 assert (source_ok, \"'A' channel Logical carries invalid source ID\" + extra)\n"); // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@84451.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 106:14:freechips.rocketchip.system.LowRiscConfig.fir@84452.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:107 assert (is_aligned, \"'A' channel Logical address not aligned to size\" + extra)\n"); // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@84458.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_132) begin
$fatal; // @[Monitor.scala 107:14:freechips.rocketchip.system.LowRiscConfig.fir@84459.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at Debug.scala:464:46)\n at Monitor.scala:108 assert (TLAtomics.isLogical(bundle.param), \"'A' channel Logical carries invalid opcode param\" + extra)\n"); // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@84466.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 108:14:freechips.rocketchip.system.LowRiscConfig.fir@84467.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_59 & _T_276) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Logical contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:109 assert (bundle.mask === mask, \"'A' channel Logical contains invalid mask\" + extra)\n"); // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@84474.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_59 & _T_276) begin
$fatal; // @[Monitor.scala 109:14:freechips.rocketchip.system.LowRiscConfig.fir@84475.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel carries Hint type unsupported by manager (connected at Debug.scala:464:46)\n at Monitor.scala:113 assert (edge.manager.supportsHintSafe(edge.address(bundle), bundle.size), \"'A' channel carries Hint type unsupported by manager\" + extra)\n"); // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@84522.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_119) begin
$fatal; // @[Monitor.scala 113:14:freechips.rocketchip.system.LowRiscConfig.fir@84523.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:114 assert (source_ok, \"'A' channel Hint carries invalid source ID\" + extra)\n"); // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@84529.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 114:14:freechips.rocketchip.system.LowRiscConfig.fir@84530.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_132) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint address not aligned to size (connected at Debug.scala:464:46)\n at Monitor.scala:115 assert (is_aligned, \"'A' channel Hint address not aligned to size\" + extra)\n"); // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@84536.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_132) begin
$fatal; // @[Monitor.scala 115:14:freechips.rocketchip.system.LowRiscConfig.fir@84537.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_65 & _T_276) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint contains invalid mask (connected at Debug.scala:464:46)\n at Monitor.scala:116 assert (bundle.mask === mask, \"'A' channel Hint contains invalid mask\" + extra)\n"); // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@84544.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_65 & _T_276) begin
$fatal; // @[Monitor.scala 116:14:freechips.rocketchip.system.LowRiscConfig.fir@84545.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel Hint is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:117 assert (!bundle.corrupt, \"'A' channel Hint is corrupt\" + extra)\n"); // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@84552.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 117:14:freechips.rocketchip.system.LowRiscConfig.fir@84553.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (io_in_d_valid & _T_572) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel has invalid opcode (connected at Debug.scala:464:46)\n at Monitor.scala:268 assert (TLMessages.isD(bundle.opcode), \"'D' channel has invalid opcode\" + extra)\n"); // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@84563.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (io_in_d_valid & _T_572) begin
$fatal; // @[Monitor.scala 268:12:freechips.rocketchip.system.LowRiscConfig.fir@84564.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:276 assert (source_ok, \"'D' channel ReleaseAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84577.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_585) begin
$fatal; // @[Monitor.scala 276:14:freechips.rocketchip.system.LowRiscConfig.fir@84578.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_589) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at Debug.scala:464:46)\n at Monitor.scala:277 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel ReleaseAck smaller than a beat\" + extra)\n"); // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@84585.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_589) begin
$fatal; // @[Monitor.scala 277:14:freechips.rocketchip.system.LowRiscConfig.fir@84586.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:278 assert (bundle.param === UInt(0), \"'D' channel ReleaseeAck carries invalid param\" + extra)\n"); // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@84593.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_593) begin
$fatal; // @[Monitor.scala 278:14:freechips.rocketchip.system.LowRiscConfig.fir@84594.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_597) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:279 assert (!bundle.corrupt, \"'D' channel ReleaseAck is corrupt\" + extra)\n"); // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@84601.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_597) begin
$fatal; // @[Monitor.scala 279:14:freechips.rocketchip.system.LowRiscConfig.fir@84602.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_71 & _T_601) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel ReleaseAck is denied (connected at Debug.scala:464:46)\n at Monitor.scala:280 assert (!bundle.denied, \"'D' channel ReleaseAck is denied\" + extra)\n"); // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@84609.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_71 & _T_601) begin
$fatal; // @[Monitor.scala 280:14:freechips.rocketchip.system.LowRiscConfig.fir@84610.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:284 assert (source_ok, \"'D' channel Grant carries invalid source ID\" + extra)\n"); // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@84619.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_585) begin
$fatal; // @[Monitor.scala 284:14:freechips.rocketchip.system.LowRiscConfig.fir@84620.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at Debug.scala:464:46)\n at Monitor.scala:285 assert (sink_ok, \"'D' channel Grant carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@84626.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_119) begin
$fatal; // @[Monitor.scala 285:14:freechips.rocketchip.system.LowRiscConfig.fir@84627.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_589) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant smaller than a beat (connected at Debug.scala:464:46)\n at Monitor.scala:286 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel Grant smaller than a beat\" + extra)\n"); // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@84634.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_589) begin
$fatal; // @[Monitor.scala 286:14:freechips.rocketchip.system.LowRiscConfig.fir@84635.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_616) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries invalid cap param (connected at Debug.scala:464:46)\n at Monitor.scala:287 assert (TLPermissions.isCap(bundle.param), \"'D' channel Grant carries invalid cap param\" + extra)\n"); // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@84642.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_616) begin
$fatal; // @[Monitor.scala 287:14:freechips.rocketchip.system.LowRiscConfig.fir@84643.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant carries toN param (connected at Debug.scala:464:46)\n at Monitor.scala:288 assert (bundle.param =/= TLPermissions.toN, \"'D' channel Grant carries toN param\" + extra)\n"); // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@84650.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_620) begin
$fatal; // @[Monitor.scala 288:14:freechips.rocketchip.system.LowRiscConfig.fir@84651.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_597) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:289 assert (!bundle.corrupt, \"'D' channel Grant is corrupt\" + extra)\n"); // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@84658.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_597) begin
$fatal; // @[Monitor.scala 289:14:freechips.rocketchip.system.LowRiscConfig.fir@84659.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_81 & _T_601) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel Grant is denied (connected at Debug.scala:464:46)\n at Monitor.scala:290 assert (deny_put_ok || !bundle.denied, \"'D' channel Grant is denied\" + extra)\n"); // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@84667.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_81 & _T_601) begin
$fatal; // @[Monitor.scala 290:14:freechips.rocketchip.system.LowRiscConfig.fir@84668.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:294 assert (source_ok, \"'D' channel GrantData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@84677.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_585) begin
$fatal; // @[Monitor.scala 294:14:freechips.rocketchip.system.LowRiscConfig.fir@84678.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_119) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at Debug.scala:464:46)\n at Monitor.scala:295 assert (sink_ok, \"'D' channel GrantData carries invalid sink ID\" + extra)\n"); // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@84684.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_119) begin
$fatal; // @[Monitor.scala 295:14:freechips.rocketchip.system.LowRiscConfig.fir@84685.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_589) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData smaller than a beat (connected at Debug.scala:464:46)\n at Monitor.scala:296 assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), \"'D' channel GrantData smaller than a beat\" + extra)\n"); // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@84692.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_589) begin
$fatal; // @[Monitor.scala 296:14:freechips.rocketchip.system.LowRiscConfig.fir@84693.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_616) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at Debug.scala:464:46)\n at Monitor.scala:297 assert (TLPermissions.isCap(bundle.param), \"'D' channel GrantData carries invalid cap param\" + extra)\n"); // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@84700.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_616) begin
$fatal; // @[Monitor.scala 297:14:freechips.rocketchip.system.LowRiscConfig.fir@84701.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_620) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData carries toN param (connected at Debug.scala:464:46)\n at Monitor.scala:298 assert (bundle.param =/= TLPermissions.toN, \"'D' channel GrantData carries toN param\" + extra)\n"); // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@84708.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_620) begin
$fatal; // @[Monitor.scala 298:14:freechips.rocketchip.system.LowRiscConfig.fir@84709.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_653) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:299 assert (!bundle.denied || bundle.corrupt, \"'D' channel GrantData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@84717.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_653) begin
$fatal; // @[Monitor.scala 299:14:freechips.rocketchip.system.LowRiscConfig.fir@84718.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_95 & _T_601) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel GrantData is denied (connected at Debug.scala:464:46)\n at Monitor.scala:300 assert (deny_get_ok || !bundle.denied, \"'D' channel GrantData is denied\" + extra)\n"); // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@84726.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_95 & _T_601) begin
$fatal; // @[Monitor.scala 300:14:freechips.rocketchip.system.LowRiscConfig.fir@84727.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:304 assert (source_ok, \"'D' channel AccessAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@84736.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_585) begin
$fatal; // @[Monitor.scala 304:14:freechips.rocketchip.system.LowRiscConfig.fir@84737.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:306 assert (bundle.param === UInt(0), \"'D' channel AccessAck carries invalid param\" + extra)\n"); // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@84744.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_593) begin
$fatal; // @[Monitor.scala 306:14:freechips.rocketchip.system.LowRiscConfig.fir@84745.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_597) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:307 assert (!bundle.corrupt, \"'D' channel AccessAck is corrupt\" + extra)\n"); // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@84752.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_597) begin
$fatal; // @[Monitor.scala 307:14:freechips.rocketchip.system.LowRiscConfig.fir@84753.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_109 & _T_601) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAck is denied (connected at Debug.scala:464:46)\n at Monitor.scala:308 assert (deny_put_ok || !bundle.denied, \"'D' channel AccessAck is denied\" + extra)\n"); // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@84761.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_109 & _T_601) begin
$fatal; // @[Monitor.scala 308:14:freechips.rocketchip.system.LowRiscConfig.fir@84762.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:312 assert (source_ok, \"'D' channel AccessAckData carries invalid source ID\" + extra)\n"); // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@84771.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_585) begin
$fatal; // @[Monitor.scala 312:14:freechips.rocketchip.system.LowRiscConfig.fir@84772.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:314 assert (bundle.param === UInt(0), \"'D' channel AccessAckData carries invalid param\" + extra)\n"); // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@84779.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_593) begin
$fatal; // @[Monitor.scala 314:14:freechips.rocketchip.system.LowRiscConfig.fir@84780.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_653) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:315 assert (!bundle.denied || bundle.corrupt, \"'D' channel AccessAckData is denied but not corrupt\" + extra)\n"); // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@84788.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_653) begin
$fatal; // @[Monitor.scala 315:14:freechips.rocketchip.system.LowRiscConfig.fir@84789.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_117 & _T_601) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel AccessAckData is denied (connected at Debug.scala:464:46)\n at Monitor.scala:316 assert (deny_get_ok || !bundle.denied, \"'D' channel AccessAckData is denied\" + extra)\n"); // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@84797.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_117 & _T_601) begin
$fatal; // @[Monitor.scala 316:14:freechips.rocketchip.system.LowRiscConfig.fir@84798.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_585) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at Debug.scala:464:46)\n at Monitor.scala:320 assert (source_ok, \"'D' channel HintAck carries invalid source ID\" + extra)\n"); // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@84807.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_585) begin
$fatal; // @[Monitor.scala 320:14:freechips.rocketchip.system.LowRiscConfig.fir@84808.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_593) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck carries invalid param (connected at Debug.scala:464:46)\n at Monitor.scala:322 assert (bundle.param === UInt(0), \"'D' channel HintAck carries invalid param\" + extra)\n"); // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@84815.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_593) begin
$fatal; // @[Monitor.scala 322:14:freechips.rocketchip.system.LowRiscConfig.fir@84816.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_597) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is corrupt (connected at Debug.scala:464:46)\n at Monitor.scala:323 assert (!bundle.corrupt, \"'D' channel HintAck is corrupt\" + extra)\n"); // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@84823.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_597) begin
$fatal; // @[Monitor.scala 323:14:freechips.rocketchip.system.LowRiscConfig.fir@84824.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_GEN_125 & _T_601) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel HintAck is denied (connected at Debug.scala:464:46)\n at Monitor.scala:324 assert (deny_put_ok || !bundle.denied, \"'D' channel HintAck is denied\" + extra)\n"); // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@84832.10]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_GEN_125 & _T_601) begin
$fatal; // @[Monitor.scala 324:14:freechips.rocketchip.system.LowRiscConfig.fir@84833.10]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'B' channel valid and not TL-C (connected at Debug.scala:464:46)\n at Monitor.scala:341 assert (!bundle.b.valid, \"'B' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@84842.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 341:14:freechips.rocketchip.system.LowRiscConfig.fir@84843.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'C' channel valid and not TL-C (connected at Debug.scala:464:46)\n at Monitor.scala:342 assert (!bundle.c.valid, \"'C' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@84850.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 342:14:freechips.rocketchip.system.LowRiscConfig.fir@84851.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'E' channel valid and not TL-C (connected at Debug.scala:464:46)\n at Monitor.scala:343 assert (!bundle.e.valid, \"'E' channel valid and not TL-C\" + extra)\n"); // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@84858.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 343:14:freechips.rocketchip.system.LowRiscConfig.fir@84859.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_756 & _T_760) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:355 assert (a.bits.opcode === opcode, \"'A' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@84898.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_756 & _T_760) begin
$fatal; // @[Monitor.scala 355:14:freechips.rocketchip.system.LowRiscConfig.fir@84899.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel param changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:356 assert (a.bits.param === param, \"'A' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@84906.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 356:14:freechips.rocketchip.system.LowRiscConfig.fir@84907.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel size changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:357 assert (a.bits.size === size, \"'A' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@84914.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 357:14:freechips.rocketchip.system.LowRiscConfig.fir@84915.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel source changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:358 assert (a.bits.source === source, \"'A' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@84922.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (1'h0) begin
$fatal; // @[Monitor.scala 358:14:freechips.rocketchip.system.LowRiscConfig.fir@84923.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_756 & _T_776) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel address changed with multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:359 assert (a.bits.address=== address,\"'A' channel address changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@84930.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_756 & _T_776) begin
$fatal; // @[Monitor.scala 359:14:freechips.rocketchip.system.LowRiscConfig.fir@84931.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_813 & _T_817) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:425 assert (d.bits.opcode === opcode, \"'D' channel opcode changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@84980.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_813 & _T_817) begin
$fatal; // @[Monitor.scala 425:14:freechips.rocketchip.system.LowRiscConfig.fir@84981.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_813 & _T_821) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel param changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:426 assert (d.bits.param === param, \"'D' channel param changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@84988.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_813 & _T_821) begin
$fatal; // @[Monitor.scala 426:14:freechips.rocketchip.system.LowRiscConfig.fir@84989.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_813 & _T_825) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel size changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:427 assert (d.bits.size === size, \"'D' channel size changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@84996.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_813 & _T_825) begin
$fatal; // @[Monitor.scala 427:14:freechips.rocketchip.system.LowRiscConfig.fir@84997.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_813 & _T_829) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel source changed within multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:428 assert (d.bits.source === source, \"'D' channel source changed within multibeat operation\" + extra)\n"); // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@85004.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_813 & _T_829) begin
$fatal; // @[Monitor.scala 428:14:freechips.rocketchip.system.LowRiscConfig.fir@85005.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_813 & _T_833) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel sink changed with multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:429 assert (d.bits.sink === sink, \"'D' channel sink changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@85012.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_813 & _T_833) begin
$fatal; // @[Monitor.scala 429:14:freechips.rocketchip.system.LowRiscConfig.fir@85013.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_813 & _T_837) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at Debug.scala:464:46)\n at Monitor.scala:430 assert (d.bits.denied === denied, \"'D' channel denied changed with multibeat operation\" + extra)\n"); // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@85020.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_813 & _T_837) begin
$fatal; // @[Monitor.scala 430:14:freechips.rocketchip.system.LowRiscConfig.fir@85021.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_888 & _T_896) begin
$fwrite(32'h80000002,"Assertion failed: 'A' channel re-used a source ID (connected at Debug.scala:464:46)\n at Monitor.scala:460 assert(!inflight(bundle.a.bits.source), \"'A' channel re-used a source ID\" + extra)\n"); // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@85098.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_888 & _T_896) begin
$fatal; // @[Monitor.scala 460:13:freechips.rocketchip.system.LowRiscConfig.fir@85099.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_904 & _T_911) begin
$fwrite(32'h80000002,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at Debug.scala:464:46)\n at Monitor.scala:467 assert((a_set | inflight)(bundle.d.bits.source), \"'D' channel acknowledged for nothing inflight\" + extra)\n"); // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@85121.8]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_904 & _T_911) begin
$fatal; // @[Monitor.scala 467:13:freechips.rocketchip.system.LowRiscConfig.fir@85122.8]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_918) begin
$fwrite(32'h80000002,"Assertion failed: 'A' and 'D' concurrent, despite minlatency 3 (connected at Debug.scala:464:46)\n at Monitor.scala:471 assert(a_set =/= d_clr || !a_set.orR, s\"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}\" + extra)\n"); // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@85133.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_918) begin
$fatal; // @[Monitor.scala 471:13:freechips.rocketchip.system.LowRiscConfig.fir@85134.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
if (`PRINTF_COND) begin
`endif
if (_T_932) begin
$fwrite(32'h80000002,"Assertion failed: TileLink timeout expired (connected at Debug.scala:464:46)\n at Monitor.scala:479 assert (!inflight.orR || limit === UInt(0) || watchdog < limit, \"TileLink timeout expired\" + extra)\n"); // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@85153.6]
end
`ifdef PRINTF_COND
end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef STOP_COND
if (`STOP_COND) begin
`endif
if (_T_932) begin
$fatal; // @[Monitor.scala 479:12:freechips.rocketchip.system.LowRiscConfig.fir@85154.6]
end
`ifdef STOP_COND
end
`endif
`endif // SYNTHESIS
end
endmodule
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85290.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85291.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85292.4]
input io_d, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85293.4]
output io_q // @[:freechips.rocketchip.system.LowRiscConfig.fir@85293.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85298.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85298.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85298.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85298.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85298.4]
wire sync_1_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85302.4]
wire sync_1_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85302.4]
wire sync_1_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85302.4]
wire sync_1_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85302.4]
wire sync_1_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85302.4]
wire sync_2_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85306.4]
wire sync_2_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85306.4]
wire sync_2_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85306.4]
wire sync_2_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85306.4]
wire sync_2_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85306.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85298.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d(sync_0_io_d),
.io_q(sync_0_io_q),
.io_en(sync_0_io_en)
);
AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85302.4]
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d(sync_1_io_d),
.io_q(sync_1_io_q),
.io_en(sync_1_io_en)
);
AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85306.4]
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d(sync_2_io_d),
.io_q(sync_2_io_q),
.io_en(sync_2_io_en)
);
assign io_q = sync_0_io_q; // @[ShiftReg.scala 70:8:freechips.rocketchip.system.LowRiscConfig.fir@85316.4]
assign sync_0_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85300.4]
assign sync_0_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85301.4]
assign sync_0_io_d = sync_1_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.LowRiscConfig.fir@85312.4]
assign sync_0_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@85313.4]
assign sync_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85304.4]
assign sync_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85305.4]
assign sync_1_io_d = sync_2_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.LowRiscConfig.fir@85314.4]
assign sync_1_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@85315.4]
assign sync_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85308.4]
assign sync_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85309.4]
assign sync_2_io_d = io_d; // @[ShiftReg.scala 63:19:freechips.rocketchip.system.LowRiscConfig.fir@85310.4]
assign sync_2_io_en = 1'h1; // @[ShiftReg.scala 64:20:freechips.rocketchip.system.LowRiscConfig.fir@85311.4]
endmodule
module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85504.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85505.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85506.4]
input io_d, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85507.4]
output io_q // @[:freechips.rocketchip.system.LowRiscConfig.fir@85507.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85512.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85512.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85512.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85512.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85512.4]
wire sync_1_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85516.4]
wire sync_1_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85516.4]
wire sync_1_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85516.4]
wire sync_1_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85516.4]
wire sync_1_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85516.4]
wire sync_2_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85520.4]
wire sync_2_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85520.4]
wire sync_2_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85520.4]
wire sync_2_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85520.4]
wire sync_2_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85520.4]
wire sync_3_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85524.4]
wire sync_3_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85524.4]
wire sync_3_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85524.4]
wire sync_3_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85524.4]
wire sync_3_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85524.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85512.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d(sync_0_io_d),
.io_q(sync_0_io_q),
.io_en(sync_0_io_en)
);
AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85516.4]
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d(sync_1_io_d),
.io_q(sync_1_io_q),
.io_en(sync_1_io_en)
);
AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85520.4]
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d(sync_2_io_d),
.io_q(sync_2_io_q),
.io_en(sync_2_io_en)
);
AsyncResetRegVec_w1_i0 sync_3 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85524.4]
.clock(sync_3_clock),
.reset(sync_3_reset),
.io_d(sync_3_io_d),
.io_q(sync_3_io_q),
.io_en(sync_3_io_en)
);
assign io_q = sync_0_io_q; // @[ShiftReg.scala 70:8:freechips.rocketchip.system.LowRiscConfig.fir@85536.4]
assign sync_0_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85514.4]
assign sync_0_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85515.4]
assign sync_0_io_d = sync_1_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.LowRiscConfig.fir@85530.4]
assign sync_0_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@85531.4]
assign sync_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85518.4]
assign sync_1_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85519.4]
assign sync_1_io_d = sync_2_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.LowRiscConfig.fir@85532.4]
assign sync_1_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@85533.4]
assign sync_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85522.4]
assign sync_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85523.4]
assign sync_2_io_d = sync_3_io_q; // @[ShiftReg.scala 67:15:freechips.rocketchip.system.LowRiscConfig.fir@85534.4]
assign sync_2_io_en = 1'h1; // @[ShiftReg.scala 68:16:freechips.rocketchip.system.LowRiscConfig.fir@85535.4]
assign sync_3_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85526.4]
assign sync_3_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85527.4]
assign sync_3_io_d = io_d; // @[ShiftReg.scala 63:19:freechips.rocketchip.system.LowRiscConfig.fir@85528.4]
assign sync_3_io_en = 1'h1; // @[ShiftReg.scala 64:20:freechips.rocketchip.system.LowRiscConfig.fir@85529.4]
endmodule
module AsyncValidSync( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85538.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85539.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85540.4]
output io_out // @[:freechips.rocketchip.system.LowRiscConfig.fir@85541.4]
);
wire source_valid_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85543.4]
wire source_valid_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85543.4]
wire source_valid_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85543.4]
wire source_valid_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85543.4]
AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85543.4]
.clock(source_valid_clock),
.reset(source_valid_reset),
.io_d(source_valid_io_d),
.io_q(source_valid_io_q)
);
assign io_out = source_valid_io_q; // @[AsyncQueue.scala 63:10:freechips.rocketchip.system.LowRiscConfig.fir@85551.4]
assign source_valid_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85545.4]
assign source_valid_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85546.4]
assign source_valid_io_d = 1'h1; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.LowRiscConfig.fir@85547.4]
endmodule
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85584.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85585.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85586.4]
input io_d, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85587.4]
output io_q // @[:freechips.rocketchip.system.LowRiscConfig.fir@85587.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85592.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85592.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85592.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85592.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85592.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:freechips.rocketchip.system.LowRiscConfig.fir@85592.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d(sync_0_io_d),
.io_q(sync_0_io_q),
.io_en(sync_0_io_en)
);
assign io_q = sync_0_io_q; // @[ShiftReg.scala 70:8:freechips.rocketchip.system.LowRiscConfig.fir@85598.4]
assign sync_0_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85594.4]
assign sync_0_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85595.4]
assign sync_0_io_d = io_d; // @[ShiftReg.scala 63:19:freechips.rocketchip.system.LowRiscConfig.fir@85596.4]
assign sync_0_io_en = 1'h1; // @[ShiftReg.scala 64:20:freechips.rocketchip.system.LowRiscConfig.fir@85597.4]
endmodule
module AsyncValidSync_1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85600.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85601.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85602.4]
input io_in, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85603.4]
output io_out // @[:freechips.rocketchip.system.LowRiscConfig.fir@85603.4]
);
wire sink_extend_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85605.4]
wire sink_extend_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85605.4]
wire sink_extend_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85605.4]
wire sink_extend_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85605.4]
AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85605.4]
.clock(sink_extend_clock),
.reset(sink_extend_reset),
.io_d(sink_extend_io_d),
.io_q(sink_extend_io_q)
);
assign io_out = sink_extend_io_q; // @[AsyncQueue.scala 63:10:freechips.rocketchip.system.LowRiscConfig.fir@85613.4]
assign sink_extend_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85607.4]
assign sink_extend_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85608.4]
assign sink_extend_io_d = io_in; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.LowRiscConfig.fir@85609.4]
endmodule
module AsyncValidSync_2( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85736.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85737.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85738.4]
input io_in, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85739.4]
output io_out // @[:freechips.rocketchip.system.LowRiscConfig.fir@85739.4]
);
wire sink_valid_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85741.4]
wire sink_valid_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85741.4]
wire sink_valid_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85741.4]
wire sink_valid_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85741.4]
AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85741.4]
.clock(sink_valid_clock),
.reset(sink_valid_reset),
.io_d(sink_valid_io_d),
.io_q(sink_valid_io_q)
);
assign io_out = sink_valid_io_q; // @[AsyncQueue.scala 63:10:freechips.rocketchip.system.LowRiscConfig.fir@85749.4]
assign sink_valid_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85743.4]
assign sink_valid_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85744.4]
assign sink_valid_io_d = io_in; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.LowRiscConfig.fir@85745.4]
endmodule
module AsyncQueueSource( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85751.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85752.4]
input reset, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85753.4]
output io_enq_ready, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input io_enq_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input [2:0] io_enq_bits_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input [8:0] io_enq_bits_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input [3:0] io_enq_bits_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input [31:0] io_enq_bits_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output [2:0] io_async_mem_0_opcode, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output [8:0] io_async_mem_0_address, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output [3:0] io_async_mem_0_mask, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output [31:0] io_async_mem_0_data, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input io_async_ridx, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output io_async_widx, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input io_async_safe_ridx_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output io_async_safe_widx_valid, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
output io_async_safe_source_reset_n, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
input io_async_safe_sink_reset_n // @[:freechips.rocketchip.system.LowRiscConfig.fir@85754.4]
);
wire widx_bin_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85762.4]
wire widx_bin_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85762.4]
wire widx_bin_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85762.4]
wire widx_bin_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85762.4]
wire widx_bin_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85762.4]
wire ridx_gray_clock; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85774.4]
wire ridx_gray_reset; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85774.4]
wire ridx_gray_io_d; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85774.4]
wire ridx_gray_io_q; // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85774.4]
wire ready_reg_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85796.4]
wire ready_reg_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85796.4]
wire ready_reg_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85796.4]
wire ready_reg_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85796.4]
wire ready_reg_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85796.4]
wire widx_gray_clock; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85805.4]
wire widx_gray_reset; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85805.4]
wire widx_gray_io_d; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85805.4]
wire widx_gray_io_q; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85805.4]
wire widx_gray_io_en; // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85805.4]
wire AsyncValidSync_clock; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@85820.4]
wire AsyncValidSync_reset; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@85820.4]
wire AsyncValidSync_io_out; // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@85820.4]
wire AsyncValidSync_1_clock; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.LowRiscConfig.fir@85823.4]
wire AsyncValidSync_1_reset; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.LowRiscConfig.fir@85823.4]
wire AsyncValidSync_1_io_in; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.LowRiscConfig.fir@85823.4]
wire AsyncValidSync_1_io_out; // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.LowRiscConfig.fir@85823.4]
wire AsyncValidSync_2_clock; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.LowRiscConfig.fir@85826.4]
wire AsyncValidSync_2_reset; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.LowRiscConfig.fir@85826.4]
wire AsyncValidSync_2_io_in; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.LowRiscConfig.fir@85826.4]
wire AsyncValidSync_2_io_out; // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.LowRiscConfig.fir@85826.4]
reg [2:0] mem_0_opcode; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.LowRiscConfig.fir@85758.4]
reg [31:0] _RAND_0;
reg [8:0] mem_0_address; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.LowRiscConfig.fir@85758.4]
reg [31:0] _RAND_1;
reg [3:0] mem_0_mask; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.LowRiscConfig.fir@85758.4]
reg [31:0] _RAND_2;
reg [31:0] mem_0_data; // @[AsyncQueue.scala 76:16:freechips.rocketchip.system.LowRiscConfig.fir@85758.4]
reg [31:0] _RAND_3;
wire _T_43; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@85759.4]
wire sink_ready; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85756.4 :freechips.rocketchip.system.LowRiscConfig.fir@85757.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.LowRiscConfig.fir@85841.4]
wire _T_44; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.LowRiscConfig.fir@85760.4]
wire _T_48; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.LowRiscConfig.fir@85769.4]
wire widx; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@85770.4]
wire ridx; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.LowRiscConfig.fir@85779.4 ShiftReg.scala 50:24:freechips.rocketchip.system.LowRiscConfig.fir@85781.4]
wire _T_52; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.LowRiscConfig.fir@85782.4]
wire _T_53; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.LowRiscConfig.fir@85783.4]
wire ready_reg_1; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.LowRiscConfig.fir@85802.4]
wire _T_58; // @[AsyncQueue.scala 99:43:freechips.rocketchip.system.LowRiscConfig.fir@85830.4]
AsyncResetRegVec_w1_i0 widx_bin ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85762.4]
.clock(widx_bin_clock),
.reset(widx_bin_reset),
.io_d(widx_bin_io_d),
.io_q(widx_bin_io_q),
.io_en(widx_bin_io_en)
);
AsyncResetSynchronizerShiftReg_w1_d3_i0 ridx_gray ( // @[ShiftReg.scala 47:23:freechips.rocketchip.system.LowRiscConfig.fir@85774.4]
.clock(ridx_gray_clock),
.reset(ridx_gray_reset),
.io_d(ridx_gray_io_d),
.io_q(ridx_gray_io_q)
);
AsyncResetRegVec_w1_i0 ready_reg ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85796.4]
.clock(ready_reg_clock),
.reset(ready_reg_reset),
.io_d(ready_reg_io_d),
.io_q(ready_reg_io_q),
.io_en(ready_reg_io_en)
);
AsyncResetRegVec_w1_i0 widx_gray ( // @[AsyncResetReg.scala 97:21:freechips.rocketchip.system.LowRiscConfig.fir@85805.4]
.clock(widx_gray_clock),
.reset(widx_gray_reset),
.io_d(widx_gray_io_d),
.io_q(widx_gray_io_q),
.io_en(widx_gray_io_en)
);
AsyncValidSync AsyncValidSync ( // @[AsyncQueue.scala 96:30:freechips.rocketchip.system.LowRiscConfig.fir@85820.4]
.clock(AsyncValidSync_clock),
.reset(AsyncValidSync_reset),
.io_out(AsyncValidSync_io_out)
);
AsyncValidSync_1 AsyncValidSync_1 ( // @[AsyncQueue.scala 97:30:freechips.rocketchip.system.LowRiscConfig.fir@85823.4]
.clock(AsyncValidSync_1_clock),
.reset(AsyncValidSync_1_reset),
.io_in(AsyncValidSync_1_io_in),
.io_out(AsyncValidSync_1_io_out)
);
AsyncValidSync_2 AsyncValidSync_2 ( // @[AsyncQueue.scala 98:30:freechips.rocketchip.system.LowRiscConfig.fir@85826.4]
.clock(AsyncValidSync_2_clock),
.reset(AsyncValidSync_2_reset),
.io_in(AsyncValidSync_2_io_in),
.io_out(AsyncValidSync_2_io_out)
);
assign _T_43 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:freechips.rocketchip.system.LowRiscConfig.fir@85759.4]
assign sink_ready = AsyncValidSync_2_io_out; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85756.4 :freechips.rocketchip.system.LowRiscConfig.fir@85757.4 AsyncQueue.scala 106:16:freechips.rocketchip.system.LowRiscConfig.fir@85841.4]
assign _T_44 = sink_ready == 1'h0; // @[AsyncQueue.scala 77:49:freechips.rocketchip.system.LowRiscConfig.fir@85760.4]
assign _T_48 = widx_bin_io_q + _T_43; // @[AsyncQueue.scala 53:43:freechips.rocketchip.system.LowRiscConfig.fir@85769.4]
assign widx = _T_44 ? 1'h0 : _T_48; // @[AsyncQueue.scala 53:23:freechips.rocketchip.system.LowRiscConfig.fir@85770.4]
assign ridx = ridx_gray_io_q; // @[ShiftReg.scala 50:24:freechips.rocketchip.system.LowRiscConfig.fir@85779.4 ShiftReg.scala 50:24:freechips.rocketchip.system.LowRiscConfig.fir@85781.4]
assign _T_52 = ridx ^ 1'h1; // @[AsyncQueue.scala 79:44:freechips.rocketchip.system.LowRiscConfig.fir@85782.4]
assign _T_53 = widx != _T_52; // @[AsyncQueue.scala 79:34:freechips.rocketchip.system.LowRiscConfig.fir@85783.4]
assign ready_reg_1 = ready_reg_io_q; // @[AsyncQueue.scala 84:59:freechips.rocketchip.system.LowRiscConfig.fir@85802.4]
assign _T_58 = io_async_safe_sink_reset_n == 1'h0; // @[AsyncQueue.scala 99:43:freechips.rocketchip.system.LowRiscConfig.fir@85830.4]
assign io_enq_ready = ready_reg_1 & sink_ready; // @[AsyncQueue.scala 85:16:freechips.rocketchip.system.LowRiscConfig.fir@85804.4]
assign io_async_mem_0_opcode = mem_0_opcode; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.LowRiscConfig.fir@85819.4]
assign io_async_mem_0_address = mem_0_address; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.LowRiscConfig.fir@85815.4]
assign io_async_mem_0_mask = mem_0_mask; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.LowRiscConfig.fir@85814.4]
assign io_async_mem_0_data = mem_0_data; // @[AsyncQueue.scala 92:31:freechips.rocketchip.system.LowRiscConfig.fir@85813.4]
assign io_async_widx = widx_gray_io_q; // @[AsyncQueue.scala 88:17:freechips.rocketchip.system.LowRiscConfig.fir@85811.4]
assign io_async_safe_widx_valid = AsyncValidSync_io_out; // @[AsyncQueue.scala 103:20:freechips.rocketchip.system.LowRiscConfig.fir@85838.4]
assign io_async_safe_source_reset_n = reset == 1'h0; // @[AsyncQueue.scala 107:24:freechips.rocketchip.system.LowRiscConfig.fir@85844.4]
assign widx_bin_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85764.4]
assign widx_bin_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85765.4]
assign widx_bin_io_d = _T_44 ? 1'h0 : _T_48; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@85766.4]
assign widx_bin_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.LowRiscConfig.fir@85767.4]
assign ridx_gray_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85776.4]
assign ridx_gray_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85777.4]
assign ridx_gray_io_d = io_async_ridx; // @[ShiftReg.scala 49:16:freechips.rocketchip.system.LowRiscConfig.fir@85778.4]
assign ready_reg_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85798.4]
assign ready_reg_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85799.4]
assign ready_reg_io_d = sink_ready & _T_53; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@85800.4]
assign ready_reg_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.LowRiscConfig.fir@85801.4]
assign widx_gray_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85807.4]
assign widx_gray_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85808.4]
assign widx_gray_io_d = _T_44 ? 1'h0 : _T_48; // @[AsyncResetReg.scala 99:14:freechips.rocketchip.system.LowRiscConfig.fir@85809.4]
assign widx_gray_io_en = 1'h1; // @[AsyncResetReg.scala 100:15:freechips.rocketchip.system.LowRiscConfig.fir@85810.4]
assign AsyncValidSync_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85821.4]
assign AsyncValidSync_reset = reset | _T_58; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85822.4 AsyncQueue.scala 99:24:freechips.rocketchip.system.LowRiscConfig.fir@85832.4]
assign AsyncValidSync_1_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85824.4]
assign AsyncValidSync_1_reset = reset | _T_58; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85825.4 AsyncQueue.scala 100:24:freechips.rocketchip.system.LowRiscConfig.fir@85836.4]
assign AsyncValidSync_1_io_in = io_async_safe_ridx_valid; // @[AsyncQueue.scala 104:23:freechips.rocketchip.system.LowRiscConfig.fir@85839.4]
assign AsyncValidSync_2_clock = clock; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85827.4]
assign AsyncValidSync_2_reset = reset; // @[:freechips.rocketchip.system.LowRiscConfig.fir@85828.4]
assign AsyncValidSync_2_io_in = AsyncValidSync_1_io_out; // @[AsyncQueue.scala 105:22:freechips.rocketchip.system.LowRiscConfig.fir@85840.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
mem_0_opcode = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
mem_0_address = _RAND_1[8:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
mem_0_mask = _RAND_2[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
mem_0_data = _RAND_3[31:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (_T_43) begin
mem_0_opcode <= io_enq_bits_opcode;
end
if (_T_43) begin
mem_0_address <= io_enq_bits_address;
end
if (_T_43) begin
mem_0_mask <= io_enq_bits_mask;
end
if (_T_43) begin
mem_0_data <= io_enq_bits_data;
end
end
endmodule
module SynchronizerShiftReg_w43_d1( // @[:freechips.rocketchip.system.LowRiscConfig.fir@85998.2]
input clock, // @[:freechips.rocketchip.system.LowRiscConfig.fir@85999.4]
input [42:0] io_d, // @[:freechips.rocketchip.system.LowRiscConfig.fir@86001.4]
output [42:0] io_q // @[:freechips.rocketchip.system.LowRiscConfig.fir@86001.4]
);
reg [42:0] sync_0; // @[ShiftReg.scala 114:16:freechips.rocketchip.system.LowRiscConfig.fir@86006.4]
reg [63:0] _RAND_0;
assign io_q = sync_0; // @[ShiftReg.scala 123:8:freechips.rocketchip.system.LowRiscConfig.fir@86008.4]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
sync_0 = _RAND_0[42:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <