Add framework for simple tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Makefile

-SUBDIRS = verific bigsim
+SUBDIRS = verific bigsim simple
 
 all: $(addsuffix /.stamp,$(SUBDIRS))
 	echo; find * -name "*.status" | sort | xargs grep -H . | sed 's,^,    ,; s,.status:,\t,; s,PASS,pass,;' | expand -t40; echo

bigsim/Makefile

-all::
+all: work
 	touch .stamp
 
+clean::
+	rm -f .stamp
+
 define template
-all:: $(addprefix $(1)/.stamp_,sim $(2))
+work:: $(addprefix $(1)/.stamp_,sim $(2))
 
 $(1)/.stamp_sim:
 	bash run.sh $(1) sim

simple/.gitignore

+/alu/work_*/
+/.stamp

simple/Makefile

+all: work
+	touch .stamp
+
+clean::
+	rm -f .stamp
+
+define template
+work:: $(1)/work_$(2)/.stamp
+
+$(1)/work_$(2)/.stamp:
+	bash run.sh $(1) $(2)
+
+clean::
+	rm -rf $(1)/work_$(2)
+endef
+
+$(eval $(call template,alu,gates))
+$(eval $(call template,alu,luts))
+
+.PHONY: all clean

simple/alu/testbench.v

+module testbench;
+	reg clock;
+
+	initial begin
+		// $dumpfile("testbench.vcd");
+		// $dumpvars(0, testbench);
+
+		#5 clock = 0;
+		repeat (10000) begin
+			#5 clock = 1;
+			#5 clock = 0;
+		end
+
+		$display("OKAY");
+	end
+
+	reg  [31:0] dinA;
+	reg  [31:0] dinB;
+	reg  [2:0]  opcode;
+	wire [31:0] dout;
+
+	top uut (
+		.clock  (clock ),
+		.dinA   (dinA  ),
+		.dinB   (dinB  ),
+		.opcode (opcode),
+		.dout   (dout  )
+	);
+
+	reg [31:0] ref;
+
+	always @(posedge clock) begin
+		case (opcode)
+		0: ref <= dinA + dinB;
+		1: ref <= dinA - dinB;
+		2: ref <= dinA >> dinB;
+		3: ref <= $signed(dinA) >>> dinB;
+		4: ref <= dinA << dinB;
+		5: ref <= dinA & dinB;
+		6: ref <= dinA | dinB;
+		7: ref <= dinA ^ dinB;
+		endcase
+	end
+
+	reg [127:0] rngstate = 1;
+	reg [63:0] rng;
+
+	task rngnext;
+		// xorshift128plus
+		reg [63:0] x, y;
+		begin
+			{y, x} = rngstate;
+			rngstate[63:0] = y;
+			x ^= x << 23;
+			rngstate[63:0] = x ^ y ^ (x >> 17) ^ (y >> 26);
+			rng = rngstate[63:0] + y;
+		end
+	endtask
+
+	initial begin
+		dinA <= 1;
+		dinB <= 2;
+		opcode <= 0;
+
+		repeat (100)
+			rngnext;
+
+		forever @(posedge clock) begin
+			if (ref != dout) begin
+				$display("ERROR at %t: A=%b B=%b OP=%b OUT=%b (expected %b)",
+						$time, dinA, dinB, opcode, dout, ref);
+				$stop;
+			end
+
+			dinA <= rng;
+			rngnext;
+
+			dinB <= rng;
+			rngnext;
+
+			opcode <= rng;
+			rngnext;
+		end
+	end
+endmodule

simple/alu/top.v

+module top (
+	input clock,
+	input [31:0] dinA, dinB,
+	input [2:0] opcode,
+	output reg [31:0] dout
+);
+	always @(posedge clock) begin
+		case (opcode)
+		0: dout <= dinA + dinB;
+		1: dout <= dinA - dinB;
+		2: dout <= dinA >> dinB;
+		3: dout <= $signed(dinA) >>> dinB;
+		4: dout <= dinA << dinB;
+		5: dout <= dinA & dinB;
+		6: dout <= dinA | dinB;
+		7: dout <= dinA ^ dinB;
+		endcase
+	end
+endmodule

simple/run.sh

+#!/bin/bash
+
+set -ex
+test -d $1
+test -f scripts/$2.ys
+
+rm -rf $1/work_$2
+mkdir $1/work_$2
+cd $1/work_$2
+
+yosys -ql yosys.log ../../scripts/$2.ys
+iverilog -o testbench ../testbench.v synth.v
+
+if ! vvp -N testbench > testbench.log 2>&1; then
+	grep 'ERROR' testbench.log
+	echo fail > ${1}_${2}.status
+elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
+	echo fail > ${1}_${2}.status
+else
+	echo pass > ${1}_${2}.status
+fi
+
+touch .stamp

simple/scripts/gates.ys

+read_verilog ../top.v
+synth -top top
+abc -g gates
+write_verilog synth.v

simple/scripts/luts.ys

+read_verilog ../top.v
+synth -top top
+abc -lut 4
+write_verilog synth.v