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yosys-tests
Commit e50ebb88 by SergeyDegtyar
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New closed issues automated

parent ec684f6b
Showing with 1934 additions and 2 deletions
regression/Makefile
......@@ -362,5 +362,48 @@ $(eval $(call template,issue_00922,issue_00922))
#issue_00931
$(eval $(call template,issue_00931,issue_00931))
#issue_00935
$(eval $(call template,issue_00935,issue_00935))
#issue_00938
$(eval $(call template,issue_00938,issue_00938))
#issue_00940
$(eval $(call template,issue_00940,issue_00940))
#issue_00948
$(eval $(call template,issue_00948,issue_00948))
#issue_00954
$(eval $(call template,issue_00954,issue_00954))
#issue_00955
$(eval $(call template,issue_00955,issue_00955))
#issue_00956
$(eval $(call template,issue_00956,issue_00956))
#issue_00961
$(eval $(call template,issue_00961,issue_00961))
#issue_00968
$(eval $(call template,issue_00968,issue_00968))
#issue_00981
$(eval $(call template,issue_00981,issue_00981))
#issue_00982
$(eval $(call template,issue_00982,issue_00982))
#issue_00987
$(eval $(call template,issue_00987,issue_00987))
#issue_00993
$(eval $(call template,issue_00993,issue_00993))
#issue_00997
$(eval $(call template,issue_00997,issue_00997))
.PHONY: all clean
regression/issue_00938/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
/*initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end*/
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
regression/issue_00940/LEDMatrixInitial.txt 0 → 100644
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regression/issue_00940/SinusTableInit.txt 0 → 100644
000_0000_0000_0000
000_0000_0000_0000
000_0000_0000_0001
000_0000_0000_0010
000_0000_0000_0011
000_0000_0000_0011
000_0000_0000_0100
000_0000_0000_0101
000_0000_0000_0110
000_0000_0000_0111
000_0000_0000_0111
000_0000_0000_1000
000_0000_0000_1001
000_0000_0000_1010
000_0000_0000_1010
000_0000_0000_1011
000_0000_0000_1100
000_0000_0000_1100
000_0000_0000_1101
000_0000_0000_1110
000_0000_0000_1111
000_0000_0000_1111
000_0000_0001_0000
000_0000_0001_0001
000_0000_0001_0001
000_0000_0001_0010
000_0000_0001_0011
000_0000_0001_0011
000_0000_0001_0100
000_0000_0001_0100
000_0000_0001_0101
000_0000_0001_0110
000_0000_0001_0110
000_0000_0001_0111
000_0000_0001_0111
000_0000_0001_1000
000_0000_0001_1000
000_0000_0001_1001
000_0000_0001_1001
000_0000_0001_1010
000_0000_0001_1010
000_0000_0001_1011
000_0000_0001_1011
000_0000_0001_1011
000_0000_0001_1100
000_0000_0001_1100
000_0000_0001_1100
000_0000_0001_1101
000_0000_0001_1101
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000_0000_0001_1110
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111_1111_1111_0101
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111_1111_1111_0111
111_1111_1111_1000
111_1111_1111_1001
111_1111_1111_1001
111_1111_1111_1010
111_1111_1111_1011
111_1111_1111_1100
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111_1111_1111_1101
111_1111_1111_1110
111_1111_1111_1111
000_0000_0000_0000
regression/issue_00940/SinusTableInit_.txt 0 → 100644
000_0000_0000_0000
000_0000_0000_0000
000_0000_0000_0001
000_0000_0000_0010
000_0000_0000_0011
000_0000_0000_0011
000_0000_0000_0100
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000_0000_0000_0110
000_0000_0000_0111
000_0000_0000_0111
000_0000_0000_1000
000_0000_0000_1001
000_0000_0000_1010
000_0000_0000_1010
000_0000_0000_1011
000_0000_0000_1100
000_0000_0000_1100
000_0000_0000_1101
000_0000_0000_1110
000_0000_0000_1111
000_0000_0000_1111
000_0000_0001_0000
000_0000_0001_0001
000_0000_0001_0001
000_0000_0001_0010
000_0000_0001_0011
000_0000_0001_0011
000_0000_0001_0100
000_0000_0001_0100
000_0000_0001_0101
000_0000_0001_0110
000_0000_0001_0110
000_0000_0001_0111
000_0000_0001_0111
000_0000_0001_1000
000_0000_0001_1000
000_0000_0001_1001
000_0000_0001_1001
000_0000_0001_1010
000_0000_0001_1010
000_0000_0001_1011
000_0000_0001_1011
000_0000_0001_1011
000_0000_0001_1100
000_0000_0001_1100
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000_0000_0001_1101
000_0000_0001_1101
000_0000_0001_1101
000_0000_0001_1110
000_0000_0001_1110
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000_0000_0001_1110
000_0000_0001_1111
000_0000_0001_1111
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000_0000_0001_1111
000_0000_0001_1111
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000_0000_0001_1111
000_0000_0010_0000
000_0000_0001_1111
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000_0000_0000_1111
000_0000_0000_1111
000_0000_0000_1110
000_0000_0000_1101
000_0000_0000_1100
000_0000_0000_1100
000_0000_0000_1011
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000_0000_0000_1000
000_0000_0000_0111
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000_0000_0000_0110
000_0000_0000_0101
000_0000_0000_0100
000_0000_0000_0011
000_0000_0000_0011
000_0000_0000_0010
000_0000_0000_0001
000_0000_0000_0000
000_0000_0000_0000
000_0000_0000_0000
111_1111_1111_1111
111_1111_1111_1110
111_1111_1111_1101
111_1111_1111_1101
111_1111_1111_1100
111_1111_1111_1011
111_1111_1111_1010
111_1111_1111_1001
111_1111_1111_1001
111_1111_1111_1000
111_1111_1111_0111
111_1111_1111_0110
111_1111_1111_0110
111_1111_1111_0101
111_1111_1111_0100
111_1111_1111_0100
111_1111_1111_0011
111_1111_1111_0010
111_1111_1111_0001
111_1111_1111_0001
111_1111_1111_0000
111_1111_1110_1111
111_1111_1110_1111
111_1111_1110_1110
111_1111_1110_1101
111_1111_1110_1101
111_1111_1110_1100
111_1111_1110_1100
111_1111_1110_1011
111_1111_1110_1010
111_1111_1110_1010
111_1111_1110_1001
111_1111_1110_1001
111_1111_1110_1000
111_1111_1110_1000
111_1111_1110_0111
111_1111_1110_0111
111_1111_1110_0110
111_1111_1110_0110
111_1111_1110_0101
111_1111_1110_0101
111_1111_1110_0101
111_1111_1110_0100
111_1111_1110_0100
111_1111_1110_0100
111_1111_1110_0011
111_1111_1110_0011
111_1111_1110_0011
111_1111_1110_0010
111_1111_1110_0010
111_1111_1110_0010
111_1111_1110_0010
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0000
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0001
111_1111_1110_0010
111_1111_1110_0010
111_1111_1110_0010
111_1111_1110_0010
111_1111_1110_0011
111_1111_1110_0011
111_1111_1110_0011
111_1111_1110_0100
111_1111_1110_0100
111_1111_1110_0100
111_1111_1110_0101
111_1111_1110_0101
111_1111_1110_0101
111_1111_1110_0110
111_1111_1110_0110
111_1111_1110_0111
111_1111_1110_0111
111_1111_1110_1000
111_1111_1110_1000
111_1111_1110_1001
111_1111_1110_1001
111_1111_1110_1010
111_1111_1110_1010
111_1111_1110_1011
111_1111_1110_1100
111_1111_1110_1100
111_1111_1110_1101
111_1111_1110_1101
111_1111_1110_1110
111_1111_1110_1111
111_1111_1110_1111
111_1111_1111_0000
111_1111_1111_0001
111_1111_1111_0001
111_1111_1111_0010
111_1111_1111_0011
111_1111_1111_0100
111_1111_1111_0100
111_1111_1111_0101
111_1111_1111_0110
111_1111_1111_0110
111_1111_1111_0111
111_1111_1111_1000
111_1111_1111_1001
111_1111_1111_1001
111_1111_1111_1010
111_1111_1111_1011
111_1111_1111_1100
111_1111_1111_1101
111_1111_1111_1101
111_1111_1111_1110
111_1111_1111_1111
000_0000_0000_0000
regression/issue_00940/SuperTopEntity.v 0 → 100644
module SuperTopEntity
( // Inputs
input CLOCK // clock
, input RESET // asynchronous reset: active high
, input RX
, input SDO
, input BUTRST
// Output
, output wire MANRST
, output wire TX
, output wire [6:0] LED
, output wire CLK_OUT
, output wire [2:0] C1
, output wire [2:0] C2
, output wire [3:0] DATA
, output wire LAT
, output wire OE
, output wire CS_AG
, output wire CS_M
, output wire CS_ALT
, output wire SDI
, output wire SCK
, output wire INT
, output wire DRDY_M
, output wire PM1_0
, output wire PM1_2
, output wire PM1_5
, output wire PM1_7
);
wire LOCALRESET;
reg [3:0] counter;
reg DCLOCK;
assign LOCALRESET = RESET | BUTRST;
TopEntity main (.CLOCK(DCLOCK), .RESET(LOCALRESET), .RX(RX), .SDO(SDO), .LED(LED), .TX(TX), .MANRST(MANRST),
.CS_AG(CS_AG), .CS_M(CS_M), .CS_ALT(CS_ALT), .SDI(SDI), .SCK(SCK), .INT(INT), .DRDY_M(DRDY_M),
.PM1_0(PM1_0), .PM1_2(PM1_2), .PM1_5(PM1_5), .PM1_7(PM1_7),
.CLK_OUT(CLK_OUT), .C1(C1), .C2(C2), .DATA(DATA), .LAT(LAT), .OE(OE));
always @(posedge CLOCK)
begin
if (counter == 4)
begin
counter <= 0;
DCLOCK <= !DCLOCK;
end
else
counter <= counter + 1;
end
initial
begin
counter <= 15;
DCLOCK <= 0;
end
endmodule
regression/issue_00940/TopEntity.manifest 0 → 100644
Manifest {manifestHash = (1308240127543765173,Nothing), portInNames = ["CLOCK","RESET","RX","SDO"], portInTypes = ["","","",""], portOutNames = ["MANRST","TX","LED","CLK_OUT","C1","C2","DATA","LAT","OE","CS_AG","CS_M","CS_ALT","SDI","SCK","INT","DRDY_M","PM1_0","PM1_2","PM1_5","PM1_7"], portOutTypes = ["","","[6:0]","","[2:0]","[2:0]","[3:0]","","","","","","","","","","","","",""], componentNames = ["TopEntity"]}
regression/issue_00940/TopEntity.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00948/bug.rtlil 0 → 100644
module \top
wire width 1 input 0 $signal
wire width 1 output 1 \a
wire width 1 $next\a
wire width 1 $1
cell $reduce_bool $2
parameter \A_SIGNED 0
parameter \A_WIDTH 0
parameter \Y_WIDTH 1
connect \A {}
connect \Y $1
end
process $group_0
assign $next\a 1'0
assign $next\a $1
sync init
sync always
update \a $next\a
end
end
regression/issue_00954/top.v 0 → 100644
module lutbug ( addr, out);
input [7:0] addr;
output [3:0] out;
assign out = addr[7:4] * addr[3:0];
endmodule
regression/issue_00955/top.v 0 → 100644
module shifttest ( addr, out );
input [7:0] addr;
output [7:0] out;
assign out[0] = 256'haaaa0000aaaa0000aaaa0000aaaa0000aaaa0000aaaa0000aaaa0000aaaa0000 >> addr;
assign out[1] = 256'h6666aaaacccc00006666aaaacccc00006666aaaacccc00006666aaaacccc0000 >> addr;
assign out[2] = 256'h1e1e66665a5aaaaab4b4ccccf0f000001e1e66665a5aaaaab4b4ccccf0f00000 >> addr;
assign out[3] = 256'h01fe1e1e39c666666d925a5a55aaaaaaab54b4b4936cccccc738f0f0ff000000 >> addr;
assign out[4] = 256'h5554ab545294b4b44924936c66cccccc3398c7381c70f0f007c0ff0000000000 >> addr;
assign out[5] = 256'h999833986318c7388e381c7078f0f0f0c3e007c01f80ff00f800000000000000 >> addr;
assign out[6] = 256'he1e0c3e083e007c00fc01f807f00ff00fc00f800e00000000000000000000000 >> addr;
assign out[7] = 256'hfe00fc00fc00f800f000e0008000000000000000000000000000000000000000 >> addr;
endmodule
regression/issue_00956/top.v 0 → 100644
module inivalue(i_clk, i_val, o_val);
input wire i_clk;
input wire [2:0] i_val;
output reg [1:0] o_val;
reg [2:0] r_val;
initial r_val = 0;
always @(posedge i_clk)
r_val <= r_val + i_val;
always @(*)
o_val = r_val[1:0];
endmodule
regression/issue_00961/top.v 0 → 100644
module mux_if_33_8 #(parameter N=33, parameter W=8) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
always @*
if (s == 0) o <= i[0+:W];
else if (s == 1) o <= i[1*W+:W];
else if (s == 2) o <= i[2*W+:W];
else if (s == 3) o <= i[3*W+:W];
else if (s == 4) o <= i[4*W+:W];
else if (s == 5) o <= i[5*W+:W];
else if (s == 6) o <= i[6*W+:W];
else if (s == 7) o <= i[7*W+:W];
else if (s == 8) o <= i[8*W+:W];
else if (s == 9) o <= i[9*W+:W];
else if (s == 10) o <= i[10*W+:W];
else if (s == 11) o <= i[11*W+:W];
else if (s == 12) o <= i[12*W+:W];
else if (s == 13) o <= i[13*W+:W];
else if (s == 14) o <= i[14*W+:W];
else if (s == 15) o <= i[15*W+:W];
else if (s == 16) o <= i[16*W+:W];
else if (s == 17) o <= i[17*W+:W];
else if (s == 18) o <= i[18*W+:W];
else if (s == 19) o <= i[19*W+:W];
else if (s == 20) o <= i[20*W+:W];
else if (s == 21) o <= i[21*W+:W];
else if (s == 22) o <= i[22*W+:W];
else if (s == 23) o <= i[23*W+:W];
else if (s == 24) o <= i[24*W+:W];
else if (s == 25) o <= i[25*W+:W];
else if (s == 26) o <= i[26*W+:W];
else if (s == 27) o <= i[27*W+:W];
else if (s == 28) o <= i[28*W+:W];
else if (s == 29) o <= i[29*W+:W];
else if (s == 30) o <= i[30*W+:W];
else if (s == 31) o <= i[31*W+:W];
else if (s == 32) o <= i[32*W+:W];
else o <= {W{1'bx}};
endmodule
regression/issue_00968/top.v 0 → 100644
module mcve1(i_value, o_value);
input wire [3:0] i_value;
output reg [7:0] o_value;
integer k;
always @(*)
begin
for(k=0; k<4; k=k+1)
o_value[k] = i_value[k];
o_value[4] = i_value[k];
o_value[5] = i_value[k];
o_value[6] = i_value[k];
o_value[7] = i_value[k];
end
endmodule
regression/issue_00981/top.v 0 → 100644
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00982/top.v 0 → 100644
module lfsr_24 (input clk, output dout);
reg [24:1] state = 24'b0;
always @(posedge clk)
state <= { state[24-1:1], state[24] ~^ state[23] ~^ state[22] ~^ state[17] };
assign dout = state[24];
endmodule
regression/issue_00987/top.v 0 → 100644
module test(output var a, input b);
always_comb a = b;
endmodule
regression/issue_00993/top.v 0 → 100644
module top(y, clk, wire1);
output wire [1:0] y;
input wire clk;
input wire [1:0] wire1;
reg [1:0] reg1 = 0;
reg [1:0] reg2 = 0;
always @(posedge clk) begin
reg1 <= wire1 == 1;
end
always @(posedge clk) begin
reg2 <= 1 >> reg1[1:1];
end
assign y = reg2;
endmodule
regression/issue_00997/top.v 0 → 100644
module top (y, clk, wire4);
output wire [1:0] y;
input clk;
input signed wire4;
reg [1:0] reg10 = 0;
always @(posedge clk) begin
reg10 <= wire4;
end
assign y = reg10;
endmodule
regression/run.sh
......@@ -80,7 +80,21 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00873" ] ||\
[ "$1" = "issue_00888" ] ||\
[ "$1" = "issue_00922" ] ||\
[ "$1" = "issue_00931" ]; then
[ "$1" = "issue_00931" ] ||\
[ "$1" = "issue_00935" ] ||\
[ "$1" = "issue_00938" ] ||\
[ "$1" = "issue_00940" ] ||\
[ "$1" = "issue_00948" ] ||\
[ "$1" = "issue_00954" ] ||\
[ "$1" = "issue_00955" ] ||\
[ "$1" = "issue_00956" ] ||\
[ "$1" = "issue_00961" ] ||\
[ "$1" = "issue_00968" ] ||\
[ "$1" = "issue_00981" ] ||\
[ "$1" = "issue_00982" ] ||\
[ "$1" = "issue_00987" ] ||\
[ "$1" = "issue_00993" ] ||\
[ "$1" = "issue_00997" ]; then
expected_string=""
expected="1"
......@@ -100,7 +114,9 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00826" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00870" ]; then
[ "$1" = "issue_00870" ] ||\
[ "$1" = "issue_00948" ] ||\
[ "$1" = "issue_00987" ]; then
expected_string="Successfully finished Verilog frontend"
elif [ "$1" = "issue_00655" ]; then
expected_string="Executing EDIF backend"
......@@ -138,6 +154,34 @@ elif [ "$1" = "issue_00502" ] ||\
expected="0"
elif [ "$1" = "issue_00931" ]; then
expected_string="Number of cells: 5"
elif [ "$1" = "issue_00935" ]; then
expected_string="Found logic loop in module"
expected="0"
elif [ "$1" = "issue_00938" ]; then
expected_string="terminate called after throwing"
expected="0"
elif [ "$1" = "issue_00940" ]; then
expected_string="failed: return code 134"
expected="0"
elif [ "$1" = "issue_00954" ]; then
expected_string="out = 4'1000"
elif [ "$1" = "issue_00955" ]; then
expected_string="out = 8'00001000"
elif [ "$1" = "issue_00956" ]; then
expected_string="Wire inivalue.r_val has an unprocessed 'init' attribute"
expected="0"
elif [ "$1" = "issue_00961" ]; then
expected_string="Executing PROC_DFF pass"
elif [ "$1" = "issue_00968" ]; then
expected_string="assign o_value = { 4'hx, i_value }"
elif [ "$1" = "issue_00981" ]; then
expected_string="Executing CHECK pass"
elif [ "$1" = "issue_00982" ]; then
expected_string="INIT 1'0"
elif [ "$1" = "issue_00993" ]; then
expected_string="_DFF_P_ 1"
elif [ "$1" = "issue_00997" ]; then
expected_string="h0"
fi
yosys -ql yosys.log ../../scripts/$2.ys;
......
regression/scripts/issue_00935.ys 0 → 100644
read_verilog ../top.v
prep -top picorv32 -nordff
opt -fast
tee -a result.log write_smt2 picorv32.smt2
regression/scripts/issue_00938.ys 0 → 100644
read_verilog ../top.v
proc
memory_dff -nordff
opt_reduce
clean
tee -a result.log write_firrtl firrtl.firrtl
regression/scripts/issue_00940.ys 0 → 100644
read_verilog ../*.v
tee -a result.log synth_ice40 -top SuperTopEntity -json TopEntity.json
regression/scripts/issue_00948.ys 0 → 100644
read_ilang ../bug.rtlil
synth
opt_expr
write_verilog bug.v
delete
tee -a result.log read_verilog bug.v
regression/scripts/issue_00954.ys 0 → 100644
read_verilog ../top.v
synth
abc
eval -set addr 24
aigmap
tee -a result.log eval -set addr 24
regression/scripts/issue_00955.ys 0 → 100644
read_verilog ../top.v
synth
eval -set addr 24
abc
tee -a result.log eval -set addr 24
regression/scripts/issue_00956.ys 0 → 100644
read_verilog ../top.v
tee -a result.log synth_ice40 -top inivalue
regression/scripts/issue_00961.ys 0 → 100644
read_verilog ../top.v
tee -a result.log proc
regression/scripts/issue_00968.ys 0 → 100644
read -sv ../top.v
synth
write_verilog result.log
regression/scripts/issue_00981.ys 0 → 100644
read_verilog ../top.v
tee -a result.log synth_ice40
regression/scripts/issue_00982.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
tee -a result.log dump t:FDRE
regression/scripts/issue_00987.ys 0 → 100644
tee -a result.log read_verilog -sv ../top.v
regression/scripts/issue_00993.ys 0 → 100644
read -formal ../top.v
tee -a result.log synth
#write_verilog rtl_yosys.v
regression/scripts/issue_00997.ys 0 → 100644
read -formal ../top.v
synth
write_verilog -noattr result.log
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