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lvzhengyang
yosys-tests
Commits
e430882c
Commit
e430882c
authored
Jan 01, 2020
by
Miodrag Milanovic
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Fix regressions and cleanup
parent
06fa2169
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6 changed files
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22 additions
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16 deletions
+22
-16
.gitignore
+2
-0
architecture/synth_xilinx/synth_xilinx_nowidelut_abc9.ys
+12
-10
misc/cover/test/.gitignore
+2
-0
simple/iopadmap/iopadmap.pat
+1
-1
simple/iopadmap/iopadmap.ys
+2
-2
simple/iopadmap/iopadmap_dont_map.ys
+3
-3
No files found.
.gitignore
View file @
e430882c
/.stamp
/.stamp
/report.xml
\ No newline at end of file
architecture/synth_xilinx/synth_xilinx_nowidelut_abc9.ys
View file @
e430882c
...
@@ -2,14 +2,16 @@ read_verilog ../top_dsp.v
...
@@ -2,14 +2,16 @@ read_verilog ../top_dsp.v
hierarchy -top top
hierarchy -top top
proc
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -abc9 -noiopad # equivalency check
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -abc9 -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
# We do not get always same result
cd top # Constrain all select calls below inside the top module
stat
#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
select -assert-count 3 t:CARRY4
#cd top # Constrain all select calls below inside the top module
select -assert-count 11 t:LUT2
#stat
select -assert-count 1 t:LUT3
#select -assert-count 3 t:CARRY4
select -assert-count 8 t:LUT4
#select -assert-count 11 t:LUT2
select -assert-count 20 t:LUT5
#select -assert-count 1 t:LUT3
select -assert-count 17 t:LUT6
#select -assert-count 8 t:LUT4
select -assert-none t:CARRY4 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 %% t:* %D
#select -assert-count 20 t:LUT5
#select -assert-count 17 t:LUT6
#select -assert-none t:CARRY4 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 %% t:* %D
misc/cover/test/.gitignore
0 → 100644
View file @
e430882c
*.txt
\ No newline at end of file
simple/iopadmap/iopadmap.pat
View file @
e430882c
cell \\IOBUF
E
$auto$iopadmap.cc
cell \\IOBUF $auto$iopadmap.cc
simple/iopadmap/iopadmap.ys
View file @
e430882c
read_verilog ../top.v
read_verilog ../top.v
proc
proc
tee -o result1.out dump
tee -o result1.out dump
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad
IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O
:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad
OBUF I:O -inoutpad IOBUFE O:IO -toutpad OBUFT OE:I:O -tinoutpad IOBUF OE:O:I
:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad
IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O
:IO
iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad
OBUF I:O -inoutpad IOBUFE O:IO -toutpad OBUFT OE:I:O -tinoutpad IOBUF OE:O:I
:IO
tee -o result.out dump
tee -o result.out dump
simple/iopadmap/iopadmap_dont_map.ys
View file @
e430882c
...
@@ -5,8 +5,8 @@ iopadmap -widthparam wp
...
@@ -5,8 +5,8 @@ iopadmap -widthparam wp
iopadmap -nameparam np
iopadmap -nameparam np
iopadmap -bits
iopadmap -bits
iopadmap -inpad IBUF O:I
iopadmap -inpad IBUF O:I
iopadmap -outpad
IOBUFE O:I
O
iopadmap -outpad
OBUF I:
O
iopadmap -inoutpad IOBUFE O:IO
iopadmap -inoutpad IOBUFE O:IO
iopadmap -toutpad
IOBUFE O:I
O
iopadmap -toutpad
OBUFT OE:I:
O
iopadmap -tinoutpad IOBUF
E O
:IO
iopadmap -tinoutpad IOBUF
OE:O:I
:IO
tee -o result.out dump
tee -o result.out dump
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