Fix xc7mux test infra

architecture/synth_xilinx_mux/assert_area.py

@@ -4,7 +4,7 @@ import glob
 import re
 import os
 
-re_mux = re.compile(r'mux_(index|case|if)_(\d+)_(\d+)\.v')
+re_mux = re.compile(r'mux_(index|case|if_bal|if_unbal)_(\d+)_(\d+)\.v')
 
 area = {}
 #              1  2  3  4  5  6 F7 F8

architecture/synth_xilinx_mux/run-test.sh

@@ -22,7 +22,7 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
 wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
 python3 generate_small.py
 python3 generate_large.py
-${MAKE:-make} -f ../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'synth_xilinx -abc9' -l ../../../../techlibs/xilinx/cells_sim.v"
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'synth_xilinx -abc9' -l ../../../../../techlibs/xilinx/cells_sim.v"
 
-python3 assert_area.py > assert_area.ys
+python3 ../assert_area.py > assert_area.ys
 yosys -q assert_area.ys