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yosys-tests
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lvzhengyang
yosys-tests
Commits
d323bec2
Commit
d323bec2
authored
Nov 25, 2020
by
Miodrag Milanovic
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test for write_verilog simple-lhs option
parent
230c440f
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backends/write_verilog/top_lhs.v
+7
-0
backends/write_verilog/write_verilog_simple_lhs.pat
+2
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backends/write_verilog/write_verilog_simple_lhs.ys
+3
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backends/write_verilog/top_lhs.v
0 → 100644
View file @
d323bec2
module
top
()
;
wire
[
1
:
2
]
b
;
wire
[
3
:
1
]
c
;
wire
f
;
assign
{
b
,
f
}
=
c
;
endmodule
\ No newline at end of file
backends/write_verilog/write_verilog_simple_lhs.pat
0 → 100644
View file @
d323bec2
assign b = c\[3:2\];
\ No newline at end of file
backends/write_verilog/write_verilog_simple_lhs.ys
0 → 100644
View file @
d323bec2
read_verilog ../top_lhs.v
proc
write_verilog -simple-lhs result.out
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