Commit d323bec2 by Miodrag Milanovic

test for write_verilog simple-lhs option

parent 230c440f
module top();
wire [1:2] b;
wire [3:1] c;
wire f;
assign {b, f} = c;
endmodule
\ No newline at end of file
assign b = c\[3:2\];
\ No newline at end of file
read_verilog ../top_lhs.v
proc
write_verilog -simple-lhs result.out
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