test for write_verilog simple-lhs option

d323bec2 · Miodrag Milanovic · 230c440f · d323bec2 · d323bec2 · d323bec2
Commit d323bec2 authored Nov 25, 2020 by Miodrag Milanovic
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backends/write_verilog/top_lhs.v
+7 -0

backends/write_verilog/write_verilog_simple_lhs.pat
+2 -0

backends/write_verilog/write_verilog_simple_lhs.ys
+3 -0

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--- a/backends/write_verilog/top_lhs.v
+++ b/backends/write_verilog/top_lhs.v
+module top();
+wire [1:2] b;
+wire [3:1] c;
+wire f;
+assign {b, f} = c;
+endmodule
\ No newline at end of file
--- a/backends/write_verilog/write_verilog_simple_lhs.pat
+++ b/backends/write_verilog/write_verilog_simple_lhs.pat
+assign b = c\[3:2\];
\ No newline at end of file
--- a/backends/write_verilog/write_verilog_simple_lhs.ys
+++ b/backends/write_verilog/write_verilog_simple_lhs.ys
+read_verilog ../top_lhs.v
+proc
+write_verilog -simple-lhs result.out