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yosys-tests
Unverified Commit d280be7e by Miodrag Milanović Committed by GitHub
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Merge pull request #77 from SergeyDegtyar/review_backends_group 

Review backends group
parents 8da72764 48311829
Showing with 4127 additions and 8448 deletions
backends/.gitignore
*/work_*/ */work_*/
/.stamp /.stamp
/run-test.mk
backends/Makefile
all: work PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
touch .stamp
clean::
rm -f .stamp
define template
$(foreach design,$(1),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
bash run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
#write_aiger
$(eval $(call template,write_aiger,write_aiger write_aiger_ascii write_aiger_zinit write_aiger_miter write_aiger_symbols write_aiger_map write_aiger_vmap write_aiger_I write_aiger_O write_aiger_B ))
$(eval $(call template,write_aiger_error, write_aiger_cant_find_top_module write_aiger_cant_open_file write_aiger_miter_and_asserts write_aiger_unsupported_cell_type ))
#write_xaiger
$(eval $(call template,write_xaiger,write_xaiger write_xaiger_ascii write_xaiger_map write_xaiger_vmap ))
$(eval $(call template,write_xaiger_fsm,write_xaiger write_xaiger_ascii write_xaiger_map write_xaiger_vmap ))
$(eval $(call template,write_xaiger_mem,write_xaiger write_xaiger_ascii write_xaiger_map write_xaiger_vmap ))
$(eval $(call template,write_xaiger_error, write_xaiger_cant_find_top_module write_xaiger_cant_open_file ))
#write_blif
$(eval $(call template,write_blif,write_blif write_blif_top write_blif_buf write_blif_unbuf write_blif_true write_blif_false write_blif_undef write_blif_noalias write_blif_icells write_blif_gates write_blif_conn write_blif_attr write_blif_param write_blif_cname write_blif_iname write_blif_iattr write_blif_blackbox write_blif_impltf))
$(eval $(call template,write_blif_error, write_blif_unmapped_mem write_blif_cant_find_top_module write_blif_unmapped_proc))
#write_btor
$(eval $(call template,write_btor,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_shift,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_div_mod,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_fsm,write_btor write_btor_v write_btor_s write_btor_shift))
$(eval $(call template,write_btor_shift_shiftx,write_btor_shift))
$(eval $(call template,write_btor_logic,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor_mem_s))
$(eval $(call template,write_btor_pmux,write_btor_pmux))
$(eval $(call template,write_btor_and_or,write_btor_and_or))
$(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_init_assert,write_btor write_btor_v write_btor_s))
$(eval $(call template,write_btor_error, write_btor_no_top_module write_btor_unsupported_cell_type))
#write_edif
$(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
$(eval $(call template,write_edif_error, write_edif_cyclic_dependency write_edif_constant_nodes write_edif_unmapped_mem write_edif_unmapped_proc write_edif_no_module_found ))
#write_firrtl
$(eval $(call template,write_firrtl,write_firrtl))
$(eval $(call template,write_firrtl_fsm,write_firrtl_fsm))
$(eval $(call template,write_firrtl_mem,write_firrtl_mem write_firrtl_mem_wr))
$(eval $(call template,write_firrtl_logic,write_firrtl ))
$(eval $(call template,write_firrtl_reduce,write_firrtl ))
$(eval $(call template,write_firrtl_shift,write_firrtl ))
$(eval $(call template,write_firrtl_shiftx,write_firrtl ))
$(eval $(call template,write_firrtl_paramod,write_firrtl))
$(eval $(call template,write_firrtl_mul,write_firrtl))
$(eval $(call template,write_firrtl_sub,write_firrtl))
$(eval $(call template,write_firrtl_pow,write_firrtl))
$(eval $(call template,write_firrtl_error, write_firrtl_fully_selected write_firrtl_negative_edge_ff write_firrtl_inout_port write_firrtl_unclocked_write_port write_firrtl_complex_write_enable ))
#write_ilang
$(eval $(call template,write_ilang,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_mem,write_ilang_mem))
$(eval $(call template,write_ilang_mux,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_fsm,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_tri,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_error,write_ilang_error))
#write_intersynth
$(eval $(call template,write_intersynth,write_intersynth write_intersynth_selected write_intersynth_lib write_intersynth_notypes))
$(eval $(call template,write_intersynth_error, write_intersynth_cant_export write_intersynth_unprocessed_proc write_intersynth_cant_open_lib_file))
#write_json
$(eval $(call template,write_json,write_json write_json_aig json json_o json_o_aig json_aig))
$(eval $(call template,write_json_error,write_json_error))
#write_simplec
$(eval $(call template,write_simplec,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
$(eval $(call template,write_simplec_mux,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
$(eval $(call template,write_simplec_logic,write_simplec write_simplec_cmos3 write_simplec_cmos4 write_simplec_verbose write_simplec_i8 write_simplec_i16 write_simplec_i32 write_simplec_i64))
$(eval $(call template,write_simplec_error,write_simplec_no_c_model write_simplec_not_top_module ))
#write_smt2
$(eval $(call template,write_smt2,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_logic,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_mem_memtest write_smt2_memtest write_smt2_stbv_memtest write_smt2_anyseq))
$(eval $(call template,write_smt2_fsm,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_init_assert,write_smt2_init_assert))
$(eval $(call template,write_smt2_reduce,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_shiftx,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
$(eval $(call template,write_smt2_error, write_smt2_cyclic_dependency write_smt2_cant_open_tpl write_smt2_multiple_drivers write_smt2_logic_loop ))
#write_smv
$(eval $(call template,write_smv,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_wide,write_smv write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_shift,write_smv_shift))
$(eval $(call template,write_smv_fsm,write_smv write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_reduce,write_smv_noproc))
$(eval $(call template,write_smv_logic,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_init_assert,write_smv_init_assert))
$(eval $(call template,write_smv_cmos4,write_smv_cmos4))
$(eval $(call template,write_smv_shiftx,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_error,write_smv_cant_open_template write_smv_unsupported_cell))
#write_spice
$(eval $(call template,write_spice,write_spice write_spice_top write_spice_big_endian write_spice_neg_i write_spice_pos_i write_spice_nc_prefix write_spice_inames ))
$(eval $(call template,write_spice_error, write_spice_cant_find_top_module write_spice_unmapped_mem write_spice_unmapped_proc))
#write_table
$(eval $(call template,write_table,write_table ))
#write_verilog
$(eval $(call template,write_verilog,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v write_verilog_slice write_verilog_lut))
$(eval $(call template,write_verilog_tri,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
$(eval $(call template,write_verilog_ffs,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
$(eval $(call template,write_verilog_latch,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
$(eval $(call template,write_verilog_concat,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
$(eval $(call template,write_verilog_shiftx,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
$(eval $(call template,write_verilog_shift_shiftx,write_verilog_shift ))
all:: run-test.mk
@touch .stamp
@$(MAKE) -f run-test.mk
clean:: run-test.mk
@rm -f .stamp
@$(MAKE) -f run-test.mk clean
run-test.mk: ../generate.py
@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
.PHONY: all clean .PHONY: all clean
backends/common.v deleted 100644 → 0
module assert_equal(input clk, input test, input pat);
always @(posedge clk)
begin
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
backends/common/add_sub.v 0 → 100644
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
assign A = x + y;
assign B = x - y;
endmodule
backends/common/adffs.v 0 → 100644
module top( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
backends/common/counter.v 0 → 100644
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule
backends/common/dffs.v 0 → 100644
module top ( input d, clk, output reg q );
always @( posedge clk )
q <= d;
endmodule
backends/common/latches.v 0 → 100644
module top ( input d, clk, en, output reg q );
always @*
if ( en )
q <= d;
endmodule
backends/common/logic.v 0 → 100644
module top
(
input [0:7] in,
output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
);
assign B1 = in[0] & in[1];
assign B2 = in[0] | in[1];
assign B3 = in[0] ~& in[1];
assign B4 = in[0] ~| in[1];
assign B5 = in[0] ^ in[1];
assign B6 = in[0] ~^ in[1];
assign B7 = ~in[0];
assign B8 = in[0];
assign B9 = in[0:1] && in [2:3];
assign B10 = in[0:1] || in [2:3];
endmodule
backends/common/memory.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
backends/common/mul.v 0 → 100644
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
backends/common/mux.v 0 → 100644
module top ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
backends/common/shifter.v 0 → 100644
module top(out, clk, in);
output [7:0] out;
input signed clk, in;
reg signed [7:0] out = 0;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
endmodule
backends/common/tribuf.v 0 → 100644
module top(en, i, o);
input en;
input i;
output reg o;
always @(en or i)
o <= (en)? i : 1'bZ;
endmodule
backends/run.sh deleted 100644 → 0
#!/bin/bash
set -x
test -d $1
test -f scripts/$2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
# cases where 'syntax error' or other errors are expected
if echo "$1" | grep ".*_error"; then
expected_string=""
#Change checked string for check other errors
if [ "$2" = "write_aiger_cant_find_top_module" ]; then
expected_string="ERROR: Can't find top module in current design!"
elif [ "$2" = "write_aiger_cant_open_file" ]; then
expected_string="ERROR: Can't open file "
elif [ "$2" = "write_aiger_miter_and_asserts" ]; then
expected_string="ERROR: Running AIGER back-end in -miter mode, but design contains \$assert, \$assume, \$live and/or \$fair cells!"
elif [ "$2" = "write_aiger_unsupported_cell_type" ]; then
expected_string="ERROR: Unsupported cell type: "
elif [ "$2" = "write_xaiger_cant_find_top_module" ]; then
expected_string="ERROR: Can't find top module in current design!"
elif [ "$2" = "write_xaiger_cant_open_file" ]; then
expected_string="ERROR: Can't open file "
elif [ "$2" = "write_blif_unmapped_mem" ]; then
expected_string="ERROR: Found unmapped memories in module "
elif [ "$2" = "write_blif_cant_find_top_module" ]; then
expected_string="ERROR: Can't find top module "
elif [ "$2" = "write_blif_unmapped_proc" ]; then
expected_string="ERROR: Found unmapped processes in module "
elif [ "$2" = "write_btor_no_top_module" ]; then
expected_string="ERROR: No top module found."
elif [ "$2" = "write_btor_unsupported_cell_type" ]; then
expected_string="ERROR: Unsupported cell type: "
elif [ "$2" = "write_btor_no_driver" ]; then
expected_string="ERROR: No driver for signal bit "
elif [ "$2" = "write_edif_cyclic_dependency" ]; then
expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
elif [ "$2" = "write_edif_constant_nodes" ]; then
expected_string="ERROR: Design contains constant nodes (map with \"hilomap\" first)."
elif [ "$2" = "write_edif_unmapped_mem" ]; then
expected_string="ERROR: Found unmapped memories in module "
elif [ "$2" = "write_edif_unmapped_proc" ]; then
expected_string="ERROR: Found unmapped processes in module "
elif [ "$2" = "write_edif_no_module_found" ]; then
expected_string="ERROR: No module found in design!"
elif [ "$2" = "write_firrtl_fully_selected" ]; then
expected_string="ERROR: This command only operates on fully selected designs!"
elif [ "$2" = "write_firrtl_negative_edge_ff" ]; then
expected_string="ERROR: Negative edge clock on FF "
elif [ "$2" = "write_firrtl_inout_port" ]; then
expected_string="ERROR: Module port top.q_a is inout!"
elif [ "$2" = "write_firrtl_unclocked_write_port" ]; then
expected_string="ERROR: Unclocked write port "
elif [ "$2" = "write_firrtl_complex_write_enable" ]; then
expected_string="ERROR: Complex write enable on port "
elif [ "$2" = "write_ilang_error" ]; then
expected_string="ERROR: Can't open file \`tt/file1.il' for writing: No such file or directory"
elif [ "$2" = "write_intersynth_cant_export" ]; then
expected_string="ERROR: Can't export composite or non-word-wide signal "
elif [ "$2" = "write_intersynth_unprocessed_proc" ]; then
expected_string="ERROR: Can't generate a netlist for a module with unprocessed memories or processes!"
elif [ "$2" = "write_intersynth_cant_open_lib_file" ]; then
expected_string="ERROR: Can't open lib file "
elif [ "$2" = "write_json_error" ]; then
expected_string="ERROR: Can't open file "
elif [ "$2" = "write_simplec_no_c_model" ]; then
expected_string="ERROR: No C model for \$lut available at the moment (FIXME)."
elif [ "$2" = "write_simplec_not_top_module" ]; then
expected_string="ERROR: Current design has no top module."
elif [ "$2" = "write_smt2_cyclic_dependency" ]; then
expected_string="ERROR: Cyclic dependency between modules found! Cycle includes module "
elif [ "$2" = "write_smt2_cant_open_tpl" ]; then
expected_string="ERROR: Can't open template file "
elif [ "$2" = "write_smt2_multiple_drivers" ]; then
expected_string="ERROR: Found multiple drivers for "
elif [ "$2" = "write_smt2_logic_loop" ]; then
expected_string="ERROR: Found logic loop in module "
elif [ "$2" = "write_smv_cant_open_template" ]; then
expected_string="ERROR: Can't open template file "
elif [ "$2" = "write_smv_unsupported_cell" ]; then
expected_string="ERROR: Found currently unsupported cell type "
elif [ "$2" = "write_spice_cant_find_top_module" ]; then
expected_string="ERROR: Can't find top module "
elif [ "$2" = "write_spice_unmapped_mem" ]; then
expected_string="ERROR: Found unmapped memories in module "
elif [ "$2" = "write_spice_unmapped_proc" ]; then
expected_string="ERROR: Found unmapped processes in module"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
fi
else
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
sed -i 's/reg =/dummy =/' ./synth.v
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
else
COMMON_PREFIX=/usr/local/share/yosys
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
fi
touch .stamp
backends/scripts/write_aiger.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_B.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -B aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_I.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -I aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_O.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -O aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_ascii.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -ascii aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_cant_find_top_module.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_cant_open_file.ys deleted 100644 → 0
read_verilog -sv ../top2.v
aigmap
write_aiger -map tt/tt.map aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_map.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -map a.map aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_miter.ys deleted 100644 → 0
read_verilog -sv ../top_clean.v
synth -top top
aigmap
write_aiger -miter aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_miter_and_asserts.ys deleted 100644 → 0
read_verilog -sv ../top2.v
aigmap
write_aiger -miter aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_symbols.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -symbols aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_unsupported_cell_type.ys deleted 100644 → 0
read_verilog -sv ../top2.v
synth
write_aiger aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_vmap.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_aiger -vmap a.map aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_zinit.ys deleted 100644 → 0
read_verilog -sv ../top_clean.v
aigmap
write_aiger -zinit aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_blif.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
write_blif blif1.blif
design -reset
read_verilog -sv ../top.v
proc
opt
write_blif blif2.blif
design -reset
read_verilog -sv ../top.v
synth
abc -lut 2
write_blif blif3.blif
design -reset
read_verilog -sv ../top.v
synth
abc -sop
write_blif blif4.blif
design -reset
read_verilog -sv ../top.v
synth
abc -g AND,XOR,NOR
write_blif blif4.blif
design -reset
read_verilog -sv ../top.v
synth
abc -g ANDNOT,ORNOT
write_blif blif4.blif
design -reset
read_verilog -sv ../top.v
synth
abc -g cmos3
write_blif blif4.blif
design -reset
read_verilog -sv ../top.v
abc -g AOI4
synth -top top
write_blif blif4.blif
design -reset
read_verilog -sv ../top.v
synth -top top
write_blif blif5.blif
write_verilog synth.v
backends/scripts/write_btor.ys deleted 100644 → 0
read_verilog -sv ../top.v
hierarchy -top top
proc
write_btor btor.btor
design -reset
read_verilog -sv ../top.v
synth -top top
write_btor btor1.btor
design -reset
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
write_btor btor2.btor
design -reset
read_verilog -sv ../top.v
synth
abc
write_btor btor3.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g AND,XOR,NOR
write_btor btor4.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g ANDNOT,ORNOT
write_btor btor5.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g cmos3
write_btor btor6.btor
design -reset
read_verilog -sv ../top.v
abc -g AOI4
synth -top top
write_btor btor7.btor
design -reset
read_verilog -sv ../top.v
abc -g OAI4
synth -top top
write_btor btor8.btor
design -reset
read_verilog -sv ../top.v
aigmap
proc
write_btor btor9.btor
synth -top top
write_btor btor10.btor
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
backends/scripts/write_btor_mem.ys deleted 100644 → 0
read_verilog -sv ../top.v
memory
proc
write_btor btor.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
write_btor btor1.btor
design -reset
read_verilog -sv ../top.v
memory
synth
abc
write_btor btor3.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g AND,XOR,NOR
write_btor btor4.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g ANDNOT,ORNOT
write_btor btor5.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g cmos3
write_btor btor6.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g AOI4
synth -top top
write_btor btor7.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g OAI4
synth -top top
write_btor btor8.btor
design -reset
read_verilog -sv ../top.v
memory
aigmap
proc
write_btor btor9.btor
synth -top top
write_btor btor10.btor
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
backends/scripts/write_btor_mem_s.ys deleted 100644 → 0
read_verilog -sv ../top.v
memory_collect
proc
write_btor -s btor.btor
design -reset
read_verilog -sv ../top.v
synth -top top
design -reset
read_verilog -sv ../top.v
memory
synth
abc
write_btor -s btor3.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g AND,XOR,NOR
write_btor -s btor4.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g ANDNOT,ORNOT
write_btor -s btor5.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g cmos3
write_btor -s btor6.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g AOI4
synth -top top
write_btor -s btor7.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g OAI4
synth -top top
write_btor -s btor8.btor
design -reset
read_verilog -sv ../top.v
memory
aigmap
proc
write_btor -s btor9.btor
synth -top top
write_btor -v btor10.btor
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
backends/scripts/write_btor_mem_v.ys deleted 100644 → 0
read_verilog -sv ../top.v
memory_collect
proc
write_btor -v btor.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
write_btor -v btor1.btor
design -reset
read_verilog -sv ../top.v
synth -top top
design -reset
read_verilog -sv ../top.v
memory
synth
abc
write_btor -v btor3.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g AND,XOR,NOR
write_btor -v btor4.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g ANDNOT,ORNOT
write_btor -v btor5.btor
design -reset
read_verilog -sv ../top.v
memory
synth -top top
abc -g cmos3
write_btor -v btor6.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g AOI4
synth -top top
write_btor -v btor7.btor
design -reset
read_verilog -sv ../top.v
memory
abc -g OAI4
synth -top top
write_btor -v btor8.btor
design -reset
read_verilog -sv ../top.v
memory
aigmap
proc
write_btor -v btor9.btor
synth -top top
write_btor -v btor10.btor
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
backends/scripts/write_btor_s.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
write_btor -s btor.btor
design -reset
read_verilog -sv ../top.v
synth -top top
write_btor -s btor1.btor
design -reset
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
write_btor -s btor2.btor
design -reset
read_verilog -sv ../top.v
synth
abc
write_btor -s btor3.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g AND,XOR,NOR
write_btor -s btor4.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g ANDNOT,ORNOT
write_btor -s btor5.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g cmos3
write_btor -s btor6.btor
design -reset
read_verilog -sv ../top.v
abc -g AOI4
synth -top top
write_btor -s btor7.btor
design -reset
read_verilog -sv ../top.v
abc -g OAI4
synth -top top
write_btor -s btor8.btor
design -reset
read_verilog -sv ../top.v
aigmap
proc
write_btor -s btor9.btor
synth -top top
write_btor -s btor10.btor
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
backends/scripts/write_btor_unsupported_cell_type.ys deleted 100644 → 0
read_verilog ../top3.v
synth_ice40
write_btor btor.btor
backends/scripts/write_btor_v.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
write_btor -v btor.btor
design -reset
read_verilog -sv ../top.v
synth -top top
write_btor -v btor1.btor
design -reset
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
write_btor -v btor2.btor
design -reset
read_verilog -sv ../top.v
synth
abc
write_btor -v btor3.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g AND,XOR,NOR
write_btor -v btor4.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g ANDNOT,ORNOT
write_btor -v btor5.btor
design -reset
read_verilog -sv ../top.v
synth -top top
abc -g cmos3
write_btor -v btor6.btor
design -reset
read_verilog -sv ../top.v
abc -g AOI4
synth -top top
write_btor -v btor7.btor
design -reset
read_verilog -sv ../top.v
abc -g OAI4
synth -top top
write_btor -v btor8.btor
design -reset
read_verilog -sv ../top.v
aigmap
proc
write_btor -v btor9.btor
synth -top top
write_btor -v btor10.btor
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
backends/scripts/write_edif_constant_nodes.ys deleted 100644 → 0
read_verilog -sv ../top3.v
proc
write_edif -nogndvcc blif1.blif
backends/scripts/write_edif_cyclic_dependency.ys deleted 100644 → 0
read_verilog -sv ../top4.v
proc
write_edif blif1.blif
backends/scripts/write_firrtl_mem_wr.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory_dff -nordff
memory_collect
opt_reduce
clean
write_firrtl firrtl.firrtl
write_verilog synth.v
backends/scripts/write_smt2_multiple_drivers.ys deleted 100644 → 0
read_verilog ../top2.v
proc
memory
write_smt2 smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_stdt.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory
write_smt2 -stdt smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_tpl.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory
write_smt2 -tpl ../top.tpl smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_verbose.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory
write_smt2 -verbose smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_wires.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory
write_smt2 -wires smt2.smt2
write_verilog synth.v
backends/scripts/write_smv_cmos4.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
abc -g cmos4
write_smv smv.smv
write_verilog synth.v
backends/scripts/write_smv_shift.ys deleted 100644 → 0
read_verilog ../top.v
proc
write_smv smv.smv
design -reset
read_verilog ../top_clean.v
proc
write_smv smv.smv
write_verilog synth.v
backends/scripts/write_smv_synth.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_smv smv.smv
write_verilog synth.v
backends/scripts/write_xaiger.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_xaiger xaiger.xaiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_xaiger xaiger.xaiger
synth -top top
write_verilog synth.v
backends/scripts/write_xaiger_ascii.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_xaiger -ascii xaiger.xaiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_xaiger xaiger.xaiger
synth -top top
write_verilog synth.v
backends/scripts/write_xaiger_cant_find_top_module.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_xaiger xaiger.xaiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_xaiger xaiger.xaiger
synth -top top
write_verilog synth.v
backends/scripts/write_xaiger_cant_open_file.ys deleted 100644 → 0
read_verilog -sv ../top2.v
aigmap
write_xaiger -map tt/tt.map xaiger.xaiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_xaiger xaiger.xaiger
synth -top top
write_verilog synth.v
backends/scripts/write_xaiger_map.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
aigmap
write_xaiger -map a.map xaiger.xaiger
design -reset
read_verilog -sv ../top_clean.v
synth
aigmap
write_xaiger xaiger.xaiger
synth -top top
write_verilog synth.v
backends/scripts/write_xaiger_vmap.ys deleted 100644 → 0
read_verilog -sv ../top.v
aigmap
write_xaiger -vmap a.map xaiger.xaiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_xaiger xaiger.xaiger
synth -top top
write_verilog synth.v
backends/write_aiger/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_aiger/top_clean.v → backends/write_aiger/top3.v
...@@ -7,21 +7,18 @@ module top ...@@ -7,21 +7,18 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_aiger/top.v → backends/write_aiger/top_diff_cells.v
...@@ -7,13 +7,13 @@ module top ...@@ -7,13 +7,13 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg ASSERT = 1; reg ASSERT = 1;
(* anyconst *) reg foo; (* anyconst *) reg foo;
(* anyseq *) reg too; (* anyseq *) reg too;
initial begin initial begin
begin begin
A = 0; A = 0;
...@@ -21,23 +21,19 @@ module top ...@@ -21,23 +21,19 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
A <= y + cin + too; A <= y + cin + too;
assume(too); assume(too);
assume(s_eventually too); assume(s_eventually too);
end end
always @(negedge x) begin always @(negedge x) begin
if ($initstate) if ($initstate)
cout <= 0; cout <= 0;
cout <= y + A + foo; cout <= y + A + foo;
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_aiger/top_two_mods.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
endmodule
module top2
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
endmodule
backends/write_aiger_error/top2.v → backends/write_aiger/top_x_z.v
...@@ -22,7 +22,7 @@ module top ...@@ -22,7 +22,7 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 1'bX; A <= 1'bX;
...@@ -39,9 +39,6 @@ always @(negedge x) begin ...@@ -39,9 +39,6 @@ always @(negedge x) begin
end end
assign X = 1'bX; assign X = 1'bX;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_aiger/write_aiger.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger_B.pat 0 → 100644
aig 5 5 0 2 0 1 0 0 0
2
10
0
c
backends/write_aiger/write_aiger_B.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -B result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger_I.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -I aiger.aiger
design -reset
read_aiger aiger.aiger
backends/write_aiger/write_aiger_O.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -O aiger.aiger
design -reset
read_aiger aiger.aiger
backends/write_aiger/write_aiger__add_sub.pat 0 → 100644
aig 72 8 0 8 64
22
38
58
78
85
104
124
144
backends/write_aiger/write_aiger__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__adffs.ys 0 → 100644
read_verilog -sv ../../common/adffs.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__counter.pat 0 → 100644
aig 10 10 0 8 0
2
4
6
8
10
12
14
16
c
backends/write_aiger/write_aiger__counter.ys 0 → 100644
read_verilog -sv ../../common/counter.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__latches.ys 0 → 100644
read_verilog -sv ../../common/latches.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__logic.pat 0 → 100644
aig 24 8 0 10 16
18
21
23
24
30
37
17
16
42
49
backends/write_aiger/write_aiger__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__mux.ys 0 → 100644
read_verilog -sv ../../common/mux.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
aigmap
write_aiger result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger_ascii.pat 0 → 100644
aag 5 5 0 2 0
2
4
6
8
10
2
10
c
backends/write_aiger/write_aiger_ascii.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -ascii result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger_ascii_diff_cells.ys 0 → 100644
read_verilog -sv ../top_diff_cells.v
aigmap
write_aiger -ascii aiger.aiger
backends/write_aiger/write_aiger_cant_find_top_module_fail.pat 0 → 100644
ERROR: Can't find top module in current design!
backends/write_aiger/write_aiger_cant_find_top_module_fail.ys 0 → 100644
read_verilog -sv ../top_two_mods.v
aigmap
write_aiger aiger.aiger
backends/write_aiger/write_aiger_cant_open_file_fail.ys 0 → 100644
read_verilog -sv ../top_x_z.v
aigmap
write_aiger -map tt/tt.map aiger.aiger
backends/write_aiger/write_aiger_diff_cells.ys 0 → 100644
read_verilog -sv ../top_diff_cells.v
aigmap
write_aiger aiger.aiger
backends/write_aiger/write_aiger_diff_cells_proc.ys 0 → 100644
read_verilog -sv ../top_diff_cells.v
synth
aigmap
write_aiger aiger.aiger
backends/write_aiger/write_aiger_map.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -map a.map aiger.aiger
design -reset
read_aiger aiger.aiger
backends/write_aiger/write_aiger_miter.ys 0 → 100644
read_verilog -sv ../top3.v
synth -top top
aigmap
write_aiger -miter result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger_miter_and_asserts_fail.pat 0 → 100644
ERROR: Running AIGER back-end in -miter mode, but design contains \$assert, \$assume, \$live and/or \$fair cells!
backends/write_aiger/write_aiger_miter_and_asserts_fail.ys 0 → 100644
read_verilog -sv ../top_x_z.v
aigmap
write_aiger -miter aiger.aiger
backends/write_aiger/write_aiger_symbols.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -symbols result.out
design -reset
read_aiger result.out
backends/write_aiger/write_aiger_symbols_diff_cells.ys 0 → 100644
read_verilog -sv ../top_diff_cells.v
aigmap
write_aiger -symbols aiger.aiger
backends/write_aiger/write_aiger_unsupported_cell_type_fail.ys 0 → 100644
read_verilog -sv ../top_x_z.v
synth
write_aiger aiger.aiger
backends/write_aiger/write_aiger_vmap.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -vmap a.map aiger.aiger
design -reset
read_aiger aiger.aiger
backends/write_aiger/write_aiger_zinit.ys 0 → 100644
read_verilog -sv ../top3.v
aigmap
write_aiger -zinit aiger.aiger
design -reset
read_aiger aiger.aiger
backends/write_aiger_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_blif/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_blif/top.v
...@@ -7,15 +7,14 @@ module top ...@@ -7,15 +7,14 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg A1,cout1; reg A1,cout1;
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A1 <= ~y + &cin; A1 <= ~y + &cin;
end end
...@@ -31,9 +30,6 @@ always @(*) begin ...@@ -31,9 +30,6 @@ always @(*) begin
if (~x) if (~x)
cout <= cout1&cin~|y; cout <= cout1&cin~|y;
end end
`else
assign {cout,A} = 1'bZ;
`endif
bb ubb (cin,y,x,A); bb ubb (cin,y,x,A);
......
backends/write_blif/top_mux.v 0 → 100644
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M16
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_blif/write_blif.ys 0 → 100644
read_verilog -sv ../top.v
proc
write_blif blif.blif
design -reset
read_blif blif.blif
backends/write_blif/write_blif_abc_and_nor.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -g AND,XOR,NOR
write_blif blif.blif
design -reset
read_blif blif.blif
backends/write_blif/write_blif_abc_lut.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -lut 2
write_blif blif.blif
design -reset
read_blif blif.blif
backends/write_blif/write_blif_abc_sop.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -sop
write_blif blif.blif
design -reset
read_blif blif.blif
backends/write_blif/write_blif_andnot.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -g ANDNOT,ORNOT
write_blif blif.blif
design -reset
read_blif blif.blif
backends/write_blif/write_blif_aoi4.ys 0 → 100644
read_verilog -sv ../top.v
abc -g AOI4
synth -top top
write_blif blif.blif
design -reset
read_blif blif.blif
backends/scripts/write_blif_attr.ys → backends/write_blif/write_blif_attr.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -attr blif.blif write_blif -attr blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_blackbox.ys → backends/write_blif/write_blif_blackbox.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -blackbox blif.blif write_blif -blackbox blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_buf.ys → backends/write_blif/write_blif_buf.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -buf a a a blif.blif write_blif -buf a a a blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/write_blif/write_blif_cmos3.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -g cmos3
write_blif blif.blif
design -reset
read_blif blif.blif
backends/write_blif/write_blif_cmos4.ys 0 → 100644
read_verilog -sv ../top_mux.v
synth -top top
abc -g cmos4
write_blif blif.blif
design -reset
read_blif blif.blif
backends/scripts/write_blif_cname.ys → backends/write_blif/write_blif_cname.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -cname blif.blif write_blif -cname blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_conn.ys → backends/write_blif/write_blif_conn.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -conn blif.blif write_blif -conn blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_false.ys → backends/write_blif/write_blif_false.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -false a a blif.blif write_blif -false a a blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_gates.ys → backends/write_blif/write_blif_gates.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -gates blif.blif write_blif -gates blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_iattr.ys → backends/write_blif/write_blif_iattr.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -iattr blif.blif write_blif -iattr blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_icells.ys → backends/write_blif/write_blif_icells.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -icells blif.blif write_blif -icells blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_impltf.ys → backends/write_blif/write_blif_impltf.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -impltf blif.blif write_blif -impltf blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_iname.ys → backends/write_blif/write_blif_iname.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -iname blif.blif write_blif -iname blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_noalias.ys → backends/write_blif/write_blif_noalias.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -noalias blif.blif write_blif -noalias blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/write_blif/write_blif_opt.ys 0 → 100644
read_verilog -sv ../top.v
proc
opt
write_blif blif.blif
design -reset
read_blif blif.blif
backends/scripts/write_blif_param.ys → backends/write_blif/write_blif_param.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -param blif.blif write_blif -param blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_smv_init_assert.ys → backends/write_blif/write_blif_synth_top.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_smv smv.smv write_blif blif.blif
design -reset design -reset
read_verilog -sv ../top_clean.v read_blif blif.blif
synth -top top
write_verilog synth.v
backends/scripts/write_blif_top.ys → backends/write_blif/write_blif_top.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -top top blif.blif write_blif -top top blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_true.ys → backends/write_blif/write_blif_true.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -true a a blif.blif write_blif -true a a blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_unbuf.ys → backends/write_blif/write_blif_unbuf.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -unbuf a a a blif.blif write_blif -unbuf a a a blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/scripts/write_blif_undef.ys → backends/write_blif/write_blif_undef.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
synth -top top synth -top top
write_blif -undef a a blif.blif write_blif -undef a a blif.blif
write_verilog synth.v design -reset
read_blif blif.blif
backends/write_blif/write_blif_unmapped_mem_fail.pat 0 → 100644
ERROR: Found unmapped memories in module
backends/scripts/write_blif_unmapped_mem.ys → backends/write_blif/write_blif_unmapped_mem_fail.ys
read_verilog -sv ../top2.v read_verilog -sv ../top_mem.v
proc proc
write_blif -top u blif1.blif write_blif -top u blif1.blif
backends/write_blif/write_blif_unmapped_proc_fail.pat 0 → 100644
ERROR: Found unmapped processes in module
backends/write_blif_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_btor/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_btor/top.v
...@@ -5,17 +5,15 @@ module top ...@@ -5,17 +5,15 @@ module top
input cin, input cin,
output reg A, output reg A,
output reg cout, output reg cout
output reg B,C
); );
reg ASSERT = 1; reg ASSERT = 1;
(* anyconst *) reg foo; (* anyconst *) reg foo;
(* anyseq *) reg too; (* anyseq *) reg too;
initial begin initial begin
begin begin
A = 0; A = 0;
...@@ -23,24 +21,19 @@ module top ...@@ -23,24 +21,19 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
A <= y + cin + too; A <= y + cin + too;
assume(too); assume(too);
assume(s_eventually too); assume(s_eventually too);
end end
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
cout <= 0; cout <= 0;
cout <= y + A + foo; cout <= y + A + foo;
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
assign {B,C} = {cout,A} <<< 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_btor_and_or/top.v → backends/write_btor/top_and_or.v
...@@ -8,22 +8,16 @@ module top ...@@ -8,22 +8,16 @@ module top
input A, input A,
output reg B output reg B
); );
initial begin initial begin
B = 0; B = 0;
end end
`ifndef BUG
always @(posedge clk) begin always @(posedge clk) begin
if (x || y && z) if (x || y && z)
B <= A & z; B <= A & z;
if (x || y && !z) if (x || y && !z)
B <= A | x; B <= A | x;
end end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule endmodule
backends/write_btor_div_mod/top.v → backends/write_btor/top_div_mod.v
...@@ -23,7 +23,6 @@ module top ...@@ -23,7 +23,6 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y / too; A <= y / too;
end end
...@@ -31,8 +30,5 @@ always @(posedge x) begin ...@@ -31,8 +30,5 @@ always @(posedge x) begin
cout <= y + A % foo; cout <= y + A % foo;
end end
assign {B,C} = {cout,A} << 1; assign {B,C} = {cout,A} << 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_btor_init_assert/top.v → backends/write_btor/top_init_assert.v
...@@ -7,13 +7,13 @@ module top ...@@ -7,13 +7,13 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg ASSERT = 1; reg ASSERT = 1;
(* anyconst *) reg foo; (* anyconst *) reg foo;
(* anyseq *) reg too; (* anyseq *) reg too;
initial begin initial begin
begin begin
A = 0; A = 0;
...@@ -21,12 +21,11 @@ module top ...@@ -21,12 +21,11 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
A <= y + cin + too; A <= y + cin + too;
assume(too); assume(too);
assume(s_eventually too); assume(s_eventually too);
end end
always @(posedge x) begin always @(posedge x) begin
...@@ -36,8 +35,5 @@ always @(posedge x) begin ...@@ -36,8 +35,5 @@ always @(posedge x) begin
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_btor_logic/top.v → backends/write_btor/top_logic.v
...@@ -15,7 +15,7 @@ module top ...@@ -15,7 +15,7 @@ module top
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A1 <= ~y + &cin; A1 <= ~y + &cin;
end end
...@@ -29,8 +29,5 @@ end ...@@ -29,8 +29,5 @@ end
always @(posedge x) begin always @(posedge x) begin
cout <= cout1&cin~|y; cout <= cout1&cin~|y;
end end
`else
assign {cout,A} = 1'bZ;
`endif
endmodule endmodule
backends/write_btor_error/top2.v → backends/write_btor/top_mem.v
...@@ -16,11 +16,7 @@ module top ...@@ -16,11 +16,7 @@ module top
// Port A // Port A
always @ (posedge clk) always @ (posedge clk)
begin begin
`ifndef BUG
if (we_a) if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
...@@ -34,11 +30,7 @@ module top ...@@ -34,11 +30,7 @@ module top
// Port B // Port B
always @ (posedge clk) always @ (posedge clk)
begin begin
`ifndef BUG
if (we_b) if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
......
backends/write_btor/top_no_top_mod.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
end
endmodule
module top2
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
end
always @(posedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
end
endmodule
backends/write_btor_shift/top.v → backends/write_btor/top_shift.v
...@@ -23,7 +23,6 @@ module top ...@@ -23,7 +23,6 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y >> too; A <= y >> too;
end end
...@@ -31,8 +30,5 @@ always @(posedge x) begin ...@@ -31,8 +30,5 @@ always @(posedge x) begin
cout <= y + A >>> foo; cout <= y + A >>> foo;
end end
assign {B,C} = {cout,A} << 1; assign {B,C} = {cout,A} << 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_btor_shift_shiftx/top.v → backends/write_btor/top_shift_shiftx.v
...@@ -4,19 +4,19 @@ ...@@ -4,19 +4,19 @@
req_0, req_0,
req_1, req_1,
gnt_0, gnt_0,
gnt_1 gnt_1
); );
input clock,reset,req_0,req_1; input clock,reset,req_0,req_1;
output gnt_0,gnt_1; output gnt_0,gnt_1;
wire clock,reset,req_0,req_1; wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1; reg gnt_0,gnt_1;
parameter SIZE = 3 ; parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state; reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state; reg [SIZE-1:0] next_state;
always @ (posedge clock) always @ (posedge clock)
begin : FSM begin : FSM
if (reset == 1'b1) begin if (reset == 1'b1) begin
...@@ -27,11 +27,7 @@ ...@@ -27,11 +27,7 @@
case(state) case(state)
IDLE : if (req_0 == 1'b1) begin IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0; state <= #1 GNT0;
`ifndef BUG
gnt_0 <= 1; gnt_0 <= 1;
`else
gnt_0 <= 1'bZ;
`endif
end else if (req_1 == 1'b1) begin end else if (req_1 == 1'b1) begin
gnt_1 <= 1; gnt_1 <= 1;
state <= #1 GNT0; state <= #1 GNT0;
...@@ -51,13 +47,13 @@ ...@@ -51,13 +47,13 @@
GNT2 : if (req_0 == 1'b1) begin GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1; state <= #1 GNT1;
gnt_1 <= req_1; gnt_1 <= req_1;
end end
default : state <= #1 IDLE; default : state <= #1 IDLE;
endcase endcase
end end
endmodule endmodule
module top ( module top (
input clk, input clk,
input rst, input rst,
...@@ -68,10 +64,10 @@ output g1 ...@@ -68,10 +64,10 @@ output g1
); );
fsm u_fsm ( .clock(clk), fsm u_fsm ( .clock(clk),
.reset(rst), .reset(rst),
.req_0(a), .req_0(a),
.req_1(b), .req_1(b),
.gnt_0(g0), .gnt_0(g0),
.gnt_1(g1)); .gnt_1(g1));
endmodule endmodule
backends/write_btor_logic/top_clean.v → backends/write_btor/top_unsupp_cell.v
...@@ -7,21 +7,33 @@ module top ...@@ -7,21 +7,33 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin initial begin
A = 0; begin
cout = 0; A = 0;
cout = 0;
end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_btor/write_btor.ys 0 → 100644
read_verilog -sv ../top.v
hierarchy -top top
proc
write_btor btor.btor
backends/write_btor/write_btor__add_sub.pat 0 → 100644
4 sub 1 3 2
5 output 4 B
6 add 1 3 2
7 output 6 A
backends/write_btor/write_btor__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
hierarchy -top top
proc
write_btor result.out
backends/write_btor/write_btor__dffs.pat 0 → 100644
1 sort bitvec 1
2 input 1 clk
3 input 1 d
4 state 1
5 output 4 q
6 next 1 4 3
backends/write_btor/write_btor__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
hierarchy -top top
proc
write_btor result.out
backends/write_btor/write_btor__logic.pat 0 → 100644
13 and 3 11 12
14 output 13 B9
15 slice 3 2 7 7
16 output 15 B8
17 not 3 15
18 output 17 B7
19 slice 3 2 6 6
20 xnor 3 15 19
21 output 20 B6
22 xor 3 15 19
23 output 22 B5
24 or 3 15 19
25 not 3 24
26 output 25 B4
27 and 3 15 19
28 not 3 27
29 output 28 B3
30 or 3 15 19
31 output 30 B2
32 and 3 15 19
33 output 32 B1
backends/write_btor/write_btor__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
hierarchy -top top
proc
write_btor result.out
backends/write_btor/write_btor__mul.ys 0 → 100644
read_verilog -sv ../../common/mul.v
hierarchy -top top
proc
write_btor result.out
backends/write_btor/write_btor__shifter.ys 0 → 100644
read_verilog -sv ../../common/shifter.v
hierarchy -top top
proc
write_btor result.out
backends/write_btor/write_btor__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
hierarchy -top top
proc
write_btor result.out
backends/write_btor/write_btor_abc.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc
write_btor btor.btor
backends/write_btor/write_btor_abc_and_nor.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
abc -g AND,XOR,NOR
write_btor btor.btor
backends/scripts/write_btor_and_or.ys → backends/write_btor/write_btor_and_or.ys
read_verilog -sv ../top.v read_verilog -sv ../top_and_or.v
proc proc
write_btor btor.btor write_btor btor.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top_and_or.v
synth -top top synth -top top
write_verilog synth.v write_verilog synth.v
backends/scripts/write_btor_logic_and.ys → backends/write_btor/write_btor_andnot.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
memory_collect
proc
write_btor btor.btor
design -reset
read_verilog -sv ../top.v
synth -top top synth -top top
write_verilog synth.v abc -g ANDNOT,ORNOT
write_btor btor.btor
backends/write_btor/write_btor_aoi4.ys 0 → 100644
read_verilog -sv ../top.v
abc -g cmos4
synth -top top
write_btor btor.btor
backends/write_btor/write_btor_cmos3.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
abc -g cmos3
write_btor btor6.btor
backends/write_btor/write_btor_div_mod.ys 0 → 100644
read_verilog -sv ../top_div_mod.v
hierarchy -top top
proc
write_btor btor.btor
backends/scripts/write_btor_shift.ys → backends/write_btor/write_btor_fsm.ys
read_verilog -sv ../top.v read_verilog -sv ../top_fsm.v
proc proc
pmux2shiftx pmux2shiftx
hierarchy -top top hierarchy -top top
......
backends/write_btor/write_btor_init_assert.ys 0 → 100644
read_verilog -sv ../top_init_assert.v
hierarchy -top top
proc
write_btor btor.btor
backends/write_btor/write_btor_logic.ys 0 → 100644
read_verilog -sv ../top_logic.v
hierarchy -top top
proc
write_btor btor.btor
backends/scripts/write_btor_no_top_module.ys → backends/write_btor/write_btor_mem.ys
read_verilog ../top3.v read_verilog -sv ../top_mem.v
memory memory
proc proc
write_btor btor.btor write_btor btor.btor
backends/write_btor/write_btor_mem_s.ys 0 → 100644
read_verilog -sv ../top_mem.v
memory
proc
write_btor -s btor.btor
backends/write_btor/write_btor_mem_v.ys 0 → 100644
read_verilog -sv ../top_mem.v
memory
proc
write_btor -v btor.btor
backends/write_btor/write_btor_no_top_module_fail.ys 0 → 100644
read_verilog -sv ../top_no_top_mod.v
proc
write_btor btor.btor
backends/write_btor/write_btor_oai3.ys 0 → 100644
read_verilog -sv ../top_fsm.v
synth -top top
abc -g cmos3
write_btor btor6.btor
backends/write_btor/write_btor_oai4.ys 0 → 100644
read_verilog -sv ../top_fsm.v
abc -g OAI4
synth -top top
write_btor btor.btor
backends/write_btor/write_btor_pmux.ys 0 → 100644
read_verilog -sv ../top_pmux.v
proc
write_btor -v btor.btor
synth -top top
write_verilog synth.v
backends/write_btor/write_btor_proc.ys 0 → 100644
read_verilog -sv ../top.v
proc_prune
proc_init
proc_mux
proc_dff
write_btor btor.btor
backends/write_btor/write_btor_s.ys 0 → 100644
read_verilog -sv ../top.v
hierarchy -top top
proc
write_btor -s btor.btor
backends/write_btor/write_btor_shift.ys 0 → 100644
read_verilog -sv ../top_shift.v
proc
pmux2shiftx
hierarchy -top top
flatten
write_btor btor.btor
write_verilog synth.v
backends/write_btor/write_btor_shift_shiftx.ys 0 → 100644
read_verilog -sv ../top_shift_shiftx.v
proc
pmux2shiftx
hierarchy -top top
flatten
write_btor btor.btor
write_verilog synth.v
backends/write_btor/write_btor_shiftx.ys 0 → 100644
read_verilog -sv ../top_shiftx.v
proc
pmux2shiftx
hierarchy -top top
flatten
write_btor btor.btor
write_verilog synth.v
backends/scripts/write_btor_simplemap.ys → backends/write_btor/write_btor_simplemap.ys
...@@ -2,7 +2,3 @@ read_verilog -sv ../top.v ...@@ -2,7 +2,3 @@ read_verilog -sv ../top.v
synth -top top synth -top top
simplemap simplemap
write_btor btor.btor write_btor btor.btor
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
backends/write_btor/write_btor_synth.ys 0 → 100644
read_verilog -sv ../top.v
synth -top top
write_btor btor1.btor
backends/write_btor/write_btor_unsupported_cell_type_fail.ys 0 → 100644
read_verilog -sv ../top_unsupp_cell.v
synth
abc
write_btor btor.btor
backends/scripts/write_btor_pmux.ys → backends/write_btor/write_btor_v.ys
read_verilog -sv ../top.v read_verilog -sv ../top.v
hierarchy -top top
proc proc
write_btor -v btor.btor write_btor -v btor.btor
synth -top top
write_verilog synth.v
backends/write_btor_and_or/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
backends/write_btor_div_mod/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_btor_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_btor_init_assert/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_btor_logic/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_btor_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_btor_pmux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] S = 0;
wire [3:0] Y;
top uut (
.C (clk),
.S (S ),
.Y (Y )
);
always @(posedge clk) begin
//#3;
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(Y[0]|Y[1]|Y[2]|Y[3]));
endmodule
backends/write_btor_shift/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_btor_shift_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
backends/write_btor_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg [4:0] in;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
wire out,y;
top uut (
.a(in),
.y(out)
);
integer i, j;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[in];
assert_comb out_test(.A(y), .B(out));
endmodule
backends/write_edif/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_edif/top.v
...@@ -15,16 +15,12 @@ module top ...@@ -15,16 +15,12 @@ module top
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
bb ubb (cin,y,x,bb_out); bb ubb (cin,y,x,bb_out);
......
backends/write_edif_error/top3.v → backends/write_edif/top_const_nodes.v
...@@ -16,16 +16,12 @@ module top ...@@ -16,16 +16,12 @@ module top
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
assign X = 1'bX; assign X = 1'bX;
......
backends/write_edif_error/top4.v → backends/write_edif/top_cyclic_dep.v
...@@ -16,16 +16,13 @@ module top ...@@ -16,16 +16,13 @@ module top
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
assign X = 1'bX; assign X = 1'bX;
......
backends/write_btor_error/top.v → backends/write_edif/top_unmap_mem.v
...@@ -14,13 +14,9 @@ module top ...@@ -14,13 +14,9 @@ module top
end end
// Port A // Port A
always @ (posedge clk, posedge re_b) always @ (posedge clk)
begin begin
`ifndef BUG
if (we_a) if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
...@@ -34,11 +30,7 @@ module top ...@@ -34,11 +30,7 @@ module top
// Port B // Port B
always @ (posedge clk) always @ (posedge clk)
begin begin
`ifndef BUG
if (we_b) if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
......
backends/write_edif/write_edif.pat 0 → 100644
(cell top
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port cout (direction OUTPUT))
(port A (direction OUTPUT))
(port cin (direction INPUT))
(port y (direction INPUT))
(port x (direction INPUT))
)
backends/scripts/write_verilog_shift.ys → backends/write_edif/write_edif.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
pmux2shiftx write_edif result.out
write_verilog synth.v
backends/write_edif/write_edif__add_sub.pat 0 → 100644
(cell (rename id00001 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 4) (direction INPUT))
(port (array B 4) (direction INPUT))
(port (array Y 4) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$sub")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 4) (direction INPUT))
(port (array B 4) (direction INPUT))
(port (array Y 4) (direction OUTPUT))
)
)
)
backends/write_edif/write_edif__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_edif result.out
backends/write_edif/write_edif__adffs.pat 0 → 100644
(cell (rename id00001 "$adff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port ARST (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends/write_edif/write_edif__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_edif result.out
backends/write_edif/write_edif__counter.pat 0 → 100644
(cell (rename id00001 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 8) (direction INPUT))
(port (array B 32) (direction INPUT))
(port (array Y 32) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$adff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port ARST (direction INPUT))
(port (array Q 8) (direction OUTPUT))
(port (array D 8) (direction INPUT))
)
)
)
backends/write_edif/write_edif__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_edif result.out
backends/write_edif/write_edif__dffs.pat 0 → 100644
(cell (rename id00001 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends/write_edif/write_edif__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_edif result.out
backends/write_edif/write_edif__latches.pat 0 → 100644
(cell (rename id00005 "$dlatch")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port EN (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
backends/write_edif/write_edif__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_edif result.out
backends/write_edif/write_edif__logic.pat 0 → 100644
(cell (rename id00001 "$not")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00002 "$and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00003 "$or")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00004 "$xor")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00005 "$xnor")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00006 "$logic_and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 2) (direction INPUT))
(port (array B 2) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00007 "$logic_or")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 2) (direction INPUT))
(port (array B 2) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
backends/write_edif/write_edif__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_edif result.out
backends/write_edif/write_edif__mul.pat 0 → 100644
(cell (rename id00001 "$mul")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 6) (direction INPUT))
(port (array B 6) (direction INPUT))
(port (array Y 12) (direction OUTPUT))
)
)
)
backends/write_edif/write_edif__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_edif result.out
backends/write_edif/write_edif__mux.pat 0 → 100644
(cell (rename id00001 "$eq")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 3) (direction INPUT))
(port (array B 3) (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00002 "$pmux")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port (array B 8) (direction INPUT))
(port Y (direction OUTPUT))
(port (array S 8) (direction INPUT))
)
)
)
backends/write_edif/write_edif__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_edif result.out
backends/write_edif/write_edif__shifter.pat 0 → 100644
(cell (rename id00001 "$shr")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port (array A 8) (direction INPUT))
(port (array B 32) (direction INPUT))
(port (array Y 8) (direction OUTPUT))
)
)
)
(cell (rename id00002 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port (array Q 8) (direction OUTPUT))
(port (array D 8) (direction INPUT))
)
)
)
backends/write_edif/write_edif__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_edif result.out
backends/write_edif/write_edif_attrprop.pat 0 → 100644
(property src (string "../top.v:39")))
backends/scripts/write_smt2_stbv.ys → backends/write_edif/write_edif_attrprop.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory write_edif -attrprop result.out
write_smt2 -stbv smt2.smt2
write_verilog synth.v
backends/write_edif/write_edif_constant_nodes_fail.pat 0 → 100644
ERROR: Design contains constant nodes (map with "hilomap" first).
backends/scripts/write_edif_nogndvcc.ys → backends/write_edif/write_edif_constant_nodes_fail.ys
read_verilog ../top.v read_verilog -sv ../top_const_nodes.v
proc proc
write_edif -nogndvcc edif.edif write_edif -nogndvcc edif.edif
write_verilog synth.v
backends/write_edif/write_edif_cyclic_dependency_fail.pat 0 → 100644
ERROR: Cyclic dependency between modules found! Cycle includes module bb.
backends/scripts/write_edif.ys → backends/write_edif/write_edif_cyclic_dependency_fail.ys
read_verilog ../top.v read_verilog -sv ../top_cyclic_dep.v
proc proc
write_edif edif.edif write_edif edif.edif
write_verilog synth.v
backends/scripts/write_smt2_stbv_memtest.ys → backends/write_edif/write_edif_nogndvcc.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory write_edif -nogndvcc result.out
write_smt2 -stbv smt2.smt2
write_verilog synth.v
backends/scripts/write_edif_pvector_ang.ys → backends/write_edif/write_edif_pvector_ang.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_edif -pvector ang edif.edif write_edif -pvector ang edif.edif
write_verilog synth.v
backends/scripts/write_edif_pvector_bra.ys → backends/write_edif/write_edif_pvector_bra.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_edif -pvector bra edif.edif write_edif -pvector bra edif.edif
write_verilog synth.v
backends/scripts/write_edif_pvector_par.ys → backends/write_edif/write_edif_pvector_par.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_edif -pvector par edif.edif write_edif -pvector par edif.edif
write_verilog synth.v
backends/scripts/json_o_aig.ys → backends/write_edif/write_edif_top.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
json -aig -o json.json write_edif -top top result.out
write_verilog synth.v
backends/write_edif/write_edif_unmapped_mem_fail.pat 0 → 100644
ERROR: Found unmapped memories in module top: unmapped memories are not supported in EDIF backend!
backends/scripts/write_edif_unmapped_mem.ys → backends/write_edif/write_edif_unmapped_mem_fail.ys
read_verilog ../top2.v read_verilog ../top_unmap_mem.v
proc proc
write_edif -top top edif.edif write_edif -top top edif.edif
write_verilog synth.v
backends/write_edif/write_edif_unmapped_proc_fail.pat 0 → 100644
ERROR: Found unmapped processes in module bb: unmapped processes are not supported in EDIF backend!
backends/scripts/write_edif_unmapped_proc.ys → backends/write_edif/write_edif_unmapped_proc_fail.ys
read_verilog ../top.v read_verilog ../top.v
write_edif -top top edif.edif write_edif -top top edif.edif
write_verilog synth.v
backends/write_edif_error/edif.edif deleted 100644 → 0
(edif (rename id00001 "u/u")
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(comment "Generated by Yosys 0.8+553 (git sha1 c9949dba, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)")
(external LIB
(edifLevel 0)
(technology (numberDefinition))
(cell GND
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface (port G (direction OUTPUT)))
)
)
(cell VCC
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface (port P (direction OUTPUT)))
)
)
(cell (rename id00002 "$and")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00003 "$add")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port A (direction INPUT))
(port B (direction INPUT))
(port Y (direction OUTPUT))
)
)
)
(cell (rename id00004 "$dff")
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port CLK (direction INPUT))
(port Q (direction OUTPUT))
(port D (direction INPUT))
)
)
)
)
(library DESIGN
(edifLevel 0)
(technology (numberDefinition))
(cell bb
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port out1 (direction OUTPUT))
(port clk (direction INPUT))
(port in2 (direction INPUT))
(port in1 (direction INPUT))
)
(contents
(instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))
(instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))
(instance (rename id00005 "$procdff$8")
(viewRef VIEW_NETLIST (cellRef id00004 (libraryRef LIB)))
(property CLK_POLARITY (integer 1))
(property WIDTH (integer 1)))
(instance (rename id00006 "$and$top.v:40$7")
(viewRef VIEW_NETLIST (cellRef id00002 (libraryRef LIB)))
(property Y_WIDTH (integer 1))
(property B_WIDTH (integer 1))
(property A_WIDTH (integer 1))
(property B_SIGNED (integer 0))
(property A_SIGNED (integer 0)))
(net out1 (joined
(portRef Q (instanceRef id00005))
(portRef out1)
))
(net clk (joined
(portRef CLK (instanceRef id00005))
(portRef clk)
))
(net (rename id00007 "$and$top.v:40$7_Y") (joined
(portRef D (instanceRef id00005))
(portRef Y (instanceRef id00006))
))
(net in2 (joined
(portRef B (instanceRef id00006))
(portRef in2)
))
(net in1 (joined
(portRef A (instanceRef id00006))
(portRef in1)
))
)
)
)
(cell top
(cellType GENERIC)
(view VIEW_NETLIST
(viewType NETLIST)
(interface
(port cout (direction OUTPUT))
(port A (direction OUTPUT))
(port cin (direction INPUT))
(port y (direction INPUT))
(port x (direction INPUT))
)
(contents
(instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))
(instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))
(instance (rename id00008 "$procdff$10")
(viewRef VIEW_NETLIST (cellRef id00004 (libraryRef LIB)))
(property CLK_POLARITY (integer 1))
(property WIDTH (integer 1)))
(instance (rename id00009 "$procdff$9")
(viewRef VIEW_NETLIST (cellRef id00004 (libraryRef LIB)))
(property CLK_POLARITY (integer 0))
(property WIDTH (integer 1)))
(instance ubb
(viewRef VIEW_NETLIST (cellRef bb)))
(instance (rename id00014 "$add$top.v:23$4")
(viewRef VIEW_NETLIST (cellRef id00003 (libraryRef LIB)))
(property Y_WIDTH (integer 1))
(property B_WIDTH (integer 1))
(property A_WIDTH (integer 1))
(property B_SIGNED (integer 0))
(property A_SIGNED (integer 0)))
(instance (rename id00015 "$add$top.v:20$2")
(viewRef VIEW_NETLIST (cellRef id00003 (libraryRef LIB)))
(property Y_WIDTH (integer 1))
(property B_WIDTH (integer 1))
(property A_WIDTH (integer 1))
(property B_SIGNED (integer 0))
(property A_SIGNED (integer 0)))
(net y (joined
(portRef A (instanceRef id00014))
(portRef A (instanceRef id00015))
(portRef id00012 (instanceRef ubb))
(portRef y)
))
(net x (joined
(portRef CLK (instanceRef id00008))
(portRef CLK (instanceRef id00009))
(portRef id00011 (instanceRef ubb))
(portRef x)
))
(net cout (joined
(portRef Q (instanceRef id00009))
(portRef cout)
))
(net cin (joined
(portRef B (instanceRef id00015))
(portRef cin)
(portRef id00013 (instanceRef ubb))
))
(net bb_out (joined
(portRef id00010 (instanceRef ubb))
))
(net (rename id00016 "$add$top.v:20$2_Y") (joined
(portRef D (instanceRef id00008))
(portRef Y (instanceRef id00015))
))
(net (rename id00017 "$add$top.v:23$4_Y") (joined
(portRef D (instanceRef id00009))
(portRef Y (instanceRef id00014))
))
(net A (joined
(portRef A)
(portRef B (instanceRef id00014))
(portRef Q (instanceRef id00008))
))
)
)
)
)
(design (rename id00001 "u/u")
(cellRef id00001 (libraryRef DESIGN))
)
)
backends/write_edif_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_edif_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
wire bb_out;
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
bb ubb (cin,y,x,bb_out);
endmodule
(* black_box *) module bb(in1, in2, clk, out1);
input in1;
input in2;
input clk;
output reg out1;
always @(posedge clk)
out1 <= in1 & in2;
endmodule
backends/write_firrtl/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
backends/write_firrtl/top.v
...@@ -8,22 +8,16 @@ module top ...@@ -8,22 +8,16 @@ module top
input A, input A,
output reg B output reg B
); );
initial begin initial begin
B = 0; B = 0;
end end
`ifndef BUG
always @(posedge clk) begin always @(posedge clk) begin
if (x || y && z) if (x || y && z)
B <= A & z; B <= A & z;
if (x || y && !z) if (x || y && !z)
B <= A | x; B <= A | x;
end end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule endmodule
backends/write_firrtl/top_complex_write_enable.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [0:0] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl_fsm/top.v → backends/write_firrtl/top_fsm.v
...@@ -4,19 +4,19 @@ ...@@ -4,19 +4,19 @@
req_0, req_0,
req_1, req_1,
gnt_0, gnt_0,
gnt_1 gnt_1
); );
input clock,reset,req_0,req_1; input clock,reset,req_0,req_1;
output gnt_0,gnt_1; output gnt_0,gnt_1;
wire clock,reset,req_0,req_1; wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1; reg gnt_0,gnt_1;
parameter SIZE = 3 ; parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg [SIZE-1:0] state; reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state; reg [SIZE-1:0] next_state;
always @ (posedge clock) always @ (posedge clock)
begin : FSM begin : FSM
if (reset == 1'b1) begin if (reset == 1'b1) begin
...@@ -27,11 +27,7 @@ ...@@ -27,11 +27,7 @@
case(state) case(state)
IDLE : if (req_0 == 1'b1) begin IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0; state <= #1 GNT0;
`ifndef BUG
gnt_0 <= 1; gnt_0 <= 1;
`else
gnt_0 <= 1'bZ;
`endif
end else if (req_1 == 1'b1) begin end else if (req_1 == 1'b1) begin
gnt_1 <= 1; gnt_1 <= 1;
state <= #1 GNT0; state <= #1 GNT0;
...@@ -51,13 +47,13 @@ ...@@ -51,13 +47,13 @@
GNT2 : if (req_0 == 1'b1) begin GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1; state <= #1 GNT1;
gnt_1 <= req_1; gnt_1 <= req_1;
end end
default : state <= #1 IDLE; default : state <= #1 IDLE;
endcase endcase
end end
endmodule endmodule
module top ( module top (
input clk, input clk,
input rst, input rst,
...@@ -68,10 +64,10 @@ output g1 ...@@ -68,10 +64,10 @@ output g1
); );
fsm u_fsm ( .clock(clk), fsm u_fsm ( .clock(clk),
.reset(rst), .reset(rst),
.req_0(a), .req_0(a),
.req_1(b), .req_1(b),
.gnt_0(g0), .gnt_0(g0),
.gnt_1(g1)); .gnt_1(g1));
endmodule endmodule
backends/write_firrtl/top_inout_port.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
inout reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[0:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl/top_logic.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg A1,cout1;
reg int1,int2,int3;
initial begin
A = 0;
cout = 0;
end
always @(posedge x) begin
A1 <= ~y + &cin;
end
always @(posedge x) begin
cout1 <= cin ? |y : ~^A;
end
always @(posedge x) begin
A <= A1|y~&cin~^A1;
end
always @(posedge x) begin
cout <= cout1&cin~|y;
end
always @(posedge x)
begin
if (x == 1'b1) begin
int1 = x ^ y;
end
if (x != 1'b1) begin
if (y > 1'b0) begin
if (cin < 1'b1) begin
int2 = cout1;
end
end
end
end
always @(posedge x)
if (x >= 1'b1) begin
if (y <= 1'b0) begin
int3 = A1;
end
end
endmodule
backends/write_firrtl/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl/top_mul.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign cout = cin / y;
assign A = cin * x;
endmodule
backends/write_aiger_error/top_clean.v → backends/write_firrtl/top_negative_edge_ff.v
...@@ -7,21 +7,17 @@ module top ...@@ -7,21 +7,17 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_firrtl/top_paramod.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle #(1'b0) u_mid1 (.x(x),.o(o),.y(1'b0));
middle #(1'b0) u_mid2 (.x(x),.o(o),.y(1'b1));
middle #(1'b0) u_mid3 (.x(x),.o(o),.y(1'bX));
middle #(1'b0) u_mid4 (.x(x),.o(o),.y(1'bX));
endmodule
module middle
(
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl u_urtl (.x(x),.o(o),.y(Y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
backends/write_firrtl/top_pow.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout,
output signed pow,
output signed pow2
);
wire p,n;
assign pow = 2 ** y;
assign pow2 = 2 ** 2;
assign p = +x;
assign n = -x;
assign A = cin * x;
endmodule
backends/write_firrtl/top_reduce.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire A1,cout1;
assign A1 = ~y + &cin;
assign cout1 = cin ? |y : ^A;
assign A = A1|y~&cin~^A1;
assign cout = cout1&cin~|y;
endmodule
backends/write_firrtl/top_reduce_bool.v 0 → 100644
module top(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule
backends/write_firrtl/top_shift.v 0 → 100644
module top
(
input signed x,
input signed y,
input signed cin,
output signed A,
output signed cout,
output signed B,C,
output signed D,E
);
assign A = y >> x;
assign cout = y + A >>> y;
assign D = y >> 2;
assign E = y + A >>> 2;
assign {B,C} = {cout,A} << 1;
endmodule
backends/write_firrtl/top_shiftx.v 0 → 100644
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer signed i = 0, j = 0;
reg signed [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_firrtl/top_sub.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
assign cout = cin % y;
assign A = cin - x;
endmodule
backends/scripts/write_firrtl.ys → backends/write_firrtl/write_firrtl.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
synth
write_verilog synth.v
backends/write_firrtl/write_firrtl_complex_write_enable_fail.pat 0 → 100644
ERROR: Complex write enable on port 1 on memory top.ram.
backends/scripts/write_firrtl_unclocked_write_port.ys → backends/write_firrtl/write_firrtl_complex_write_enable_fail.ys
read_verilog ../top.v read_verilog ../top_complex_write_enable.v
memory
proc proc
memory
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
write_verilog synth.v
backends/write_firrtl/write_firrtl_dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_firrtl result.out
backends/scripts/write_firrtl_fsm.ys → backends/write_firrtl/write_firrtl_fsm.ys
read_verilog ../top.v read_verilog ../top_fsm.v
proc proc
pmux2shiftx pmux2shiftx
clean clean
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
write_verilog synth.v
backends/write_firrtl/write_firrtl_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
backends/scripts/write_firrtl_fully_selected.ys → backends/write_firrtl/write_firrtl_fully_selected_fail.ys
read_verilog ../top1.v read_verilog ../top_complex_write_enable.v
proc proc
memory_dff -nordff memory_dff -nordff
memory_collect memory_collect
...@@ -6,4 +6,3 @@ opt_reduce ...@@ -6,4 +6,3 @@ opt_reduce
clean clean
select top22 select top22
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
write_verilog synth.v
backends/scripts/write_firrtl_inout_port.ys → backends/write_firrtl/write_firrtl_inout_port_fail.ys
read_verilog ../top2.v read_verilog ../top_inout_port.v
proc proc
memory_dff -nordff memory_dff -nordff
memory_collect memory_collect
opt_reduce opt_reduce
clean clean
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
write_verilog synth.v
backends/scripts/write_firrtl_negative_edge_ff.ys → backends/write_firrtl/write_firrtl_logic.ys
read_verilog ../top3.v read_verilog ../top_logic.v
proc proc
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
write_verilog synth.v
backends/write_firrtl/write_firrtl_mem.pat 0 → 100644
mem ram:
data-type => UInt<8>
depth => 64
reader => r0
reader => r1
writer => w0
writer => w1
read-latency => 0
write-latency => 1
read-under-write => undefined
backends/scripts/write_firrtl_mem.ys → backends/write_firrtl/write_firrtl_mem.ys
read_verilog ../top.v read_verilog ../top_mem.v
proc proc
memory_dff -nordff memory_dff -nordff
memory_collect memory_collect
opt_reduce opt_reduce
clean clean
write_firrtl firrtl.firrtl write_firrtl result.out
write_verilog synth.v
backends/write_firrtl/write_firrtl_mem_wr.pat 0 → 100644
mem ram:
data-type => UInt<8>
depth => 64
reader => r0
reader => r1
writer => w0
writer => w1
read-latency => 0
write-latency => 1
read-under-write => undefined
backends/write_firrtl/write_firrtl_mem_wr.ys 0 → 100644
read_verilog ../top_mem.v
write_firrtl result.out
backends/write_firrtl/write_firrtl_mul.pat 0 → 100644
_mul____top_mul_v_12_2 <= mul(cin, asUInt(x))
_div____top_mul_v_11_1 <= div(cin, asUInt(y))
backends/write_firrtl/write_firrtl_mul.ys 0 → 100644
read_verilog ../top_mul.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_mux.pat 0 → 100644
_auto_pmuxtree_cc_37_or_generator_27 <= orr(pad(cat(_auto_rtlil_cc_1875_Or_16, cat(_procmux_5_CMP, _procmux_6_CMP)), 1))
_auto_pmuxtree_cc_65_recursive_mux_generator_25 <= mux(_auto_rtlil_cc_1875_Or_24, _auto_rtlil_cc_1918_Mux_20, _auto_rtlil_cc_1918_Mux_22)
_auto_pmuxtree_cc_35_or_generator_23 <= or(_procmux_8_CMP, asUInt(_procmux_7_CMP))
_auto_pmuxtree_cc_65_recursive_mux_generator_21 <= mux(_procmux_9_CMP, bits(D, 1, 1), bits(D, 0, 0))
_auto_pmuxtree_cc_65_recursive_mux_generator_19 <= mux(_procmux_7_CMP, bits(D, 3, 3), bits(D, 2, 2))
_auto_pmuxtree_cc_65_recursive_mux_generator_17 <= mux(_auto_rtlil_cc_1875_Or_16, _auto_rtlil_cc_1918_Mux_12, _auto_rtlil_cc_1918_Mux_14)
_auto_pmuxtree_cc_35_or_generator_15 <= or(_procmux_4_CMP, asUInt(_procmux_3_CMP))
_auto_pmuxtree_cc_65_recursive_mux_generator_13 <= mux(_procmux_5_CMP, bits(D, 5, 5), bits(D, 4, 4))
_auto_pmuxtree_cc_65_recursive_mux_generator_11 <= mux(_procmux_3_CMP, bits(D, 7, 7), bits(D, 6, 6))
_procmux_10_CMP0 <= eq(S, asUInt(UInt<3>("h0")))
_procmux_9_CMP0 <= eq(S, asUInt(UInt<3>("h1")))
_procmux_8_CMP0 <= eq(S, asUInt(UInt<3>("h2")))
_procmux_7_CMP0 <= eq(S, asUInt(UInt<3>("h3")))
_procmux_6_CMP0 <= eq(S, asUInt(UInt<3>("h4")))
_procmux_5_CMP0 <= eq(S, asUInt(UInt<3>("h5")))
_procmux_4_CMP0 <= eq(S, asUInt(UInt<3>("h6")))
_auto_pmuxtree_cc_65_recursive_mux_generator_29 <= mux(_auto_rtlil_cc_1848_ReduceOr_28, _auto_rtlil_cc_1918_Mux_18, _auto_rtlil_cc_1918_Mux_26)
_procmux_3_CMP0 <= eq(S, asUInt(UInt<3>("h7")))
backends/write_firrtl/write_firrtl_mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_negative_edge_ff_fail.pat 0 → 100644
ERROR: Negative edge clock on FF top.$procdff$6.
backends/write_firrtl/write_firrtl_negative_edge_ff_fail.ys 0 → 100644
read_verilog ../top_negative_edge_ff.v
proc
write_firrtl firrtl.firrtl
backends/write_firrtl/write_firrtl_paramod.pat 0 → 100644
_ternary____top_paramod_v_16_2 <= mux(cin, y, x)
backends/write_firrtl/write_firrtl_paramod.ys 0 → 100644
read_verilog ../top_paramod.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_pow.pat 0 → 100644
_pow____top_pow_v_16_2 <= asUInt(bits(shl(SInt(1), 2), 31, 0))
_pow____top_pow_v_15_1 <= asUInt(bits(dshl(SInt(1), asUInt(y)), 31, 0))
backends/write_firrtl/write_firrtl_pow.ys 0 → 100644
read_verilog -noopt ../top_pow.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_reduce.pat 0 → 100644
_reduce_xor____top_reduce_v_14_5 <= xorr(pad(A, 1))
_reduce_or____top_reduce_v_14_4 <= orr(pad(y, 1))
_add____top_reduce_v_13_3 <= add(_not____top_reduce_v_13_1_Y, asUInt(_reduce_and____top_reduce_v_13_2_Y))
_reduce_and____top_reduce_v_13_2 <= andr(pad(cin, 1))
backends/write_firrtl/write_firrtl_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_reduce_bool.pat 0 → 100644
_ne____top_reduce_bool_v_26_4 <= neq(in_count, UInt<32>(0))
backends/write_firrtl/write_firrtl_reduce_bool.ys 0 → 100644
read_verilog ../top_reduce_bool.v
prep -top top -nordff
write_firrtl result.out
backends/write_firrtl/write_firrtl_shift.pat 0 → 100644
_shl____top_shift_v_18_7 <= bits(shl(cat(cout, A), 1), 1, 0)
_sshr____top_shift_v_17_6 <= asUInt(shr(asSInt(_add____top_shift_v_17_5_Y), 2))
_add____top_shift_v_17_5 <= asUInt(add(asSInt(y), asSInt(A)))
_shr____top_shift_v_16_4 <= asUInt(shr(asUInt(asSInt(y)), 2))
_sshr____top_shift_v_15_3 <= asUInt(dshr(asSInt(_add____top_shift_v_15_2_Y), asUInt(y)))
_add____top_shift_v_15_2 <= asUInt(add(asSInt(y), asSInt(A)))
_shr____top_shift_v_14_1 <= asUInt(dshr(asUInt(asSInt(y)), asUInt(x)))
backends/write_firrtl/write_firrtl_shift.ys 0 → 100644
read_verilog ../top_shift.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_shiftx.pat 0 → 100644
_shiftx____top_shiftx_v_21_107 <= dshr(lut, a)
backends/write_firrtl/write_firrtl_shiftx.ys 0 → 100644
read_verilog ../top_shiftx.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_sub.pat 0 → 100644
_sub____top_sub_v_12_2 <= asUInt(sub(cin, asUInt(x)))
_mod____top_sub_v_11_1 <= rem(cin, asUInt(y))
backends/write_firrtl/write_firrtl_sub.ys 0 → 100644
read_verilog ../top_sub.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_tribuf.pat 0 → 100644
_ternary_______common_tribuf_v_7_2 <= mux(en, i, UInt<1>("h0"))
backends/write_firrtl/write_firrtl_tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_firrtl result.out
backends/write_firrtl/write_firrtl_unclocked_write_port_fail.pat 0 → 100644
ERROR: Unclocked write port 0 on memory top.ram.
backends/scripts/write_firrtl_complex_write_enable.ys → backends/write_firrtl/write_firrtl_unclocked_write_port_fail.ys
read_verilog ../top1.v read_verilog ../top_mem.v
proc
memory memory
proc
write_firrtl firrtl.firrtl write_firrtl firrtl.firrtl
write_verilog synth.v write_verilog synth.v
backends/write_firrtl_error/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl_error/top1.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [0:0] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl_error/top2.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
inout reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[0:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl_error/top3.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_firrtl_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
backends/write_firrtl_logic/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_firrtl_logic/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg A1,cout1;
reg int1,int2,int3;
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A1 <= ~y + &cin;
end
always @(posedge x) begin
cout1 <= cin ? |y : ~^A;
end
always @(posedge x) begin
A <= A1|y~&cin~^A1;
end
always @(posedge x) begin
cout <= cout1&cin~|y;
end
always @(posedge x)
begin
if (x == 1'b1) begin
int1 = x ^ y;
end
if (x != 1'b1) begin
if (y > 1'b0) begin
if (cin < 1'b1) begin
int2 = cout1;
end
end
end
end
always @(posedge x)
if (x >= 1'b1) begin
if (y <= 1'b0) begin
int3 = A1;
end
end
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
backends/write_firrtl_logic/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_firrtl_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_firrtl_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_firrtl_mul/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign patt_carry_out = in[2] / in[1];
assign patt_out = in[2] * in[0];
assert_comb out_test(.A(patt_out), .B(out));
//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_firrtl_mul/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign cout = cin / y;
assign A = cin * x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_firrtl_paramod/testbench.v deleted 100644 → 0
module middle_tb
(
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl_tb u_urtl (.x(x),.o(o),.y(Y));
endmodule
module urtl_tb
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
module testbench;
reg [0:2] in;
reg patt_A = 1'bX;
wire patt_cout;
wire cout,o;
wire A;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(A),
.cout(cout)
);
always @(posedge in[2])
patt_A <= o;
assign pattcout = in[2]? in[1] : in[0];
middle_tb #(1'b0) u_mid1 (.x(in[0]),.o(o),.y(1'b0));
middle_tb #(1'b0) u_mid2 (.x(in[0]),.o(o),.y(1'b1));
middle_tb #(1'b0) u_mid3 (.x(in[0]),.o(o),.y(1'bX));
middle_tb #(1'b0) u_mid4 (.x(in[0]),.o(o),.y(1'bX));
assert_comb out_test(.A(patt_A), .B(A));
endmodule
backends/write_firrtl_paramod/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle #(1'b0) u_mid1 (.x(x),.o(o),.y(1'b0));
middle #(1'b0) u_mid2 (.x(x),.o(o),.y(1'b1));
middle #(1'b0) u_mid3 (.x(x),.o(o),.y(1'bX));
middle #(1'b0) u_mid4 (.x(x),.o(o),.y(1'bX));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
output o
);
parameter Y = 1'b1;
urtl u_urtl (.x(x),.o(o),.y(Y));
endmodule
module urtl
(
input x,
input y,
output o
);
assign o = x + y;
endmodule
backends/write_firrtl_pow/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
//assign patt_carry_out = in[2] ** in[1];
assign patt_out = in[2] * in[0];
assert_comb out_test(.A(patt_out), .B(out));
//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_firrtl_pow/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
wire pow,p,n;
assign pow = 2 ** y;
assign p = +x;
assign n = -x;
assign A = cin * x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_firrtl_reduce/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_firrtl_reduce/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire A1,cout1;
// initial begin
// A = 0;
// cout = 0;
// end
`ifndef BUG
assign A1 = ~y + &cin;
assign cout1 = cin ? |y : ^A;
assign A = A1|y~&cin~^A1;
assign cout = cout1&cin~|y;
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
backends/write_firrtl_shift/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_tri out_test(.A(patt_out), .B(out), .en(1'b1));
assert_tri carry_test(.A(patt_carry_out), .B(carryout), .en(1'b1));
endmodule
backends/write_firrtl_shift/top.v deleted 100644 → 0
module top
(
input signed x,
input signed y,
input signed cin,
output signed A,
output signed cout,
output signed B,C
);
`ifndef BUG
assign A = y >> x;
assign cout = y + A >>> y;
assign {B,C} = {cout,A} << 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_firrtl_shift/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_firrtl_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg [4:0] in;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
wire out,y;
top uut (
.a(in),
.y(out)
);
integer i, j;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[in];
assert_comb out_test(.A(y), .B(out));
endmodule
backends/write_firrtl_shiftx/top.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer signed i = 0, j = 0;
reg signed [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_firrtl_shiftx/top_clean.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input [4:0] a;
output y;
integer i = 0, j = 0;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_firrtl_sub/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign patt_carry_out = in[2] % in[1];
assign patt_out = in[2] - in[0];
assert_comb out_test(.A(patt_out), .B(out));
//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_firrtl_sub/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign cout = cin % y;
assign A = cin - x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_ilang/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
backends/write_ilang/top.v
...@@ -8,22 +8,21 @@ module top ...@@ -8,22 +8,21 @@ module top
input A, input A,
output reg B output reg B
); );
initial begin initial begin
B = 0; B = 0;
end end
`ifndef BUG
always @(posedge clk) begin always @(posedge clk) begin
if (x || y && z) if (x || y && z)
B <= A & z; B <= A & z;
if (x || y && !z) if (x || y && !z)
B <= A | x; B <= A | x;
end end
`else
always @(posedge clk) begin always @(negedge clk) begin
B = z - y + x; if (x || y && z)
A <= x & z;
end end
`endif
endmodule endmodule
backends/write_ilang/top_fsm.v 0 → 100644
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
backends/write_btor_mem/top.v → backends/write_ilang/top_mem.v
...@@ -2,43 +2,35 @@ module top ...@@ -2,43 +2,35 @@ module top
( (
input [7:0] data_a, data_b, input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b, input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk, input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b output reg [7:0] q_a, q_b
); );
// Declare the RAM variable // Declare the RAM variable
reg [7:0] ram[63:0]; reg [7:0] ram[63:0];
initial begin initial begin
q_a <= 8'h00; q_a <= 8'h00;
q_b <= 8'd0; q_b <= 8'd0;
end end
// Port A // Port A
always @ (posedge clk) always @ (posedge clka)
begin begin
`ifndef BUG if (we_a)
if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
end end
if (re_b) if (re_b)
begin begin
q_a <= ram[addr_a]; q_a <= ram[addr_a];
end end
end end
// Port B // Port B
always @ (posedge clk) always @ (posedge clkb)
begin begin
`ifndef BUG if (we_b)
if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
...@@ -48,5 +40,5 @@ module top ...@@ -48,5 +40,5 @@ module top
q_b <= ram[addr_b]; q_b <= ram[addr_b];
end end
end end
endmodule endmodule
backends/write_ilang/top_mux.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_ilang/top_tri.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/scripts/write_ilang_mem.ys → backends/write_ilang/write_ilang.ys
read_verilog ../top.v read_verilog ../top.v
write_ilang ilang.ilang
proc proc
memory
dump -o file.il dump -o file.il
write_ilang ilang.ilang write_ilang result.out
dump -n -o file1.il dump -n -o file1.il
write_verilog synth.v design -reset
read_ilang result.out
backends/write_ilang/write_ilang__add_sub.pat 0 → 100644
cell $add $add$../../common/add_sub.v:10$1
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \x
connect \B \y
connect \Y $add$../../common/add_sub.v:10$1_Y
end
attribute \src "../../common/add_sub.v:11"
cell $sub $sub$../../common/add_sub.v:11$2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
connect \A \x
connect \B \y
connect \Y $sub$../../common/add_sub.v:11$2_Y
end
backends/write_ilang/write_ilang__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends/write_ilang/write_ilang__adffs.pat 0 → 100644
cell $adff $procdff$3
parameter \ARST_POLARITY 1'1
parameter \ARST_VALUE 1'0
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \ARST \clr
connect \CLK \clk
connect \D \d
connect \Q \q
end
backends/write_ilang/write_ilang__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends/write_ilang/write_ilang__dffs.pat 0 → 100644
cell $dff $procdff$2
parameter \CLK_POLARITY 1'1
parameter \WIDTH 1
connect \CLK \clk
connect \D \d
connect \Q \q
end
backends/write_ilang/write_ilang__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends/write_ilang/write_ilang__latches.pat 0 → 100644
cell $dlatch $auto$proc_dlatch.cc:409:proc_dlatch$14
parameter \EN_POLARITY 1
parameter \WIDTH 1
connect \D $procmux$2_Y
connect \EN $auto$rtlil.cc:1844:Not$13
connect \Q \q
end
backends/write_ilang/write_ilang__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends/write_ilang/write_ilang__mul.pat 0 → 100644
cell $mul $mul$../../common/mul.v:8$1
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 12
connect \A \x
connect \B \y
connect \Y $mul$../../common/mul.v:8$1_Y
end
backends/write_ilang/write_ilang__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends/write_ilang/write_ilang__mux.pat 0 → 100644
cell $pmux $procmux$2
parameter \S_WIDTH 8
parameter \WIDTH 1
connect \A 1'x
connect \B { \D [0] \D [1] \D [2] \D [3] \D [4] \D [5] \D [6] \D [7] }
connect \S { $procmux$10_CMP $procmux$9_CMP $procmux$8_CMP $procmux$7_CMP $procmux$6_CMP $procmux$5_CMP $procmux$4_CMP $procmux$3_CMP }
connect \Y $procmux$2_Y
end
backends/write_ilang/write_ilang__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_ilang result.out
design -reset
read_ilang result.out
backends/write_ilang/write_ilang_error_fail.pat 0 → 100644
ERROR: Can't open file `tt/file1.il' for writing: No such file or directory
backends/scripts/write_ilang_error.ys → backends/write_ilang/write_ilang_error_fail.ys
...@@ -5,4 +5,3 @@ dump -o file.il ...@@ -5,4 +5,3 @@ dump -o file.il
write_ilang ilang.ilang write_ilang ilang.ilang
dump -n -o tt/file1.il dump -n -o tt/file1.il
synth synth
write_verilog synth.v
backends/scripts/write_ilang.ys → backends/write_ilang/write_ilang_fsm.ys
read_verilog ../top.v read_verilog ../top_fsm.v
write_ilang ilang.ilang write_ilang ilang.ilang
proc proc
dump -o file.il dump -o file.il
write_ilang ilang.ilang write_ilang result.out
dump -n -o file1.il dump -n -o file1.il
synth design -reset
write_verilog synth.v read_ilang result.out
backends/write_ilang/write_ilang_mem.pat 0 → 100644
cell $mem \ram
parameter \ABITS 6
parameter \INIT 512'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
parameter \MEMID "\\ram"
parameter \OFFSET 0
parameter \RD_CLK_ENABLE 2'00
parameter \RD_CLK_POLARITY 2'00
parameter \RD_PORTS 2
parameter \RD_TRANSPARENT 2'00
parameter \SIZE 64
parameter \WIDTH 8
parameter \WR_CLK_ENABLE 2'11
parameter \WR_CLK_POLARITY 2'11
parameter \WR_PORTS 2
connect \RD_ADDR { \addr_b \addr_a }
connect \RD_CLK 2'xx
connect \RD_DATA { $memrd$\ram$../top_mem.v:40$12_DATA $memrd$\ram$../top_mem.v:26$7_DATA }
connect \RD_EN 2'xx
connect \WR_ADDR { $0$memwr$\ram$../top_mem.v:35$2_ADDR[5:0]$9 $0$memwr$\ram$../top_mem.v:21$1_ADDR[5:0]$4 }
connect \WR_CLK { \clkb \clka }
connect \WR_DATA { $0$memwr$\ram$../top_mem.v:35$2_DATA[7:0]$10 $0$memwr$\ram$../top_mem.v:21$1_DATA[7:0]$5 }
connect \WR_EN { $0$memwr$\ram$../top_mem.v:35$2_EN[7:0]$11 $0$memwr$\ram$../top_mem.v:21$1_EN[7:0]$6 }
end
backends/write_ilang/write_ilang_mem.ys 0 → 100644
read_verilog ../top_mem.v
write_ilang result2.out
proc
write_ilang result1.out
memory
dump -o file.il
write_ilang result.out
dump -n -o file1.il
design -reset
read_ilang result.out
backends/write_ilang/write_ilang_mux.ys 0 → 100644
read_verilog ../top_mux.v
write_ilang ilang.ilang
proc
dump -o file.il
write_ilang result.out
dump -n -o file1.il
design -reset
read_ilang result.out
backends/scripts/write_ilang_selected.ys → backends/write_ilang/write_ilang_selected.ys
...@@ -4,4 +4,5 @@ proc ...@@ -4,4 +4,5 @@ proc
dump -a file.il dump -a file.il
write_ilang -selected ilang.ilang write_ilang -selected ilang.ilang
dump -m -a file1.il dump -m -a file1.il
write_verilog synth.v design -reset
read_ilang ilang.ilang
backends/write_ilang/write_ilang_tri.pat 0 → 100644
cell $mux $ternary$../top_tri.v:10$2
parameter \WIDTH 1
connect \A 1'z
connect \B \en
connect \S \i
connect \Y $ternary$../top_tri.v:10$2_Y
end
attribute \src "../top_tri.v:8"
cell $mux $ternary$../top_tri.v:8$1
parameter \WIDTH 1
connect \A 1'z
connect \B \i
connect \S \en
connect \Y $ternary$../top_tri.v:8$1_Y
end
backends/write_ilang/write_ilang_tri.ys 0 → 100644
read_verilog ../top_tri.v
write_ilang ilang.ilang
proc
dump -o file.il
write_ilang result.out
dump -n -o file1.il
design -reset
read_ilang result.out
backends/write_ilang_error/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
reg patt_B = 0;
wire B;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
always @(negedge in[0]) begin
if (in[1:2] || in[3:4] && in[5:6])
patt_B <= in[7] & in[5:6];
if (in[1:2] || in[3:4] && !in[5:6])
patt_B <= in[7] | in[1:2];
end
assert_tri out_test(.A(patt_B), .B(B), .en(1'b1));
endmodule
backends/write_ilang_error/top.v deleted 100644 → 0
module top
(
input [1:0] x,
input [1:0] y,
input [1:0] z,
input clk,
input A,
output reg B
);
initial begin
B = 0;
end
`ifndef BUG
always @(posedge clk) begin
if (x || y && z)
B <= A & z;
if (x || y && !z)
B <= A | x;
end
`else
always @(posedge clk) begin
B = z - y + x;
end
`endif
endmodule
backends/write_ilang_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_ilang_fsm/top.v deleted 100644 → 0
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
backends/write_ilang_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_ilang_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_ilang_mux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
backends/write_ilang_mux/top.v deleted 100644 → 0
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_ilang_tri/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_ilang_tri/top.v deleted 100644 → 0
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/write_intersynth/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_intersynth/top.v
...@@ -5,23 +5,22 @@ module top ...@@ -5,23 +5,22 @@ module top
input cin, input cin,
output reg A, output reg A,
output reg cout output reg cout,
output c
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG assign c = 1'b0;
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_intersynth/write_intersynth.pat 0 → 100644
node $procdff$7 $dff CLK x Q A D $add$../top.v:20$2_Y CLK_POLARITY '1 WIDTH 0x1
node $procdff$6 $dff CLK x Q cout D $add$../top.v:23$4_Y CLK_POLARITY '0 WIDTH 0x1
node $add$../top.v:23$4 $add Y $add$../top.v:23$4_Y B A A y Y_WIDTH 0x1 B_WIDTH 0x1 A_WIDTH 0x1 B_SIGNED 0x0 A_SIGNED 0x0
node $add$../top.v:20$2 $add Y $add$../top.v:20$2_Y B cin A y Y_WIDTH 0x1 B_WIDTH 0x1 A_WIDTH 0x1 B_SIGNED 0x0 A_SIGNED 0x0
# constant cells
node CONST_1_0x0 CONST_1 CONST CONST_1_0x0 VALUE 0x0
backends/scripts/write_edif_attrprop.ys → backends/write_intersynth/write_intersynth.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_edif -attrprop edif.edif write_intersynth result.out
write_verilog synth.v
backends/write_intersynth/write_intersynth__latches.pat 0 → 100644
node $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch Q q D $procmux$2_Y EN $auto$rtlil.cc:1844:Not$13 WIDTH 0x1 EN_POLARITY 0x1
node $auto$proc_dlatch.cc:409:proc_dlatch$12 $not Y $auto$rtlil.cc:1844:Not$13 A $auto$rtlil.cc:1848:ReduceOr$11 Y_WIDTH 0x1 A_WIDTH 0x1 A_SIGNED 0x0
backends/write_intersynth/write_intersynth__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_intersynth result.out
backends/write_intersynth/write_intersynth__memory.pat 0 → 100644
node ram $mem RD_EN CONST_1_0x0 RD_DATA $memrd$\\ram$../../common/memory.v:19$6_DATA RD_ADDR addr_a RD_CLK CONST_1_0x0 WR_EN $memwr$\\ram$../../common/memory.v:16$1_EN WR_DATA $memwr$\\ram$../../common/memory.v:16$1_DATA WR_ADDR $memwr$\\ram$../../common/memory.v:16$1_ADDR WR_CLK CONST_1_0x0 RD_TRANSPARENT '0 RD_CLK_POLARITY '0 RD_CLK_ENABLE '0 RD_PORTS 0x1 WR_CLK_POLARITY '0 WR_CLK_ENABLE '0 WR_PORTS 0x1 INIT '00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ABITS 0x6 SIZE 0x40 OFFSET 0x0 WIDTH 0x8 MEMID 0x5c72616d
backends/write_intersynth/write_intersynth__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory_collect
write_intersynth result.out
backends/write_intersynth/write_intersynth__mul.pat 0 → 100644
node $mul$../../common/mul.v:8$1 $mul Y $mul$../../common/mul.v:8$1_Y B y A x Y_WIDTH 0xc B_WIDTH 0x6 A_WIDTH 0x6 B_SIGNED 0x0 A_SIGNED 0x0
backends/write_intersynth/write_intersynth__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_intersynth result.out
backends/write_intersynth/write_intersynth__tribuf.pat 0 → 100644
node $ternary$../../common/tribuf.v:7$2 $mux Y $ternary$../../common/tribuf.v:7$2_Y S en B i A CONST_1_0x0 WIDTH 0x1
backends/write_intersynth/write_intersynth__tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_intersynth result.out
backends/write_intersynth/write_intersynth_cant_export_fail.pat 0 → 100644
ERROR: Can't export composite or non-word-wide signal { \\y \\A }.
backends/scripts/write_intersynth_cant_export.ys → backends/write_intersynth/write_intersynth_cant_export_fail.ys
...@@ -3,4 +3,3 @@ proc ...@@ -3,4 +3,3 @@ proc
synth synth
abc -lut 4 abc -lut 4
write_intersynth intersynth.intersynth write_intersynth intersynth.intersynth
write_verilog synth.v
backends/scripts/write_intersynth_cant_open_lib_file.ys → backends/write_intersynth/write_intersynth_cant_open_lib_file_fail.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_intersynth -lib u intersynth.intersynth write_intersynth -lib u intersynth.intersynth
write_verilog synth.v
backends/scripts/write_edif_top.ys → backends/write_intersynth/write_intersynth_lib.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_edif -top top edif.edif write_intersynth -lib ../top.v result.out
write_verilog synth.v
backends/scripts/write_smt2_mem_memtest.ys → backends/write_intersynth/write_intersynth_notypes.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory write_intersynth -notypes result.out
write_smt2 -mem smt2.smt2
write_verilog synth.v
backends/scripts/write_intersynth_lib.ys → backends/write_intersynth/write_intersynth_selected.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_intersynth -lib ../top.v intersynth.intersynth write_intersynth -selected result.out
write_verilog synth.v
backends/write_intersynth/write_intersynth_unprocessed_proc_fail.pat 0 → 100644
ERROR: Can't generate a netlist for a module with unprocessed memories or processes!
backends/scripts/write_intersynth_unprocessed_proc.ys → backends/write_intersynth/write_intersynth_unprocessed_proc_fail.ys
read_verilog ../top.v read_verilog ../top.v
write_intersynth intersynth.intersynth write_intersynth intersynth.intersynth
write_verilog synth.v
backends/write_intersynth_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_intersynth_error/top2.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/scripts/json.ys → backends/write_json/json.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
json json
write_verilog synth.v
backends/scripts/json_aig.ys → backends/write_json/json_aig.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
json -aig json -aig
write_verilog synth.v
backends/write_json/json_o.pat 0 → 100644
"cells": {
"$add$../top.v:17$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "../top.v:17"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$../top.v:20$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "../top.v:20"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "0",
"WIDTH": 1
},
"attributes": {
"src": "../top.v:19"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../top.v:16"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
backends/write_json/json_o.ys 0 → 100644
read_verilog ../top.v
proc
json -o result.out
design -reset
read_json result.out
backends/write_json/json_o_aig.pat 0 → 100644
"model": "$add:0:0:1:1:1",
backends/scripts/write_intersynth.ys → backends/write_json/json_o_aig.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_intersynth intersynth.intersynth json -aig -o result.out
write_verilog synth.v
backends/write_json/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_json/top.v
...@@ -7,21 +7,17 @@ module top ...@@ -7,21 +7,17 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_json/write_json.pat 0 → 100644
"cells": {
"$add$../top.v:17$2": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "../top.v:17"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 4 ],
"Y": [ 7 ]
}
},
"$add$../top.v:20$4": {
"hide_name": 1,
"type": "$add",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 1,
"B_SIGNED": 0,
"B_WIDTH": 1,
"Y_WIDTH": 1
},
"attributes": {
"src": "../top.v:20"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": [ 3 ],
"B": [ 5 ],
"Y": [ 8 ]
}
},
"$procdff$6": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "0",
"WIDTH": 1
},
"attributes": {
"src": "../top.v:19"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 8 ],
"Q": [ 6 ]
}
},
"$procdff$7": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../top.v:16"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": [ 2 ],
"D": [ 7 ],
"Q": [ 5 ]
}
}
},
backends/write_json/write_json.ys 0 → 100644
read_verilog ../top.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__adffs.pat 0 → 100644
"cells": {
"$procdff$3": {
"hide_name": 1,
"type": "$adff",
"parameters": {
"ARST_POLARITY": "1",
"ARST_VALUE": "0",
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../../common/adffs.v:5"
},
"port_directions": {
"ARST": "input",
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"ARST": \[ 4 \],
"CLK": \[ 3 \],
"D": \[ 2 \],
"Q": \[ 5 \]
}
}
},
backends/write_json/write_json__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__dffs.pat 0 → 100644
"cells": {
"$procdff$2": {
"hide_name": 1,
"type": "$dff",
"parameters": {
"CLK_POLARITY": "1",
"WIDTH": 1
},
"attributes": {
"src": "../../common/dffs.v:2"
},
"port_directions": {
"CLK": "input",
"D": "input",
"Q": "output"
},
"connections": {
"CLK": \[ 3 \],
"D": \[ 2 \],
"Q": \[ 4 \]
}
}
},
backends/write_json/write_json__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__latches.pat 0 → 100644
"$auto$proc_dlatch.cc:409:proc_dlatch$14": {
"hide_name": 1,
"type": "$dlatch",
"parameters": {
"EN_POLARITY": 1,
"WIDTH": 1
},
"attributes": {
"src": "../../common/latches.v:2"
},
"port_directions": {
"D": "input",
"EN": "input",
"Q": "output"
},
"connections": {
"D": \[ 11 \],
"EN": \[ 10 \],
"Q": \[ 5 \]
}
},
backends/write_json/write_json__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__memory.pat 0 → 100644
"ram": {
"hide_name": 0,
"type": "$mem",
"parameters": {
"ABITS": 6,
"INIT": "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx",
"MEMID": "\\ram",
"OFFSET": 0,
"RD_CLK_ENABLE": "0",
"RD_CLK_POLARITY": "0",
"RD_PORTS": 1,
"RD_TRANSPARENT": "0",
"SIZE": 64,
"WIDTH": 8,
"WR_CLK_ENABLE": "0",
"WR_CLK_POLARITY": "0",
"WR_PORTS": 1
},
"attributes": {
},
"port_directions": {
"RD_ADDR": "input",
"RD_CLK": "input",
"RD_DATA": "output",
"RD_EN": "input",
"WR_ADDR": "input",
"WR_CLK": "input",
"WR_DATA": "input",
"WR_EN": "input"
},
"connections": {
"RD_ADDR": \[ 10, 11, 12, 13, 14, 15 \],
"RD_CLK": \[ "x" \],
"RD_DATA": \[ 26, 27, 28, 29, 30, 31, 32, 33 \],
"RD_EN": \[ "x" \],
"WR_ADDR": \[ 40, 41, 42, 43, 44, 45 \],
"WR_CLK": \[ "x" \],
"WR_DATA": \[ 54, 55, 56, 57, 58, 59, 60, 61 \],
"WR_EN": \[ 70, 71, 72, 73, 74, 75, 76, 77 \]
}
}
backends/write_json/write_json__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory_collect
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__mul.pat 0 → 100644
"cells": {
"$mul$../../common/mul.v:8$1": {
"hide_name": 1,
"type": "$mul",
"parameters": {
"A_SIGNED": 0,
"A_WIDTH": 6,
"B_SIGNED": 0,
"B_WIDTH": 6,
"Y_WIDTH": 12
},
"attributes": {
"src": "../../common/mul.v:8"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"connections": {
"A": \[ 2, 3, 4, 5, 6, 7 \],
"B": \[ 8, 9, 10, 11, 12, 13 \],
"Y": \[ 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 \]
}
}
},
backends/write_json/write_json__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__mux.pat 0 → 100644
"$procmux$2": {
"hide_name": 1,
"type": "$pmux",
"parameters": {
"S_WIDTH": 8,
"WIDTH": 1
},
"attributes": {
"full_case": 1,
"src": "../../common/mux.v:20|../../common/mux.v:12"
},
"port_directions": {
"A": "input",
"B": "input",
"S": "input",
"Y": "output"
},
"connections": {
"A": \[ "x" \],
"B": \[ 12, 11, 10, 9, 8, 7, 6, 5 \],
"S": \[ 15, 16, 17, 18, 19, 20, 21, 14 \],
"Y": \[ 13 \]
}
},
backends/write_json/write_json__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_json result.out
design -reset
read_json result.out
backends/write_json/write_json__tribuf.pat 0 → 100644
"cells": {
"$ternary$../../common/tribuf.v:7$2": {
"hide_name": 1,
"type": "$mux",
"parameters": {
"WIDTH": 1
},
"attributes": {
"src": "../../common/tribuf.v:7"
},
"port_directions": {
"A": "input",
"B": "input",
"S": "input",
"Y": "output"
},
"connections": {
"A": \[ "z" \],
"B": \[ 3 \],
"S": \[ 2 \],
"Y": \[ 4 \]
}
}
},
backends/write_json/write_json__tribuf.ys 0 → 100644
read_verilog ../../common/tribuf.v
proc
write_json result.out
design -reset
read_json result.out
backends/scripts/write_intersynth_notypes.ys → backends/write_json/write_json_aig.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_intersynth -notypes intersynth.intersynth write_json -aig result.out
write_verilog synth.v
backends/write_json/write_json_error_fail.pat 0 → 100644
ERROR: Can't open file `tt/json.json' for writing: No such file or directory
backends/scripts/write_json_error.ys → backends/write_json/write_json_error_fail.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
json -o tt/json.json json -o tt/json.json
write_verilog synth.v
backends/write_json_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_json_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_simplec/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_equal b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_equal c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_equal cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_simplec/top.v
module tristate (en, i, o); module mux16 (D, S, Y);
input en; input [15:0] D;
input i; input [3:0] S;
output [1:0] o; output Y;
assign Y = D[S];
wire [1:0] io;
`ifndef BUG
assign io[0] = i & ~en;
assign io[1] = i ? en : ~en;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule endmodule
module top ( module top (
input en, input [3:0] S,
input a, input [15:0] D,
inout [1:0] b, output M16
output [1:0] c
); );
reg A;
tristate u_tri ( initial begin
.en (en ), A = 0;
.i (a ), end
.o (c )
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
); );
endmodule endmodule
backends/scripts/write_smv_noproc.ys → backends/write_simplec/write_simplec.ys
read_verilog ../top.v read_verilog ../top.v
write_smv smv.smv
synth -top top synth -top top
write_verilog synth.v write_simplec result.out
backends/scripts/write_simplec_cmos3.ys → backends/write_simplec/write_simplec_cmos3.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
abc -g cmos3 abc -g cmos3
write_simplec c.c write_simplec result.out
write_verilog synth.v
backends/scripts/write_simplec_cmos4.ys → backends/write_simplec/write_simplec_cmos4.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
abc -g cmos4 abc -g cmos4
write_simplec c.c write_simplec result.out
write_verilog synth.v
backends/scripts/write_simplec_i16.ys → backends/write_simplec/write_simplec_i16.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_simplec -i16 c.c write_simplec -i16 result.out
write_verilog synth.v
backends/scripts/write_simplec_i32.ys → backends/write_simplec/write_simplec_i32.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_simplec -i32 c.c write_simplec -i32 result.out
write_verilog synth.v
backends/scripts/write_simplec_i64.ys → backends/write_simplec/write_simplec_i64.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_simplec -i64 c.c write_simplec -i64 result.out
write_verilog synth.v
backends/scripts/write_simplec_i8.ys → backends/write_simplec/write_simplec_i8.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_simplec -i8 c.c write_simplec -i8 result.out
write_verilog synth.v
backends/write_simplec/write_simplec_no_c_model_fail.pat 0 → 100644
ERROR: No C model for $lut available at the moment (FIXME).
backends/scripts/write_simplec_not_top_module.ys → backends/write_simplec/write_simplec_not_top_module_fail.ys
read_verilog ../top.v read_verilog ../top.v
write_simplec c.c write_simplec c.c
write_verilog synth.v
backends/scripts/write_simplec.ys → backends/write_simplec/write_simplec_verbose.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_simplec c.c write_simplec -verbose result.out
write_verilog synth.v
backends/write_simplec_error/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_equal b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_equal c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_equal cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_simplec_error/top.v deleted 100644 → 0
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = i & ~en;
assign io[1] = i ? en : ~en;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_simplec_logic/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
wire patt_B;
wire B;
wire x,y,z,A;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
assign patt_B = (x || y || !z)? (A & z) : ~x;
assign x = in[1:2];
assign y = in[3:4];
assign z = in[5:6];
assign A = in[7];
assert_comb out_test(.A(patt_B), .B(B));
endmodule
backends/write_simplec_logic/top.v deleted 100644 → 0
module top
(
input x,
input y,
input z,
input clk,
input A,
output B
);
`ifndef BUG
assign B = (x || y || !z)? (A & z) : ~x;
`else
assign B = z - y + x;
`endif
endmodule
backends/write_simplec_mux/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M16;
top uut (
.S (S ),
.D (D ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
backends/write_simplec_mux/top.v deleted 100644 → 0
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
`ifndef BUG
assign Y = D[S];
`else
assign Y = D[S+1];
`endif
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M16
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_smt2/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_smt2/top.v
module tristate (en, i, o); module tristate (en, i, o);
input en; input en;
input i; input i;
output [1:0] o; output [1:0] o;
wire [1:0] io; wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ; assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ; assign io[1] = (i)? en : 1'bZ;
assign o = io; assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule endmodule
......
backends/write_smt2/top_cyclic_dep.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
top utop (en,i,o,io);
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_smt2/top_fsm.v 0 → 100644
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
backends/write_smt2/top_init_assert.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout,
output reg B,C
);
reg ASSERT = 1;
(* allconst *) reg foo;
(* allseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(posedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
assign {B,C} = {cout,A} << 1;
endmodule
backends/write_smt2/top_logic.v 0 → 100644
module top
(
input x,
input y,
input z,
input clk,
input A,
output B
);
assign B = (x || y || !z)? (A & z) : ~x;
endmodule
backends/write_smt2/top_logic_loop.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? o[1] : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_edif_error/top2.v → backends/write_smt2/top_mem.v
...@@ -2,43 +2,35 @@ module top ...@@ -2,43 +2,35 @@ module top
( (
input [7:0] data_a, data_b, input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b, input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk, input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b output reg [7:0] q_a, q_b
); );
// Declare the RAM variable // Declare the RAM variable
reg [7:0] ram[63:0]; reg [7:0] ram[63:0];
initial begin initial begin
q_a <= 8'h00; q_a <= 8'h00;
q_b <= 8'd0; q_b <= 8'd0;
end end
// Port A // Port A
always @ (posedge clk) always @ (posedge clka)
begin begin
`ifndef BUG if (we_a)
if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
end end
if (re_b) if (re_b)
begin begin
q_a <= ram[addr_a]; q_a <= ram[addr_a];
end end
end end
// Port B // Port B
always @ (posedge clk) always @ (posedge clkb)
begin begin
`ifndef BUG if (we_b)
if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
...@@ -48,5 +40,5 @@ module top ...@@ -48,5 +40,5 @@ module top
q_b <= ram[addr_b]; q_b <= ram[addr_b];
end end
end end
endmodule endmodule
backends/write_smt2/top_multiple_drivers.v 0 → 100644
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign io[0] = (~en)? ~i : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_btor_init_assert/top_clean.v → backends/write_smt2/top_reduce.v
...@@ -7,21 +7,26 @@ module top ...@@ -7,21 +7,26 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg A1,cout1;
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A1 <= ~y + &cin;
end
always @(posedge x) begin
cout1 <= cin ? |y : ^A;
end
always @(posedge x) begin
A <= A1|y~&cin~^A1;
end end
always @(negedge x) begin always @(posedge x) begin
cout <= y + A; cout <= cout1&cin~|y;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_smt2/top_shiftx.v 0 → 100644
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer signed i = 0, j = 0;
reg signed [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/scripts/write_intersynth_selected.ys → backends/write_smt2/write_smt2.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_intersynth -selected intersynth.intersynth write_smt2 result.out
write_verilog synth.v
backends/scripts/write_smt2_anyseq.ys → backends/write_smt2/write_smt2_anyseq.ys
read_verilog ../top.v read_verilog ../top_mem.v
proc proc
setundef -anyseq setundef -anyseq
memory memory
write_smt2 -mem smt2.smt2 write_smt2 -mem result.out
write_verilog synth.v
backends/write_smt2/write_smt2_bv.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory
write_smt2 -bv result.out
backends/scripts/write_smt2_cant_open_tpl.ys → backends/write_smt2/write_smt2_cant_open_tpl_fail.ys
...@@ -2,4 +2,3 @@ read_verilog ../top.v ...@@ -2,4 +2,3 @@ read_verilog ../top.v
proc proc
memory memory
write_smt2 -tpl u smt2.smt2 write_smt2 -tpl u smt2.smt2
write_verilog synth.v
backends/write_smt2/write_smt2_cyclic_dependency_fail.pat 0 → 100644
ERROR: Cyclic dependency between modules found! Cycle includes module tristate.
backends/scripts/write_smt2.ys → backends/write_smt2/write_smt2_cyclic_dependency_fail.ys
read_verilog ../top.v read_verilog ../top_cyclic_dep.v
proc proc
memory memory
write_smt2 smt2.smt2 write_smt2 smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_init_assert.ys → backends/write_smt2/write_smt2_init_assert.ys
read_verilog -sv ../top.v read_verilog -sv ../top_init_assert.v
proc proc
write_smt2 -stbv smt2.smt2 write_smt2 -stbv smt2.smt2
synth -top top synth -top top
write_smt2 -stbv smt2.smt2 write_smt2 -stbv smt2.smt2
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
backends/write_smt2/write_smt2_logic.ys 0 → 100644
read_verilog ../top_logic.v
proc
write_smt2 result.out
backends/scripts/write_smt2_cyclic_dependency.ys → backends/write_smt2/write_smt2_logic_loop_fail.ys
read_verilog ../top3.v read_verilog ../top_logic_loop.v
proc proc
memory memory
write_smt2 smt2.smt2 write_smt2 smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_mem.ys → backends/write_smt2/write_smt2_mem.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory memory
write_smt2 -mem smt2.smt2 write_smt2 -mem result.out
write_verilog synth.v
backends/write_smt2/write_smt2_mem_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
memory
write_smt2 -mem result.out
backends/write_smt2/write_smt2_mem_memtest.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory
write_smt2 -mem result.out
backends/write_smt2/write_smt2_memtest.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory
write_smt2 result.out
backends/scripts/write_smt2_logic_loop.ys → backends/write_smt2/write_smt2_multiple_drivers_fail.ys
read_verilog ../top1.v read_verilog ../top_multiple_drivers.v
proc proc
memory memory
write_smt2 smt2.smt2 write_smt2 smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_nobv.ys → backends/write_smt2/write_smt2_nobv.ys
read_verilog ../top.v read_verilog ../top.v
synth synth
write_smt2 -nobv smt2.smt2 write_smt2 -nobv result.out
write_verilog synth.v
backends/write_smt2/write_smt2_nobv_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
synth
write_smt2 -nobv result.out
backends/scripts/write_json.ys → backends/write_smt2/write_smt2_nomem.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_json json.json write_smt2 -nomem result.out
write_verilog synth.v
backends/write_smt2/write_smt2_reduce.ys 0 → 100644
read_verilog ../top_reduce.v
proc
write_smt2 result.out
backends/write_smt2/write_smt2_shiftx.ys 0 → 100644
read_verilog ../top_shiftx.v
proc
write_smt2 result.out
backends/scripts/write_json_aig.ys → backends/write_smt2/write_smt2_stbv.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_json -aig json.json write_smt2 -stbv result.out
write_verilog synth.v
backends/write_smt2/write_smt2_stbv_memtest.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory
write_smt2 -stbv result.out
backends/scripts/write_smv.ys → backends/write_smt2/write_smt2_stdt.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_smv smv.smv write_smt2 -stdt result.out
write_verilog synth.v
backends/scripts/write_simplec_verbose.ys → backends/write_smt2/write_smt2_synth.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_simplec -verbose c.c write_smt2 result.out
write_verilog synth.v
backends/scripts/write_smv_tpl.ys → backends/write_smt2/write_smt2_tpl.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_smv -tpl ../top.tpl smv.smv write_smt2 -tpl ../top.tpl result.out
write_verilog synth.v
backends/scripts/write_smt2_bv.ys → backends/write_smt2/write_smt2_verbose.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory memory
write_smt2 -bv smt2.smt2 write_smt2 -verbose result.out
write_verilog synth.v
backends/write_smt2/write_smt2_verbose_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
memory
write_smt2 -verbose result.out
backends/scripts/write_smv_verbose.ys → backends/write_smt2/write_smt2_wires.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_smv -verbose smv.smv write_smt2 -wires result.out
write_verilog synth.v
backends/write_smt2_error/top.v deleted 100644 → 0
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_smt2_error/top1.v deleted 100644 → 0
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? o[1] : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_smt2_error/top2.v deleted 100644 → 0
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign io[0] = (~en)? ~i : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_smt2_error/top3.v deleted 100644 → 0
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
top utop (en,i,o,io);
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_smt2_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_smt2_fsm/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smt2_fsm/top.v deleted 100644 → 0
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
backends/write_smt2_init_assert/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_smt2_init_assert/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smt2_init_assert/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout,
output reg B,C
);
reg ASSERT = 1;
(* allconst *) reg foo;
(* allseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(posedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
assign {B,C} = {cout,A} << 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_smt2_init_assert/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_smt2_logic/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
wire patt_B;
wire B;
wire x,y,z,A;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
assign patt_B = (x || y || !z)? (A & z) : ~x;
assign x = in[1:2];
assign y = in[3:4];
assign z = in[5:6];
assign A = in[7];
assert_comb out_test(.A(patt_B), .B(B));
endmodule
backends/write_smt2_logic/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smt2_logic/top.v deleted 100644 → 0
module top
(
input x,
input y,
input z,
input clk,
input A,
output B
);
`ifndef BUG
assign B = (x || y || !z)? (A & z) : ~x;
`else
assign B = z - y + x;
`endif
endmodule
backends/write_smt2_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_smt2_mem/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smt2_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_smt2_nobv/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA;
wire [1:0] dinB;
wire [1:0] dinC;
top uut (
.en (en ),
.a (dinA ),
.b (dinB ),
.c (dinC )
);
initial begin
dinA <= 1;
#10
dinA <= 0;
#10
dinA <= 1;
end
endmodule
backends/write_smt2_nobv/top.v deleted 100644 → 0
module tristate (en, i, o);
input en;
input i;
output [1:0] o;
wire [1:0] io;
assign io[0] = i & ~en;
assign io[1] = i ? en : ~en;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.o (c )
);
endmodule
backends/write_smt2_reduce/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_smt2_reduce/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smt2_reduce/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg A1,cout1;
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A1 <= ~y + &cin;
end
always @(posedge x) begin
cout1 <= cin ? |y : ^A;
end
always @(posedge x) begin
A <= A1|y~&cin~^A1;
end
always @(posedge x) begin
cout <= cout1&cin~|y;
end
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
backends/write_smt2_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg [4:0] in;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
wire out,y;
top uut (
.a(in),
.y(out)
);
integer i, j;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[in];
assert_comb out_test(.A(y), .B(out));
endmodule
backends/write_smt2_shiftx/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smt2_shiftx/top.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer signed i = 0, j = 0;
reg signed [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_smt2_shiftx/top_clean.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input [4:0] a;
output y;
integer i = 0, j = 0;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_smv/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_smv/top.v
module tristate (en, i, io, o); module tristate (en, i, io, o);
input en; input en;
input i; input i;
inout [1:0] io; inout [1:0] io;
output [1:0] o; output [1:0] o;
wire [1:0] io; wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ; assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ; assign io[1] = (i)? en : 1'bZ;
assign o = io; assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule endmodule
......
backends/write_smv/top_cmos4_mux.v 0 → 100644
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M16
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_smv/top_fsm.v 0 → 100644
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
backends/write_btor/top_clean.v → backends/write_smv/top_fulladder.v
...@@ -7,21 +7,17 @@ module top ...@@ -7,21 +7,17 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_btor_shift/top_clean.v → backends/write_smv/top_init_assert.v
...@@ -5,23 +5,23 @@ module top ...@@ -5,23 +5,23 @@ module top
input cin, input cin,
output reg A, output reg A,
output reg cout output reg cout,
output reg B,C
); );
reg ASSERT = 1;
initial begin initial begin
A = 0; begin
cout = 0; A = 0;
cout = 0;
end
end end
`ifndef BUG assign A = y + cin;
always @(posedge x) begin assign cout = y + A;
A <= y + cin; always @*
end assert(ASSERT);
always @(negedge x) begin assign {B,C} = {cout,A} <<< 1;
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_smv/top_logic.v 0 → 100644
module top
(
input x,
input y,
input z,
input clk,
input A,
output signed B,
output signed C,D,E
);
assign B = (x || y || !z)? (A & z) : ~x;
assign {D,C} = {y,z} >>> 1;
assign E = {x,y,z} / 3;
endmodule
backends/write_btor_error/top3.v → backends/write_smv/top_mem.v
...@@ -2,7 +2,7 @@ module top ...@@ -2,7 +2,7 @@ module top
( (
input [7:0] data_a, data_b, input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b, input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk, input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b output reg [7:0] q_a, q_b
); );
// Declare the RAM variable // Declare the RAM variable
...@@ -14,13 +14,9 @@ module top ...@@ -14,13 +14,9 @@ module top
end end
// Port A // Port A
always @ (posedge clk) always @ (posedge clka)
begin begin
`ifndef BUG
if (we_a) if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
...@@ -32,66 +28,9 @@ module top ...@@ -32,66 +28,9 @@ module top
end end
// Port B // Port B
always @ (posedge clk) always @ (posedge clkb)
begin begin
`ifndef BUG
if (we_b) if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
module top2
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
......
backends/write_smv/top_noproc_reduce.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire A1,cout1;
assign A1 = ~y + &cin;
assign cout1 = cin ? |y : ^A;
assign A = A1|y~&cin~^A1;
assign cout = cout1&cin~|y;
endmodule
backends/write_smv/top_shift.v 0 → 100644
module top
(
input signed x,
input signed y,
input signed cin,
output signed A,
output signed cout,
output signed B,C
);
assign A = y >> x;
assign cout = y + A >>> y;
assign {B,C} = {cout,A} << 1;
endmodule
backends/write_smv/top_shiftx.v 0 → 100644
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer signed i = 0, j = 0;
reg signed [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_smv/top_wide_tri.v 0 → 100644
module tristate (en, i, io, o);
input en;
input [3:0] i;
inout [3:0] io;
output [1:0] o;
wire [3:0] io;
assign io[1:0] = (en)? i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0])? en : 1'bZ;
assign o = io[2:1];
endmodule
module top (
input en,
input [3:0] a,
inout [3:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/write_smv/write_smv.pat 0 → 100644
_$ternary$###top#v#11$2_Y := bool(_i) ? _en : 0ub1_0;
_$ternary$###top#v#9$1_Y := bool(_en) ? _i : 0ub1_0;
_io := (_$ternary$###top#v#11$2_Y :: _$ternary$###top#v#9$1_Y);
_o := (_$ternary$###top#v#11$2_Y :: _$ternary$###top#v#9$1_Y);
backends/scripts/write_spice.ys → backends/write_smv/write_smv.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice sp.sp write_smv result.out
write_verilog synth.v
backends/write_smv/write_smv__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_smv result.out
backends/write_smv/write_smv__memory.pat 0 → 100644
ASSIGN
next(_q_a) := _$memory#ram$rdreg#0#$d$149;
next(_ram#63#) := (_$memory#ram$wrmux#63##0##7#$y$2586 :: _$memory#ram$wrmux#63##0##6#$y$2582 :: _$memory#ram$wrmux#63##0##5#$y$2578 :: _$memory#ram$wrmux#63##0##4#$y$2574 :: _$memory#ram$wrmux#63##0##3#$y$2570 :: _$memory#ram$wrmux#63##0##2#$y$2566 :: _$memory#ram$wrmux#63##0##1#$y$2562 :: _$memory#ram$wrmux#63##0##0#$y$2558);
backends/write_smv/write_smv__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory
write_smv result.out
backends/write_smv/write_smv__mul.pat 0 → 100644
DEFINE
_$mul$######common#mul#v#8$1_Y := resize(_x, 12) * resize(_y, 12);
_A := _$mul$######common#mul#v#8$1_Y;
backends/write_smv/write_smv__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_smv result.out
backends/write_smv/write_smv__mux.pat 0 → 100644
DEFINE
_$procmux$10_CMP := resize(word1(resize(_S, 3) = resize(0ub3_000, 3)), 1);
_$procmux$9_CMP := resize(word1(resize(_S, 3) = resize(0ub3_001, 3)), 1);
_$procmux$8_CMP := resize(word1(resize(_S, 3) = resize(0ub3_010, 3)), 1);
_$procmux$7_CMP := resize(word1(resize(_S, 3) = resize(0ub3_011, 3)), 1);
_$procmux$6_CMP := resize(word1(resize(_S, 3) = resize(0ub3_100, 3)), 1);
_$procmux$5_CMP := resize(word1(resize(_S, 3) = resize(0ub3_101, 3)), 1);
_$procmux$4_CMP := resize(word1(resize(_S, 3) = resize(0ub3_110, 3)), 1);
_$procmux$2_Y := bool(_$procmux$3_CMP) ? _D[7:7] : bool(_$procmux$4_CMP) ? _D[6:6] : bool(_$procmux$5_CMP) ? _D[5:5] : bool(_$procmux$6_CMP) ? _D[4:4] : bool(_$procmux$7_CMP) ? _D[3:3] : bool(_$procmux$8_CMP) ? _D[2:2] : bool(_$procmux$9_CMP) ? _D[1:1] : bool(_$procmux$10_CMP) ? _D[0:0] : 0ub1_0;
_$procmux$3_CMP := resize(word1(resize(_S, 3) = resize(0ub3_111, 3)), 1);
backends/write_smv/write_smv__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_smv result.out
backends/write_smv/write_smv_cmos4.ys 0 → 100644
read_verilog ../top_cmos4_mux.v
synth -top top
abc -g cmos4
write_smv result.out
backends/write_smv/write_smv_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
proc
write_smv result.out
backends/write_smv/write_smv_fulladder.pat 0 → 100644
_$add$###top_fulladder#v#21$4_Y := resize(_y, 1) + resize(_A, 1);
_$add$###top_fulladder#v#18$2_Y := resize(_y, 1) + resize(_cin, 1);
_$0#A#0#0# := _$add$###top_fulladder#v#18$2_Y;
_$0#cout#0#0# := _$add$###top_fulladder#v#21$4_Y;
backends/write_smv/write_smv_fulladder.ys 0 → 100644
read_verilog ../top_fulladder.v
proc
write_smv result.out
backends/write_smv/write_smv_init_assert.ys 0 → 100644
read_verilog -sv ../top_init_assert.v
synth -top top
write_smv result.out
backends/write_smv/write_smv_logic.ys 0 → 100644
read_verilog ../top_logic.v
proc
write_smv result.out
backends/write_smv/write_smv_noproc.ys 0 → 100644
read_verilog ../top_noproc_reduce.v
write_smv result.out
backends/write_smv/write_smv_shift.pat 0 → 100644
_$shl$###top_shift#v#15$4_Y := 0ub32_00000000000000000000000000000001[31:2] != 0ud30_0 ? 0ud2_0 : resize(resize(_$sshr$###top_shift#v#14$3_Y :: _$shr$###top_shift#v#13$1_Y, 3) << 0ub32_00000000000000000000000000000001[1:0], 2);
_$sshr$###top_shift#v#14$3_Y := resize(unsigned(resize(signed(_$add$###top_shift#v#14$2_Y), 1) >> _y), 1);
backends/write_smv/write_smv_shift.ys 0 → 100644
read_verilog ../top_shift.v
proc
write_smv result.out
backends/write_smv/write_smv_shiftx.pat 0 → 100644
_$shiftx$###top_shiftx#v#21$107_Y := resize(resize(0ub32_10100000100010100010100010101100, 63) >> _a\[4:0\], 1);
backends/write_smv/write_smv_shiftx.ys 0 → 100644
read_verilog ../top_shiftx.v
proc
write_smv result.out
backends/scripts/write_smt2_synth.ys → backends/write_smv/write_smv_synth.ys
read_verilog ../top.v read_verilog ../top.v
synth -top top synth -top top
write_smt2 smt2.smt2 write_smv result.out
write_verilog synth.v
backends/write_smv/write_smv_synth_logic.ys 0 → 100644
read_verilog ../top_logic.v
synth -top top
write_smv result.out
backends/write_smv/write_smv_tpl.pat 0 → 100644
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
backends/scripts/write_smt2_memtest.ys → backends/write_smv/write_smv_tpl.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory write_smv -tpl ../top.tpl result.out
write_smt2 smt2.smt2
write_verilog synth.v
backends/write_smv/write_smv_unsupported_cell_fail.pat 0 → 100644
ERROR: Found currently unsupported cell type $mem (top.ram).
backends/scripts/write_smv_unsupported_cell.ys → backends/write_smv/write_smv_unsupported_cell_fail.ys
read_verilog ../top.v read_verilog ../top_mem.v
proc proc
memory memory
write_smv smv.smv write_smv smv.smv
......
backends/scripts/write_spice_big_endian.ys → backends/write_smv/write_smv_verbose.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice -big_endian sp.sp write_smv -verbose result.out
write_verilog synth.v
backends/write_smv/write_smv_wide_tri.ys 0 → 100644
read_verilog ../top_wide_tri.v
proc
write_smv result.out
backends/write_smv_cmos4/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M16;
top uut (
.S (S ),
.D (D ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
backends/write_smv_cmos4/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_cmos4/top.v deleted 100644 → 0
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
`ifndef BUG
assign Y = D[S];
`else
assign Y = D[S+1];
`endif
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M16
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_smv_error/top.tpl deleted 100644 → 0
asdfsfSmodule u
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_smv_error/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_smv_error/top1.v deleted 100644 → 0
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/write_smv_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_smv_fsm/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_fsm/top.v deleted 100644 → 0
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
backends/write_smv_init_assert/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_smv_init_assert/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_init_assert/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout,
output reg B,C
);
reg ASSERT = 1;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
always @*
assert(ASSERT);
assign {B,C} = {cout,A} <<< 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_smv_init_assert/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_smv_logic/testbench.v deleted 100644 → 0
module testbench;
reg [0:7] in;
wire patt_B;
wire B;
wire x,y,z,A;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[1:2]),
.y(in[3:4]),
.z(in[5:6]),
.clk(in[0]),
.A(in[7]),
.B(B)
);
assign patt_B = (x || y || !z)? (A & z) : ~x;
assign x = in[1:2];
assign y = in[3:4];
assign z = in[5:6];
assign A = in[7];
assert_comb out_test(.A(patt_B), .B(B));
endmodule
backends/write_smv_logic/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_logic/top.v deleted 100644 → 0
module top
(
input x,
input y,
input z,
input clk,
input A,
output signed B,
output signed C,D,E
);
`ifndef BUG
assign B = (x || y || !z)? (A & z) : ~x;
assign {D,C} = {y,z} >>> 1;
assign E = {x,y,z} / 3;
`else
assign B = z - y + x;
`endif
endmodule
backends/write_smv_reduce/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
endmodule
backends/write_smv_reduce/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_reduce/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
wire A1,cout1;
// initial begin
// A = 0;
// cout = 0;
// end
`ifndef BUG
assign A1 = ~y + &cin;
assign cout1 = cin ? |y : ^A;
assign A = A1|y~&cin~^A1;
assign cout = cout1&cin~|y;
`else
assign {cout,A} = 1'bZ;
`endif
endmodule
backends/write_smv_shift/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_smv_shift/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_shift/top.v deleted 100644 → 0
module top
(
input signed x,
input signed y,
input signed cin,
output signed A,
output signed cout,
output signed B,C
);
`ifndef BUG
assign A = y >> x;
assign cout = y + A >>> y;
assign {B,C} = {cout,A} << 1;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_smv_shift/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_smv_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg [4:0] in;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
wire out,y;
top uut (
.a(in),
.y(out)
);
integer i, j;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[in];
assert_comb out_test(.A(y), .B(out));
endmodule
backends/write_smv_shiftx/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_shiftx/top.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer signed i = 0, j = 0;
reg signed [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_smv_shiftx/top_clean.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input [4:0] a;
output y;
integer i = 0, j = 0;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_smv_wide/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg [3:0] dinA = 0;
wire [3:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
assert_dff b_test(.clk(en), .test(dinA[0]), .pat(dioB[0]));
//assert_dff c_test(.clk(en), .test(dinA[0]), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_smv_wide/top.tpl deleted 100644 → 0
; we need QF_UFBV for this poof
(set-logic QF_UFBV)
; insert the auto-generated code here
%%
; declare two state variables s1 and s2
(declare-fun s1 () test_s)
(declare-fun s2 () test_s)
; state s2 is the successor of state s1
(assert (test_t s1 s2))
; we are looking for a model with y non-zero in s1
(assert (distinct (|test_n y| s1) #b0000))
; we are looking for a model with y zero in s2
(assert (= (|test_n y| s2) #b0000))
; is there such a model?
(check-sat)
backends/write_smv_wide/top.v deleted 100644 → 0
module tristate (en, i, io, o);
input en;
input [3:0] i;
inout [3:0] io;
output [1:0] o;
wire [3:0] io;
`ifndef BUG
assign io[1:0] = (en)? i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0])? en : 1'bZ;
assign o = io[2:1];
`else
assign io[1:0] = (en)? ~i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0])? ~en : 1'bZ;
assign o = ~io[2:1];
`endif
endmodule
module top (
input en,
input [3:0] a,
inout [3:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/write_spice/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_spice/top.v
module tristate (en, i, io, o); module tristate (en, i, io, o);
input en; input en;
input i; input i;
inout [1:0] io; inout [1:0] io;
output [1:0] o; output [1:0] o;
wire [1:0] io; wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ; assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ; assign io[1] = (i)? en : 1'bZ;
assign o = io; assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule endmodule
......
backends/write_spice/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_spice/write_spice.pat 0 → 100644
X0 1 i en _NC0 _mux
X1 2 en i _NC1 _mux
backends/scripts/write_spice_inames.ys → backends/write_spice/write_spice.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice -inames sp.sp write_spice result.out
write_verilog synth.v
backends/write_spice/write_spice__add_sub.pat 0 → 100644
X0 1.0 1.1 1.2 1.3 y.0 y.1 y.2 y.3 x.0 x.1 x.2 x.3 _sub
X1 2.0 2.1 2.2 2.3 y.0 y.1 y.2 y.3 x.0 x.1 x.2 x.3 _add
backends/write_spice/write_spice__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_spice result.out
backends/write_spice/write_spice__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_spice result.out
backends/write_spice/write_spice__counter.pat 0 → 100644
X0 clk reset out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 _adff
X1 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.20 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.30 1.31 Vdd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 _add
backends/write_spice/write_spice__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_spice result.out
backends/write_spice/write_spice__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_spice result.out
backends/write_spice/write_spice__latches.pat 0 → 100644
X0 q 1 2 _dlatch
X1 2 3 _not
X2 3 4 _reduce_or
X3 4 5 6 _and
X4 5 Vdd _reduce_or
X5 6 en _not
X6 1 en d d _mux
backends/write_spice/write_spice__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_spice result.out
backends/write_spice/write_spice__logic.pat 0 → 100644
X0 1 in.4 in.5 in.6 in.7 _logic_or
X1 2 in.4 in.5 in.6 in.7 _logic_and
X2 3 in.7 _not
X3 4 in.6 in.7 _xnor
X4 5 in.6 in.7 _xor
X5 6 7 _not
X6 7 in.6 in.7 _or
X7 8 9 _not
X8 9 in.6 in.7 _and
X9 10 in.6 in.7 _or
X10 11 in.6 in.7 _and
backends/write_spice/write_spice__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_spice result.out
backends/write_spice/write_spice__memory.pat 0 → 100644
X1186 1189.0 1189.1 1189.2 1189.3 1189.4 1189.5 1189.6 1189.7 q_a.0 q_a.1 q_a.2 q_a.3 q_a.4 q_a.5 q_a.6 q_a.7 clk _dff
backends/write_spice/write_spice__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
memory
write_spice result.out
backends/write_spice/write_spice__mul.pat 0 → 100644
X0 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 y.0 y.1 y.2 y.3 y.4 y.5 x.0 x.1 x.2 x.3 x.4 x.5 _mul
backends/write_spice/write_spice__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_spice result.out
backends/write_spice/write_spice__mux.pat 0 → 100644
X0 1 Vss Vss Vss S.0 S.1 S.2 _eq
X1 2 Vdd Vss Vss S.0 S.1 S.2 _eq
X2 3 Vss Vdd Vss S.0 S.1 S.2 _eq
X3 4 Vdd Vdd Vss S.0 S.1 S.2 _eq
X4 5 Vss Vss Vdd S.0 S.1 S.2 _eq
X5 6 Vdd Vss Vdd S.0 S.1 S.2 _eq
X6 7 Vss Vdd Vdd S.0 S.1 S.2 _eq
X7 8 9 7 6 5 4 3 2 1 D.7 D.6 D.5 D.4 D.3 D.2 D.1 D.0 _NC0 _pmux
X8 9 Vdd Vdd Vdd S.0 S.1 S.2 _eq
backends/write_spice/write_spice__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_spice result.out
backends/write_spice/write_spice__shifter.pat 0 → 100644
X0 clk out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 1.0 1.1 1.2 1.3 1.4 1.5 1.6 in _dff
X1 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Vdd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss out.0 out.1 out.2 out.3 out.4 out.5 out.6 out.7 _shr
backends/write_spice/write_spice__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_spice result.out
backends/scripts/write_spice_nc_prefix.ys → backends/write_spice/write_spice_big_endian.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice -nc_prefix sp.sp write_spice -big_endian result.out
write_verilog synth.v
backends/write_spice/write_spice_inames.pat 0 → 100644
X0 _ternary_../top.v:11_2_Y i en _NC0 _mux
X1 _ternary_../top.v:9_1_Y en i _NC1 _mux
backends/scripts/json_o.ys → backends/write_spice/write_spice_inames.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
json -o json.json write_spice -inames result.out
write_verilog synth.v
backends/write_spice/write_spice_nc_prefix.pat 0 → 100644
X0 1 i en _NotCon0 _mux
X1 2 en i _NotCon1 _mux
backends/scripts/write_spice_neg_i.ys → backends/write_spice/write_spice_nc_prefix.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice -neg i sp.sp write_spice -nc_prefix _NotCon result.out
write_verilog synth.v
backends/scripts/write_spice_pos_i.ys → backends/write_spice/write_spice_neg_i.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice -pos i sp.sp write_spice -neg i result.out
write_verilog synth.v
backends/scripts/write_spice_top.ys → backends/write_spice/write_spice_pos_i.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_spice -top top sp.sp write_spice -pos i result.out
write_verilog synth.v
backends/scripts/write_smt2_nomem.ys → backends/write_spice/write_spice_top.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
memory write_spice -top top result.out
write_smt2 -nomem smt2.smt2
write_verilog synth.v
backends/write_spice/write_spice_top_n.pat 0 → 100644
.SUBCKT top en a b.0 b.1 c.0 c.1
backends/write_spice/write_spice_unmapped_mem_fail.pat 0 → 100644
ERROR: Found unmapped memories in module top: unmapped memories are not supported in SPICE backend!
backends/scripts/write_spice_unmapped_mem.ys → backends/write_spice/write_spice_unmapped_mem_fail.ys
read_verilog ../top.v read_verilog ../top_mem.v
proc proc
write_spice sp.sp write_spice sp.sp
write_verilog synth.v write_verilog synth.v
backends/write_spice/write_spice_unmapped_proc_fail.pat 0 → 100644
ERROR: Found unmapped processes in module top: unmapped processes are not supported in SPICE backend!
backends/scripts/write_spice_unmapped_proc.ys → backends/write_spice/write_spice_unmapped_proc_fail.ys
read_verilog ../top.v read_verilog ../top_mem.v
write_spice sp.sp write_spice sp.sp
write_verilog synth.v write_verilog synth.v
backends/write_spice_error/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_table/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_table/top.v
module tristate (en, i, io, o); module tristate (en, i, io, o);
input en; input en;
input i; input i;
inout [1:0] io; inout [1:0] io;
output [1:0] o; output [1:0] o;
wire [1:0] io; wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ; assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ; assign io[1] = (i)? en : 1'bZ;
assign o = io; assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule endmodule
......
backends/write_table/write_table.pat 0 → 100644
tristate $ternary$../top.v:10$2 $mux A in 1'z
tristate $ternary$../top.v:10$2 $mux B in \\en
tristate $ternary$../top.v:10$2 $mux S in \\i
tristate $ternary$../top.v:10$2 $mux Y out $ternary$../top.v:10$2_Y
tristate $ternary$../top.v:8$1 $mux A in 1'z
tristate $ternary$../top.v:8$1 $mux B in \\i
tristate $ternary$../top.v:8$1 $mux S in \\en
tristate $ternary$../top.v:8$1 $mux Y out $ternary$../top.v:8$1_Y
backends/scripts/write_table.ys → backends/write_table/write_table.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
write_table tb.tb write_table result.out
write_verilog synth.v
backends/write_table/write_table__add_sub.pat 0 → 100644
top $add$../../common/add_sub.v:10$1 $add A in \\x
top $add$../../common/add_sub.v:10$1 $add B in \\y
top $add$../../common/add_sub.v:10$1 $add Y out $add$../../common/add_sub.v:10$1_Y
top $sub$../../common/add_sub.v:11$2 $sub A in \\x
top $sub$../../common/add_sub.v:11$2 $sub B in \\y
top $sub$../../common/add_sub.v:11$2 $sub Y out $sub$../../common/add_sub.v:11$2_Y
backends/write_table/write_table__add_sub.ys 0 → 100644
read_verilog ../../common/add_sub.v
proc
write_table result.out
backends/write_table/write_table__adffs.pat 0 → 100644
top $procdff$3 $adff ARST in \\clr
top $procdff$3 $adff CLK in \\clk
top $procdff$3 $adff D in \\d
top $procdff$3 $adff Q out \\q
backends/write_table/write_table__adffs.ys 0 → 100644
read_verilog ../../common/adffs.v
proc
write_table result.out
backends/write_table/write_table__counter.pat 0 → 100644
top $add$../../common/counter.v:10$2 $add A in \\out
top $add$../../common/counter.v:10$2 $add B in 1
top $add$../../common/counter.v:10$2 $add Y out $add$../../common/counter.v:10$2_Y
top $procdff$3 $adff ARST in \\reset
top $procdff$3 $adff CLK in \\clk
top $procdff$3 $adff D in $add$../../common/counter.v:10$2_Y \[7:0\]
top $procdff$3 $adff Q out \\out
backends/write_table/write_table__counter.ys 0 → 100644
read_verilog ../../common/counter.v
proc
write_table result.out
backends/write_table/write_table__dffs.pat 0 → 100644
top $procdff$2 $dff CLK in \\clk
top $procdff$2 $dff D in \\d
top $procdff$2 $dff Q out \\q
backends/write_table/write_table__dffs.ys 0 → 100644
read_verilog ../../common/dffs.v
proc
write_table result.out
backends/write_table/write_table__latches.pat 0 → 100644
top $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch D in $procmux$2_Y
top $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch EN in $auto$rtlil.cc:1844:Not$13
top $auto$proc_dlatch.cc:409:proc_dlatch$14 $dlatch Q out \\q
backends/write_table/write_table__latches.ys 0 → 100644
read_verilog ../../common/latches.v
proc
write_table result.out
backends/write_table/write_table__logic.pat 0 → 100644
top $xnor$../../common/logic.v:11$8 $xnor A in \\in [7]
top $xnor$../../common/logic.v:11$8 $xnor B in \\in [6]
top $xnor$../../common/logic.v:11$8 $xnor Y out $xnor$../../common/logic.v:11$8_Y
top $xor$../../common/logic.v:10$7 $xor A in \\in [7]
top $xor$../../common/logic.v:10$7 $xor B in \\in [6]
top $xor$../../common/logic.v:10$7 $xor Y out $xor$../../common/logic.v:10$7_Y
backends/write_table/write_table__logic.ys 0 → 100644
read_verilog ../../common/logic.v
proc
write_table result.out
backends/write_table/write_table__memory.pat 0 → 100644
top $memrd$\\ram$../../common/memory.v:19$6 $memrd ADDR in \\addr_a
top $memrd$\\ram$../../common/memory.v:19$6 $memrd CLK in 1'x
top $memrd$\\ram$../../common/memory.v:19$6 $memrd DATA out $memrd$\\ram$../../common/memory.v:19$6_DATA
top $memrd$\\ram$../../common/memory.v:19$6 $memrd EN in 1'x
top $memwr$\\ram$../../common/memory.v:16$7 $memwr ADDR in $memwr$\\ram$../../common/memory.v:16$1_ADDR
top $memwr$\\ram$../../common/memory.v:16$7 $memwr CLK in 1'x
top $memwr$\\ram$../../common/memory.v:16$7 $memwr DATA in $memwr$\\ram$../../common/memory.v:16$1_DATA
top $memwr$\\ram$../../common/memory.v:16$7 $memwr EN in $memwr$\\ram$../../common/memory.v:16$1_EN
backends/write_table/write_table__memory.ys 0 → 100644
read_verilog ../../common/memory.v
proc
write_table result.out
backends/write_table/write_table__mul.pat 0 → 100644
top $mul$../../common/mul.v:8$1 $mul A in \\x
top $mul$../../common/mul.v:8$1 $mul B in \\y
top $mul$../../common/mul.v:8$1 $mul Y out $mul$../../common/mul.v:8$1_Y
backends/write_table/write_table__mul.ys 0 → 100644
read_verilog ../../common/mul.v
proc
write_table result.out
backends/write_table/write_table__mux.pat 0 → 100644
top $procmux$2 $pmux B in { \\D [0] \\D [1] \\D [2] \\D [3] \\D [4] \\D [5] \\D [6] \\D [7] }
top $procmux$2 $pmux S in { $procmux$10_CMP $procmux$9_CMP $procmux$8_CMP $procmux$7_CMP $procmux$6_CMP $procmux$5_CMP $procmux$4_CMP $procmux$3_CMP }
top $procmux$2 $pmux Y out $procmux$2_Y
backends/write_table/write_table__mux.ys 0 → 100644
read_verilog ../../common/mux.v
proc
write_table result.out
backends/write_table/write_table__shifter.pat 0 → 100644
top $shr$../../common/shifter.v:8$2 $shr A in \\out
top $shr$../../common/shifter.v:8$2 $shr B in 1
top $shr$../../common/shifter.v:8$2 $shr Y out $shr$../../common/shifter.v:8$2_Y
backends/write_table/write_table__shifter.ys 0 → 100644
read_verilog ../../common/shifter.v
proc
write_table result.out
backends/write_verilog/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg [3:0] dinA = 0;
wire [3:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
assert_dff b_test(.clk(en), .test(dinA[0]), .pat(dioB[0]));
//assert_dff c_test(.clk(en), .test(dinA[0]), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_verilog/top.v
...@@ -5,19 +5,12 @@ module tristate (en, i, io, o); ...@@ -5,19 +5,12 @@ module tristate (en, i, io, o);
output [1:0] o; output [1:0] o;
wire [3:0] io; wire [3:0] io;
`ifndef BUG
assign io[1:0] = (en)? i[1:0] : 1'bZ; assign io[1:0] = (en)? i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0])? en : 1'bZ; assign io[3:2] = (i[1:0])? en : 1'bZ;
assign o = io[2:1]; assign o = io[2:1];
`else
assign io[1:0] = (en)? ~i[1:0] : 1'bZ;
assign io[3:2] = (i[1:0])? ~en : 1'bZ;
assign o = ~io[2:1];
`endif
endmodule endmodule
......
backends/write_verilog/top_concat.v 0 → 100644
module top
(
input x,
input [1:0] y,
input z,
output [1:0] A,
output [2:0] B,
output [3:0] C
);
assign A = {x,z};
assign B = {x,y};
assign C = {x,y,z};
endmodule
module test(input [7:0] A, B, output [7:0] Y);
wire [15:0] AB = (A * B) + {A, B}; // merging to create {A, B}
assign Y = AB[15:8] + AB[7:0]; // splitting to create AB[15:8] and AB[7:0]
endmodule
backends/write_verilog/top_concat_signed.v 0 → 100644
module top
(
input signed x,
input signed [1:0] y,
input signed z,
output signed [1:0] A,
output signed [2:0] B,
output signed [3:0] C
);
assign A = {x,z};
assign B = {x,y};
assign C = {x,y,z};
endmodule
module test(input [7:0] A, B, output [7:0] Y);
wire [15:0] AB = (A * B) + {A, B}; // merging to create {A, B}
assign Y = AB[15:8] + AB[7:0]; // splitting to create AB[15:8] and AB[7:0]
endmodule
backends/write_verilog/top_ffs.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
backends/write_verilog/top_latch.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
backends/write_blif_error/top.v → backends/write_verilog/top_logic.v
...@@ -8,16 +8,16 @@ module top ...@@ -8,16 +8,16 @@ module top
output reg cout output reg cout
); );
reg A1,cout1; reg A1,cout1,A2;
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A1 <= ~y + &cin; A1 <= ~y + &cin;
A2 <= y ~^ cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout1 <= cin ? |y : ^A; cout1 <= cin ? |y : ^A;
...@@ -31,9 +31,6 @@ always @(*) begin ...@@ -31,9 +31,6 @@ always @(*) begin
if (~x) if (~x)
cout <= cout1&cin~|y; cout <= cout1&cin~|y;
end end
`else
assign {cout,A} = 1'bZ;
`endif
bb ubb (cin,y,x,A); bb ubb (cin,y,x,A);
......
backends/write_blif_error/top2.v → backends/write_verilog/top_mem.v
...@@ -7,38 +7,30 @@ module top ...@@ -7,38 +7,30 @@ module top
); );
// Declare the RAM variable // Declare the RAM variable
reg [7:0] ram[63:0]; reg [7:0] ram[63:0];
initial begin initial begin
q_a <= 8'h00; q_a <= 8'h00;
q_b <= 8'd0; q_b <= 8'd0;
end end
// Port A // Port A
always @ (posedge clk) always @ (posedge clk)
begin begin
`ifndef BUG if (we_a)
if (we_a)
`else
if (we_b)
`endif
begin begin
ram[addr_a] <= data_a; ram[addr_a] <= data_a;
q_a <= data_a; q_a <= data_a;
end end
if (re_b) if (re_b)
begin begin
q_a <= ram[addr_a]; q_a <= ram[addr_a];
end end
end end
// Port B // Port B
always @ (posedge clk) always @ (posedge clk)
begin begin
`ifndef BUG if (we_b)
if (we_b)
`else
if (we_a)
`endif
begin begin
ram[addr_b] <= data_b; ram[addr_b] <= data_b;
q_b <= data_b; q_b <= data_b;
...@@ -48,5 +40,5 @@ module top ...@@ -48,5 +40,5 @@ module top
q_b <= ram[addr_b]; q_b <= ram[addr_b];
end end
end end
endmodule endmodule
backends/write_verilog/top_mux.v 0 → 100644
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M16
);
reg A;
initial begin
A = 0;
end
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
backends/write_verilog/top_shift_fsm.v 0 → 100644
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output signed gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg signed [SIZE-1:0] state;
reg signed [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
backends/write_btor_shiftx/top_clean.v → backends/write_verilog/top_shiftx.v
...@@ -3,8 +3,8 @@ ...@@ -3,8 +3,8 @@
module top(a, y); module top(a, y);
input [4:0] a; input signed [4:0] a;
output y; output signed y;
integer i = 0, j = 0; integer i = 0, j = 0;
reg [31:0] lut; reg [31:0] lut;
......
backends/write_verilog/top_tri.v 0 → 100644
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/scripts/write_verilog.ys → backends/write_verilog/write_verilog.ys
...@@ -2,4 +2,4 @@ read_verilog ../top.v ...@@ -2,4 +2,4 @@ read_verilog ../top.v
proc proc
tribuf tribuf
dff2dffe dff2dffe
write_verilog synth.v write_verilog result.out
backends/write_verilog/write_verilog_concat.ys 0 → 100644
read_verilog ../top_concat.v
proc
tribuf
dff2dffe
write_verilog result.out
backends/write_verilog/write_verilog_concat_signed.ys 0 → 100644
read_verilog ../top_concat_signed.v
proc
tribuf
dff2dffe
write_verilog result.out
backends/write_verilog/write_verilog_ffs.ys 0 → 100644
read_verilog ../top_ffs.v
proc
tribuf
dff2dffe
write_verilog result.out
backends/write_verilog/write_verilog_ffs_cmos3.ys 0 → 100644
read_verilog ../top_logic.v
synth -top top
abc -g cmos3
write_verilog result.out
backends/write_verilog/write_verilog_ffs_cmos4.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
abc -g cmos4
stat
write_verilog result.out
backends/write_verilog/write_verilog_ffs_synth.ys 0 → 100644
read_verilog ../top_ffs.v
proc
synth
write_verilog result.out
backends/write_verilog/write_verilog_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
tribuf
dff2dffe
write_verilog result.out
backends/scripts/write_verilog_lut.ys → backends/write_verilog/write_verilog_lut.ys
...@@ -2,4 +2,4 @@ read_verilog ../top.v ...@@ -2,4 +2,4 @@ read_verilog ../top.v
proc proc
synth synth
abc -lut 5 abc -lut 5
write_verilog synth.v write_verilog result.out
backends/write_verilog/write_verilog_mem.ys 0 → 100644
read_verilog ../top_mem.v
proc
memory_collect
stat
write_verilog result.out
backends/scripts/write_verilog_nostr.ys → backends/write_verilog/write_verilog_nostr.ys
...@@ -2,4 +2,4 @@ read_verilog ../top.v ...@@ -2,4 +2,4 @@ read_verilog ../top.v
proc proc
tribuf tribuf
dff2dffe dff2dffe
write_verilog -nostr synth.v write_verilog -nostr result.out
backends/write_verilog/write_verilog_shift.ys 0 → 100644
read_verilog ../top_shift_fsm.v
proc
pmux2shiftx
write_verilog result.out
backends/write_verilog/write_verilog_shiftx.ys 0 → 100644
read_verilog ../top_shiftx.v
proc
tribuf
dff2dffe
write_verilog result.out
backends/scripts/write_verilog_siminit.ys → backends/write_verilog/write_verilog_siminit.ys
...@@ -2,4 +2,4 @@ read_verilog ../top.v ...@@ -2,4 +2,4 @@ read_verilog ../top.v
proc proc
tribuf tribuf
dff2dffe dff2dffe
write_verilog -siminit synth.v write_verilog -siminit result.out
backends/scripts/write_verilog_slice.ys → backends/write_verilog/write_verilog_slice.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
splice splice
write_verilog synth.v write_verilog result.out
backends/write_verilog/write_verilog_tri.ys 0 → 100644
read_verilog ../top_tri.v
proc
tribuf
dff2dffe
write_verilog result.out
backends/scripts/write_verilog_v.ys → backends/write_verilog/write_verilog_v.ys
read_verilog ../top.v read_verilog ../top.v
proc proc
dff2dffe dff2dffe
write_verilog -v synth.v write_verilog -v result.out
backends/write_verilog_concat/testbench.v deleted 100644 → 0
module testbench;
reg [4:0] in;
wire [1:0] Ap;
wire [2:0] Bp;
wire [2:0] Cp;
wire [1:0] A;
wire [2:0] B;
wire [2:0] C;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[2:1]),
.z(in[3]),
.A(A),
.B(B),
.C(C)
);
assign Ap = {in[0],in[3]};
assign Bp = {in[0],in[2:1]};
assign Cp = {in[0],in[2:1],in[3]};
assert_comb A_test(.A(A[0]), .B(Ap[0]));
assert_comb B_test(.A(B[0]), .B(Bp[0]));
assert_comb C_test(.A(C[0]), .B(Cp[0]));
endmodule
backends/write_verilog_concat/top.v deleted 100644 → 0
module top
(
input x,
input [1:0] y,
input z,
output [1:0] A,
output [2:0] B,
output [3:0] C
);
`ifndef BUG
assign A = {x,z};
assign B = {x,y};
assign C = {x,y,z};
`else
assign A = x + z;
assign B = x * y;
assign C = x - y - z;
`endif
endmodule
module test(input [7:0] A, B, output [7:0] Y);
wire [15:0] AB = (A * B) + {A, B}; // merging to create {A, B}
assign Y = AB[15:8] + AB[7:0]; // splitting to create AB[15:8] and AB[7:0]
endmodule
backends/write_verilog_ffs/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
backends/write_verilog_ffs/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
backends/write_verilog_latch/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3;
reg lat,nlat,alat,alatn = 0;
top uut (
.en (en ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( dinA[2] )
lat <= 1'b0;
else if ( dinA[1] )
lat <= 1'b1;
else if ( en )
lat <= dinA[0];
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( !dinA[2] )
nlat <= 1'b0;
else if ( !dinA[1] )
nlat <= 1'b1;
else if (!en)
nlat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( dinA[2] )
alat <= 1'b0;
else if (en)
alat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( !dinA[2] )
alatn <= 1'b0;
else if (!en)
alatn <= dinA[0];
assert_dff lat_test(.clk(en), .test(doutB), .pat(lat));
assert_dff nlat_test(.clk(en), .test(doutB1), .pat(nlat));
assert_dff alat_test(.clk(en), .test(doutB2), .pat(alat));
assert_dff alatn_test(.clk(en), .test(doutB3), .pat(alatn));
endmodule
backends/write_verilog_latch/top.v deleted 100644 → 0
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
backends/write_verilog_shift_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire a = xorshift32(rng * 5);
wire b = xorshift32(rng * 7);
reg rst;
wire g0;
wire g1;
top uut (
.a (a),
.b (b),
.clk (clk),
.rst (rst),
.g0(g0),
.g1(g1)
);
initial begin
rst <= 1;
#5
rst <= 0;
end
assert_Z g0_test(.clk(clk), .A(g0));
assert_Z g1_test(.clk(clk), .A(g1));
endmodule
backends/write_verilog_shift_shiftx/top.v deleted 100644 → 0
module fsm (
clock,
reset,
req_0,
req_1,
gnt_0,
gnt_1
);
input clock,reset,req_0,req_1;
output signed gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
reg signed [SIZE-1:0] state;
reg signed [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
`ifndef BUG
gnt_0 <= 1;
`else
gnt_0 <= 1'bZ;
`endif
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
module top (
input clk,
input rst,
input a,
input b,
output g0,
output g1
);
fsm u_fsm ( .clock(clk),
.reset(rst),
.req_0(a),
.req_1(b),
.gnt_0(g0),
.gnt_1(g1));
endmodule
backends/write_verilog_shiftx/testbench.v deleted 100644 → 0
module testbench;
reg [4:0] in;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
wire out,y;
top uut (
.a(in),
.y(out)
);
integer i, j;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[in];
assert_comb out_test(.A(y), .B(out));
endmodule
backends/write_verilog_shiftx/top.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input signed [4:0] a;
output signed y;
integer i = 0, j = 0;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_verilog_shiftx/top_clean.v deleted 100644 → 0
// VERIFIC-SKIP
module top(a, y);
input [4:0] a;
output y;
integer i = 0, j = 0;
reg [31:0] lut;
initial begin
for (i = 0; i < 32; i = i+1) begin
lut[i] = i > 1;
for (j = 2; j*j <= i; j = j+1)
if (i % j == 0)
lut[i] = 0;
end
end
assign y = lut[a];
endmodule
backends/write_verilog_tri/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
backends/write_verilog_tri/top.v deleted 100644 → 0
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
wire [1:0] io;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
backends/write_xaiger/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_xaiger/top.v
...@@ -7,13 +7,13 @@ module top ...@@ -7,13 +7,13 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
reg ASSERT = 1; reg ASSERT = 1;
(* anyconst *) reg foo; (* anyconst *) reg foo;
(* anyseq *) reg too; (* anyseq *) reg too;
initial begin initial begin
begin begin
A = 0; A = 0;
...@@ -21,23 +21,19 @@ module top ...@@ -21,23 +21,19 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
A <= y + cin + too; A <= y + cin + too;
assume(too); assume(too);
assume(s_eventually too); assume(s_eventually too);
end end
always @(negedge x) begin always @(negedge x) begin
if ($initstate) if ($initstate)
cout <= 0; cout <= 0;
cout <= y + A + foo; cout <= y + A + foo;
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_aiger_error/top.v → backends/write_xaiger/top_cant_find_top.v
...@@ -21,7 +21,7 @@ module top ...@@ -21,7 +21,7 @@ module top
end end
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
if ($initstate) if ($initstate)
A <= 0; A <= 0;
...@@ -36,9 +36,6 @@ always @(negedge x) begin ...@@ -36,9 +36,6 @@ always @(negedge x) begin
assert(ASSERT); assert(ASSERT);
assert(s_eventually ASSERT); assert(s_eventually ASSERT);
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
......
backends/write_xaiger/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_btor_div_mod/top_clean.v → backends/write_xaiger/top_fulladder.v
...@@ -7,21 +7,18 @@ module top ...@@ -7,21 +7,18 @@ module top
output reg A, output reg A,
output reg cout output reg cout
); );
initial begin initial begin
A = 0; A = 0;
cout = 0; cout = 0;
end end
`ifndef BUG
always @(posedge x) begin always @(posedge x) begin
A <= y + cin; A <= y + cin;
end end
always @(negedge x) begin always @(negedge x) begin
cout <= y + A; cout <= y + A;
end end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
backends/write_xaiger/top_mem.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_xaiger/write_xaiger.pat 0 → 100644
aig 17 17 0 10 0
2
10
16
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20
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24
26
28
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backends/write_xaiger/write_xaiger.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__add_sub.pat 0 → 100644
aig 72 8 0 8 64
22
38
58
78
85
104
124
144
backends/write_xaiger/write_xaiger__add_sub.ys 0 → 100644
read_verilog -sv ../../common/add_sub.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__adffs.ys 0 → 100644
read_verilog -sv ../../common/adffs.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__counter.pat 0 → 100644
aig 10 10 0 8 0
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12
14
16
c
backends/write_xaiger/write_xaiger__counter.ys 0 → 100644
read_verilog -sv ../../common/counter.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__dffs.ys 0 → 100644
read_verilog -sv ../../common/dffs.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__latches.ys 0 → 100644
read_verilog -sv ../../common/latches.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__logic.pat 0 → 100644
aig 24 8 0 10 16
18
21
23
24
30
37
17
16
42
49
backends/write_xaiger/write_xaiger__logic.ys 0 → 100644
read_verilog -sv ../../common/logic.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__mux.ys 0 → 100644
read_verilog -sv ../../common/mux.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger__tribuf.ys 0 → 100644
read_verilog -sv ../../common/tribuf.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger_ascii.pat 0 → 100644
aag 17 17 0 10 0
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32
34
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backends/write_xaiger/write_xaiger_ascii.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_xaiger -ascii result.out
backends/write_xaiger/write_xaiger_cant_find_top_module_fail.pat 0 → 100644
ERROR: Can't find top module in current design!
backends/write_xaiger/write_xaiger_cant_find_top_module_fail.ys 0 → 100644
read_verilog -sv ../top_cant_find_top.v
aigmap
write_xaiger xaiger.xaiger
backends/write_xaiger/write_xaiger_cant_open_file_fail.pat 0 → 100644
ERROR: Can't open file `tt/tt.map' for writing: No such file or directory
backends/write_xaiger/write_xaiger_cant_open_file_fail.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_xaiger -map tt/tt.map xaiger.xaiger
backends/write_xaiger/write_xaiger_fsm.ys 0 → 100644
read_verilog -sv ../top_fsm.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger_fulladder.ys 0 → 100644
read_verilog -sv ../top_fulladder.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger_map.pat 0 → 100644
aig 29 17 0 14 12
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58
backends/write_xaiger/write_xaiger_map.ys 0 → 100644
read_verilog -sv ../top.v
proc
aigmap
write_xaiger -map a.map result.out
backends/write_xaiger/write_xaiger_mem.ys 0 → 100644
read_verilog -sv ../top_mem.v
aigmap
write_xaiger result.out
backends/write_xaiger/write_xaiger_vmap.pat 0 → 100644
aig 17 17 0 10 0
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backends/write_xaiger/write_xaiger_vmap.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_xaiger -vmap a.map result.out
backends/write_xaiger_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
wire out;
wire carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
always @(posedge in[0])
patt_out <= in[1] + in[2];
always @(negedge in[0])
patt_carry_out <= in[1] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
backends/write_xaiger_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top2
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_xaiger_error/top2.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout,
output X
);
reg ASSERT = 1'bX;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 1'bX;
cout = 1'bZ;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 1'bX;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 1'bZ;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
assign X = 1'bX;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_xaiger_error/top_clean.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
initial begin
A = 0;
cout = 0;
end
`ifndef BUG
always @(posedge x) begin
A <= y + cin;
end
always @(negedge x) begin
cout <= y + A;
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
backends/write_xaiger_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_xaiger_fsm/top.v deleted 100644 → 0
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (b == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (a == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (a == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (a == 1'b1 && b == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (a == 1'b1 || b == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign s = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign f = (st == S13) ? 1'b1 : 1'b0;
assign bs = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
backends/write_xaiger_fsm/top_clean.v deleted 100644 → 0
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (b == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (a == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (a == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (a == 1'b1 && b == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (a == 1'b1 || b == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign s = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign f = (st == S13) ? 1'b1 : 1'b0;
assign bs = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
backends/write_xaiger_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
reg re_a = 1;
reg re_b = 1;
wire [7:0] q_a,q_b;
reg mem_init = 0;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.re_a(re_a),
.re_b(re_b),
.clka(clk),
.clkb(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
backends/write_xaiger_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
backends/write_xaiger_mem/top_clean.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
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