Merge pull request #27 from SergeyDegtyar/master

Add missing files to frontends and misc; Add new tests to regression.

backends/write_blif/top.v

@@ -45,4 +45,7 @@ endmodule
  input clk;
 
  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
 endmodule

frontends/scripts/verilog_lexer.ys

+read_verilog -sv ../top.v
+proc
+write_verilog synth.v

frontends/scripts/verilog_lexer_assert.ys

+read_verilog -sv ../top2.v
+design -reset
+read_verilog -sv ../top.v
+proc
+write_verilog synth.v

frontends/scripts/verilog_lexer_sv.ys

+read -sv ../top.sv
+proc
+write_verilog synth.v

misc/rename/top.v

@@ -28,6 +28,10 @@ module middle
 	input y,
 	output o
 );
+wire dd;
 
 assign o = x + y;
 endmodule
+
+module low ();
+endmodule

misc/scripts/cutpoint.ys

+read_verilog ../top.v
+tee -o result.log cutpoint top/y top/x top/cout top/A top/cin
+tee -o result.log cutpoint top
+

misc/scripts/cutpoint_undef.ys

+read_verilog ../top.v
+tee -o result.log cutpoint top/y top/x top/cout top/A
+tee -o result.log cutpoint -undef top/cin
+tee -o result.log cutpoint -undef top

misc/scripts/fmcombine.ys

+read_verilog ../top.v
+tee -o result.log fmcombine top u_mid1 u_mid3
+tee -o result.log fmcombine top u_mid2 u_mid4
+tee -o result.log fmcombine top u_mid1_u_mid3 u_mid2_u_mid4
+

misc/scripts/fmcombine_bwd.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -bwd top u_mid1 u_mid2
+

misc/scripts/fmcombine_bwd_fwd.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2
+

misc/scripts/fmcombine_fwd.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -fwd top u_mid1 u_mid2
+

misc/scripts/fmcombine_nop.ys

+read_verilog ../top.v
+tee -o result.log fmcombine -nop top u_mid1 u_mid2
+

misc/scripts/mutate_all.ys

+read_verilog ../top.v
+mutate -list 512 -o mutate.ys
+script mutate.ys
+
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 1 -wire cout -wirebit 0 -src ../top.v:8 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port B -portbit 0 -wire x -wirebit 0 -src ../top.v:3 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port A -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -src ../top.v:12
+#tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$1 -port Y -portbit 0 -ctrlbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port Y -portbit 1 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port B -portbit 0 -wire y -wirebit 0 -src ../top.v:4 -src ../top.v:12
+#tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+#tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+#tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$1 -port A -portbit 0 -wire cin -wirebit 0 -src ../top.v:5 -src ../top.v:12
+

misc/scripts/mutate_cnot0.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode cnot0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -ctrlbit 1 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+
+

misc/scripts/mutate_cnot1.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode cnot1 -module top -cell $add$../top.v:12$2 -port A -portbit 0 -ctrlbit 1 -src top.v:12
+
+
+

misc/scripts/mutate_const0.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode const0 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+

misc/scripts/mutate_const1.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode const1 -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+
+

misc/scripts/mutate_inv.ys

+read_verilog ../top.v
+tee -o result.log mutate -mode inv -module top -cell $add$../top.v:12$2 -port Y -portbit 0 -wire A -wirebit 0 -src ../top.v:7 -src ../top.v:12
+
+

misc/scripts/mutate_list.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32
+

misc/scripts/mutate_list_cfg.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -cfg weight_cover 1
+
+

misc/scripts/mutate_list_ctrl.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -ctrl A 1 1
+

misc/scripts/mutate_list_none.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -none
+

misc/scripts/mutate_list_o.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -o o.txt
+

misc/scripts/mutate_list_s.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -s s.txt
+

misc/scripts/mutate_list_seed.ys

+read_verilog ../top.v
+tee -o result.log mutate -list 32 -seed 5
+

misc/scripts/pmuxtree.ys

+read_verilog ../top.v
+proc
+tee -o result.log pmuxtree

misc/scripts/rename_low.ys

+read_verilog ../top.v
+synth
+tee -o result.log rename low newlow

misc/scripts/rename_top_top.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log rename top new_top

regression/Makefile

@@ -341,7 +341,26 @@ $(eval $(call template,issue_00862,issue_00862))
 #issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
 $(eval $(call template,issue_00865,issue_00865))
 
+#issue_00867
+$(eval $(call template,issue_00867,issue_00867))
+
+#issue_00870
+$(eval $(call template,issue_00870,issue_00870))
+
+#issue_00873
+$(eval $(call template,issue_00873,issue_00873))
+
+#issue_00888
+$(eval $(call template,issue_00888,issue_00888))
+
+#pr_00896
 $(eval $(call template,pr_00896,pr_00896))
 
+#issue_00922
+$(eval $(call template,issue_00922,issue_00922))
+
+#issue_00931
+$(eval $(call template,issue_00931,issue_00931))
+
 
 .PHONY: all clean

regression/issue_00870/top.v

+module mux1( select, d, q );
+
+input select;
+input[1:0] d;
+output     q;
+
+wire      q;
+wire      select;
+wire[1:0] d;
+
+assign q = d[select];
+
+endmodule
+
+module top(select, d, q);
+
+input[1:0] select;
+input[1:0] d;
+output     q;
+
+wire      q;
+wire[1:0] select;
+wire[1:0] d;
+
+wire[1:0] q_tmp;
+
+mux1 m1(
+		.select(select[0]),
+		.d(d),
+		.q(q_tmp[0])
+);
+
+mux1 m2(
+		.select(select[1]),
+		.d(d),
+		.q(q_tmp[1])
+);
+
+mux1 m3(
+		.select(select[0]),
+		.d(q_tmp),
+		.q(q)
+);
+
+
+
+endmodule

regression/issue_00873/top.v

+module template (input clk, input d, output reg q);
+parameter neg_clk = 0;
+
+initial q = 1'b1;
+
+generate
+    if (neg_clk) begin
+        always @(negedge clk) q <= d;
+    end
+    else begin
+        always @(posedge clk) q <= d;
+    end
+endgenerate
+endmodule
+
+module top(input clk, input d, output [1:0] q);
+    template #(.neg_clk(1)) neg_clk(clk, d, q[0]);
+    template #(.neg_clk(0)) pos_clk(clk, d, q[1]);
+endmodule

regression/issue_00888/top.v

+module top (CLK, CE, SEL, SI, DO);
+parameter SELWIDTH = 1;
+parameter DATAWIDTH = 2;
+input    CLK, CE;
+input [DATAWIDTH-1:0] SI;
+input [SELWIDTH-1:0] SEL;
+output [DATAWIDTH-1:0] DO;
+localparam DATADEPTH = 2**SELWIDTH;
+reg [0:DATADEPTH-1] data1 [DATAWIDTH-1:0];
+reg [DATADEPTH-1:0] data2 [DATAWIDTH-1:0];
+
+generate
+    genvar i;
+    for (i = 0; i < DATAWIDTH; i=i+1) begin
+        always @(posedge CLK)
+        begin
+            if (CE == 1'b1) begin
+`ifdef BROKEN
+                data1[i] <= {SI[i], data1[i][0:DATADEPTH-2]};
+`else
+                data2[i] <= {data2[i][DATADEPTH-2:0], SI[i]};
+`endif
+            end
+        end
+`ifdef BROKEN
+        assign DO[i] = data1[i][SEL];
+`else
+        assign DO[i] = data2[i][SEL];
+`endif
+    end
+endgenerate
+endmodule

regression/issue_00922/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	/*initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end*/
+
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG
+		if (we_a)
+`else
+		if (we_b)
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG
+		if (we_b)
+`else
+		if (we_a)
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

regression/issue_00931/top.v

+module top (
+        input [1:0] S,
+        input [7:0] A, B, C, D,
+        output reg [7:0] Y
+);
+        always @* begin
+                case (S)
+                        2'b00: Y <= A;
+                        2'b01: Y <= B;
+                        2'b10: Y <= C;
+                        2'b11: Y <= D;
+                endcase
+        end
+endmodule

regression/run.sh

@@ -74,7 +74,13 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_00835" ] ||\
 	 [ "$1" = "issue_00857" ] ||\
 	 [ "$1" = "issue_00862" ] ||\
-	 [ "$1" = "issue_00865" ]; then
+	 [ "$1" = "issue_00865" ] ||\
+	 [ "$1" = "issue_00867" ] ||\
+	 [ "$1" = "issue_00870" ] ||\
+	 [ "$1" = "issue_00873" ] ||\
+	 [ "$1" = "issue_00888" ] ||\
+	 [ "$1" = "issue_00922" ] ||\
+	 [ "$1" = "issue_00931" ]; then
 
 	expected_string=""
 	expected="1"
@@ -92,7 +98,8 @@ elif [ "$1" = "issue_00502" ] ||\
 		 [ "$1" = "issue_00689" ] ||\
 		 [ "$1" = "issue_00708" ] ||\
 		 [ "$1" = "issue_00826" ] ||\
-		 [ "$1" = "issue_00862" ]; then
+		 [ "$1" = "issue_00862" ] ||\
+		 [ "$1" = "issue_00870" ]; then
 		expected_string="Successfully finished Verilog frontend"
 	elif [ "$1" = "issue_00655" ]; then
 		expected_string="Executing EDIF backend"
@@ -118,6 +125,18 @@ elif [ "$1" = "issue_00502" ] ||\
 		expected_string="_DFF_P_                        1"
 	elif [ "$1" = "issue_00865" ]; then
 		expected_string="FDRE                           14"
+	elif [ "$1" = "issue_00867" ]; then
+		expected_string="RAMB36E1                        1"
+	elif [ "$1" = "issue_00873" ]; then
+		expected_string="has an unprocessed 'init' attribute."
+		expected="0"
+	elif [ "$1" = "issue_00888" ]; then
+		expected_string="FDRE                            4"
+	elif [ "$1" = "issue_00922" ]; then
+		expected_string="ERROR: Unclocked write port 0 on memory top.ram."
+		expected="0"
+	elif [ "$1" = "issue_00931" ]; then
+		expected_string="Number of cells:                  5"
 	fi
 
 	yosys -ql yosys.log ../../scripts/$2.ys;

regression/scripts/issue_00867.ys

+read_verilog ../top.v
+synth_xilinx -flatten
+tee -o result.log stat

regression/scripts/issue_00870.ys

+read_verilog ../top.v
+hierarchy -auto-top -check;
+proc; clean;
+memory;
+opt -full;
+flatten;
+
+write_verilog multimux_out_1.v
+opt -full;
+write_verilog multimux_out_2.v
+
+delete;
+tee -o result.log read_verilog multimux_out_2.v
+

regression/scripts/issue_00873.ys

+tee -a result.log read_verilog ../top.v
+tee -a result.log synth_xilinx
+tee -a result.log flatten
+tee -a result.log dump top
+

regression/scripts/issue_00888.ys

+read_verilog ../top.v
+tee -a result.log synth_xilinx
+

regression/scripts/issue_00922.ys

+read_verilog ../top.v
+proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
+tee -a result.log write_firrtl firrtl.firrtl

regression/scripts/issue_00931.ys

+read_verilog ../top.v
+tee -a result.log prep