Fix multiple drivers

backends/write_verilog/top_logic.v

@@ -5,6 +5,7 @@ module top
  input cin,
 
  output reg A,
+ output B,
  output reg cout
  );
 
@@ -32,7 +33,7 @@ always @(*) begin
         cout <=  cout1&cin~|y;
 end
 
-bb ubb (cin,y,x,A);
+bb ubb (cin,y,x,B);
 
 endmodule