Commit c0788975 by whitequark

Add proc_prune before explicit proc_init.

parent 3cd49561
...@@ -8,6 +8,7 @@ synth -top top ...@@ -8,6 +8,7 @@ synth -top top
write_btor btor1.btor write_btor btor1.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
...@@ -7,6 +7,7 @@ synth -top top ...@@ -7,6 +7,7 @@ synth -top top
write_btor -s btor1.btor write_btor -s btor1.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
...@@ -7,6 +7,7 @@ synth -top top ...@@ -7,6 +7,7 @@ synth -top top
write_btor -v btor1.btor write_btor -v btor1.btor
design -reset design -reset
read_verilog -sv ../top.v read_verilog -sv ../top.v
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
read_verilog -formal ../top.v read_verilog -formal ../top.v
hierarchy hierarchy
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
read_verilog -formal ../top.v read_verilog -formal ../top.v
hierarchy hierarchy
proc_prune
proc_init proc_init
proc_mux proc_mux
proc_dff proc_dff
......
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