Add test11 (LFSRs)

architecture/run.sh

@@ -19,6 +19,9 @@ run() {
     fi
 }
 
+if [ -f ../run.sh ]; then
+    ../run.sh
+fi
 yosys -ql yosys.log ../../scripts/$2.ys
 if [ "$1" = "synth_ecp5" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/ecp5/cells_sim.v
@@ -52,24 +55,10 @@ elif [ "$1" = "synth_xilinx" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
 elif [ "$1" = "synth_xilinx_srl" ]; then
     iverilog -DTEST1 synth1.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
+    for i in {2..11}; do
         run
-    iverilog -DTEST2 synth2.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST3 synth3.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST4 synth4.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST5 synth5.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST6 synth6.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST7 synth7.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST8 synth8.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST9 synth9.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
-    run
-    iverilog -DTEST10 synth10.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
+        iverilog -DTEST$i synth$i.v -o testbench  ../testbench.v -I.. ../top.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/xilinx/cells_sim.v
+    done
 elif [ "$1" = "synth_greenpak4" ]; then
     iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/greenpak4/cells_sim_digital.v
 else 

architecture/scripts/synth_xilinx_srl.ys

@@ -17,3 +17,5 @@ design -reset
 script ../test9.ys
 design -reset
 script ../test10.ys
+design -reset
+script ../test11.ys

architecture/synth_xilinx_srl/run.sh

+wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O lfsr_generate.py
+python3 lfsr_generate.py

architecture/synth_xilinx_srl/top.v

@@ -46,6 +46,10 @@ generate
         shift_reg #(.depth(i+1), .fixed_length(0)) sr(clk, a[i], 1'b1, l[$clog2(i+1)-1:0], z[i]);
     end
     assign z[0] = 'b0; // Suppress no driver warning
+`elsif TEST11
+    for (i = 0; i < `N; i=i+1) begin : neg_clk_with_enable_with_init_inferred_var_len
+        lfsr #(.len(i+3)) sr(clk, z[i]);
+    end
 `endif
 endgenerate
 endmodule
@@ -143,4 +147,4 @@ generate
 endgenerate
 endmodule
 
-
+`include "lfsr.v"