Add initial tests for DSP muls

architecture/Makefile

@@ -72,6 +72,7 @@ $(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xili
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
 $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
+$(eval $(call template,synth_xilinx_dsp,synth_xilinx_dsp))
 endif
 
 #greenpak4

architecture/synth_xilinx_dsp/assert_area.py

+#!/usr/bin/python3
+
+import glob
+import re
+import os
+
+re_mux = re.compile(r'mul_(\d+)_(\d+)\.v')
+
+for fn in glob.glob('*.v'):
+    m = re_mux.match(fn)
+    if not m: continue
+
+    A,B = map(int, m.group(1,2))
+
+    bn,_ = os.path.splitext(fn)
+
+    with open(fn, 'a') as f:
+        print('''
+`ifndef _AUTOTB
+module __test ;
+    wire [4095:0] assert_area = "cd; select t:DSP48E1 -assert-count 1";
+endmodule
+`endif
+''', file=f)

architecture/synth_xilinx_dsp/run-test.sh

+#!/bin/bash
+set -e
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+#wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/generate.py -O generate_mul.py -o /dev/null
+cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/generate.py generate_mul.py
+python3 generate_mul.py
+python3 ../assert_area.py
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
+    -p 'design -copy-to __test __test; \
+        synth_xilinx -abc9; \
+        design -copy-from __test *; \
+        select -assert-any __test; \
+        script -scriptwire __test/w:assert_area'\
+    -l ../../../../../techlibs/xilinx/cells_sim.v"