Add {ecp5,xilinx}_{,abc9} targets

bigsim/Makefile

@@ -24,6 +24,6 @@ clean::
 	rm -f $(1)_cmos.status $(1)_ice40.status $(1)_falsify.status
 endef
 
-$(eval $(call template,navre,cmos ice40 ice40_abc9))
+$(eval $(call template,navre,cmos ice40 ice40_abc9 ecp5 ecp5_abc9 xilinx xilinx_abc9))
 
 .PHONY: all clean

bigsim/run.sh

@@ -40,6 +40,22 @@ case "$2" in
 		yosys -ql synthlog.txt -p "synth_ice40 -abc9 -top $TOP; write_verilog synth.v" $rtl_files
 		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ice40/cells_sim.v"
 		;;
+	ecp5)
+		yosys -ql synthlog.txt -p "synth_ecp5 -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v"
+		;;
+	ecp5_abc9)
+		yosys -ql synthlog.txt -p "synth_ecp5 -abc9 -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/ecp5/cells_sim.v"
+		;;
+	xilinx)
+		yosys -ql synthlog.txt -p "synth_xilinx -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
+		;;
+	xilinx_abc9)
+		yosys -ql synthlog.txt -p "synth_xilinx -abc9 -top $TOP; write_verilog synth.v" $rtl_files
+		iverilog_cmd="$iverilog_cmd synth.v $TECHLIBS_PREFIX/xilinx/cells_sim.v"
+		;;
 	*)
 		exit 1
 		;;