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yosys-tests
Unverified Commit b1230186 by Miodrag Milanović Committed by GitHub
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Merge pull request #58 from SergeyDegtyar/master 

Add new tests to 'simple' and 'misc' groups.
parents 133911ba d3210b8a
Showing with 1054 additions and 22 deletions
misc/Makefile
...@@ -88,6 +88,7 @@ $(eval $(call template,add_error, add_error )) ...@@ -88,6 +88,7 @@ $(eval $(call template,add_error, add_error ))
#blackbox #blackbox
$(eval $(call template,blackbox, blackbox )) $(eval $(call template,blackbox, blackbox ))
$(eval $(call template,blackbox_mem, blackbox blackbox_top))
# - issue #925 # - issue #925
#bugpoint ERROR: No such command: autoidx (type 'help' for a command overview) #bugpoint ERROR: No such command: autoidx (type 'help' for a command overview)
...@@ -96,8 +97,9 @@ $(eval $(call template,bugpoint_error, bugpoint_missing_script bugpoint_do_not_c ...@@ -96,8 +97,9 @@ $(eval $(call template,bugpoint_error, bugpoint_missing_script bugpoint_do_not_c
#bugpoint_grep_string_not_found - no error #bugpoint_grep_string_not_found - no error
#chformal #chformal
$(eval $(call template,chformal, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip )) $(eval $(call template,chformal, chformal chformal_ff chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
$(eval $(call template,chformal_dff, chformal chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip )) $(eval $(call template,chformal_dff, chformal chformal_ff chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
$(eval $(call template,chformal_ff, chformal chformal_ff chformal_assert2assume chformal_assert chformal_assume2assert chformal_assume chformal_cover chformal_delay chformal_early chformal_proc_early chformal_fair2live_assert2assume chformal_fair2live chformal_fair chformal_live2fair chformal_live chformal_skip ))
$(eval $(call template,chformal_error, chformal_error )) $(eval $(call template,chformal_error, chformal_error ))
#chtype #chtype
...@@ -143,6 +145,7 @@ $(eval $(call template,setundef_error, setundef_expose_without_undriven setundef ...@@ -143,6 +145,7 @@ $(eval $(call template,setundef_error, setundef_expose_without_undriven setundef
#assertpmux #assertpmux
$(eval $(call template,assertpmux, assertpmux assertpmux_noinit assertpmux_always)) $(eval $(call template,assertpmux, assertpmux assertpmux_noinit assertpmux_always))
$(eval $(call template,assertpmux_mux, assertpmux assertpmux_noinit assertpmux_always))
#eval #eval
$(eval $(call template,eval, eval eval_set eval_set_undef eval_table eval_show eval_brute_force_equiv_checker eval_show_not_set eval_table_set eval_vloghammer_report eval_vloghammer_report_rtl)) $(eval $(call template,eval, eval eval_set eval_set_undef eval_table eval_show eval_brute_force_equiv_checker eval_show_not_set eval_table_set eval_vloghammer_report eval_vloghammer_report_rtl))
...@@ -151,6 +154,7 @@ $(eval $(call template,eval_error, eval_only_one_module eval_failed_to_parse_lhs ...@@ -151,6 +154,7 @@ $(eval $(call template,eval_error, eval_only_one_module eval_failed_to_parse_lhs
#freduce #freduce
$(eval $(call template,freduce, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump )) $(eval $(call template,freduce, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_dff, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump )) $(eval $(call template,freduce_dff, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_ffs, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_mem, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump )) $(eval $(call template,freduce_mem, freduce freduce_v freduce_vv freduce_inv freduce_stop freduce_dump ))
$(eval $(call template,freduce_error, freduce_logic_loop )) $(eval $(call template,freduce_error, freduce_logic_loop ))
...@@ -204,9 +208,9 @@ $(eval $(call template,tee_error, tee_o_cant_create_file tee_a_cant_create_file ...@@ -204,9 +208,9 @@ $(eval $(call template,tee_error, tee_o_cant_create_file tee_a_cant_create_file
$(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n test_autotb_seed)) $(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n test_autotb_seed))
#abc #abc
$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff)) $(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff)) $(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff)) $(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
$(eval $(call template,abc_error, abc_cannot_open abc_constr_no_liberty abc_lut_liberty abc_unsup_gate_type abc_inv_luts_synt abc_return_code abc_clk_domain_not_found abc_script_o abc_script_top)) $(eval $(call template,abc_error, abc_cannot_open abc_constr_no_liberty abc_lut_liberty abc_unsup_gate_type abc_inv_luts_synt abc_return_code abc_clk_domain_not_found abc_script_o abc_script_top))
#hilomap #hilomap
...@@ -223,6 +227,7 @@ $(eval $(call template,mutate_error, mutate_error)) ...@@ -223,6 +227,7 @@ $(eval $(call template,mutate_error, mutate_error))
#fmconbine #fmconbine
#fmcombine_gate_cell_not_found - failed #1063 #fmcombine_gate_cell_not_found - failed #1063
$(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd fmcombine_anyeq fmcombine_initeq)) $(eval $(call template,fmcombine, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd fmcombine_anyeq fmcombine_initeq))
$(eval $(call template,fmcombine_assert_assume, fmcombine fmcombine_fwd fmcombine_bwd fmcombine_nop fmcombine_bwd_fwd fmcombine_anyeq fmcombine_initeq))
$(eval $(call template,fmcombine_error, fmcombine_invalid_number_of_param fmcombine_module_not_found fmcombine_gold_cell_not_found fmcombine_gate_cell_not_found fmcombine_types_not_match fmcombine_nop_with_fwd fmcombine_nop_with_bwd fmcombine_nop_with_fwd_bwd)) $(eval $(call template,fmcombine_error, fmcombine_invalid_number_of_param fmcombine_module_not_found fmcombine_gold_cell_not_found fmcombine_gate_cell_not_found fmcombine_types_not_match fmcombine_nop_with_fwd fmcombine_nop_with_bwd fmcombine_nop_with_fwd_bwd))
#pmuxtree #pmuxtree
...@@ -248,5 +253,23 @@ $(eval $(call template,help, help_celltype_plus help_celltype help_cells help_al ...@@ -248,5 +253,23 @@ $(eval $(call template,help, help_celltype_plus help_celltype help_cells help_al
#echo #echo
$(eval $(call template,echo, echo echo_off echo_on )) $(eval $(call template,echo, echo echo_off echo_on ))
#debug
$(eval $(call template,debug, debug ))
#muxpack
$(eval $(call template,muxpack, muxpack ))
#history
$(eval $(call template,history, history ))
#script
$(eval $(call template,script, script script_from_to script_scriptwire ))
#tcl
$(eval $(call template,tcl, tcl ))
#abc9
$(eval $(call template,abc9, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D ))
.PHONY: all clean .PHONY: all clean
misc/abc9/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/assertpmux_mux/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
default: Y = 1'bx;
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
default: Y = 1'bx;
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
reg Y;
wire[3:0] S;
wire[15:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
8 : Y = D[8];
9 : Y = D[9];
10 : Y = D[10];
11 : Y = D[11];
12 : Y = D[12];
13 : Y = D[13];
14 : Y = D[14];
15 : Y = D[15];
default: Y = 1'bx;
endcase
end
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
misc/blackbox_mem/top.v 0 → 100644
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
misc/chformal_ff/top.v 0 → 100644
module alat
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (en)
q <= d;
endmodule
module alatn
( input d, en, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (!en)
q <= d;
endmodule
module latsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else if ( en )
q <= d;
endmodule
module nlatsr
( input d, en, pre, clr, output reg q );
initial begin
q = 0;
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else if ( !en )
q <= d;
endmodule
module dlatchsr (EN, SET, CLR, D, Q);
input EN;
input SET, CLR, D;
output reg Q;
always @*
if (CLR)
Q = 0;
else if (SET)
Q = 1;
else if (EN)
Q = D;
endmodule
module top (
input en,
input clr,
input pre,
input a,
output b,b1,b2,b3
);
latsr u_latsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
misc/debug/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/fmcombine_assert_assume/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
output reg A,
output cout
);
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
assign cout = cin? y : x;
middle u_mid1 (.x(x),.A(o),.y(1'b0));
middle u_mid2 (.x(x),.A(o),.y(1'b1));
middle u_mid3 (.x(x),.A(o),.y(1'bX));
middle u_mid4 (.x(x),.A(o),.y(1'bX));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module middle
(
input x,
input y,
input cin,
output reg A,
output reg cout
);
reg ASSERT = 1;
(* anyconst *) reg foo;
(* anyseq *) reg too;
initial begin
begin
A = 0;
cout = 0;
end
end
`ifndef BUG
always @(posedge x) begin
if ($initstate)
A <= 0;
A <= y + cin + too;
assume(too);
assume(s_eventually too);
end
always @(negedge x) begin
if ($initstate)
cout <= 0;
cout <= y + A + foo;
assert(ASSERT);
assert(s_eventually ASSERT);
end
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/freduce_ffs/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
misc/history/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/muxpack/top.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
if (S == 0) Y <= D[0];
else if (S == 1) Y <= D[1];
else if (S == 2) Y <= D[2];
else if (S == 3) Y <= D[3];
else Y <= 1'bx;
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
if (S == 0) Y <= D[0];
else if (S == 1) Y <= D[1];
else if (S == 2) Y <= D[2];
else if (S == 3) Y <= D[3];
else if (S == 4) Y <= D[4];
else if (S == 5) Y <= D[5];
else if (S == 6) Y <= D[6];
else if (S == 7) Y <= D[7];
else Y <= 1'bx;
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
reg Y;
wire[3:0] S;
wire[15:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
8 : Y = D[8];
9 : Y = D[9];
10 : Y = D[10];
11 : Y = D[11];
12 : Y = D[12];
13 : Y = D[13];
14 : Y = D[14];
15 : Y = D[15];
default: Y = 1'bx;
endcase
end
endmodule
module top (
input [3:0] S,
input [15:0] D,
output M2,M4,M8,M16
);
mux2 u_mux2 (
.S (S[0]),
.A (D[0]),
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
.Y (M16)
);
endmodule
misc/script/script.ys 0 → 100644
read_verilog ../top.v
tee -o result.log dump
misc/script/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
misc/scripts/abc9_D.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -D 2 -lut 2
misc/scripts/abc9_fast.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -fast -lut 2
misc/scripts/abc9_lut.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -lut 2
misc/scripts/abc9_luts.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -luts 2,3,4
misc/scripts/abc9_markgroups.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -markgroups -lut 2
misc/scripts/abc9_nocleanup.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -nocleanup -lut 2
misc/scripts/abc9_showtmp.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
synth -top top
tee -o result.log abc9 -showtmp -lut 2
misc/scripts/abc_constr_liberty.ys 0 → 100644
read_verilog ../top.v
synth -top top
tee -o result.log abc -liberty -constr top.lib
misc/scripts/blackbox_top.ys 0 → 100644
read_verilog ../top.v
blackbox top
tee -o result.log dump
misc/scripts/chformal_ff.ys 0 → 100644
read_verilog -sv ../top.v
proc
clk2fflogic
chformal -early
tee -o result.log dump
misc/scripts/debug.ys 0 → 100644
debug read_verilog ../top.v
debug proc
tee -o result.log debug synth -top top
misc/scripts/delete_mem.ys
read_verilog ../top.v read_verilog ../top.v
delete top/$7 delete top/$memrd$\ram$../top.v:30$7
tee -o result.log dump tee -o result.log dump
misc/scripts/fmcombine.ys
read_verilog ../top.v read_verilog -sv ../top.v
proc proc
tee -o result.log fmcombine top u_mid1 u_mid3 tee -o result.log fmcombine top u_mid1 u_mid3
tee -o result.log fmcombine top u_mid2 u_mid4 tee -o result.log fmcombine top u_mid2 u_mid4
......
misc/scripts/fmcombine_anyeq.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -anyeq top u_mid1 u_mid2 tee -o result.log fmcombine -anyeq top u_mid1 u_mid2
misc/scripts/fmcombine_bwd.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -bwd top u_mid1 u_mid2 tee -o result.log fmcombine -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_bwd_fwd.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2 tee -o result.log fmcombine -bwd -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_fwd.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -fwd top u_mid1 u_mid2 tee -o result.log fmcombine -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_gate_cell_not_found.ys
read_verilog ../top.v read_verilog -sv ../top.v
proc proc
tee -o result.log fmcombine top u_mid1 u_mid8 tee -o result.log fmcombine top u_mid1 u_mid8
misc/scripts/fmcombine_gold_cell_not_found.ys
read_verilog ../top.v read_verilog -sv ../top.v
proc proc
tee -o result.log fmcombine top u_mid8 u_mid3 tee -o result.log fmcombine top u_mid8 u_mid3
misc/scripts/fmcombine_initeq.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -initeq top u_mid1 u_mid2 tee -o result.log fmcombine -initeq top u_mid1 u_mid2
misc/scripts/fmcombine_invalid_number_of_param.ys
read_verilog ../top.v read_verilog -sv ../top.v
proc proc
tee -o result.log fmcombine tee -o result.log fmcombine
misc/scripts/fmcombine_module_not_found.ys
read_verilog ../top.v read_verilog -sv ../top.v
proc proc
tee -o result.log fmcombine topp u_mid1 u_mid3 tee -o result.log fmcombine topp u_mid1 u_mid3
misc/scripts/fmcombine_nop.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -nop top u_mid1 u_mid2 tee -o result.log fmcombine -nop top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_bwd.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -nop -bwd top u_mid1 u_mid2 tee -o result.log fmcombine -nop -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_fwd.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -nop -fwd top u_mid1 u_mid2 tee -o result.log fmcombine -nop -fwd top u_mid1 u_mid2
misc/scripts/fmcombine_nop_with_fwd_bwd.ys
read_verilog ../top.v read_verilog -sv ../top.v
tee -o result.log fmcombine -nop -fwd -bwd top u_mid1 u_mid2 tee -o result.log fmcombine -nop -fwd -bwd top u_mid1 u_mid2
misc/scripts/fmcombine_types_not_match.ys
read_verilog ../top_err_1.v read_verilog -sv ../top_err_1.v
proc proc
tee -o result.log fmcombine top u_mid1 u_urtl tee -o result.log fmcombine top u_mid1 u_urtl
misc/scripts/history.ys 0 → 100644
read_verilog ../top.v
tee -o result.log history
misc/scripts/muxpack.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.log muxpack
misc/scripts/scc.ys
read_verilog ../top.v read_verilog ../top.v
tee -o result.log scc top
proc proc
tee -o result.log scc top tee -o result.log scc top
synth synth
......
misc/scripts/script.ys 0 → 100644
tee -o result.log script ../script.ys
misc/scripts/script_from_to.ys 0 → 100644
tee -o result.log script ../script.ys 1:3
misc/scripts/script_scriptwire.ys 0 → 100644
tee -o result.log script -scriptwire ../script.ys
misc/scripts/tcl.ys 0 → 100644
tee -o result.log tcl ../tcl.tcl
misc/tcl/tcl.tcl 0 → 100644
puts "Execute tcl script!"
misc/tcl/top.v 0 → 100644
(* black_box *) module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
simple/Makefile
...@@ -99,7 +99,7 @@ $(eval $(call template_error,memory_bram_error, memory_bram_syntax_error_in_rule ...@@ -99,7 +99,7 @@ $(eval $(call template_error,memory_bram_error, memory_bram_syntax_error_in_rule
$(eval $(call template,uniquify,uniquify)) $(eval $(call template,uniquify,uniquify))
#hierarchy (44% increased to 61,3%) #hierarchy (44% increased to 61,3%)
$(eval $(call template,hierarchy,hierarchy hierarchy_top hierarchy_check hierarchy_simcheck hierarchy_purge_lib hierarchy_libdir hierarchy_keep_positionals hierarchy_keep_portwidths hierarchy_nokeep_asserts hierarchy_auto_top hierarchy_generate)) $(eval $(call template,hierarchy,hierarchy hierarchy_top hierarchy_check hierarchy_simcheck hierarchy_purge_lib hierarchy_libdir hierarchy_keep_positionals hierarchy_keep_portwidths hierarchy_nokeep_asserts hierarchy_auto_top hierarchy_generate hierarchy_chparam hierarchy_chparam_overwr))
$(eval $(call template,hierarchy_huge,hierarchy_huge)) $(eval $(call template,hierarchy_huge,hierarchy_huge))
$(eval $(call template_error,hierarchy_error, hierarchy_no_top_module hierarchy_top_requires_args hierarchy_module_not_found )) $(eval $(call template_error,hierarchy_error, hierarchy_no_top_module hierarchy_top_requires_args hierarchy_module_not_found ))
...@@ -152,6 +152,7 @@ $(eval $(call template,tribuf_logic,tribuf_logic_top tribuf_merge_logic_top)) ...@@ -152,6 +152,7 @@ $(eval $(call template,tribuf_logic,tribuf_logic_top tribuf_merge_logic_top))
#expose #expose
$(eval $(call template,expose,expose_cut expose_input expose_evert expose_sep expose_shared expose_dff expose_evert_dff expose_evert_shared expose_evert_dff_shared)) $(eval $(call template,expose,expose_cut expose_input expose_evert expose_sep expose_shared expose_dff expose_evert_dff expose_evert_shared expose_evert_dff_shared))
$(eval $(call template,expose_dff,expose_cut expose_input expose_evert expose_sep expose_shared expose_dff expose_evert_dff expose_evert_shared expose_evert_dff_shared)) $(eval $(call template,expose_dff,expose_cut expose_input expose_evert expose_sep expose_shared expose_dff expose_evert_dff expose_evert_shared expose_evert_dff_shared))
$(eval $(call template,expose_ffs,expose_cut expose_input expose_evert expose_sep expose_shared expose_dff expose_evert_shared expose_evert_dff_shared))
#opt_demorgan #opt_demorgan
$(eval $(call template,opt_demorgan,opt_demorgan)) $(eval $(call template,opt_demorgan,opt_demorgan))
......
simple/expose_ffs/testbench.v 0 → 100644
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk)
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk)
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/expose_ffs/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/hierarchy/top.v
...@@ -108,6 +108,8 @@ output b,b1,b2,b3,b4 ...@@ -108,6 +108,8 @@ output b,b1,b2,b3,b4
wire a1,b11; wire a1,b11;
parameter x = 0;
dffsr u_dffsr ( dffsr u_dffsr (
.clk (clk ), .clk (clk ),
.clr (clr), .clr (clr),
......
simple/scripts/expose_evert_shared.ys
...@@ -5,4 +5,5 @@ flatten ...@@ -5,4 +5,5 @@ flatten
opt opt
opt_rmdff opt_rmdff
expose -evert -shared expose -evert -shared
expose -shared -evert
write_verilog synth.v write_verilog synth.v
simple/scripts/hierarchy_chparam.ys 0 → 100644
read_verilog ../top.v
hierarchy -chparam x 1 -top top
synth -top top
write_verilog synth.v
simple/scripts/hierarchy_chparam_overwr.ys 0 → 100644
read_verilog ../top.v
hierarchy -chparam x 1 -chparam x 2 -top top
synth -top top
write_verilog synth.v
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