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lvzhengyang
yosys-tests
Commits
ab409bd6
Commit
ab409bd6
authored
Aug 30, 2019
by
Eddie Hung
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Deprecate use of shregmap's "-tech xilinx" option
parent
2cdd01ca
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simple/scripts/shregmap_match_enpol.ys
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ab409bd6
read_verilog ../top.v
read_verilog ../top.v
synth_greenpak4 -run begin:map_luts
synth_greenpak4 -run begin:map_luts
shregmap -tech
xilinx
-match -enpol any
shregmap -tech
greenpak4
-match -enpol any
design -reset
design -reset
read_verilog ../top.v
read_verilog ../top.v
write_verilog synth.v
write_verilog synth.v
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