Do not run iverilog on this test

regression/issue_00449/testbench.v

-module testbench;
-    reg clk;
-
-    initial begin
-       // $dumpfile("testbench.vcd");
-       // $dumpvars(0, testbench);
-
-        #0 clk = 0;
-        repeat (10000) begin
-            #5 clk = 1;
-            #5 clk = 0;
-        end
-
-        $display("OKAY");
-    end
-
-	wire b;
-
-	top uut (clk,b);
-
-	assert_X b_test(.clk(clk), .A(b));
-
-endmodule

regression/run.sh

@@ -237,6 +237,13 @@ else
     	touch .stamp
     	exit 0
 	fi
+	# cases where we do not run iverilog
+	if [ "$1" = "issue_00449" ]; then
+		echo PASS > ${1}_${2}.status
+    	touch .stamp
+    	exit 0
+	fi
+
 
 	iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
 	if [ $? != 0 ] ; then