Merge pull request #76 from SergeyDegtyar/updated_architecture_group

Review and update tests in 'architecture' test group

architecture/ice40_wrapcarry/testbench.v

-module testbench;
-    reg [7:0] in;
-
-	wire [3:0] outA,outB;
-	wire [3:0] poutA,poutB;
-
-    initial begin
-       //  $dumpfile("testbench.vcd");
-       //  $dumpvars(0, testbench);
-
-        #5 in = 0;
-        repeat (10000) begin
-            #5 in = in + 1;
-        end
-
-        $display("OKAY");
-    end
-
-    top uut (
-	.x(in[3:0]),
-	.y(in[7:4]),
-	.A(outA),
-	.B(outB)
-	);
-
-
-	assign poutB =  in[3:0] / in[7:4];
-
-	check_comb div_test(in[7:4], outB, poutB);
-
-endmodule
-
-module check_comb(input [3:0] div, input [3:0] test, input [3:0] pat);
-    always @*
-    begin
-        #1;
-        if (div != 4'b0000)
-			if (test !== pat)
-			begin
-				$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
-				$stop;
-			end
-    end
-endmodule
-

architecture/ice40_wrapcarry_adders/testbench.v

-module testbench;
-    reg [31:0] in;
-
-	wire [15:0] outA,outB;
-	wire [15:0] poutA,poutB;
-
-    initial begin
-        // $dumpfile("testbench.vcd");
-        // $dumpvars(0, testbench);
-
-        #5 in = 0;
-        repeat (10000) begin
-            #5 in = in + 1;
-        end
-
-        $display("OKAY");
-    end
-
-    top uut (
-	.x(in[15:0]),
-	.y(in[31:16]),
-	.A(outA),
-	.B(outB)
-	);
-
-
-	assign poutA =  in[15:0] + in[31:16];
-	assign poutB =  in[15:0] - in[31:16];
-
-	check_comb add_test(outA, poutA);
-	check_comb sub_test(outB, poutB);
-	assert_comb sub0_test(outB[2], poutB[2]);
-
-endmodule
-
-module check_comb(input [15:0] test, input [15:0] pat);
-    always @*
-    begin
-        #1;
-        if (test != pat)
-        begin
-            $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
-            $stop;
-        end
-    end
-endmodule
-

architecture/ice40_wrapcarry_adders/top.v

-module top
-(
- input [15:0] x,
- input [15:0] y,
-
- output [15:0] A,
- output [15:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule

architecture/run.sh

@@ -2,6 +2,7 @@
 
 set -x
 test -d $1
+test -f $2.ys
 
 rm -rf $1/work_$2
 mkdir $1/work_$2
@@ -9,58 +10,58 @@ cd $1/work_$2
 
 touch .start
 
-# cases where 'syntax error' or other errors are expected
-if echo "$1" | grep ".*_error"; then
-
-	expected_string=""
-	# Change checked string for check other errors
-	if echo "$2" | grep ".*_fully_selected"; then
-		expected_string="ERROR: This command only operates on fully selected designs!"
-	elif [ "$2" = "synth_greenpak4_invalid_part" ]; then
-		expected_string="ERROR: Invalid part name: "
-	elif [ "$2" = "synth_intel_invalid_family" ]; then
-		expected_string="ERROR: Invalid or no family specified:"
-	elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
-		expected_string="ERROR: Invalid Xilinx -family setting: "
-	elif [ "$2" = "synth_xilinx_widemux_1" ]; then
-		expected_string="ERROR: -widemux value must be 0 or >= 2."
-	elif [ "$2" = "synth_xilinx_abc9_retime" ]; then
-		expected_string="ERROR: -retime option not currently compatible with -abc9!"
-	elif [ "$2" = "synth_ice40_abc9_retime" ]; then
-		expected_string="ERROR: -retime option not currently compatible with -abc9!"
-	elif [ "$2" = "synth_ice40_device_unknown" ]; then
-		expected_string="ERROR: Invalid or no device specified: "
+#
+if [ -f ../run-test.sh ]; then
+	../run-test.sh
+	if [ $? != 0 ] ; then
+		echo FAIL > ${1}_${2}.status
+	else
+		echo PASS > ${1}_${2}.status
 	fi
-
-	if yosys -ql yosys.log ../../scripts/$2.ys; then
+	touch .stamp
+	exit
+fi
+if [[ $2 =~ "_fail" ]]; then
+	#4 - An error expected
+	if yosys -ql yosys.log ../$2.ys; then
 		echo FAIL > ${1}_${2}.status
 	else
-		if  grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then
+		if [ -f "../$2.pat" ]; then
+			expectation=$(<../$2.pat)
+			if grep "$expectation" yosys.log; then
 				echo PASS > ${1}_${2}.status
 			else
 				echo FAIL > ${1}_${2}.status
 			fi
+		else
+			echo PASS > ${1}_${2}.status
+		fi
 	fi
 else
-
-	if [ -f ../run-test.sh ]; then
-		../run-test.sh
+	#2 - All asserts in .ys script
+	yosys -ql yosys.log ../$2.ys
 	if [ $? != 0 ] ; then
 		echo FAIL > ${1}_${2}.status
+		touch .stamp
+		exit 0
 	else
+		#3 Output log check
+		if [ -f "../$2.pat" ]; then # Expected behavior
+			expectation=$(<../$2.pat)
+			if grep "$expectation" result.out; then
 				echo PASS > ${1}_${2}.status
-		fi
-		touch .stamp
-		exit
 			else
-		test -f scripts/$2.ys
-		yosys -ql yosys.log ../../scripts/$2.ys
-		if [ $? != 0 ] ; then
 				echo FAIL > ${1}_${2}.status
-			touch .stamp
-			exit 0
 			fi
+		elif [ -f "../$2_n.pat" ]; then # Not expected behavior
+			expectation=$(<../$2_n.pat)
+			if grep "$expectation" result.out; then
+				echo FAIL > ${1}_${2}.status
+			else
+				echo PASS > ${1}_${2}.status
 			fi
+		#1 Iverilog run when testbench exists
+		elif [ -f "../testbench.v" ]; then
 			if [ -f "../../../../../techlibs/common/simcells.v" ]; then
 				COMMON_PREFIX=../../../../../techlibs/common
 				TECHLIBS_PREFIX=../../../../../techlibs
@@ -68,84 +69,17 @@ else
 				COMMON_PREFIX=/usr/local/share/yosys
 				TECHLIBS_PREFIX=/usr/local/share/yosys
 			fi
-
-	if [ "$1" = "synth_ecp5" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
-	elif [ "$1" = "synth_ecp5_wide_ffs" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
-	elif [ "$1" = "synth_achronix" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/achronix/speedster22i/cells_sim.v
-	elif [ "$1" = "synth_anlogic" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
-	elif [ "$1" = "synth_anlogic_fulladder" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
-	elif [ "$1" = "synth_anlogic_fsm" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
-	elif [ "$1" = "synth_anlogic_mem" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v  $TECHLIBS_PREFIX/anlogic/eagle_bb.v
-	elif [ "$1" = "synth_coolrunner2" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
-	elif [ "$1" = "synth_coolrunner2_fulladder" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
-	elif [ "$1" = "synth_gowin" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
-	elif [ "$1" = "synth_gowin_mem" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
-	elif [ "$1" = "synth_ice40" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
-	elif [ "$1" = "synth_ice40_mem" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
-	elif [ "$1" = "synth_ice40_wide_ffs" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
-	elif [ "$1" = "synth_ice40_fulladder" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
-	elif [ "$1" = "ice40_wrapcarry" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v  $TECHLIBS_PREFIX/ice40/abc9_model.v
-	elif [ "$1" = "ice40_wrapcarry_adders" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v  $TECHLIBS_PREFIX/ice40/abc9_model.v
-	elif [ "$1" = "synth_intel" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
-	elif [ "$1" = "synth_intel_a10gx" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/a10gx/cells_sim.v
-	elif [ "$1" = "synth_intel_cycloneiv" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneiv/cells_sim.v
-	elif [ "$1" = "synth_intel_cycloneive" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneive/cells_sim.v
-	elif [ "$1" = "synth_intel_cyclone10" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclone10/cells_sim.v
-	elif [ "$1" = "synth_intel_cyclonev" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclonev/cells_sim.v
-	elif [ "$1" = "synth_sf2" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
-	elif [ "$1" = "synth_xilinx" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
-	elif [ "$1" = "xilinx_srl" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
-	elif [ "$1" = "synth_greenpak4" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
-	elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
-	elif [ "$1" = "synth_greenpak4_dffs_r" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
-	elif [ "$1" = "synth_efinix" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
-	elif [ "$1" = "synth_efinix_fulladder" ]; then
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
-	elif [ "$1" = "xilinx_ug901_synthesis_examples" ] || \
-		 [ "$1" = "synth_xilinx_dsp_cov" ]; then
-		:
+			if [ -f "../iverilog_adds.txt" ]; then
+				iverilog_adds=$TECHLIBS_PREFIX/$(<../iverilog_adds.txt)
 			else
-		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
+				iverilog_adds=""
 			fi
+			iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
 			if [ $? != 0 ] ; then
 				echo FAIL > ${1}_${2}.status
 				touch .stamp
 				exit 0
 			fi
-	if  [ "$1" = "xilinx_ug901_synthesis_examples" ] || \
-		[ "$1" = "synth_xilinx_dsp_cov" ]; then
-		echo PASS > ${1}_${2}.status
-	else
 			if ! vvp -N testbench > testbench.log 2>&1; then
 				grep 'ERROR' testbench.log
 				echo FAIL > ${1}_${2}.status
@@ -154,8 +88,9 @@ else
 			else
 				echo PASS > ${1}_${2}.status
 			fi
+		else
+			echo PASS > ${1}_${2}.status
+		fi
 	fi
-
 fi
-
 touch .stamp

architecture/scripts/ice40_wrapcarry.ys

-read_verilog ../top.v
-synth_ice40
-ice40_wrapcarry
-write_verilog synth.v

architecture/scripts/ice40_wrapcarry_top.ys

-read_verilog ../top.v
-synth_ice40
-ice40_wrapcarry top
-write_verilog synth.v

architecture/scripts/synth_achronix.ys

-read_verilog ../top.v
-synth_achronix
-write_verilog synth.v 

architecture/scripts/synth_achronix_noflatten.ys

-read_verilog ../top.v
-synth_achronix -noflatten
-write_verilog synth.v 

architecture/scripts/synth_achronix_retime.ys

-read_verilog ../top.v
-synth_achronix -retime
-write_verilog synth.v 

architecture/scripts/synth_achronix_run.ys

-read_verilog ../top.v
-synth_achronix -run begin:vout
-write_verilog synth.v 

architecture/scripts/synth_achronix_top.ys

-read_verilog ../top.v
-synth_achronix -top top
-write_verilog synth.v 

architecture/scripts/synth_achronix_vout.ys

-read_verilog ../top.v
-synth_achronix -vout vout.v
-write_verilog synth.v 

architecture/scripts/synth_anlogic.ys

-read_verilog ../top.v
-synth_anlogic
-write_verilog synth.v

architecture/scripts/synth_anlogic_edif.ys

-read_verilog ../top.v
-synth_anlogic -edif edif.edif
-write_verilog synth.v

architecture/scripts/synth_anlogic_json.ys

-read_verilog ../top.v
-synth_anlogic -json json.json
-write_verilog synth.v

architecture/scripts/synth_anlogic_noflatten.ys

-read_verilog ../top.v
-synth_anlogic -noflatten
-write_verilog synth.v

architecture/scripts/synth_anlogic_retime.ys

-read_verilog ../top.v
-synth_anlogic -retime
-write_verilog synth.v

architecture/scripts/synth_anlogic_run.ys

-read_verilog ../top.v
-synth_anlogic -run begin:json
-write_verilog synth.v

architecture/scripts/synth_anlogic_top.ys

-read_verilog ../top.v
-synth_anlogic -top top
-write_verilog synth.v

architecture/scripts/synth_coolrunner2_mem.ys

-read_verilog ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v  ../yosys_rocket/SimDTM.v
-#
-synth_coolrunner2
-write_verilog synth.v

architecture/scripts/synth_coolrunner2_vlog.ys

-read_verilog ../top.v
-synth_easic -vlog vlog.v
-write_verilog synth.v 

architecture/scripts/synth_ecp5.ys

-read_verilog ../top.v
-synth_ecp5
-write_verilog synth.v 

architecture/scripts/synth_ecp5_abc2.ys

-read_verilog ../top.v
-synth_ecp5 -abc2
-write_verilog synth.v 

architecture/scripts/synth_ecp5_abc9.ys

-read_verilog ../top.v
-synth_ecp5 -abc9
-write_verilog synth.v

architecture/scripts/synth_ecp5_abc9_nowidelut.ys

-read_verilog ../top.v
-synth_ecp5 -abc9 -nowidelut
-write_verilog synth.v

architecture/scripts/synth_ecp5_blif.ys

-read_verilog ../top.v
-synth_ecp5 -blif blif.blif
-write_verilog synth.v 

architecture/scripts/synth_ecp5_edif.ys

-read_verilog ../top.v
-synth_ecp5 -edif edif.edif
-write_verilog synth.v 

architecture/scripts/synth_ecp5_flatten.ys

-read_verilog ../top.v
-synth_ecp5 -flatten
-write_verilog synth.v 

architecture/scripts/synth_ecp5_json.ys

-read_verilog ../top.v
-synth_ecp5 -json json.json
-write_verilog synth.v 

architecture/scripts/synth_ecp5_nobram.ys

-read_verilog ../top.v
-synth_ecp5 -nobram
-write_verilog synth.v 

architecture/scripts/synth_ecp5_noccu2.ys

-read_verilog ../top.v
-synth_ecp5 -noccu2
-write_verilog synth.v 

architecture/scripts/synth_ecp5_nodffe.ys

-read_verilog ../top.v
-synth_ecp5 -nodffe
-write_verilog synth.v 

architecture/scripts/synth_ecp5_nodram.ys

-read_verilog ../top.v
-synth_ecp5 -nodram
-write_verilog synth.v 

architecture/scripts/synth_ecp5_nodsp.ys

-read_verilog ../top.v
-synth_ecp5 -nodsp
-write_verilog synth.v

architecture/scripts/synth_ecp5_noflatten.ys

-read_verilog ../top.v
-synth_ecp5 -noflatten
-write_verilog synth.v 

architecture/scripts/synth_ecp5_nomux.ys

-read_verilog ../top.v
-synth_ecp5 -nomux
-write_verilog synth.v 

architecture/scripts/synth_ecp5_retime.ys

-read_verilog ../top.v
-synth_ecp5 -retime
-write_verilog synth.v 

architecture/scripts/synth_ecp5_run.ys

-read_verilog ../top.v
-synth_ecp5 -run begin:json
-write_verilog synth.v 

architecture/scripts/synth_ecp5_top.ys

-read_verilog ../top.v
-synth_ecp5 -top top
-write_verilog synth.v 

architecture/scripts/synth_ecp5_vpr.ys

-read_verilog ../top.v
-synth_ecp5 -vpr
-write_verilog synth.v 

architecture/scripts/synth_efinix.ys

-read_verilog ../top.v
-synth_efinix
-write_verilog synth.v

architecture/scripts/synth_efinix_edif.ys

-read_verilog ../top.v
-synth_efinix -edif edif.edif
-write_verilog synth.v

architecture/scripts/synth_efinix_json.ys

-read_verilog ../top.v
-synth_efinix -json json.json
-write_verilog synth.v

architecture/scripts/synth_efinix_noflatten.ys

-read_verilog ../top.v
-synth_efinix -noflatten
-write_verilog synth.v

architecture/scripts/synth_efinix_retime.ys

-read_verilog ../top.v
-synth_efinix -retime
-write_verilog synth.v

architecture/scripts/synth_efinix_run.ys

-read_verilog ../top.v
-synth_efinix -run begin:json
-write_verilog synth.v

architecture/scripts/synth_efinix_top.ys

-read_verilog ../top.v
-synth_efinix -top top
-write_verilog synth.v

architecture/scripts/synth_gowin.ys

-read_verilog ../top.v
-synth_gowin
-write_verilog synth.v 

architecture/scripts/synth_gowin_nobram.ys

-read_verilog ../top.v
-synth_gowin -nobram
-write_verilog synth.v

architecture/scripts/synth_gowin_nodffe.ys

-read_verilog ../top.v
-synth_gowin -nodffe
-write_verilog synth.v

architecture/scripts/synth_gowin_nodram.ys

-read_verilog ../top.v
-synth_gowin -nodram
-write_verilog synth.v

architecture/scripts/synth_gowin_noflatten.ys

-read_verilog ../top.v
-synth_gowin -noflatten
-write_verilog synth.v

architecture/scripts/synth_gowin_retime.ys

-read_verilog ../top.v
-synth_gowin -retime
-write_verilog synth.v 

architecture/scripts/synth_gowin_run.ys

-read_verilog ../top.v
-synth_gowin -run begin:vout
-write_verilog synth.v 

architecture/scripts/synth_gowin_top.ys

-read_verilog ../top.v
-synth_gowin -top top
-write_verilog synth.v 

architecture/scripts/synth_gowin_vout.ys

-read_verilog ../top.v
-synth_gowin -vout vout.v
-write_verilog synth.v 

architecture/scripts/synth_greenpak4.ys

-read_verilog ../top.v
-synth_greenpak4
-write_verilog synth.v

architecture/scripts/synth_greenpak4_json.ys

-read_verilog ../top.v
-synth_greenpak4 -json json.json
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_noflatten.ys

-read_verilog ../top.v
-synth_greenpak4 -noflatten
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_part140.ys

-read_verilog ../top.v
-synth_greenpak4 -part SLG46140V
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_part620.ys

-read_verilog ../top.v
-synth_greenpak4 -part SLG46620V
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_part621.ys

-read_verilog ../top.v
-synth_greenpak4 -part SLG46621V
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_retime.ys

-read_verilog ../top.v
-synth_greenpak4 -retime
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_run.ys

-read_verilog ../top.v
-synth_greenpak4 -run begin:json
-write_verilog synth.v 

architecture/scripts/synth_greenpak4_top.ys

-read_verilog ../top.v
-synth_greenpak4 -top top
-write_verilog synth.v 

architecture/scripts/synth_ice40.ys

-read_verilog ../top.v
-synth_ice40
-write_verilog synth.v 

architecture/scripts/synth_ice40_abc2.ys

-read_verilog ../top.v
-synth_ice40 -abc2
-write_verilog synth.v 

architecture/scripts/synth_ice40_abc9.ys

-read_verilog ../top.v
-synth_ice40 -abc9
-ice40_opt
-write_verilog synth.v

architecture/scripts/synth_ice40_blif.ys

-read_verilog ../top.v
-synth_ice40 -blif blif.blif
-write_verilog synth.v 

architecture/scripts/synth_ice40_device_hx.ys

-read_verilog ../top.v
-synth_ice40 -device hx
-write_verilog synth.v

architecture/scripts/synth_ice40_device_lp.ys

-read_verilog ../top.v
-synth_ice40 -device lp
-write_verilog synth.v

architecture/scripts/synth_ice40_device_u.ys

-read_verilog ../top.v
-synth_ice40 -device u
-write_verilog synth.v

architecture/scripts/synth_ice40_dsp.ys

-read_verilog ../top.v
-synth_ice40 -dsp
-write_verilog synth.v

architecture/scripts/synth_ice40_edif.ys

-read_verilog ../top.v
-synth_ice40 -edif edif.edif
-write_verilog synth.v 

architecture/scripts/synth_ice40_flatten.ys

-read_verilog ../top.v
-synth_ice40 -flatten
-write_verilog synth.v 

architecture/scripts/synth_ice40_json.ys

-read_verilog ../top.v
-synth_ice40 -json json.json
-write_verilog synth.v 

architecture/scripts/synth_ice40_min_ce.ys

-read_verilog ../top.v
-synth_ice40 -dffe_min_ce_use 2
-write_verilog synth.v

architecture/scripts/synth_ice40_noabc.ys

-read_verilog ../top.v
-synth_ice40 -noabc
-write_verilog synth.v

architecture/scripts/synth_ice40_nobram.ys

-read_verilog ../top.v
-synth_ice40 -nobram
-write_verilog synth.v 

architecture/scripts/synth_ice40_nocarry.ys

-read_verilog ../top.v
-synth_ice40 -nocarry
-write_verilog synth.v 

architecture/scripts/synth_ice40_nodffe.ys

-read_verilog ../top.v
-synth_ice40 -nodffe
-write_verilog synth.v 

architecture/scripts/synth_ice40_noflatten.ys

-read_verilog ../top.v
-synth_ice40 -noflatten
-write_verilog synth.v 

architecture/scripts/synth_ice40_opt.ys

-read_verilog ../top.v
-synth_ice40
-ice40_opt
-write_verilog synth.v

architecture/scripts/synth_ice40_relut.ys

-read_verilog ../top.v
-synth_ice40 -relut
-write_verilog synth.v

architecture/scripts/synth_ice40_retime.ys

-read_verilog ../top.v
-synth_ice40 -retime
-write_verilog synth.v 

architecture/scripts/synth_ice40_run.ys

-read_verilog ../top.v
-synth_ice40 -run begin:json
-write_verilog synth.v 

architecture/scripts/synth_ice40_top.ys

-read_verilog ../top.v
-synth_ice40 -top top
-write_verilog synth.v 

architecture/scripts/synth_ice40_vpr.ys

-read_verilog ../top.v
-synth_ice40 -vpr
-write_verilog synth.v 

architecture/scripts/synth_intel.ys

-read_verilog ../top.v
-synth_intel
-write_verilog synth.v 

architecture/scripts/synth_intel_a10gx.ys

-read_verilog ../top.v
-synth_intel -family a10gx
-write_verilog synth.v 

architecture/scripts/synth_intel_cyclone10.ys

-read_verilog ../top.v
-synth_intel -family cyclone10
-write_verilog synth.v 

architecture/scripts/synth_intel_cycloneiv.ys

-read_verilog ../top.v
-synth_intel -family cycloneiv
-write_verilog synth.v 

architecture/scripts/synth_intel_cycloneive.ys

-read_verilog ../top.v
-synth_intel -family cycloneive
-write_verilog synth.v 

architecture/scripts/synth_intel_cyclonev.ys

-read_verilog ../top.v
-synth_intel -family cyclonev
-write_verilog synth.v 

architecture/scripts/synth_intel_iopads.ys

-read_verilog ../top.v
-synth_intel -iopads
-write_verilog synth.v 

architecture/scripts/synth_intel_max10.ys

-read_verilog ../top.v
-synth_intel -family max10
-write_verilog synth.v 

architecture/scripts/synth_intel_nobram.ys

-read_verilog ../top.v
-synth_intel -nobram
-write_verilog synth.v 

architecture/scripts/synth_intel_noflatten.ys

-read_verilog ../top.v
-synth_intel -noflatten
-write_verilog synth.v