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Unverified Commit a141110e by Miodrag Milanović Committed by GitHub
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Merge pull request #76 from SergeyDegtyar/updated_architecture_group 

Review and update tests in 'architecture' test group
parents 91d39446 743baf58
Showing with 5365 additions and 6614 deletions
architecture/Makefile
...@@ -18,63 +18,44 @@ clean:: ...@@ -18,63 +18,44 @@ clean::
endef endef
#achronix #achronix
$(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_achronix_vout synth_achronix_run synth_achronix_noflatten synth_achronix_retime)) $(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_achronix_vout synth_achronix_run synth_achronix_noflatten synth_achronix_retime synth_achronix_fail))
$(eval $(call template,synth_achronix_error,synth_achronix_fully_selected))
#anlogic #anlogic
$(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime)) $(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime synth_anlogic_fail synth_anlogic_fulladder anlogic_determine_init_eqn))
$(eval $(call template,synth_anlogic_fulladder,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_fsm,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_mem,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime anlogic_determine_init_eqn))
$(eval $(call template,synth_anlogic_error,synth_anlogic_fully_selected))
#coolrunner2 #coolrunner2
$(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime)) $(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime synth_coolrunner2_fail synth_coolrunner2_for_lcov synth_coolrunner2_fulladder ))
$(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime)) $(eval $(call template,synth_coolrunner2_lcov,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
$(eval $(call template,synth_coolrunner2_error,synth_coolrunner2_fully_selected))
#easic - issue #920 #easic - issue #920
# we do not have eTools anymore available, commented until aquired # we do not have eTools anymore available, commented until aquired
#$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime)) #$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime synth_easic_fail))
$(eval $(call template,synth_easic_error,synth_easic_fully_selected)) $(eval $(call template,synth_easic, synth_easic_fail))
#ecp5 #ecp5
$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit synth_ecp5_abc9 synth_ecp5_abc9_nowidelut synth_ecp5_nodsp)) $(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit synth_ecp5_abc9 synth_ecp5_abc9_nowidelut synth_ecp5_nodsp synth_ecp5_fail synth_ecp5_wide_ffs))
$(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit synth_ecp5_abc9 synth_ecp5_abc9_nowidelut))
$(eval $(call template,synth_ecp5_error,synth_ecp5_fully_selected)) #efinix
$(eval $(call template,synth_efinix, synth_efinix synth_efinix_edif synth_efinix_json synth_efinix_noflatten synth_efinix_retime synth_efinix_run synth_efinix_top synth_efinix_fulladder))
#gowin #gowin
$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe )) $(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe))
$(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe ))
$(eval $(call template,synth_gowin_error,synth_gowin_fully_selected )) #greenpak4
$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140 synth_greenpak4_fully_selected_fail synth_greenpak4_invalid_part_fail synth_greenpak4_adffs synth_greenpak4_adffsr synth_greenpak4_gp_dffs synth_greenpak4_inv_inputs))
#ice40 #ice40
$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt)) $(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt synth_ice40_fully_selected_fail synth_ice40_device_unknown_fail synth_ice40_abc9 synth_ice40_abc9_retime_fail synth_ice40_mem_init synth_ice40_wide_ffs))
$(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_abc9 synth_ice40_opt))
$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
$(eval $(call template,synth_ice40_fulladder,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected synth_ice40_abc9_retime synth_ice40_device_unknown))
$(eval $(call template,ice40_wrapcarry,ice40_wrapcarry ice40_wrapcarry_top))
$(eval $(call template,ice40_wrapcarry_adders,ice40_wrapcarry ice40_wrapcarry_top))
#intel #intel
$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_iopads synth_intel_nobram synth_intel_max10 )) $(eval $(call template,synth_intel,synth_intel synth_intel_a10gx synth_intel_cyclone10 synth_intel_cycloneiv synth_intel_cycloneive synth_intel_cyclonev synth_intel_fully_selected_fail synth_intel_invalid_family_fail synth_intel_iopads synth_intel_max10 synth_intel_nobram synth_intel_noflatten synth_intel_retime synth_intel_run synth_intel_top synth_intel_vpr synth_intel_vqm ))
$(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv ))
$(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive ))
$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
$(eval $(call template,synth_intel_cyclone10,synth_intel_cyclone10 ))
$(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
$(eval $(call template,synth_intel_error ,synth_intel_fully_selected synth_intel_invalid_family ))
#sf2 #sf2
$(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime synth_sf2_vlog synth_sf2_noiobs synth_sf2_clkbuf )) $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime synth_sf2_vlog synth_sf2_noiobs synth_sf2_clkbuf synth_sf2_fully_selected_fail ))
$(eval $(call template,synth_sf2_error,synth_sf2_fully_selected )) $(eval $(call template,synth_sf2_lcov,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime synth_sf2_vlog synth_sf2_noiobs synth_sf2_clkbuf ))
#xilinx #xilinx
$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9 xilinx_srl_minlen_variable xilinx_srl_minlen synth_xilinx_nodsp synth_xilinx_noclkbuf synth_xilinx_noiopad synth_xilinx_iopad synth_xilinx_ise synth_xilinx_flatten_before_abc synth_xilinx_arch_xc6v)) $(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_nowidelut_abc9 synth_xilinx_nodsp synth_xilinx_noclkbuf synth_xilinx_noiopad synth_xilinx_iopad synth_xilinx_ise synth_xilinx_flatten_before_abc synth_xilinx_arch_xc6v synth_xilinx_abc9_retime_fail synth_xilinx_fully_selected_fail synth_xilinx_invalid_arch_fail synth_xilinx_widemux_1_fail xilinx_srl synth_xilinx_dsp))
$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch synth_xilinx_abc9_retime synth_xilinx_widemux_1))
$(eval $(call template,xilinx_srl,xilinx_srl_minlen xilinx_srl_fixed xilinx_srl_variable xilinx_srl_minlen_variable))
$(eval $(call template,synth_xilinx_dsp_cov,synth_xilinx_dsp))
ifeq ($(ENABLE_HEAVY_TESTS),1) ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,synth_xilinx_srl,synth_xilinx_srl)) $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
$(eval $(call template,synth_xilinx_mux,synth_xilinx_mux)) $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
...@@ -84,14 +65,4 @@ endif ...@@ -84,14 +65,4 @@ endif
#xilinx_ug901_synthesis_examples #xilinx_ug901_synthesis_examples
$(eval $(call template,xilinx_ug901_synthesis_examples, xilinx_ug901_asym_ram_sdp_read_wider xilinx_ug901_asym_ram_sdp_write_wider xilinx_ug901_asym_ram_tdp_read_first xilinx_ug901_asym_ram_tdp_write_first xilinx_ug901_black_box_1 xilinx_ug901_bytewrite_ram_1b xilinx_ug901_bytewrite_tdp_ram_nc xilinx_ug901_bytewrite_tdp_ram_readfirst2 xilinx_ug901_bytewrite_tdp_ram_rf xilinx_ug901_bytewrite_tdp_ram_wf xilinx_ug901_cmacc xilinx_ug901_cmult xilinx_ug901_dynamic_shift_registers_1 xilinx_ug901_dynpreaddmultadd xilinx_ug901_fsm_1 xilinx_ug901_latches xilinx_ug901_macc xilinx_ug901_mult_unsigned xilinx_ug901_presubmult xilinx_ug901_rams_dist xilinx_ug901_ram_simple_dual_one_clock xilinx_ug901_ram_simple_dual_two_clocks xilinx_ug901_rams_init_file xilinx_ug901_rams_pipeline xilinx_ug901_rams_sp_nc xilinx_ug901_rams_sp_rf xilinx_ug901_rams_sp_rf_rst xilinx_ug901_rams_sp_rom xilinx_ug901_rams_sp_rom_1 xilinx_ug901_rams_sp_wf xilinx_ug901_rams_tdp_rf_rf xilinx_ug901_registers_1 xilinx_ug901_sfir_shifter xilinx_ug901_shift_registers_0 xilinx_ug901_shift_registers_1 xilinx_ug901_squarediffmacc xilinx_ug901_squarediffmult xilinx_ug901_top_mux xilinx_ug901_tristates_1 xilinx_ug901_tristates_2 xilinx_ug901_xilinx_ultraram_single_port_no_change xilinx_ug901_xilinx_ultraram_single_port_read_first xilinx_ug901_xilinx_ultraram_single_port_write_first)) $(eval $(call template,xilinx_ug901_synthesis_examples, xilinx_ug901_asym_ram_sdp_read_wider xilinx_ug901_asym_ram_sdp_write_wider xilinx_ug901_asym_ram_tdp_read_first xilinx_ug901_asym_ram_tdp_write_first xilinx_ug901_black_box_1 xilinx_ug901_bytewrite_ram_1b xilinx_ug901_bytewrite_tdp_ram_nc xilinx_ug901_bytewrite_tdp_ram_readfirst2 xilinx_ug901_bytewrite_tdp_ram_rf xilinx_ug901_bytewrite_tdp_ram_wf xilinx_ug901_cmacc xilinx_ug901_cmult xilinx_ug901_dynamic_shift_registers_1 xilinx_ug901_dynpreaddmultadd xilinx_ug901_fsm_1 xilinx_ug901_latches xilinx_ug901_macc xilinx_ug901_mult_unsigned xilinx_ug901_presubmult xilinx_ug901_rams_dist xilinx_ug901_ram_simple_dual_one_clock xilinx_ug901_ram_simple_dual_two_clocks xilinx_ug901_rams_init_file xilinx_ug901_rams_pipeline xilinx_ug901_rams_sp_nc xilinx_ug901_rams_sp_rf xilinx_ug901_rams_sp_rf_rst xilinx_ug901_rams_sp_rom xilinx_ug901_rams_sp_rom_1 xilinx_ug901_rams_sp_wf xilinx_ug901_rams_tdp_rf_rf xilinx_ug901_registers_1 xilinx_ug901_sfir_shifter xilinx_ug901_shift_registers_0 xilinx_ug901_shift_registers_1 xilinx_ug901_squarediffmacc xilinx_ug901_squarediffmult xilinx_ug901_top_mux xilinx_ug901_tristates_1 xilinx_ug901_tristates_2 xilinx_ug901_xilinx_ultraram_single_port_no_change xilinx_ug901_xilinx_ultraram_single_port_read_first xilinx_ug901_xilinx_ultraram_single_port_write_first))
#greenpak4
$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
$(eval $(call template,synth_greenpak4_wide_ffs,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
$(eval $(call template,synth_greenpak4_dffs_r,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
$(eval $(call template,synth_greenpak4_error,synth_greenpak4_fully_selected synth_greenpak4_invalid_part))
#efinix
$(eval $(call template,synth_efinix, synth_efinix synth_efinix_edif synth_efinix_json synth_efinix_noflatten synth_efinix_retime synth_efinix_run synth_efinix_top))
$(eval $(call template,synth_efinix_fulladder, synth_efinix synth_efinix_edif synth_efinix_json synth_efinix_noflatten synth_efinix_retime synth_efinix_run synth_efinix_top))
.PHONY: all clean .PHONY: all clean
architecture/ice40_wrapcarry/testbench.v deleted 100644 → 0
module testbench;
reg [7:0] in;
wire [3:0] outA,outB;
wire [3:0] poutA,poutB;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.A(outA),
.B(outB)
);
assign poutB = in[3:0] / in[7:4];
check_comb div_test(in[7:4], outB, poutB);
endmodule
module check_comb(input [3:0] div, input [3:0] test, input [3:0] pat);
always @*
begin
#1;
if (div != 4'b0000)
if (test !== pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
$stop;
end
end
endmodule
architecture/ice40_wrapcarry_adders/testbench.v deleted 100644 → 0
module testbench;
reg [31:0] in;
wire [15:0] outA,outB;
wire [15:0] poutA,poutB;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[15:0]),
.y(in[31:16]),
.A(outA),
.B(outB)
);
assign poutA = in[15:0] + in[31:16];
assign poutB = in[15:0] - in[31:16];
check_comb add_test(outA, poutA);
check_comb sub_test(outB, poutB);
assert_comb sub0_test(outB[2], poutB[2]);
endmodule
module check_comb(input [15:0] test, input [15:0] pat);
always @*
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
$stop;
end
end
endmodule
architecture/ice40_wrapcarry_adders/top.v deleted 100644 → 0
module top
(
input [15:0] x,
input [15:0] y,
output [15:0] A,
output [15:0] B
);
assign A = x + y;
assign B = x - y;
endmodule
architecture/run.sh 100644 → 100755
...@@ -2,6 +2,7 @@ ...@@ -2,6 +2,7 @@
set -x set -x
test -d $1 test -d $1
test -f $2.ys
rm -rf $1/work_$2 rm -rf $1/work_$2
mkdir $1/work_$2 mkdir $1/work_$2
...@@ -9,58 +10,58 @@ cd $1/work_$2 ...@@ -9,58 +10,58 @@ cd $1/work_$2
touch .start touch .start
# cases where 'syntax error' or other errors are expected #
if echo "$1" | grep ".*_error"; then if [ -f ../run-test.sh ]; then
../run-test.sh
expected_string="" if [ $? != 0 ] ; then
# Change checked string for check other errors echo FAIL > ${1}_${2}.status
if echo "$2" | grep ".*_fully_selected"; then else
expected_string="ERROR: This command only operates on fully selected designs!" echo PASS > ${1}_${2}.status
elif [ "$2" = "synth_greenpak4_invalid_part" ]; then
expected_string="ERROR: Invalid part name: "
elif [ "$2" = "synth_intel_invalid_family" ]; then
expected_string="ERROR: Invalid or no family specified:"
elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
expected_string="ERROR: Invalid Xilinx -family setting: "
elif [ "$2" = "synth_xilinx_widemux_1" ]; then
expected_string="ERROR: -widemux value must be 0 or >= 2."
elif [ "$2" = "synth_xilinx_abc9_retime" ]; then
expected_string="ERROR: -retime option not currently compatible with -abc9!"
elif [ "$2" = "synth_ice40_abc9_retime" ]; then
expected_string="ERROR: -retime option not currently compatible with -abc9!"
elif [ "$2" = "synth_ice40_device_unknown" ]; then
expected_string="ERROR: Invalid or no device specified: "
fi fi
touch .stamp
if yosys -ql yosys.log ../../scripts/$2.ys; then exit
fi
if [[ $2 =~ "_fail" ]]; then
#4 - An error expected
if yosys -ql yosys.log ../$2.ys; then
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
else else
if grep "$expected_string" yosys.log && [ "$expected_string" != "" ]; then if [ -f "../$2.pat" ]; then
expectation=$(<../$2.pat)
if grep "$expectation" yosys.log; then
echo PASS > ${1}_${2}.status echo PASS > ${1}_${2}.status
else else
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
fi fi
else
echo PASS > ${1}_${2}.status
fi
fi fi
else else
#2 - All asserts in .ys script
if [ -f ../run-test.sh ]; then yosys -ql yosys.log ../$2.ys
../run-test.sh
if [ $? != 0 ] ; then if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
else else
#3 Output log check
if [ -f "../$2.pat" ]; then # Expected behavior
expectation=$(<../$2.pat)
if grep "$expectation" result.out; then
echo PASS > ${1}_${2}.status echo PASS > ${1}_${2}.status
fi
touch .stamp
exit
else else
test -f scripts/$2.ys
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi fi
elif [ -f "../$2_n.pat" ]; then # Not expected behavior
expectation=$(<../$2_n.pat)
if grep "$expectation" result.out; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi fi
#1 Iverilog run when testbench exists
elif [ -f "../testbench.v" ]; then
if [ -f "../../../../../techlibs/common/simcells.v" ]; then if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs TECHLIBS_PREFIX=../../../../../techlibs
...@@ -68,84 +69,17 @@ else ...@@ -68,84 +69,17 @@ else
COMMON_PREFIX=/usr/local/share/yosys COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys TECHLIBS_PREFIX=/usr/local/share/yosys
fi fi
if [ -f "../iverilog_adds.txt" ]; then
if [ "$1" = "synth_ecp5" ]; then iverilog_adds=$TECHLIBS_PREFIX/$(<../iverilog_adds.txt)
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
elif [ "$1" = "synth_ecp5_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ecp5/cells_sim.v
elif [ "$1" = "synth_achronix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/achronix/speedster22i/cells_sim.v
elif [ "$1" = "synth_anlogic" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fsm" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v $TECHLIBS_PREFIX/anlogic/eagle_bb.v
elif [ "$1" = "synth_coolrunner2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
elif [ "$1" = "synth_coolrunner2_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/coolrunner2/cells_sim.v
elif [ "$1" = "synth_gowin" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
elif [ "$1" = "synth_gowin_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/gowin/cells_sim.v
elif [ "$1" = "synth_ice40" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "ice40_wrapcarry" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v $TECHLIBS_PREFIX/ice40/abc9_model.v
elif [ "$1" = "ice40_wrapcarry_adders" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v $TECHLIBS_PREFIX/ice40/abc9_model.v
elif [ "$1" = "synth_intel" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
elif [ "$1" = "synth_intel_a10gx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/a10gx/cells_sim.v
elif [ "$1" = "synth_intel_cycloneiv" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneiv/cells_sim.v
elif [ "$1" = "synth_intel_cycloneive" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cycloneive/cells_sim.v
elif [ "$1" = "synth_intel_cyclone10" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclone10/cells_sim.v
elif [ "$1" = "synth_intel_cyclonev" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/cyclonev/cells_sim.v
elif [ "$1" = "synth_sf2" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "xilinx_srl" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_dffs_r" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_efinix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
elif [ "$1" = "synth_efinix_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
elif [ "$1" = "xilinx_ug901_synthesis_examples" ] || \
[ "$1" = "synth_xilinx_dsp_cov" ]; then
:
else else
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v iverilog_adds=""
fi fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
if [ $? != 0 ] ; then if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
touch .stamp touch .stamp
exit 0 exit 0
fi fi
if [ "$1" = "xilinx_ug901_synthesis_examples" ] || \
[ "$1" = "synth_xilinx_dsp_cov" ]; then
echo PASS > ${1}_${2}.status
else
if ! vvp -N testbench > testbench.log 2>&1; then if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status echo FAIL > ${1}_${2}.status
...@@ -154,8 +88,9 @@ else ...@@ -154,8 +88,9 @@ else
else else
echo PASS > ${1}_${2}.status echo PASS > ${1}_${2}.status
fi fi
else
echo PASS > ${1}_${2}.status
fi
fi fi
fi fi
touch .stamp touch .stamp
architecture/scripts/ice40_wrapcarry.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
ice40_wrapcarry
write_verilog synth.v
architecture/scripts/ice40_wrapcarry_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
ice40_wrapcarry top
write_verilog synth.v
architecture/scripts/synth_achronix.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix
write_verilog synth.v
architecture/scripts/synth_achronix_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -noflatten
write_verilog synth.v
architecture/scripts/synth_achronix_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -retime
write_verilog synth.v
architecture/scripts/synth_achronix_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -run begin:vout
write_verilog synth.v
architecture/scripts/synth_achronix_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -top top
write_verilog synth.v
architecture/scripts/synth_achronix_vout.ys deleted 100644 → 0
read_verilog ../top.v
synth_achronix -vout vout.v
write_verilog synth.v
architecture/scripts/synth_anlogic.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic
write_verilog synth.v
architecture/scripts/synth_anlogic_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_anlogic_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -json json.json
write_verilog synth.v
architecture/scripts/synth_anlogic_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -noflatten
write_verilog synth.v
architecture/scripts/synth_anlogic_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -retime
write_verilog synth.v
architecture/scripts/synth_anlogic_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -run begin:json
write_verilog synth.v
architecture/scripts/synth_anlogic_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_anlogic -top top
write_verilog synth.v
architecture/scripts/synth_coolrunner2_mem.ys deleted 100644 → 0
read_verilog ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/SimDTM.v
#
synth_coolrunner2
write_verilog synth.v
architecture/scripts/synth_coolrunner2_vlog.ys deleted 100644 → 0
read_verilog ../top.v
synth_easic -vlog vlog.v
write_verilog synth.v
architecture/scripts/synth_ecp5.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5
write_verilog synth.v
architecture/scripts/synth_ecp5_abc2.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -abc2
write_verilog synth.v
architecture/scripts/synth_ecp5_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -abc9
write_verilog synth.v
architecture/scripts/synth_ecp5_abc9_nowidelut.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -abc9 -nowidelut
write_verilog synth.v
architecture/scripts/synth_ecp5_blif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -blif blif.blif
write_verilog synth.v
architecture/scripts/synth_ecp5_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_ecp5_flatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -flatten
write_verilog synth.v
architecture/scripts/synth_ecp5_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -json json.json
write_verilog synth.v
architecture/scripts/synth_ecp5_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nobram
write_verilog synth.v
architecture/scripts/synth_ecp5_noccu2.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -noccu2
write_verilog synth.v
architecture/scripts/synth_ecp5_nodffe.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nodffe
write_verilog synth.v
architecture/scripts/synth_ecp5_nodram.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nodram
write_verilog synth.v
architecture/scripts/synth_ecp5_nodsp.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nodsp
write_verilog synth.v
architecture/scripts/synth_ecp5_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -noflatten
write_verilog synth.v
architecture/scripts/synth_ecp5_nomux.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -nomux
write_verilog synth.v
architecture/scripts/synth_ecp5_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -retime
write_verilog synth.v
architecture/scripts/synth_ecp5_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -run begin:json
write_verilog synth.v
architecture/scripts/synth_ecp5_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -top top
write_verilog synth.v
architecture/scripts/synth_ecp5_vpr.ys deleted 100644 → 0
read_verilog ../top.v
synth_ecp5 -vpr
write_verilog synth.v
architecture/scripts/synth_efinix.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix
write_verilog synth.v
architecture/scripts/synth_efinix_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_efinix_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -json json.json
write_verilog synth.v
architecture/scripts/synth_efinix_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -noflatten
write_verilog synth.v
architecture/scripts/synth_efinix_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -retime
write_verilog synth.v
architecture/scripts/synth_efinix_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -run begin:json
write_verilog synth.v
architecture/scripts/synth_efinix_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_efinix -top top
write_verilog synth.v
architecture/scripts/synth_gowin.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin
write_verilog synth.v
architecture/scripts/synth_gowin_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -nobram
write_verilog synth.v
architecture/scripts/synth_gowin_nodffe.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -nodffe
write_verilog synth.v
architecture/scripts/synth_gowin_nodram.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -nodram
write_verilog synth.v
architecture/scripts/synth_gowin_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -noflatten
write_verilog synth.v
architecture/scripts/synth_gowin_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -retime
write_verilog synth.v
architecture/scripts/synth_gowin_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -run begin:vout
write_verilog synth.v
architecture/scripts/synth_gowin_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -top top
write_verilog synth.v
architecture/scripts/synth_gowin_vout.ys deleted 100644 → 0
read_verilog ../top.v
synth_gowin -vout vout.v
write_verilog synth.v
architecture/scripts/synth_greenpak4.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4
write_verilog synth.v
architecture/scripts/synth_greenpak4_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -json json.json
write_verilog synth.v
architecture/scripts/synth_greenpak4_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -noflatten
write_verilog synth.v
architecture/scripts/synth_greenpak4_part140.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part SLG46140V
write_verilog synth.v
architecture/scripts/synth_greenpak4_part620.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part SLG46620V
write_verilog synth.v
architecture/scripts/synth_greenpak4_part621.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -part SLG46621V
write_verilog synth.v
architecture/scripts/synth_greenpak4_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -retime
write_verilog synth.v
architecture/scripts/synth_greenpak4_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -run begin:json
write_verilog synth.v
architecture/scripts/synth_greenpak4_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_greenpak4 -top top
write_verilog synth.v
architecture/scripts/synth_ice40.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
write_verilog synth.v
architecture/scripts/synth_ice40_abc2.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -abc2
write_verilog synth.v
architecture/scripts/synth_ice40_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -abc9
ice40_opt
write_verilog synth.v
architecture/scripts/synth_ice40_blif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -blif blif.blif
write_verilog synth.v
architecture/scripts/synth_ice40_device_hx.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -device hx
write_verilog synth.v
architecture/scripts/synth_ice40_device_lp.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -device lp
write_verilog synth.v
architecture/scripts/synth_ice40_device_u.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -device u
write_verilog synth.v
architecture/scripts/synth_ice40_dsp.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -dsp
write_verilog synth.v
architecture/scripts/synth_ice40_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_ice40_flatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -flatten
write_verilog synth.v
architecture/scripts/synth_ice40_json.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -json json.json
write_verilog synth.v
architecture/scripts/synth_ice40_min_ce.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -dffe_min_ce_use 2
write_verilog synth.v
architecture/scripts/synth_ice40_noabc.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -noabc
write_verilog synth.v
architecture/scripts/synth_ice40_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -nobram
write_verilog synth.v
architecture/scripts/synth_ice40_nocarry.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -nocarry
write_verilog synth.v
architecture/scripts/synth_ice40_nodffe.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -nodffe
write_verilog synth.v
architecture/scripts/synth_ice40_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -noflatten
write_verilog synth.v
architecture/scripts/synth_ice40_opt.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40
ice40_opt
write_verilog synth.v
architecture/scripts/synth_ice40_relut.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -relut
write_verilog synth.v
architecture/scripts/synth_ice40_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -retime
write_verilog synth.v
architecture/scripts/synth_ice40_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -run begin:json
write_verilog synth.v
architecture/scripts/synth_ice40_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -top top
write_verilog synth.v
architecture/scripts/synth_ice40_vpr.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -vpr
write_verilog synth.v
architecture/scripts/synth_intel.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel
write_verilog synth.v
architecture/scripts/synth_intel_a10gx.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -family a10gx
write_verilog synth.v
architecture/scripts/synth_intel_cyclone10.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -family cyclone10
write_verilog synth.v
architecture/scripts/synth_intel_cycloneiv.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -family cycloneiv
write_verilog synth.v
architecture/scripts/synth_intel_cycloneive.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -family cycloneive
write_verilog synth.v
architecture/scripts/synth_intel_cyclonev.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -family cyclonev
write_verilog synth.v
architecture/scripts/synth_intel_iopads.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -iopads
write_verilog synth.v
architecture/scripts/synth_intel_max10.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -family max10
write_verilog synth.v
architecture/scripts/synth_intel_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -nobram
write_verilog synth.v
architecture/scripts/synth_intel_noflatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -noflatten
write_verilog synth.v
architecture/scripts/synth_intel_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -retime
write_verilog synth.v
architecture/scripts/synth_intel_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -run family:vpr
write_verilog synth.v
architecture/scripts/synth_intel_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -top top
write_verilog synth.v
architecture/scripts/synth_intel_vpr.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -vpr vpr.vpr
write_verilog synth.v
architecture/scripts/synth_intel_vqm.ys deleted 100644 → 0
read_verilog ../top.v
synth_intel -vqm vqm.vqm
write_verilog synth.v
architecture/scripts/synth_sf2_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_sf2 -top top
write_verilog synth.v
architecture/scripts/synth_xilinx.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
write_verilog synth.v
architecture/scripts/synth_xilinx_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -abc9
write_verilog synth.v
architecture/scripts/synth_xilinx_arch_xc6s.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -arch xc6s
write_verilog synth.v
architecture/scripts/synth_xilinx_arch_xc6s_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -arch xc6s -abc9
write_verilog synth.v
architecture/scripts/synth_xilinx_arch_xc6v.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -arch xc6v
write_verilog synth.v
architecture/scripts/synth_xilinx_arch_xc7.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -arch xc7
write_verilog synth.v
architecture/scripts/synth_xilinx_arch_xcu.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -arch xcu
write_verilog synth.v
architecture/scripts/synth_xilinx_arch_xcup.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -arch xcup
write_verilog synth.v
architecture/scripts/synth_xilinx_blif.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -blif blif.blif
write_verilog synth.v
architecture/scripts/synth_xilinx_dsp.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
select -assert-count 3 t:DSP48E1
architecture/scripts/synth_xilinx_edif.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_xilinx_flatten.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -flatten
write_verilog synth.v
architecture/scripts/synth_xilinx_flatten_before_abc.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -flatten_before_abc
write_verilog synth.v
architecture/scripts/synth_xilinx_iopad.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -iopad
write_verilog synth.v
architecture/scripts/synth_xilinx_ise.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -ise
write_verilog synth.v
architecture/scripts/synth_xilinx_nobram.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nobram
write_verilog synth.v
architecture/scripts/synth_xilinx_nocarry.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nocarry
write_verilog synth.v
architecture/scripts/synth_xilinx_noclkbuf.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -noclkbuf
write_verilog synth.v
architecture/scripts/synth_xilinx_nodram.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nodram
write_verilog synth.v
architecture/scripts/synth_xilinx_nodsp.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nodsp
write_verilog synth.v
architecture/scripts/synth_xilinx_noiopad.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -noiopad
write_verilog synth.v
architecture/scripts/synth_xilinx_nosrl.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nosrl
write_verilog synth.v
architecture/scripts/synth_xilinx_nosrt.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nosrl
write_verilog synth.v
architecture/scripts/synth_xilinx_nowidelut.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nowidelut
write_verilog synth.v
architecture/scripts/synth_xilinx_nowidelut_abc9.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nowidelut -abc9
write_verilog synth.v
architecture/scripts/synth_xilinx_retime.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -retime
write_verilog synth.v
architecture/scripts/synth_xilinx_run.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -run begin:blif
write_verilog synth.v
architecture/scripts/synth_xilinx_top.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -top top
write_verilog synth.v
architecture/scripts/synth_xilinx_vpr.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -vpr
write_verilog synth.v
architecture/scripts/synth_xilinx_widemux.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -widemux 5
write_verilog synth.v
architecture/scripts/synth_xilinx_widemux_2.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -widemux 2
write_verilog synth.v
architecture/scripts/synth_xilinx_widemux_3.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -widemux 3
write_verilog synth.v
architecture/scripts/synth_xilinx_widemux_9.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -widemux 9
write_verilog synth.v
architecture/scripts/xilinx_srl_fixed.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
xilinx_srl -fixed
write_verilog synth.v
architecture/scripts/xilinx_srl_minlen.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
xilinx_srl -fixed -minlen 1
design -reset
read_verilog ../top.v
synth_xilinx
write_verilog synth.v
architecture/scripts/xilinx_srl_minlen_variable.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
xilinx_srl -variable -minlen 1
design -reset
read_verilog ../top.v
synth_xilinx
write_verilog synth.v
architecture/scripts/xilinx_srl_variable.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
xilinx_srl -variable
write_verilog synth.v
architecture/scripts/xilinx_ug901_presubmult.ys deleted 100644 → 0
read_verilog ../presubmult.v
hierarchy -top presubmult
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd presubmult
#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/scripts/xilinx_ug901_ram_simple_dual_one_clock.ys deleted 100644 → 0
read_verilog ../ram_simple_dual_one_clock.v
hierarchy -top simple_dual_one_clock
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_one_clock
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/scripts/xilinx_ug901_ram_simple_dual_two_clocks.ys deleted 100644 → 0
read_verilog ../ram_simple_dual_two_clocks.v
hierarchy -top simple_dual_two_clocks
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_two_clocks
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/scripts/xilinx_ug901_rams_dist.ys deleted 100644 → 0
read_verilog ../rams_dist.v
hierarchy -top rams_dist
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_dist
stat
#Vivado synthesizes 32 RAM64X1D.
select -assert-count 1 t:BUFG
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:RAM64X1D %% t:* %D
architecture/scripts/xilinx_ug901_rams_init_file.ys deleted 100644 → 0
read_verilog ../rams_init_file.v
hierarchy -top rams_init_file
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_init_file
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
architecture/scripts/xilinx_ug901_rams_pipeline.ys deleted 100644 → 0
read_verilog ../rams_pipeline.v
hierarchy -top rams_pipeline
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_pipeline
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 2 t:RAMB18E1
select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D
architecture/scripts/xilinx_ug901_rams_sp_nc.ys deleted 100644 → 0
read_verilog ../rams_sp_nc.v
hierarchy -top rams_sp_nc
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_nc
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 2 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/scripts/xilinx_ug901_rams_sp_rf.ys deleted 100644 → 0
read_verilog ../rams_sp_rf.v
hierarchy -top rams_sp_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/scripts/xilinx_ug901_rams_sp_rf_rst.ys deleted 100644 → 0
read_verilog ../rams_sp_rf_rst.v
hierarchy -top rams_sp_rf_rst
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf_rst
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 5 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 13 t:LUT4
select -assert-count 23 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
architecture/scripts/xilinx_ug901_rams_sp_rom.ys deleted 100644 → 0
read_verilog ../rams_sp_rom.v
hierarchy -top rams_sp_rom
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 20 t:RAM64X1D
select -assert-count 20 t:FDRE
select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
architecture/scripts/xilinx_ug901_rams_sp_rom_1.ys deleted 100644 → 0
read_verilog ../rams_sp_rom_1.v
hierarchy -top rams_sp_rom_1
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom_1
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 14 t:LUT6
select -assert-count 14 t:FDRE
select -assert-none t:BUFG t:LUT6 t:FDRE %% t:* %D
architecture/scripts/xilinx_ug901_rams_sp_wf.ys deleted 100644 → 0
read_verilog ../rams_sp_wf.v
hierarchy -top rams_sp_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_wf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 44 t:LUT5
select -assert-count 38 t:LUT6
select -assert-count 10 t:MUXF7
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture/scripts/xilinx_ug901_rams_tdp_rf_rf.ys deleted 100644 → 0
read_verilog ../rams_tdp_rf_rf.v
hierarchy -top rams_tdp_rf_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_tdp_rf_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:LUT2
select -assert-none t:$mem t:LUT2 %% t:* %D
architecture/scripts/xilinx_ug901_registers_1.ys deleted 100644 → 0
read_verilog ../registers_1.v
hierarchy -top registers_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 8 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 9 t:LUT2
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
architecture/scripts/xilinx_ug901_sfir_shifter.ys deleted 100644 → 0
read_verilog ../sfir_shifter.v
hierarchy -top sfir_shifter
proc
flatten
#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd sfir_shifter
#Vivado synthesizes 32 FDRE, 16 SRL16E.
stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
architecture/scripts/xilinx_ug901_shift_registers_0.ys deleted 100644 → 0
read_verilog ../shift_registers_0.v
hierarchy -top shift_registers_0
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_0 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/scripts/xilinx_ug901_shift_registers_1.ys deleted 100644 → 0
read_verilog ../shift_registers_1.v
hierarchy -top shift_registers_1
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/scripts/xilinx_ug901_squarediffmacc.ys deleted 100644 → 0
read_verilog ../squarediffmacc.v
hierarchy -top squarediffmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd squarediffmacc
#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 17 t:FDRE
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/scripts/xilinx_ug901_squarediffmult.ys deleted 100644 → 0
read_verilog ../squarediffmult.v
hierarchy -top squarediffmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd squarediffmult
stat
#Vivado synthesizes 16 FDRE, 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 32 t:FDRE
select -assert-count 65 t:LUT2
select -assert-count 16 t:MUXCY
select -assert-count 17 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/scripts/xilinx_ug901_top_mux.ys deleted 100644 → 0
read_verilog ../top_mux.v
hierarchy -top mux4
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4
#Vivado synthesizes 2 LUT.
stat
select -assert-count 2 t:LUT6
select -assert-none t:LUT6 %% t:* %D
architecture/scripts/xilinx_ug901_tristates_1.ys deleted 100644 → 0
read_verilog ../tristates_1.v
hierarchy -top tristates_1
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/scripts/xilinx_ug901_tristates_2.ys deleted 100644 → 0
read_verilog ../tristates_2.v
hierarchy -top tristates_2
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_2 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/scripts/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys deleted 100644 → 0
read_verilog ../xilinx_ultraram_single_port_no_change.v
hierarchy -top xilinx_ultraram_single_port_no_change
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_no_change
stat
#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 9 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/scripts/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys deleted 100644 → 0
read_verilog ../xilinx_ultraram_single_port_read_first.v
hierarchy -top xilinx_ultraram_single_port_read_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_read_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 8 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/scripts/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys deleted 100644 → 0
read_verilog ../xilinx_ultraram_single_port_write_first.v
hierarchy -top xilinx_ultraram_single_port_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_write_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 44 t:FDRE
select -assert-count 8 t:LUT5
select -assert-count 8 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/synth_achronix/synth_achronix.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/achronix/speedster22i/cells_sim.v synth_achronix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top
select -assert-count 2 t:LUT4
select -assert-count 3 t:PADIN
select -assert-count 2 t:PADOUT
select -assert-none t:LUT4 t:PADIN t:PADOUT %% t:* %D
architecture/synth_achronix/synth_achronix_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_achronix_fully_selected.ys → architecture/synth_achronix/synth_achronix_fail.ys
read_verilog ../top.v read_verilog ../top.v
select top2 select top2
synth_achronix synth_achronix
write_verilog synth.v
architecture/synth_achronix/synth_achronix_noflatten.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/achronix/speedster22i/cells_sim.v synth_achronix -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top
select -assert-count 2 t:LUT4
select -assert-count 3 t:PADIN
select -assert-count 2 t:PADOUT
select -assert-none t:LUT4 t:PADIN t:PADOUT %% t:* %D
architecture/synth_achronix/synth_achronix_retime.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/achronix/speedster22i/cells_sim.v synth_achronix -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top
select -assert-count 2 t:LUT4
select -assert-count 3 t:PADIN
select -assert-count 2 t:PADOUT
select -assert-none t:LUT4 t:PADIN t:PADOUT %% t:* %D
architecture/synth_achronix/synth_achronix_run.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/achronix/speedster22i/cells_sim.v synth_achronix -run begin:vout # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top
select -assert-count 2 t:LUT4
select -assert-count 3 t:PADIN
select -assert-count 2 t:PADOUT
select -assert-none t:LUT4 t:PADIN t:PADOUT %% t:* %D
architecture/synth_achronix/synth_achronix_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/achronix/speedster22i/cells_sim.v synth_achronix -top top # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top
select -assert-count 2 t:LUT4
select -assert-count 3 t:PADIN
select -assert-count 2 t:PADOUT
select -assert-none t:LUT4 t:PADIN t:PADOUT %% t:* %D
architecture/synth_achronix/synth_achronix_vout.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
equiv_opt -assert -map +/achronix/speedster22i/cells_sim.v synth_achronix -vout vout.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top
select -assert-count 2 t:LUT4
select -assert-count 3 t:PADIN
select -assert-count 2 t:PADOUT
select -assert-none t:LUT4 t:PADIN t:PADOUT %% t:* %D
architecture/synth_achronix/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_achronix/top.v
...@@ -8,10 +8,6 @@ module top ...@@ -8,10 +8,6 @@ module top
output cout output cout
); );
`ifndef BUG
assign {cout,A} = cin + y + x; assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
architecture/synth_achronix_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_achronix_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module top2
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/scripts/anlogic_determine_init_eqn.ys → architecture/synth_anlogic/anlogic_determine_init_eqn.ys
read_verilog ../top.v read_verilog ../top_mem.v
read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v
proc proc
flatten flatten
...@@ -7,7 +7,7 @@ deminout ...@@ -7,7 +7,7 @@ deminout
synth -run coarse synth -run coarse
memory_bram -rules +/anlogic/drams.txt memory_bram -rules +/anlogic/drams.txt
techmap -map +/anlogic/drams_map.v techmap -map +/anlogic/drams_map.v
anlogic_determine_init #anlogic_determine_init
opt -fast -mux_undef -undriven -fine opt -fast -mux_undef -undriven -fine
memory_map memory_map
opt -undriven -fine opt -undriven -fine
......
architecture/synth_anlogic/synth_anlogic.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/synth_anlogic_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/synth_anlogic_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_anlogic_fully_selected.ys → architecture/synth_anlogic/synth_anlogic_fail.ys
read_verilog ../top.v read_verilog ../top.v
select dffe select dffe
synth_anlogic synth_anlogic
write_verilog synth.v
architecture/synth_anlogic/synth_anlogic_fulladder.ys 0 → 100644
read_verilog ../top_fulladder.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 7 t:AL_MAP_ADDER
select -assert-count 8 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT3 %% t:* %D
architecture/synth_anlogic/synth_anlogic_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/synth_anlogic_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/synth_anlogic_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/synth_anlogic_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/synth_anlogic_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_SEQ %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-count 1 t:AL_MAP_SEQ
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
architecture/synth_anlogic/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_anlogic/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge clr ) always @( posedge clk )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -37,92 +14,5 @@ module dffe ...@@ -37,92 +14,5 @@ module dffe
end end
always @( posedge clk) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/ice40_wrapcarry/top.v → architecture/synth_anlogic/top_fulladder.v
...@@ -2,11 +2,12 @@ module top ...@@ -2,11 +2,12 @@ module top
( (
input [3:0] x, input [3:0] x,
input [3:0] y, input [3:0] y,
input [3:0] cin,
output [3:0] A, output [4:0] A,
output [3:0] B output [4:0] cout
); );
assign B = x / y; assign {cout,A} = cin + y + x;
endmodule endmodule
architecture/synth_anlogic/top_mem.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_anlogic_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_anlogic_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_anlogic_fsm/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_anlogic_fsm/top.v deleted 100644 → 0
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
architecture/synth_anlogic_fulladder/testbench.v deleted 100644 → 0
module testbench;
reg [11:0] in;
wire [4:0] patt_out,out;
wire [4:0] patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.cin(in[11:8]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[11:8] + in[7:4] + in[3:0];
assert_comb out_test(.A(patt_out[3]), .B(out[3]));
assert_comb carry_test(.A(patt_carry_out[3]), .B(carryout[3]));
endmodule
architecture/synth_anlogic_fulladder/top.v deleted 100644 → 0
module top
(
input [3:0] x,
input [3:0] y,
input [3:0] cin,
output [4:0] A,
output [4:0] cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_anlogic_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [5:0] addr_a = 0;
reg we_a = 0;
wire [7:0] q_a;
reg mem_init = 0;
top uut (
.data_a(data_a),
.addr_a(addr_a),
.we_a(we_a),
.clk(clk),
.q_a(q_a)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
addr_a <= addr_a + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_anlogic_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_coolrunner2/synth_coolrunner2.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-count 1 t:MACROCELL_XOR
select -assert-count 1 t:ORTERM
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/synth_coolrunner2_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_coolrunner2_fully_selected.ys → architecture/synth_coolrunner2/synth_coolrunner2_fail.ys
read_verilog ../top.v read_verilog ../top.v
select dffe select dffe
synth_coolrunner2 synth_coolrunner2
write_verilog synth.v
architecture/synth_coolrunner2/synth_coolrunner2_for_lcov.ys 0 → 100644
read_verilog ../top.v
synth_coolrunner2 -retime
design -reset
read_verilog ../top.v
synth_coolrunner2 -noflatten
design -reset
read_verilog ../top.v
synth_coolrunner2 -top dff
design -reset
read_verilog ../top.v
synth_coolrunner2 -json json.json
design -reset
read_verilog ../top.v
synth_coolrunner2 -run begin:json
architecture/synth_coolrunner2/synth_coolrunner2_fulladder.ys 0 → 100644
read_verilog ../top_fulladder.v
hierarchy -top top
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 7 t:ANDTERM
select -assert-count 3 t:IBUF
select -assert-count 2 t:IOBUFE
select -assert-count 2 t:MACROCELL_XOR
select -assert-count 2 t:ORTERM
select -assert-none t:ANDTERM t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/synth_coolrunner2_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -noflatten # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -noflatten # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-count 1 t:MACROCELL_XOR
select -assert-count 1 t:ORTERM
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/synth_coolrunner2_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -retime # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -retime # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-count 1 t:MACROCELL_XOR
select -assert-count 1 t:ORTERM
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/synth_coolrunner2_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -run begin:json # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -run begin:json # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-count 1 t:MACROCELL_XOR
select -assert-count 1 t:ORTERM
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/synth_coolrunner2_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -top dff # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -top dffe # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-count 1 t:MACROCELL_XOR
select -assert-count 1 t:ORTERM
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/synth_coolrunner2_vout.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -json json.json # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FDCP
select -assert-count 2 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-none t:FDCP t:IBUF t:IOBUFE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option skipped because of unproven cells
#equiv_opt -assert -map +/coolrunner2/cells_sim.v synth_coolrunner2 -json json.json # equivalency check
equiv_opt -map +/coolrunner2/cells_sim.v synth_coolrunner2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:ANDTERM
select -assert-count 1 t:FDCP
select -assert-count 3 t:IBUF
select -assert-count 1 t:IOBUFE
select -assert-count 1 t:MACROCELL_XOR
select -assert-count 1 t:ORTERM
select -assert-none t:ANDTERM t:FDCP t:IBUF t:IOBUFE t:MACROCELL_XOR t:ORTERM %% t:* %D
architecture/synth_coolrunner2/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_coolrunner2/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge clr ) always @( posedge clk )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -35,94 +12,7 @@ module dffe ...@@ -35,94 +12,7 @@ module dffe
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge en ) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_coolrunner2/top_fulladder.v 0 → 100644
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_coolrunner2_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_coolrunner2_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_coolrunner2_fulladder/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_coolrunner2_fulladder/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/scripts/synth_coolrunner2.ys → architecture/synth_coolrunner2_lcov/synth_coolrunner2.ys
read_verilog ../top.v read_verilog ../top.v
synth_coolrunner2 synth_coolrunner2
write_verilog synth.v
architecture/scripts/synth_coolrunner2_noflatten.ys → architecture/synth_coolrunner2_lcov/synth_coolrunner2_noflatten.ys
read_verilog ../top.v read_verilog ../top.v
synth_coolrunner2 -noflatten synth_coolrunner2 -noflatten
write_verilog synth.v
architecture/scripts/synth_coolrunner2_retime.ys → architecture/synth_coolrunner2_lcov/synth_coolrunner2_retime.ys
read_verilog ../top.v read_verilog ../top.v
synth_coolrunner2 -retime synth_coolrunner2 -retime
write_verilog synth.v
architecture/scripts/synth_coolrunner2_run.ys → architecture/synth_coolrunner2_lcov/synth_coolrunner2_run.ys
read_verilog ../top.v read_verilog ../top.v
synth_coolrunner2 -run begin:json synth_coolrunner2 -run begin:json
write_verilog synth.v
architecture/scripts/synth_coolrunner2_top.ys → architecture/synth_coolrunner2_lcov/synth_coolrunner2_top.ys
read_verilog ../top.v read_verilog ../top.v
synth_coolrunner2 -top top synth_coolrunner2 -top top
write_verilog synth.v
architecture/scripts/synth_coolrunner2_vout.ys → architecture/synth_coolrunner2_lcov/synth_coolrunner2_vout.ys
read_verilog ../top.v read_verilog ../top.v
synth_coolrunner2 -json json.json synth_coolrunner2 -json json.json
write_verilog synth.v
architecture/synth_coolrunner2_lcov/top.v 0 → 100644
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_easic/synth_easic_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_easic_fully_selected.ys → architecture/synth_easic/synth_easic_fail.ys
read_verilog ../top.v read_verilog ../top.v
select dffe select dffe
synth_easic synth_easic
write_verilog synth.v
architecture/synth_easic/top.v
...@@ -5,11 +5,7 @@ module adff ...@@ -5,11 +5,7 @@ module adff
end end
always @( posedge clk, posedge clr ) always @( posedge clk, posedge clr )
if ( clr ) if ( clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else else
q <= d; q <= d;
endmodule endmodule
...@@ -21,11 +17,7 @@ module adffn ...@@ -21,11 +17,7 @@ module adffn
end end
always @( posedge clk, negedge clr ) always @( posedge clk, negedge clr )
if ( !clr ) if ( !clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else else
q <= d; q <= d;
endmodule endmodule
...@@ -37,11 +29,7 @@ module dffe ...@@ -37,11 +29,7 @@ module dffe
end end
always @( posedge clk, posedge en ) always @( posedge clk, posedge en )
if ( en ) if ( en )
`ifndef BUG
q <= d; q <= d;
`else
q <= 1'b0;
`endif
endmodule endmodule
module dffsr module dffsr
...@@ -51,11 +39,7 @@ module dffsr ...@@ -51,11 +39,7 @@ module dffsr
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk, posedge pre, posedge clr )
if ( clr ) if ( clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else if ( pre ) else if ( pre )
q <= 1'b1; q <= 1'b1;
else else
...@@ -69,11 +53,7 @@ module ndffnsnr ...@@ -69,11 +53,7 @@ module ndffnsnr
end end
always @( negedge clk, negedge pre, negedge clr ) always @( negedge clk, negedge pre, negedge clr )
if ( !clr ) if ( !clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre ) else if ( !pre )
q <= 1'b1; q <= 1'b1;
else else
......
architecture/synth_easic_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_easic_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ecp5/synth_ecp5.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_abc2.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_abc9_nowidelut.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -abc9 -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_blif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_ecp5_fully_selected.ys → architecture/synth_ecp5/synth_ecp5_fail.ys
read_verilog ../top.v read_verilog ../top.v
select dffe select dffe
synth_ecp5 synth_ecp5
write_verilog synth.v
architecture/synth_ecp5/synth_ecp5_flatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_nobram.ys 0 → 100644
read_verilog ../top_dpram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#Blocked by issue #1358 (Missing ECP5 simulation models)
#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:DP16KD
select -assert-none t:DP16KD %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#Blocked by issue #1358 (Missing ECP5 simulation models)
#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 144 t:LUT4
select -assert-count 17 t:PFUMX
select -assert-count 32 t:TRELLIS_DPR16X4
select -assert-count 143 t:TRELLIS_FF
select -assert-none t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_noccu2.ys 0 → 100644
read_verilog ../top_counter.v
design -save read
hierarchy -top top
proc
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:CCU2C
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 -noccu2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT4
select -assert-count 1 t:PFUMX
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_nodffe.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT4
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
architecture/synth_ecp5/synth_ecp5_nodram.ys 0 → 100644
read_verilog ../top_dpram.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -nodram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#Blocked by issue #1358 (Missing ECP5 simulation models)
#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:DP16KD
select -assert-none t:DP16KD %% t:* %D
architecture/synth_ecp5/synth_ecp5_nodsp.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:MULT18X18D
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:MULT18X18D t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT4
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_nomux.ys 0 → 100644
read_verilog ../top_mux.v
design -save read
hierarchy -top mux8
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:L6MUX21
select -assert-count 7 t:LUT4
select -assert-count 2 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -nomux # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
stat
select -assert-count 5 t:LUT4
select -assert-none t:LUT4 %% t:* %D
architecture/synth_ecp5/synth_ecp5_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_vpr.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
architecture/synth_ecp5/synth_ecp5_wide_ffs.ys 0 → 100644
read_verilog ../top_wide_ffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:LUT4
select -assert-count 4 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top adff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffsr
proc
flatten
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffsr # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:TRELLIS_FF
select -assert-count 5 t:LUT4
select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
write_verilog synth.v
architecture/synth_ecp5/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_ecp5/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, negedge clr ) always @( posedge clk )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -37,92 +14,17 @@ module dffe ...@@ -37,92 +14,17 @@ module dffe
end end
always @( posedge clk) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d; q <= d;
`else
q <= 1'b0;
`endif
endmodule endmodule
module dffsr module adff
( input d, clk, pre, clr, output reg q ); ( input d, clk, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk, posedge clr )
if ( clr ) if ( clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ecp5/top_counter.v 0 → 100644
module top ( out, clk, reset );
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, posedge reset)
if (reset)
out <= 8'b0;
else
out <= out + 1;
endmodule
architecture/synth_ecp5/top_dpram.v 0 → 100644
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture/synth_ecp5/top_dsp.v 0 → 100644
(* top *)
module top #(parameter AW=2, BW=2, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
architecture/synth_ecp5/top_mux.v 0 → 100644
module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
always @(*)
Y = (S)? B : A;
endmodule
module mux4 ( S, D, Y );
input[1:0] S;
input[3:0] D;
output Y;
reg Y;
wire[1:0] S;
wire[3:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
endcase
end
endmodule
module mux8 ( S, D, Y );
input[2:0] S;
input[7:0] D;
output Y;
reg Y;
wire[2:0] S;
wire[7:0] D;
always @*
begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
4 : Y = D[4];
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
endcase
end
endmodule
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
architecture/synth_ecp5/top_wide_ffs.v 0 → 100644
module dff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffsr
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
architecture/synth_ecp5_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_ecp5_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ecp5_wide_ffs/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( !dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, posedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
endmodule
architecture/synth_ecp5_wide_ffs/top.v deleted 100644 → 0
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b0110;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0100;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0100;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 4'b0000;
`endif
endmodule
module dffsr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b1010;
`else
q <= d;
`endif
else if ( !pre )
q <= 4'b0101;
else
q <= d;
endmodule
module dffs
( input [3:0] d, input clk, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 4'b1111;
else
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
module ndffnsnr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( negedge clk, posedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0010;
`else
q <= d;
`endif
else if ( pre )
q <= 4'b1101;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b,b1,b2,b3,b4
);
wire b5,b6;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b5 )
);
dffse u_dffse (
.clk (clk ),
.pre (pre),
.en (en),
.d (a ),
.q (b6 )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_efinix/synth_efinix.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_fulladder.ys 0 → 100644
read_verilog ../top_fulladder.v
hierarchy -top top
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 7 t:EFX_ADD
select -assert-count 8 t:EFX_LUT4
select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/synth_efinix_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:EFX_FF
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_LUT4
select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
architecture/synth_efinix/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_efinix/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge clr ) always @( posedge clk )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -37,92 +14,5 @@ module dffe ...@@ -37,92 +14,5 @@ module dffe
end end
always @( posedge clk) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_efinix/top_fulladder.v 0 → 100644
module top
(
input [3:0] x,
input [3:0] y,
input [3:0] cin,
output [4:0] A,
output [4:0] cout
);
assign {cout,A} = cin + y + x;
endmodule
architecture/synth_efinix_fulladder/testbench.v deleted 100644 → 0
module testbench;
reg [11:0] in;
wire [4:0] patt_out,out;
wire [4:0] patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.cin(in[11:8]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[11:8] + in[7:4] + in[3:0];
assert_comb out_test(.A(patt_out[3]), .B(out[3]));
assert_comb carry_test(.A(patt_carry_out[3]), .B(carryout[3]));
endmodule
architecture/synth_efinix_fulladder/top.v deleted 100644 → 0
module top
(
input [3:0] x,
input [3:0] y,
input [3:0] cin,
output [4:0] A,
output [4:0] cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_gowin/synth_gowin.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_gowin_fully_selected.ys → architecture/synth_gowin/synth_gowin_fail.ys
read_verilog ../top.v read_verilog ../top.v
select top2 select top2
synth_gowin synth_gowin
write_verilog synth.v
architecture/synth_gowin/synth_gowin_nobram.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
stat
select -assert-count 35 t:DFF
select -assert-count 16 t:IBUF
select -assert-count 6 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 24 t:LUT4
select -assert-count 8 t:OBUF
select -assert-count 8 t:RAM16S4
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF t:RAM16S4 %% t:* %D
architecture/synth_gowin/synth_gowin_nodffe.ys 0 → 100644
read_verilog ../top_dffe.v
design -save read
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:$_DFFE_PP_
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:$_DFFE_PP_ t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nodffe # equivalency check
#equiv_opt -map +/gowin/cells_sim.v synth_gowin -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DFF
select -assert-count 3 t:IBUF
select -assert-count 1 t:LUT3
select -assert-count 1 t:OBUF
select -assert-none t:DFF t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_nodram.ys 0 → 100644
read_verilog ../top_mem.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
stat
select -assert-count 35 t:DFF
select -assert-count 16 t:IBUF
select -assert-count 6 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 24 t:LUT4
select -assert-count 8 t:OBUF
select -assert-count 8 t:RAM16S4
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF t:RAM16S4 %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin -nodram -nodffe
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
stat
select -assert-count 520 t:DFF
select -assert-count 16 t:IBUF
select -assert-count 9 t:LUT2
select -assert-count 622 t:LUT3
select -assert-count 345 t:LUT4
select -assert-count 8 t:OBUF
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_noflatten.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_retime.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_run.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -run begin:vout # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -top top # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_vout.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -vout vout.v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
architecture/synth_gowin/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_gowin/top.v
module top module top
( (
input x, input [3:0] x,
input y, input [3:0] y,
input cin, input [3:0] cin,
output A, output [4:0] A,
output cout output [4:0] cout
); );
`ifndef BUG
assign {cout,A} = cin + y + x; assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
architecture/synth_gowin/top_dffe.v 0 → 100644
module top
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
architecture/synth_gowin/top_mem.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_gowin_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_gowin_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_gowin_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [5:0] addr_a = 0;
reg we_a = 0;
wire [7:0] q_a;
reg mem_init = 0;
top uut (
data_a,
addr_a,
we_a,
clk,
q_a
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
addr_a <= addr_a + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_gowin_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_greenpak4/synth_greenpak4.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_adffs.ys 0 → 100644
read_verilog ../top_adffs.v
design -save read
hierarchy -top dffr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSR
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSR t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSR
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSR t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_adffsr.ys 0 → 100644
read_verilog ../top_dffsr.v
design -save read
hierarchy -top dffsr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffsr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:GP_2LUT
select -assert-count 4 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:$_DFFSR_PPP_ t:GP_2LUT t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top ndffnsnr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnsnr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:$_DFFSR_NPP_
select -assert-count 1 t:GP_2LUT
select -assert-count 4 t:GP_IBUF
select -assert-count 1 t:GP_INV
select -assert-count 1 t:GP_OBUF
select -assert-none t:$_DFFSR_NPP_ t:GP_2LUT t:GP_IBUF t:GP_INV t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_greenpak4_fully_selected.ys → architecture/synth_greenpak4/synth_greenpak4_fully_selected_fail.ys
read_verilog ../top.v read_verilog ../top.v
select dffe select dffe
synth_greenpak4 synth_greenpak4
write_verilog synth.v
architecture/synth_greenpak4/synth_greenpak4_gp_dffs.ys 0 → 100644
read_verilog ../top_gp_dffs.v
design -save read
hierarchy -top gp_dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFI t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_dffr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dffr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSRI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSRI t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_dffs
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dffs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSRI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSRI t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_dffsi
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dffsi # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSR
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSR t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_latchs
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_latchs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DLATCHSRI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DLATCHSRI t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_inv_inputs.ys 0 → 100644
read_verilog ../top_inv_inputs.v
hierarchy -top top
proc
flatten
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 -top top # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:GP_DFFSRI
select -assert-count 7 t:GP_IBUF
select -assert-count 1 t:GP_INV
select -assert-count 4 t:GP_OBUF
select -assert-none t:GP_DFFSRI t:GP_IBUF t:GP_INV t:GP_OBUF %% t:* %D
architecture/scripts/synth_greenpak4_invalid_part.ys → architecture/synth_greenpak4/synth_greenpak4_invalid_part_fail.ys
read_verilog ../top.v read_verilog ../top.v
synth_greenpak4 -part ggg synth_greenpak4 -part ggg
write_verilog synth.v
architecture/synth_greenpak4/synth_greenpak4_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_part140.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46140V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46140V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_part620.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46620V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46620V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_part621.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46621V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46621V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/synth_greenpak4_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture/synth_greenpak4/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_greenpak4/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge clr ) always @( posedge clk )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -37,92 +14,5 @@ module dffe ...@@ -37,92 +14,5 @@ module dffe
end end
always @( posedge clk) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_greenpak4/top_adffs.v 0 → 100644
module dffs
( input d, clk, pre, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffr
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture/synth_greenpak4/top_dffsr.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
architecture/synth_greenpak4/top_gp_dffs.v 0 → 100644
module gp_dff
( input d, input clk, clr, output reg q );
wire nq;
GP_DFF u_gp_dffr (d,clk,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffr
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFR u_gp_dffr (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffs
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffsi
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFSI u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_latchs
( input d, input clk, clr, output reg q );
wire nq;
GP_DLATCHS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
architecture/synth_greenpak4/top_inv_inputs.v 0 → 100644
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b
);
adff u_adff (
.clk (~clk ),
.clr (~clr),
.d (~a ),
.q (b )
);
endmodule
architecture/synth_greenpak4_dffs_r/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1;
reg dffs,dffr = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1] )
if ( !dinA[1] )
dffs <= 1'b1;
else
dffs <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
dffr <= 1'b0;
else
dffr <= dinA[0];
assert_dff dffs_test(.clk(clk), .test(doutB), .pat(dffs));
assert_dff dffr_test(.clk(clk), .test(doutB1), .pat(dffr));
endmodule
architecture/synth_greenpak4_dffs_r/top.v deleted 100644 → 0
module dffs
( input d, clk, pre, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre )
if ( !pre )
`ifndef BUG
q <= 1'b1;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffr
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1
);
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b )
);
dffr u_dffr (
.clk (clk ),
.clr (clr ),
.d (a ),
.q (b1 )
);
endmodule
architecture/synth_greenpak4_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_greenpak4_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_greenpak4_wide_ffs/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( !dinA[1] )
dff <= 1'b1;
else
dff <= ~dinA[0];
always @( negedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( negedge clk, negedge dinA[2] )
if ( !dinA[2] )
adff <= 1'b0;
else
adff <= ~dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( negedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(~dff));
assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
endmodule
architecture/synth_greenpak4_wide_ffs/top.v deleted 100644 → 0
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b0110;
`else
q <= d;
`endif
else
q <= d;
endmodule
module gp_dff
( input d, input clk, clr, output reg q );
wire nq;
GP_DFF u_gp_dffr (d,clk,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffr
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFR u_gp_dffr (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffs
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffsi
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFSI u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_latchs
( input d, input clk, clr, output reg q );
wire nq;
GP_DLATCHS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module adffn
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0100;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0100;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 4'b0000;
`endif
endmodule
module dffsr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b1010;
`else
q <= d;
`endif
else if ( !pre )
q <= 4'b0101;
else
q <= d;
endmodule
module dffs
( input [3:0] d, input clk, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 4'b1111;
else
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
module ndffnsnr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( negedge clk, posedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0010;
`else
q <= d;
`endif
else if ( pre )
q <= 4'b1101;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b,b1,b2,b3,b4
);
wire [3:0] b5,b6,b7,b8,bn,a_i;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (~a ),
.q (bn )
);
assign b = ~bn;
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b5 )
);
gp_dffr u_gp_dffr (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[0] )
);
gp_dff u_gp_dff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b8[0] )
);
gp_dffs u_gp_dffs (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[1] )
);
gp_dffsi u_gp_dffsi (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[2] )
);
gp_latchs u_gp_latchs (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b7[3] )
);
dffse u_dffse (
.clk (clk ),
.pre (pre),
.en (en),
.d (~a ),
.q (b6 )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (~clr),
.pre (~pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (~clk ),
.clr (~clr),
.d (~a ),
.q (b2 )
);
assign a_i[1:0] = a[1:0];
assign a_i[3:2] = ~a[3:2];
adffn u_adffn (
.clk (clk ),
.clr (~clr),
.d (a_i ),
.q (b3 )
);
dffe u_dffe (
.clk (~clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ice40/init1.txt 0 → 100644
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architecture/synth_ice40/synth_ice40.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_abc2.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_abc9_retime_fail.pat 0 → 100644
ERROR: -retime option not currently compatible with -abc9!
architecture/scripts/synth_ice40_abc9_retime.ys → architecture/synth_ice40/synth_ice40_abc9_retime_fail.ys
read_verilog ../top.v read_verilog ../top.v
synth_ice40 -abc9 -retime synth_ice40 -abc9 -retime
write_verilog synth.v
architecture/synth_ice40/synth_ice40_blif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_device_hx.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device hx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device hx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_device_lp.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device lp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device lp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_device_u.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device u # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device u # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_device_unknown_fail.pat 0 → 100644
ERROR: Invalid or no device specified: 'unknown'
architecture/synth_ice40/synth_ice40_dsp.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:SB_CARRY
select -assert-count 32 t:SB_DFF
select -assert-count 159 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 16 t:SB_DFF
select -assert-count 1 t:SB_MAC16
select -assert-none t:SB_DFF t:SB_MAC16 %% t:* %D
architecture/synth_ice40/synth_ice40_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_flatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/synth_ice40/synth_ice40_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_mem_init.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
stat
select -assert-count 2 t:SB_RAM40_4K
select -assert-none t:SB_RAM40_4K %% t:* %D
architecture/synth_ice40/synth_ice40_min_ce.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dffe_min_ce_use 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dffe_min_ce_use 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_LUT4 %% t:* %D
architecture/synth_ice40/synth_ice40_noabc.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noabc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noabc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_nobram.ys 0 → 100644
read_verilog ../top_dpram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:SB_RAM40_4K
select -assert-none t:SB_RAM40_4K %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 6 t:SB_DFF
select -assert-count 384 t:SB_DFFE
select -assert-count 368 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D
architecture/synth_ice40/synth_ice40_nocarry.ys 0 → 100644
read_verilog ../top_dsp_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_CARRY
select -assert-count 8 t:SB_DFF
select -assert-count 6 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -nocarry # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:SB_DFF
select -assert-count 4 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_LUT4 %% t:* %D
architecture/synth_ice40/synth_ice40_nodffe.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_LUT4 %% t:* %D
architecture/synth_ice40/synth_ice40_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_opt.ys 0 → 100644
read_verilog ../top_dsp_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_CARRY
select -assert-count 8 t:SB_DFF
select -assert-count 6 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top top
proc
synth_ice40
equiv_opt -assert -map +/ice40/cells_sim.v ice40_opt # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_CARRY
select -assert-count 8 t:SB_DFF
select -assert-count 6 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
architecture/synth_ice40/synth_ice40_relut.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -relut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -relut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_vpr.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture/synth_ice40/synth_ice40_wide_ffs.ys 0 → 100644
read_verilog ../top_wide_ffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_DFFSR
select -assert-count 2 t:SB_DFFSS
select -assert-none t:SB_DFFSR t:SB_DFFSS %% t:* %D
design -load read
hierarchy -top adff
proc
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_DFFR
select -assert-count 2 t:SB_DFFS
select -assert-none t:SB_DFFR t:SB_DFFS %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:SB_DFFE
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_DFFE t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top dffse
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffse # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-count 2 t:SB_DFFESR
select -assert-count 1 t:SB_DFFESS
select -assert-count 4 t:SB_LUT4
select -assert-none t:SB_DFFE t:SB_DFFESR t:SB_DFFESS t:SB_LUT4 %% t:* %D
architecture/synth_ice40/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_ice40/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge clr ) always @( posedge clk )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -35,94 +12,19 @@ module dffe ...@@ -35,94 +12,19 @@ module dffe
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk ) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d; q <= d;
`else
q <= 1'b0;
`endif
endmodule endmodule
module dffsr module adff
( input d, clk, pre, clr, output reg q ); ( input d, clk, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk, posedge clr )
if ( clr ) if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ice40/top_dpram.v 0 → 100644
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 6;
parameter data_width = 6;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture/synth_ice40/top_dsp.v 0 → 100644
(* top *)
module top #(parameter AW=8, BW=8, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
architecture/synth_ice40/top_dsp_nocarry.v 0 → 100644
(* top *)
module top #(parameter AW=2, BW=2, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
architecture/synth_ice40/top_mem.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a,
output reg [15:0] q_b,
output reg [15:0] q_c
);
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init.txt")
) \ram.0.0.0 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_b),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init1.txt")
) \ram.0.0.1 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_c),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
endmodule
architecture/synth_ice40/top_wide_ffs.v 0 → 100644
module dff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
architecture/synth_ice40_dsp/run-test.sh
...@@ -19,7 +19,7 @@ if ! which iverilog > /dev/null ; then ...@@ -19,7 +19,7 @@ if ! which iverilog > /dev/null ; then
fi fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/common.py -O common_mul.py -o /dev/null wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/common.py -O common_mul.py -o /dev/null
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py #cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
python3 ../assert_area.py python3 ../assert_area.py
cp ../*.v . cp ../*.v .
......
architecture/synth_ice40_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_ice40_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_ice40_fulladder/testbench.v deleted 100644 → 0
module testbench;
reg [11:0] in;
wire [4:0] patt_out,out;
wire [4:0] patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.cin(in[11:8]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[11:8] + in[7:4] + in[3:0];
assert_comb out_test(.A(patt_out[3]), .B(out[3]));
assert_comb carry_test(.A(patt_carry_out[3]), .B(carryout[3]));
endmodule
architecture/synth_ice40_fulladder/top.v deleted 100644 → 0
module top
(
input [3:0] x,
input [3:0] y,
input [3:0] cin,
output [4:0] A,
output [4:0] cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_ice40_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [5:0] addr_a = 0;
reg we_a = 0;
wire [7:0] q_a;
reg mem_init = 0;
top uut (
.data_a(data_a),
.addr_a(addr_a),
.we_a(we_a),
.clk(clk),
.q_a(q_a)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
addr_a <= addr_a + 1;
end
always @(posedge addr_a) begin
#10;
if(addr_a > 6'h3E)
mem_init <= 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
end
uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
endmodule
module uut_mem_checker(input clk, input init, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/synth_ice40_mem/top.v deleted 100644 → 0
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a,
output reg [15:0] q_b,
output reg [15:0] q_c
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init.txt")
) \ram.0.0.0 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_b),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init.txt")
) \ram.0.0.1 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_c),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
endmodule
architecture/synth_ice40_wide_ffs/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire [3:0] doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a ({dinA[0],dinA[0],dinA[0],dinA[0]}),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, negedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( !dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, posedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB[0]), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1[0]), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2[0]), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3[0]), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4[0]), .pat(dffe));
endmodule
architecture/synth_ice40_wide_ffs/top.v deleted 100644 → 0
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b0110;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0100;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0100;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 4'b0000;
`endif
endmodule
module dffsr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 4'b1010;
`else
q <= d;
`endif
else if ( !pre )
q <= 4'b0101;
else
q <= d;
endmodule
module dffs
( input [3:0] d, input clk, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 4'b1111;
else
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
module ndffnsnr
( input [3:0] d, input clk, pre, clr, output reg [3:0] q );
initial begin
q = 0;
end
always @( negedge clk, posedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 4'b0010;
`else
q <= d;
`endif
else if ( pre )
q <= 4'b1101;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b,b1,b2,b3,b4
);
wire b5,b6;
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
dffs u_dffs (
.clk (clk ),
.pre (pre),
.d (a ),
.q (b5 )
);
dffse u_dffse (
.clk (clk ),
.pre (pre),
.en (en),
.d (a ),
.q (b6 )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_intel/synth_intel.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_a10gx.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/a10gx/cells_sim.v synth_intel -family a10gx # equivalency check
equiv_opt -map +/intel/a10gx/cells_sim.v synth_intel -family a10gx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 12 t:$lut
select -assert-count 1 t:twentynm_lcell_comb
select -assert-none t:$lut t:twentynm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_cyclone10.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cyclone10/cells_sim.v synth_intel -family cyclone10 # equivalency check
equiv_opt -map +/intel/cyclone10/cells_sim.v synth_intel -family cyclone10 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:cyclone10lp_lcell_comb
select -assert-none t:cyclone10lp_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_cycloneiv.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cycloneiv/cells_sim.v synth_intel -family cycloneiv # equivalency check
equiv_opt -map +/intel/cycloneiv/cells_sim.v synth_intel -family cycloneiv # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:cycloneiv_lcell_comb
select -assert-none t:cycloneiv_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_cycloneive.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cycloneive/cells_sim.v synth_intel -family cycloneive # equivalency check
equiv_opt -map +/intel/cycloneive/cells_sim.v synth_intel -family cycloneive # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:cycloneive_lcell_comb
select -assert-none t:cycloneive_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_cyclonev.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/cyclonev/cells_sim.v synth_intel -family cyclonev # equivalency check
equiv_opt -map +/intel/cyclonev/cells_sim.v synth_intel -family cyclonev # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 13 t:cyclonev_lcell_comb
select -assert-none t:cyclonev_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/synth_intel/synth_intel_invalid_family_fail.pat 0 → 100644
ERROR: Invalid or no family specified: 'u'
architecture/synth_intel/synth_intel_iopads.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -iopads # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -iopads # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 12 t:fiftyfivenm_io_ibuf
select -assert-count 10 t:fiftyfivenm_io_obuf
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_io_ibuf t:fiftyfivenm_io_obuf t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_max10.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -family max10 # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -family max10 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_nobram.ys 0 → 100644
read_verilog ../top_mem.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/intel/max10/cells_sim.v synth_intel
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:altsyncram
select -assert-none t:altsyncram %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
#ERROR: Multiple edge sensitive events found for this signal!
#equiv_opt -run :prove -map +/intel/max10/cells_sim.v synth_intel -nobram
synth_intel -nobram
#memory
#opt -full
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
#design -load postopt
cd top
select -assert-count 520 t:dffeas
select -assert-count 976 t:fiftyfivenm_lcell_comb
select -assert-none t:dffeas t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_noflatten.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -noflatten # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_retime.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -retime # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_run.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -run family:vpr # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -run family:vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:$add
select -assert-none t:$add %% t:* %D
architecture/synth_intel/synth_intel_top.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -top top # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -top top # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_vpr.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -vpr vpr.vpr # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -vpr vpr.vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/synth_intel_vqm.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/intel/max10/cells_sim.v synth_intel -vqm vqm.vqm # equivalency check
equiv_opt -map +/intel/max10/cells_sim.v synth_intel -vqm vqm.vqm # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:fiftyfivenm_lcell_comb
select -assert-none t:fiftyfivenm_lcell_comb %% t:* %D
architecture/synth_intel/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel/top.v
module top module top
( (
input x, input [3:0] x,
input y, input [3:0] y,
input cin, input [3:0] cin,
output A, output [4:0] A,
output cout output [4:0] cout
); );
`ifndef BUG
assign {cout,A} = cin + y + x; assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule endmodule
architecture/synth_intel/top_dpram.v 0 → 100644
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 6;
parameter data_width = 6;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture/synth_intel/top_mem.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
q_a <= ram[addr_a];
end
endmodule
architecture/synth_intel_a10gx/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel_a10gx/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_intel_cyclone10/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel_cyclone10/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_intel_cycloneiv/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel_cycloneiv/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_intel_cycloneive/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel_cycloneive/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_intel_cyclonev/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel_cyclonev/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_intel_error/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
architecture/synth_intel_error/top.v deleted 100644 → 0
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
architecture/synth_sf2/synth_sf2.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_clkbuf.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -clkbuf # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -edif edif.edif # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -edif edif.edif # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/synth_sf2/synth_sf2_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -json json.json # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -json json.json # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -noflatten # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -noflatten # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_noiobs.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -noiobs # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -noiobs # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -retime # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -retime # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -run begin:json # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -run begin:json # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -top dff # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -top dffe # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/synth_sf2_vlog.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -vlog vlog.v # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CLKINT
select -assert-count 2 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
design -load read
hierarchy -top dffe
proc
#-assert option was skipped because of unproven cells
#equiv_opt -assert -map +/sf2/cells_sim.v synth_sf2 -vlog vlog.v # equivalency check
equiv_opt -map +/sf2/cells_sim.v synth_sf2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:CFG3
select -assert-count 1 t:CLKINT
select -assert-count 3 t:INBUF
select -assert-count 1 t:OUTBUF
select -assert-count 1 t:SLE
select -assert-none t:CFG3 t:CLKINT t:INBUF t:OUTBUF t:SLE %% t:* %D
architecture/synth_sf2/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_sf2/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, negedge clr ) always @( posedge clk )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -35,94 +12,19 @@ module dffe ...@@ -35,94 +12,19 @@ module dffe
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge en ) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d; q <= d;
`else
q <= 1'b0;
`endif
endmodule endmodule
module dffsr module adff
( input d, clk, pre, clr, output reg q ); ( input d, clk, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk, posedge clr )
if ( clr ) if ( clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_sf2_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_sf2_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge en )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/scripts/synth_sf2.ys → architecture/synth_sf2_lcov/synth_sf2.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 synth_sf2
write_verilog synth.v
architecture/scripts/synth_sf2_clkbuf.ys → architecture/synth_sf2_lcov/synth_sf2_clkbuf.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -clkbuf synth_sf2 -clkbuf
write_verilog synth.v
architecture/scripts/synth_sf2_edif.ys → architecture/synth_sf2_lcov/synth_sf2_edif.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -edif edif.edif synth_sf2 -edif edif.edif
write_verilog synth.v
architecture/scripts/synth_sf2_json.ys → architecture/synth_sf2_lcov/synth_sf2_json.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -json json.json synth_sf2 -json json.json
write_verilog synth.v
architecture/scripts/synth_sf2_noflatten.ys → architecture/synth_sf2_lcov/synth_sf2_noflatten.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -noflatten synth_sf2 -noflatten
write_verilog synth.v
architecture/scripts/synth_sf2_noiobs.ys → architecture/synth_sf2_lcov/synth_sf2_noiobs.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -noiobs synth_sf2 -noiobs
write_verilog synth.v
architecture/scripts/synth_sf2_retime.ys → architecture/synth_sf2_lcov/synth_sf2_retime.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -retime synth_sf2 -retime
write_verilog synth.v
architecture/scripts/synth_sf2_run.ys → architecture/synth_sf2_lcov/synth_sf2_run.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -run begin:json synth_sf2 -run begin:json
write_verilog synth.v
architecture/synth_sf2_lcov/synth_sf2_top.ys 0 → 100644
read_verilog ../top.v
synth_sf2 -top dff
architecture/scripts/synth_sf2_vlog.ys → architecture/synth_sf2_lcov/synth_sf2_vlog.ys
read_verilog ../top.v read_verilog ../top.v
synth_sf2 -vlog vlog.v synth_sf2 -vlog vlog.v
write_verilog synth.v
architecture/synth_sf2_lcov/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
architecture/synth_xilinx/synth_xilinx.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top adff
proc
#-assert option was skipped because of unproven cellss
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
select -assert-none t:BUFG t:FDCE %% t:* %D
architecture/synth_xilinx/synth_xilinx_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_abc9_retime_fail.pat 0 → 100644
ERROR: -retime option not currently compatible with -abc9!
architecture/synth_xilinx/synth_xilinx_arch_xc6s.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.pat 0 → 100644
Warning: 'synth_xilinx -abc9' not currently supported for the 'xc6s' family, will use timing for 'xc7' instead.
architecture/synth_xilinx/synth_xilinx_arch_xc6s_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
tee -o result.out equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6s -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xc6v.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc6v # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xc7.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc7 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xc7 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xcu.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcu # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcu # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_arch_xcup.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcup # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -arch xcup # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_blif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_dsp.ys 0 → 100644
read_verilog ../top_dsp_simd.v
design -save read
hierarchy -top simd
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd simd # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
architecture/synth_xilinx/synth_xilinx_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_flatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_flatten_before_abc.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten_before_abc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -flatten_before_abc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture/scripts/synth_xilinx_fully_selected.ys → architecture/synth_xilinx/synth_xilinx_fully_selected_fail.ys
read_verilog ../top.v read_verilog ../top.v
select dffe select dffe
synth_xilinx synth_xilinx
write_verilog synth.v
architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.pat 0 → 100644
ERROR: Invalid Xilinx -family setting: 'zinq7000'.
architecture/scripts/synth_xilinx_invalid_arch.ys → architecture/synth_xilinx/synth_xilinx_invalid_arch_fail.ys
read_verilog ../top.v read_verilog ../top.v
synth_xilinx -arch zinq7000 synth_xilinx -arch zinq7000
write_verilog synth.v
architecture/synth_xilinx/synth_xilinx_iopad.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -iopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -iopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
architecture/synth_xilinx/synth_xilinx_ise.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 2 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
architecture/synth_xilinx/synth_xilinx_nobram.ys 0 → 100644
read_verilog ../top_bram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:BUFG
select -assert-count 35 t:FDRE
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT4
select -assert-count 16 t:LUT6
select -assert-count 8 t:MUXF7
select -assert-count 32 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture/synth_xilinx/synth_xilinx_nocarry.ys 0 → 100644
read_verilog ../top_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT4
select -assert-count 4 t:LUT6
select -assert-count 5 t:MUXCY
select -assert-count 6 t:XORCY
select -assert-none t:LUT2 t:LUT4 t:LUT6 t:MUXCY t:XORCY %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nocarry # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4
select -assert-count 4 t:LUT6
select -assert-none t:LUT2 t:LUT4 t:LUT6 %% t:* %D
architecture/synth_xilinx/synth_xilinx_noclkbuf.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noclkbuf # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:FDRE
select -assert-none t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_nodram.ys 0 → 100644
read_verilog ../top_dpram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 2 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 6 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -nodram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 2 t:BUFG
select -assert-count 390 t:FDRE
select -assert-count 90 t:LUT2
select -assert-count 10 t:LUT4
select -assert-count 155 t:LUT6
select -assert-count 32 t:MUXF7
select -assert-count 2 t:MUXF8
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT4 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture/synth_xilinx/synth_xilinx_nodsp.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:DSP48E1
select -assert-none t:DSP48E1 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 15 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 4 t:LUT4
select -assert-count 5 t:LUT5
select -assert-count 45 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 9 t:MUXF7
select -assert-count 3 t:MUXF8
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
architecture/synth_xilinx/synth_xilinx_noiopad.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:IBUF
select -assert-count 1 t:IBUFG
select -assert-count 1 t:OBUF
select -assert-none t:BUFG t:FDRE t:IBUF t:IBUFG t:OBUF %% t:* %D
design -load read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -ise -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_nosrl.ys 0 → 100644
read_verilog ../top_nosrl.v
design -save read
hierarchy -top xilinx_srl_static_test
proc
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
design -load read
hierarchy -top xilinx_srl_static_test
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nosrl # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd xilinx_srl_static_test # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 5 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_nowidelut.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 6 t:LUT4
select -assert-count 1 t:LUT5
select -assert-count 33 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 1 t:MUXF7
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:LUT2
select -assert-count 6 t:LUT3
select -assert-count 5 t:LUT4
select -assert-count 2 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 11 t:MUXCY
select -assert-count 12 t:XORCY
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:XORCY %% t:* %D
architecture/synth_xilinx/synth_xilinx_nowidelut_abc9.ys 0 → 100644
read_verilog ../top_dsp.v
hierarchy -top top
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp -nowidelut -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 3 t:CARRY4
select -assert-count 12 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 8 t:LUT4
select -assert-count 21 t:LUT5
select -assert-count 16 t:LUT6
select -assert-none t:CARRY4 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 %% t:* %D
architecture/synth_xilinx/synth_xilinx_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -run begin:blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -run begin:blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_vpr.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-none t:BUFG t:FDRE %% t:* %D
architecture/synth_xilinx/synth_xilinx_widemux.ys 0 → 100644
read_verilog ../top_mux.v
design -save read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 14 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 3 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
design -load read
hierarchy -top mux16
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -widemux 9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:LUT6
select -assert-count 2 t:MUXF7
select -assert-count 1 t:MUXF8
select -assert-none t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
architecture/synth_xilinx/synth_xilinx_widemux_1_fail.pat 0 → 100644
ERROR: -widemux value must be 0 or >= 2.
architecture/scripts/synth_xilinx_widemux_1.ys → architecture/synth_xilinx/synth_xilinx_widemux_1_fail.ys
read_verilog ../top.v read_verilog ../top.v
synth_xilinx -widemux 1 synth_xilinx -widemux 1
write_verilog synth.v
architecture/synth_xilinx/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_xilinx/top.v
module adff module dff
( input d, clk, clr, output reg q ); ( input d, clk, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge clr ) always @( posedge clk )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d; q <= d;
endmodule endmodule
...@@ -35,94 +12,19 @@ module dffe ...@@ -35,94 +12,19 @@ module dffe
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk ) always @( posedge clk)
if ( en ) if ( en )
`ifndef BUG
q <= d; q <= d;
`else
q <= 1'b0;
`endif
endmodule endmodule
module dffsr module adff
( input d, clk, pre, clr, output reg q ); ( input d, clk, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk, posedge clr )
if ( clr ) if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0; q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/synth_xilinx/top_bram.v 0 → 100644
// Single-Port Block RAM Read-First Mode
// rams_sp_rf.v
module top (clk, en, we, addr, di, dout);
input clk;
input we;
input en;
input [8:0] addr;
input [7:0] di;
output [7:0] dout;
reg [7:0] RAM [511:0];
reg [7:0] dout;
always @(posedge clk)
begin
if (en)
begin
if (we)
RAM[addr]<=di;
dout <= RAM[addr];
end
end
endmodule
architecture/synth_xilinx/top_dpram.v 0 → 100644
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 6;
parameter data_width = 6;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture/synth_xilinx/top_dsp.v 0 → 100644
module top
(
input [5:0] x,
input [5:0] y,
output [11:0] A,
);
assign A = x * y;
endmodule
architecture/synth_xilinx/top_dsp_simd.v 0 → 100644
module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
generate
genvar i;
// 4 x 12-bit adder
for (i = 0; i < 4; i++)
assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
// 2 x 24-bit subtract
for (i = 0; i < 2; i++)
assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
endgenerate
reg [3*12-1:0] ro;
always @* begin
ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
end
assign o12[4*12+:3*12] = ro;
endmodule
architecture/synth_xilinx/top_mux.v 0 → 100644
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
assign Y = D[S];
endmodule
architecture/synth_xilinx/top_nocarry.v 0 → 100644
module top
(
input [2:0] x,
input [2:0] y,
output [5:0] A,
);
assign A = x * y;
endmodule
architecture/synth_xilinx/top_nosrl.v 0 → 100644
module xilinx_srl_static_test(input i, clk, output [1:0] q);
reg head = 1'b0;
reg [3:0] shift1 = 4'b0000;
reg [3:0] shift2 = 4'b0000;
always @(posedge clk) begin
head <= i;
shift1 <= {shift1[2:0], head};
shift2 <= {shift2[2:0], head};
end
assign q = {shift2[3], shift1[3]};
endmodule
architecture/synth_xilinx/top_srl.v 0 → 100644
module top (
out,
out1,
clk,
in
);
output [7:0] out;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
out <= out >> 1;
out[7] <= in;
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
architecture/synth_xilinx/top_wide_ffs.v 0 → 100644
module dff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
architecture/synth_xilinx/xilinx_srl.ys 0 → 100644
read_verilog ../top_srl.v
design -save read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
#select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -minlen 1
stat
select -assert-count 8 t:$__XILINX_SHREG_
select -assert-count 1 t:BUFG
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -variable
stat
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
design -load read
hierarchy -top top
proc
synth_xilinx
xilinx_srl -fixed -variable -minlen 1
stat
select -assert-count 8 t:$__XILINX_SHREG_
select -assert-count 1 t:BUFG
architecture/synth_xilinx_dsp_cov/top.v deleted 100644 → 0
module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
generate
genvar i;
// 4 x 12-bit adder
for (i = 0; i < 4; i++)
assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
// 2 x 24-bit subtract
for (i = 0; i < 2; i++)
assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
endgenerate
reg [3*12-1:0] ro;
always @* begin
ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
end
assign o12[4*12+:3*12] = ro;
endmodule
architecture/synth_xilinx_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
architecture/synth_xilinx_error/top.v deleted 100644 → 0
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
architecture/xilinx_srl/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg in = 0;
wire [7:0] f;
top uut ( .clk(clk),
.in(in),
.out(f));
always @(posedge clk) begin
#3
in <= ~in;
end
assert_expr f_test(.clk(clk), .A(f[0]));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
architecture/xilinx_srl/top.v deleted 100644 → 0
module top (
out,
out1,
clk,
in
);
output [7:0] out;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
`ifndef BUG
out <= out >> 1;
out[7] <= in;
`else
out <= 8'bZZZZZZZZ;
`endif
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_presubmult.ys 0 → 100644
read_verilog ../presubmult.v
hierarchy -top presubmult
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd presubmult
#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_one_clock.ys 0 → 100644
read_verilog ../ram_simple_dual_one_clock.v
hierarchy -top simple_dual_one_clock
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_one_clock
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_ram_simple_dual_two_clocks.ys 0 → 100644
read_verilog ../ram_simple_dual_two_clocks.v
hierarchy -top simple_dual_two_clocks
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd simple_dual_two_clocks
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_dist.ys 0 → 100644
read_verilog ../rams_dist.v
hierarchy -top rams_dist
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_dist
stat
#Vivado synthesizes 32 RAM64X1D.
select -assert-count 1 t:BUFG
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:RAM64X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_init_file.ys 0 → 100644
read_verilog ../rams_init_file.v
hierarchy -top rams_init_file
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_init_file
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 32 t:RAM64X1D
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_pipeline.ys 0 → 100644
read_verilog ../rams_pipeline.v
hierarchy -top rams_pipeline
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_pipeline
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 2 t:BUFG
select -assert-count 32 t:FDRE
select -assert-count 2 t:RAMB18E1
select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_nc.ys 0 → 100644
read_verilog ../rams_sp_nc.v
hierarchy -top rams_sp_nc
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_nc
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 2 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf.ys 0 → 100644
read_verilog ../rams_sp_rf.v
hierarchy -top rams_sp_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:LUT2
select -assert-count 1 t:RAMB18E1
select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rf_rst.ys 0 → 100644
read_verilog ../rams_sp_rf_rst.v
hierarchy -top rams_sp_rf_rst
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rf_rst
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 5 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 13 t:LUT4
select -assert-count 23 t:LUT5
select -assert-count 32 t:LUT6
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom.ys 0 → 100644
read_verilog ../rams_sp_rom.v
hierarchy -top rams_sp_rom
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 20 t:RAM64X1D
select -assert-count 20 t:FDRE
select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_rom_1.ys 0 → 100644
read_verilog ../rams_sp_rom_1.v
hierarchy -top rams_sp_rom_1
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_rom_1
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 14 t:LUT6
select -assert-count 14 t:FDRE
select -assert-none t:BUFG t:LUT6 t:FDRE %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_sp_wf.ys 0 → 100644
read_verilog ../rams_sp_wf.v
hierarchy -top rams_sp_wf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_sp_wf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:BUFG
select -assert-count 16 t:FDRE
select -assert-count 44 t:LUT5
select -assert-count 38 t:LUT6
select -assert-count 10 t:MUXF7
select -assert-count 128 t:RAM128X1D
select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_rams_tdp_rf_rf.ys 0 → 100644
read_verilog ../rams_tdp_rf_rf.v
hierarchy -top rams_tdp_rf_rf
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd rams_tdp_rf_rf
stat
#Vivado synthesizes 1 RAMB18E1.
select -assert-count 1 t:$mem
select -assert-count 2 t:LUT2
select -assert-none t:$mem t:LUT2 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_registers_1.ys 0 → 100644
read_verilog ../registers_1.v
hierarchy -top registers_1
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 8 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 9 t:LUT2
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_sfir_shifter.ys 0 → 100644
read_verilog ../sfir_shifter.v
hierarchy -top sfir_shifter
proc
flatten
#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd sfir_shifter
#Vivado synthesizes 32 FDRE, 16 SRL16E.
stat
select -assert-count 1 t:BUFG
select -assert-count 16 t:SRL16E
select -assert-none t:BUFG t:SRL16E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_0.ys 0 → 100644
read_verilog ../shift_registers_0.v
hierarchy -top shift_registers_0
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_0 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_shift_registers_1.ys 0 → 100644
read_verilog ../shift_registers_1.v
hierarchy -top shift_registers_1
proc
flatten
#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd shift_registers_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmacc.ys 0 → 100644
read_verilog ../squarediffmacc.v
hierarchy -top squarediffmacc
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd squarediffmacc
#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 17 t:FDRE
select -assert-count 16 t:LUT2
select -assert-count 8 t:MUXCY
select -assert-count 9 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_squarediffmult.ys 0 → 100644
read_verilog ../squarediffmult.v
hierarchy -top squarediffmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd squarediffmult
stat
#Vivado synthesizes 16 FDRE, 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 32 t:FDRE
select -assert-count 65 t:LUT2
select -assert-count 16 t:MUXCY
select -assert-count 17 t:XORCY
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:MUXCY t:XORCY %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_top_mux.ys 0 → 100644
read_verilog ../top_mux.v
hierarchy -top mux4
proc
flatten
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4
#Vivado synthesizes 2 LUT.
stat
select -assert-count 2 t:LUT6
select -assert-none t:LUT6 %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys 0 → 100644
read_verilog ../tristates_1.v
hierarchy -top tristates_1
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys 0 → 100644
read_verilog ../tristates_2.v
hierarchy -top tristates_2
proc
tribuf
flatten
synth
equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd tristates_2 # Constrain all select calls below inside the top module
#Vivado synthesizes 3 IBUF, 1 OBUFT.
select -assert-count 1 t:LUT1
select -assert-count 1 t:$_TBUF_
select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys 0 → 100644
read_verilog ../xilinx_ultraram_single_port_no_change.v
hierarchy -top xilinx_ultraram_single_port_no_change
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_no_change
stat
#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 9 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys 0 → 100644
read_verilog ../xilinx_ultraram_single_port_read_first.v
hierarchy -top xilinx_ultraram_single_port_read_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_read_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 53 t:FDRE
select -assert-count 1 t:LUT1
select -assert-count 8 t:LUT2
select -assert-count 11 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_write_first.ys 0 → 100644
read_verilog ../xilinx_ultraram_single_port_write_first.v
hierarchy -top xilinx_ultraram_single_port_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full
# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
design -load postopt
cd xilinx_ultraram_single_port_write_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 44 t:FDRE
select -assert-count 8 t:LUT5
select -assert-count 8 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 16 t:RAM128X1D
select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
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