Unverified Commit 9f9742c5 by Miodrag Milanović Committed by GitHub

Merge pull request #65 from SergeyDegtyar/SergeyDegtyar/tests_for_new_features

Add tests for new features; Tests for closed issues
parents f3acf17b 897d1f1d
......@@ -24,6 +24,7 @@ $(eval $(call template,synth_achronix_error,synth_achronix_fully_selected))
#anlogic
$(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_fulladder,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_fsm,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
$(eval $(call template,synth_anlogic_mem,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime anlogic_determine_init_eqn))
$(eval $(call template,synth_anlogic_error,synth_anlogic_fully_selected))
......@@ -53,6 +54,8 @@ $(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_b
$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
$(eval $(call template,synth_ice40_fulladder,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected synth_ice40_abc9_retime synth_ice40_device_unknown))
$(eval $(call template,ice40_wrapcarry,ice40_wrapcarry ice40_wrapcarry_top))
$(eval $(call template,ice40_wrapcarry_adders,ice40_wrapcarry ice40_wrapcarry_top))
#intel
$(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_iopads synth_intel_nobram synth_intel_max10 ))
......@@ -68,8 +71,9 @@ $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf
$(eval $(call template,synth_sf2_error,synth_sf2_fully_selected ))
#xilinx
$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9))
$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9 xilinx_srl_minlen_variable xilinx_srl_minlen))
$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch synth_xilinx_abc9_retime synth_xilinx_widemux_1))
$(eval $(call template,xilinx_srl,xilinx_srl_minlen xilinx_srl_fixed xilinx_srl_variable xilinx_srl_minlen_variable))
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
$(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
......@@ -84,4 +88,8 @@ $(eval $(call template,synth_greenpak4_wide_ffs,synth_greenpak4 synth_greenpak4_
$(eval $(call template,synth_greenpak4_dffs_r,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
$(eval $(call template,synth_greenpak4_error,synth_greenpak4_fully_selected synth_greenpak4_invalid_part))
#efinix
$(eval $(call template,synth_efinix, synth_efinix synth_efinix_edif synth_efinix_json synth_efinix_noflatten synth_efinix_retime synth_efinix_run synth_efinix_top))
$(eval $(call template,synth_efinix_fulladder, synth_efinix synth_efinix_edif synth_efinix_json synth_efinix_noflatten synth_efinix_retime synth_efinix_run synth_efinix_top))
.PHONY: all clean
module testbench;
reg [7:0] in;
wire [3:0] outA,outB;
wire [3:0] poutA,poutB;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.A(outA),
.B(outB)
);
//assign poutA = in[3:0] % in[7:4];
assign poutB = in[3:0] / in[7:4];
//check_comb mod_test(outA, poutA);
check_comb div_test(outB, poutB);
assert_comb div2_test(outB[2], poutB[2]);
endmodule
module check_comb(input [3:0] test, input [3:0] pat);
always @*
begin
#1;
if (test !== pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
$stop;
end
end
endmodule
module top
(
input [3:0] x,
input [3:0] y,
output [3:0] A,
output [3:0] B
);
//assign A = x % y;
assign B = x / y;
endmodule
module testbench;
reg [31:0] in;
wire [15:0] outA,outB;
wire [15:0] poutA,poutB;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[15:0]),
.y(in[31:16]),
.A(outA),
.B(outB)
);
assign poutA = in[15:0] + in[31:16];
assign poutB = in[15:0] - in[31:16];
check_comb add_test(outA, poutA);
check_comb sub_test(outB, poutB);
assert_comb sub0_test(outB[2], poutB[2]);
endmodule
module check_comb(input [15:0] test, input [15:0] pat);
always @*
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
$stop;
end
end
endmodule
module top
(
input [15:0] x,
input [15:0] y,
output [15:0] A,
output [15:0] B
);
assign A = x + y;
assign B = x - y;
endmodule
......@@ -79,6 +79,8 @@ else
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_fsm" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v
elif [ "$1" = "synth_anlogic_mem" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/anlogic/cells_sim.v $TECHLIBS_PREFIX/anlogic/eagle_bb.v
elif [ "$1" = "synth_coolrunner2" ]; then
......@@ -97,6 +99,10 @@ else
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_ice40_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "ice40_wrapcarry" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "ice40_wrapcarry_adders" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
elif [ "$1" = "synth_intel" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
elif [ "$1" = "synth_intel_a10gx" ]; then
......@@ -113,12 +119,18 @@ else
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/sf2/cells_sim.v
elif [ "$1" = "synth_xilinx" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "xilinx_srl" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/xilinx/cells_sim.v
elif [ "$1" = "synth_greenpak4" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_greenpak4_dffs_r" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
elif [ "$1" = "synth_efinix" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
elif [ "$1" = "synth_efinix_fulladder" ]; then
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/efinix/cells_sim.v
else
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
fi
......
read_verilog ../top.v
synth_ice40
ice40_wrapcarry
write_verilog synth.v
read_verilog ../top.v
synth_ice40
ice40_wrapcarry top
write_verilog synth.v
read_verilog ../top.v
synth_efinix
write_verilog synth.v
read_verilog ../top.v
synth_efinix -edif edif.edif
write_verilog synth.v
read_verilog ../top.v
synth_efinix -json json.json
write_verilog synth.v
read_verilog ../top.v
synth_efinix -noflatten
write_verilog synth.v
read_verilog ../top.v
synth_efinix -retime
write_verilog synth.v
read_verilog ../top.v
synth_efinix -run begin:json
write_verilog synth.v
read_verilog ../top.v
synth_efinix -top top
write_verilog synth.v
read_verilog ../top.v
synth_xilinx
xilinx_srl -fixed
write_verilog synth.v
read_verilog ../top.v
synth_xilinx
xilinx_srl -fixed -minlen 1
design -reset
read_verilog ../top.v
synth_xilinx
write_verilog synth.v
read_verilog ../top.v
synth_xilinx
xilinx_srl -variable -minlen 1
design -reset
read_verilog ../top.v
synth_xilinx
write_verilog synth.v
read_verilog ../top.v
synth_xilinx
xilinx_srl -variable
write_verilog synth.v
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg b = 0;
reg rst;
reg en;
wire s;
wire bs;
wire f;
top uut ( .clk(clk),
.rst(rst),
.en(en),
.a(a),
.b(b),
.s(s),
.bs(bs),
.f(f));
always @(posedge clk)
begin
#2
a <= ~a;
end
always @(posedge clk)
begin
#4
b <= ~b;
end
initial begin
en <= 1;
rst <= 1;
#5
rst <= 0;
end
assert_expr s_test(.clk(clk), .A(s));
assert_expr bs_test(.clk(clk), .A(bs));
assert_expr f_test(.clk(clk), .A(f));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
input wire clk;
input wire rst;
input wire en;
input wire ls;
input wire rs;
output wire stop;
output wire busy;
output wire finish;
//typedef enum logic [3:0] {S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14} sts;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
reg [3:0] ns, st;
reg [2:0] count;
always @(posedge clk)
begin : CurrstProc
if (rst)
st <= S0;
else
st <= ns;
end
always @*
begin : NextstProc
ns = st;
case (st)
S0: ns = S1;
S1: ns = S2;
S2:
if (rs == 1'b1)
ns = S3;
else
ns = S4;
S3: ns = S1;
S4: if (count > 7)
ns = S10;
else
ns = S5;
S5: if (ls == 1'b0)
ns = S6;
else
ns = S3;
S6:
if (ls == 1'b1)
ns = S7;
else
ns = S8;
S7:
if (ls == 1'b1 && rs == 1'b1)
ns = S5;
else
ns = S13;
S8: ns = S9;
S9: ns = S8;
S10:
if (ls == 1'b1 || rs == 1'b1)
ns = S11;
else
ns = S4;
S11: ns = S12;
S12: ns = S10;
S13: ;
default: ns = S0;
endcase;
end
always @(posedge clk)
if(~rst)
count <= 0;
else
begin
if(st == S4)
if (count > 7)
count <= 0;
else
count <= count + 1;
end
//FSM outputs (combinatorial)
assign stop = (st == S3 || st == S12) ? 1'b1 : 1'b0;
assign finish = (st == S13) ? 1'b1 : 1'b0;
assign busy = (st == S8 || st == S9) ? 1'b1 : 1'b0;
endmodule
module top (
input clk,
input rst,
input en,
input a,
input b,
output s,
output bs,
output f
);
FSM u_FSM ( .clk(clk),
.rst(rst),
.en(en),
.ls(a),
.rs(b),
.stop(s),
.busy(bs),
.finish(f));
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk)
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b,b1,b2,b3,b4
);
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
module testbench;
reg [11:0] in;
wire [4:0] patt_out,out;
wire [4:0] patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[3:0]),
.y(in[7:4]),
.cin(in[11:8]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[11:8] + in[7:4] + in[3:0];
assert_comb out_test(.A(patt_out[3]), .B(out[3]));
assert_comb carry_test(.A(patt_carry_out[3]), .B(carryout[3]));
endmodule
module top
(
input [3:0] x,
input [3:0] y,
input [3:0] cin,
output [4:0] A,
output [4:0] cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg in = 0;
wire [7:0] f;
top uut ( .clk(clk),
.in(in),
.out(f));
always @(posedge clk) begin
#3
in <= ~in;
end
assert_expr f_test(.clk(clk), .A(f[0]));
endmodule
module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module top (
out,
out1,
clk,
in
);
output [7:0] out;
output [7:0] out1;
input signed clk, in;
reg signed [7:0] out;
reg signed [7:0] out1;
always @(posedge clk)
begin
`ifndef BUG
out <= out >> 1;
out[7] <= in;
`else
out <= 8'bZZZZZZZZ;
`endif
end
always @(posedge clk)
begin
out1 <= out1 >> 1;
out1[7] <= in;
end
endmodule
......@@ -62,7 +62,7 @@ $(eval $(call template,read_liberty_tech,read_liberty read_liberty_nooverwrite r
$(eval $(call template,read_liberty_error, read_liberty_invalid_bus_type read_liberty_unsupp_type_for_bus read_liberty_bus_interface_only_in_lib_mode read_liberty_latch_has_no_data_in read_liberty_miss_func_on_output read_liberty_ff_has_no_next_stage_attr read_liberty_parse_error_in_function read_liberty_cant_resolve_wire_name read_liberty_missing_direction read_liberty_cant_open_input_file read_liberty_redefenition_of_module ))
#read_aiger
$(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_clk read_aiger_clk_module ))
$(eval $(call template,read_aiger,read_aiger read_aiger_proc read_aiger_ascii read_aiger_module read_aiger_map read_aiger_clk read_aiger_clk_module ))
$(eval $(call template,read_aiger_latch,read_aiger_aig))
$(eval $(call template,read_aiger_logic,read_aiger_aig))
$(eval $(call template,read_aiger_ff,read_aiger_aig))
......
......@@ -469,6 +469,30 @@ $(eval $(call template,issue_01135,issue_01135))
#issue_01144
$(eval $(call template,issue_01144,issue_01144))
#issue_01145
$(eval $(call template,issue_01145,issue_01145))
#issue_01220
$(eval $(call template,issue_01220,issue_01220))
#issue_01223
$(eval $(call template,issue_01223,issue_01223))
#issue_01231
$(eval $(call template,issue_01231,issue_01231))
#issue_01243
$(eval $(call template,issue_01243,issue_01243))
#issue_01273
$(eval $(call template,issue_01273,issue_01273))
#issue_01284
$(eval $(call template,issue_01284,issue_01284))
#issue_01329
$(eval $(call template,issue_01329,issue_01329))
......
module TopModule(
input logic clk,
input logic rst,
output logic [21:0] outOther,
input logic [1:0] sig,
input logic flip,
output logic [1:0] sig_out,
output logic [15:0] passThrough);
MyInterface #(.WIDTH(4)) MyInterfaceInstance();
SubModule1 u_SubModule1 (
.clk(clk),
.rst(rst),
.u_MyInterface(MyInterfaceInstance),
.outOther(outOther),
.sig (sig)
);
assign sig_out = MyInterfaceInstance.mysig_out;
assign MyInterfaceInstance.setting = flip;
assign passThrough = MyInterfaceInstance.passThrough;
endmodule
interface MyInterface #(
parameter WIDTH = 3)(
);
logic setting;
logic [WIDTH-1:0] other_setting;
logic [1:0] mysig_out;
logic [15:0] passThrough;
modport submodule1 (
input setting,
output other_setting,
output mysig_out,
output passThrough
);
modport submodule2 (
input setting,
output other_setting,
input mysig_out,
output passThrough
);
endinterface
module SubModule1(
input logic clk,
input logic rst,
MyInterface.submodule1 u_MyInterface,
input logic [1:0] sig,
output logic [21:0] outOther
);
always_ff @(posedge clk or posedge rst)
if(rst)
u_MyInterface.mysig_out <= 0;
else begin
if(u_MyInterface.setting)
u_MyInterface.mysig_out <= sig;
else
u_MyInterface.mysig_out <= ~sig;
end
MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
SubModule2 u_SubModule2 (
.clk(clk),
.rst(rst),
.u_MyInterfaceInSub2(u_MyInterface),
.u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
);
assign outOther = MyInterfaceInstanceInSub.other_setting;
assign MyInterfaceInstanceInSub.setting = 0;
assign MyInterfaceInstanceInSub.mysig_out = sig;
endmodule
module SubModule2(
input logic clk,
input logic rst,
MyInterface.submodule2 u_MyInterfaceInSub2,
MyInterface.submodule2 u_MyInterfaceInSub3
);
always_comb begin
if (u_MyInterfaceInSub3.mysig_out == 2'b00)
u_MyInterfaceInSub3.other_setting[21:0] = 1000;
else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
u_MyInterfaceInSub3.other_setting[21:0] = 2000;
else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
u_MyInterfaceInSub3.other_setting[21:0] = 3000;
else
u_MyInterfaceInSub3.other_setting[21:0] = 4000;
end
assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
endmodule
module submod(output q);
wire aa = 1'b1;
assign q = aa;
endmodule
module top(output q);
wire \submod_i.aa ;
submod submod_i(.q(\submod_i.aa ));
assign q = \submod_i.aa ;
endmodule
`default_nettype none
module top
(
inout wire [7:0] data_io,
output reg [7:0] rdata_o,
input wire [7:0] wdata_i,
input wire rxf_n_i,
input wire txe_n_i,
output reg rd_n_o,
output reg wr_n_o,
output reg siwua_n_o,
input wire clk_i,
output reg oe_n_o,
input wire suspend_n_i
);
initial begin
rdata_o = {8{1'b0}};
rd_n_o = 1;
wr_n_o = 1;
siwua_n_o = 1; /* Never flush TX data. */
end
assign data_io = (!txe_n_i && !wr_n_o) ? wdata_i : {8{1'bz}};
always @(posedge clk_i, negedge suspend_n_i) begin
if (!suspend_n_i) begin
wr_n_o <= 1;
rd_n_o <= 1;
oe_n_o <= 1;
rdata_o <= {8{1'b0}};
end
else begin
// Give TX bus precedence.
if (!txe_n_i) begin
wr_n_o <= 0;
rd_n_o <= 1;
oe_n_o <= 1;
rdata_o <= {8{1'b0}};
end
// oe_n_o must be driven low at least one period before we can read.
else if (!rxf_n_i && oe_n_o) begin
wr_n_o <= 1;
rd_n_o <= 1;
oe_n_o <= 0;
rdata_o <= {8{1'b0}};
end
else if (!rxf_n_i && !oe_n_o) begin
wr_n_o <= 1;
rd_n_o <= 0;
oe_n_o <= 0;
rdata_o <= data_io;
end
else begin
wr_n_o <= 1;
rd_n_o <= 1;
oe_n_o <= 1;
rdata_o <= {8{1'b0}};
end
end // else: !if(!suspend_n_i)
end
endmodule // usb
module fnmcve(o_crc);
output reg [7:0] o_crc;
always @(*)
o_crc = gencrc({ 2'b01, 6'h11, 32'h00 });
function [7:0] gencrc;
input [39:0] i_cmdword;
integer icrc;
gencrc = 0;
for(icrc=0; icrc<40; icrc=icrc+1)
if (i_cmdword[39-icrc] ^ gencrc[7])
gencrc[7:1] = { gencrc[6:1], 1'b0 } ^ 7'h09;
else
gencrc[7:1] = { gencrc[6:1], 1'b0 };
gencrc = { gencrc[7:1], 1'b1 };
endfunction
endmodule
module top (y, clk, sel);
output wire y ;
input clk;
input sel;
reg reg_assign = (1'h0) ;
reg [1:0] reg_count = (1'h0) ;
assign y = reg_assign ;
always @(posedge clk)
if (sel)
for (reg_count = 0; reg_count < 2; reg_count = reg_count + 1'h1)
if (0);
else reg_assign <= 1;
else reg_assign <= 0;
endmodule
module top (
input [5:0] S,
input [63:0] D,
output M256
);
assign M256 = D[S];
endmodule
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
module top
(
input x,
input y,
input cin,
output A,
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
// Design
// D flip-flop
// https://www.edaplayground.com/x/5dzJ
// If (asynchronous 'reset_sync' & enable') are true on the same clock,
// and then 'reset_sync' is low on the next clock,
// then the asynchronous 'reset_sync' gets ignored and the 'enable' applied
module dff (clk, reset, enable, d, q);
input clk;
input reset;
input enable;
input d;
output reg q;
always @(posedge clk or posedge reset_sync)
begin
if (reset_sync) begin
// Asynchronous reset when reset goes high
q <= 1'b0;
end
else if(enable)
begin
// Assign D to Q on positive clock edge
q <= d;
end
end
wire reset_sync;
synchronizer #(.RESET_STATE(1)) reset_synchronizer(
.clk(clk),
.reset(reset),
.data_i(0),
.data_o(reset_sync));
`ifdef FORMAL
always @($global_clock) assume(clk != $past(clk));
localparam MAX_CNT = 16;
reg[$clog2(MAX_CNT)-1:0] counter;
initial counter = 0;
always @(posedge clk) counter <= counter + 1;
initial assume(reset);
initial assume(enable);
always @(posedge clk) if(counter == (MAX_CNT >> 1)) assume(reset != $past(reset));
//always @(*) assume(d == 1'b1);
always @(clk)
begin
if(clk) assume(d == 1'b0);
else assume(d == 1'b1);
end
always @(clk)
begin
if(clk) assume(!enable);
else assume(enable);
end
always @(posedge clk)
begin
if(reset_sync) assert(q == 0);
else if(enable) assert(q == d);
else assert(q == $past(q));
end
always @(posedge clk) cover(reset && enable && d && !clk);
`endif
endmodule
// https://github.com/jbush001/NyuziProcessor/blob/master/hardware/core/synchronizer.sv
//
// Copyright 2011-2015 Jeff Bush
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//
// Transfer a signal into a clock domain, avoiding metastability and
// race conditions due to propagation delay.
//
module synchronizer
#(parameter WIDTH = 1,
parameter RESET_STATE = 0)
(input clk,
input reset,
output logic[WIDTH - 1:0] data_o,
input [WIDTH - 1:0] data_i);
logic[WIDTH - 1:0] sync0;
logic[WIDTH - 1:0] sync1;
always_ff @(posedge clk, posedge reset)
begin
if (reset)
begin
sync0 <= {WIDTH{RESET_STATE}};
sync1 <= {WIDTH{RESET_STATE}};
data_o <= {WIDTH{RESET_STATE}};
end
else
begin
sync0 <= data_i;
sync1 <= sync0;
data_o <= sync1;
end
end
endmodule
\ No newline at end of file
......@@ -121,7 +121,14 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_01118" ] ||\
[ "$1" = "issue_01128" ] ||\
[ "$1" = "issue_01132" ] ||\
[ "$1" = "issue_01135" ]; then
[ "$1" = "issue_01135" ] ||\
[ "$1" = "issue_01145" ] ||\
[ "$1" = "issue_01220" ] ||\
[ "$1" = "issue_01223" ] ||\
[ "$1" = "issue_01231" ] ||\
[ "$1" = "issue_01243" ] ||\
[ "$1" = "issue_01273" ] ||\
[ "$1" = "issue_01329" ]; then
expected_string=""
expected="1"
......@@ -245,6 +252,19 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="\$_MUX4_ 1"
elif [ "$1" = "issue_01135" ]; then
expected_string="\$pmux 1"
elif [ "$1" = "issue_01145" ] ||\
[ "$1" = "issue_01220" ]; then
expected_string="Executing FLATTEN pass (flatten design)."
elif [ "$1" = "issue_01223" ]; then
expected_string=" Executing CHECK pass (checking for obvious problems)."
elif [ "$1" = "issue_01231" ]; then
expected_string="Successfully finished Verilog frontend."
elif [ "$1" = "issue_01243" ]; then
expected_string="assign y = reg_assign;"
elif [ "$1" = "issue_01273" ]; then
expected_string="\$_MUX8_ 9"
elif [ "$1" = "issue_01329" ]; then
expected_string="\$mux 1"
fi
if [ "$1" = "issue_01118" ]; then
......
read_verilog -sv ../top.sv
hierarchy -check -top TopModule
proc
tee -o result.log flatten
read_verilog ../top.v
hierarchy -top top
proc
tee -o result.log flatten
read_verilog ../top.v
tee -o result.log synth_xilinx
tee -o result.log read -formal ../top.v
read_verilog ../top.v
synth
write_verilog -noattr result.log
read_verilog ../top.v
synth
write_verilog -noattr result.log
read_verilog ../top.v
synth -top top
muxcover -mux8
tee -o result.log stat
read_verilog ../top.v
proc
synth -top top
extract_fa -ha -v
tee -o result.log dump
synth -top top
write_verilog synth.v
# read design
read_verilog ../dff.v
read_verilog -sv ../synchronizer.sv
hierarchy -check
# high-level synthesis
proc; opt; fsm; opt; memory; opt
flatten
cd dff # Constrain all select calls below inside the top module
select -assert-count 4 t:$adff
select -assert-count 1 t:$mux
select -assert-none t:$adff t:$mux %% t:* %D
tee -o result.log stat
......@@ -235,4 +235,7 @@ $(eval $(call template, simplemap_mem_slice_concat, simplemap simplemap_top simp
#techmap
$(eval $(call template, techmap, techmap techmap_wb techmap_autoproc techmap_recursive techmap_extern techmap_assert techmap_i techmap_d techmap_max_iter techmap_map))
#test_pmgen
$(eval $(call template, test_pmgen, test_pmgen_eqpmux test_pmgen_generate_eqpmux test_pmgen_generate_ice40_dsp test_pmgen_generate_peepopt_muldiv test_pmgen_generate_peepopt_shiftmul test_pmgen_generate_reduce test_pmgen_generate_xilinx_srl_fixed test_pmgen_generate_xilinx_srl_variable test_pmgen_reduce_chain test_pmgen_reduce_tree))
.PHONY: all clean
read_verilog ../top.v
proc
tee -o result.log test_pmgen -eqpmux
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate eqpmux
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate ice40_dsp
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate peepopt-muldiv
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate peepopt-shiftmul
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate reduce
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate xilinx_srl.fixed
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -generate xilinx_srl.variable
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -reduce_chain
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
read_verilog ../top.v
proc
tee -o result.log test_pmgen -reduce_tree
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire [1:0] dioB;
wire [1:0] doutC;
top uut (
.en (en ),
.a (dinA ),
.b (dioB ),
.c (doutC )
);
always @(posedge en) begin
#3;
dinA <= !dinA;
end
assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
endmodule
module tristate (en, i, io, o);
input en;
input i;
inout [1:0] io;
output [1:0] o;
`ifndef BUG
assign io[0] = (en)? i : 1'bZ;
assign io[1] = (i)? en : 1'bZ;
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign o = ~io;
`endif
endmodule
module top (
input en,
input a,
inout [1:0] b,
output [1:0] c
);
tristate u_tri (
.en (en ),
.i (a ),
.io (b ),
.o (c )
);
endmodule
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